lsq_unit_impl.hh revision 13954:2f400a5f2627
16166Ssteve.reinhardt@amd.com 26928SBrad.Beckmann@amd.com/* 36166Ssteve.reinhardt@amd.com * Copyright (c) 2010-2014, 2017-2018 ARM Limited 46166Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 56166Ssteve.reinhardt@amd.com * All rights reserved 66166Ssteve.reinhardt@amd.com * 76166Ssteve.reinhardt@amd.com * The license below extends only to copyright in the software and shall 86166Ssteve.reinhardt@amd.com * not be construed as granting a license to any other intellectual 96166Ssteve.reinhardt@amd.com * property including but not limited to intellectual property relating 106166Ssteve.reinhardt@amd.com * to a hardware implementation of the functionality of the software 116166Ssteve.reinhardt@amd.com * licensed hereunder. You may use the software subject to the license 126166Ssteve.reinhardt@amd.com * terms below provided that you ensure that this notice is replicated 136166Ssteve.reinhardt@amd.com * unmodified and in its entirety in all distributions of the software, 146166Ssteve.reinhardt@amd.com * modified or unmodified, in source code or in binary form. 156166Ssteve.reinhardt@amd.com * 166166Ssteve.reinhardt@amd.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 176166Ssteve.reinhardt@amd.com * All rights reserved. 186166Ssteve.reinhardt@amd.com * 196166Ssteve.reinhardt@amd.com * Redistribution and use in source and binary forms, with or without 206166Ssteve.reinhardt@amd.com * modification, are permitted provided that the following conditions are 216166Ssteve.reinhardt@amd.com * met: redistributions of source code must retain the above copyright 226166Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer; 236166Ssteve.reinhardt@amd.com * redistributions in binary form must reproduce the above copyright 246166Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer in the 256166Ssteve.reinhardt@amd.com * documentation and/or other materials provided with the distribution; 266166Ssteve.reinhardt@amd.com * neither the name of the copyright holders nor the names of its 276166Ssteve.reinhardt@amd.com * contributors may be used to endorse or promote products derived from 286166Ssteve.reinhardt@amd.com * this software without specific prior written permission. 296166Ssteve.reinhardt@amd.com * 306166Ssteve.reinhardt@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 316166Ssteve.reinhardt@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 326919SBrad.Beckmann@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 336919SBrad.Beckmann@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 346919SBrad.Beckmann@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 356166Ssteve.reinhardt@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3611670Sandreas.hansson@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 376919SBrad.Beckmann@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3811670Sandreas.hansson@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3911682Sandreas.hansson@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 406919SBrad.Beckmann@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 416919SBrad.Beckmann@amd.com * 428920Snilay@cs.wisc.edu * Authors: Kevin Lim 436919SBrad.Beckmann@amd.com * Korey Sewell 447570SBrad.Beckmann@amd.com */ 457570SBrad.Beckmann@amd.com 466919SBrad.Beckmann@amd.com#ifndef __CPU_O3_LSQ_UNIT_IMPL_HH__ 476919SBrad.Beckmann@amd.com#define __CPU_O3_LSQ_UNIT_IMPL_HH__ 486166Ssteve.reinhardt@amd.com 497570SBrad.Beckmann@amd.com#include "arch/generic/debugfaults.hh" 507570SBrad.Beckmann@amd.com#include "arch/locked_mem.hh" 517570SBrad.Beckmann@amd.com#include "base/str.hh" 527570SBrad.Beckmann@amd.com#include "config/the_isa.hh" 537570SBrad.Beckmann@amd.com#include "cpu/checker/cpu.hh" 547570SBrad.Beckmann@amd.com#include "cpu/o3/lsq.hh" 557570SBrad.Beckmann@amd.com#include "cpu/o3/lsq_unit.hh" 567570SBrad.Beckmann@amd.com#include "debug/Activity.hh" 577570SBrad.Beckmann@amd.com#include "debug/IEW.hh" 587570SBrad.Beckmann@amd.com#include "debug/LSQUnit.hh" 597570SBrad.Beckmann@amd.com#include "debug/O3PipeView.hh" 607570SBrad.Beckmann@amd.com#include "mem/packet.hh" 619841Snilay@cs.wisc.edu#include "mem/request.hh" 627570SBrad.Beckmann@amd.com 636166Ssteve.reinhardt@amd.comtemplate<class Impl> 646166Ssteve.reinhardt@amd.comLSQUnit<Impl>::WritebackEvent::WritebackEvent(const DynInstPtr &_inst, 656928SBrad.Beckmann@amd.com PacketPtr _pkt, LSQUnit *lsq_ptr) 666928SBrad.Beckmann@amd.com : Event(Default_Pri, AutoDelete), 6710688Sandreas.hansson@arm.com inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 688436SBrad.Beckmann@amd.com{ 6913718Sandreas.sandberg@arm.com assert(_inst->savedReq); 706166Ssteve.reinhardt@amd.com _inst->savedReq->writebackScheduled(); 716919SBrad.Beckmann@amd.com} 726919SBrad.Beckmann@amd.com 7311320Ssteve.reinhardt@amd.comtemplate<class Impl> 746919SBrad.Beckmann@amd.comvoid 7510688Sandreas.hansson@arm.comLSQUnit<Impl>::WritebackEvent::process() 769827Sakash.bagdia@arm.com{ 779827Sakash.bagdia@arm.com assert(!lsqPtr->cpu->switchedOut()); 789827Sakash.bagdia@arm.com 799827Sakash.bagdia@arm.com lsqPtr->writeback(inst, pkt); 809793Sakash.bagdia@arm.com 819793Sakash.bagdia@arm.com assert(inst->savedReq); 829793Sakash.bagdia@arm.com inst->savedReq->writebackDone(); 839827Sakash.bagdia@arm.com delete pkt; 849827Sakash.bagdia@arm.com} 859793Sakash.bagdia@arm.com 869793Sakash.bagdia@arm.comtemplate<class Impl> 879793Sakash.bagdia@arm.comconst char * 889793Sakash.bagdia@arm.comLSQUnit<Impl>::WritebackEvent::description() const 896289Snate@binkert.org{ 909826Sandreas.hansson@arm.com return "Store writeback"; 919826Sandreas.hansson@arm.com} 9210519Snilay@cs.wisc.edu 936166Ssteve.reinhardt@amd.comtemplate <class Impl> 949793Sakash.bagdia@arm.combool 959827Sakash.bagdia@arm.comLSQUnit<Impl>::recvTimingResp(PacketPtr pkt) 969827Sakash.bagdia@arm.com{ 979793Sakash.bagdia@arm.com auto senderState = dynamic_cast<LSQSenderState*>(pkt->senderState); 9810120Snilay@cs.wisc.edu LSQRequest* req = senderState->request(); 996166Ssteve.reinhardt@amd.com assert(req != nullptr); 10010120Snilay@cs.wisc.edu bool ret = true; 1016919SBrad.Beckmann@amd.com /* Check that the request is still alive before any further action. */ 10210688Sandreas.hansson@arm.com if (senderState->alive()) { 1036919SBrad.Beckmann@amd.com ret = req->recvTimingResp(pkt); 1046919SBrad.Beckmann@amd.com } else { 10510688Sandreas.hansson@arm.com senderState->outstanding--; 10610688Sandreas.hansson@arm.com } 1077938SBrad.Beckmann@amd.com return ret; 1087938SBrad.Beckmann@amd.com 1097938SBrad.Beckmann@amd.com} 1107938SBrad.Beckmann@amd.com 1117938SBrad.Beckmann@amd.comtemplate<class Impl> 1126166Ssteve.reinhardt@amd.comvoid 1136166Ssteve.reinhardt@amd.comLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 1146166Ssteve.reinhardt@amd.com{ 1156166Ssteve.reinhardt@amd.com LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 1166166Ssteve.reinhardt@amd.com DynInstPtr inst = state->inst; 1178801Sgblack@eecs.umich.edu 1186166Ssteve.reinhardt@amd.com cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt)); 119 120 /* Notify the sender state that the access is complete (for ownership 121 * tracking). */ 122 state->complete(); 123 124 assert(!cpu->switchedOut()); 125 if (!inst->isSquashed()) { 126 if (state->needWB) { 127 // Only loads, store conditionals and atomics perform the writeback 128 // after receving the response from the memory 129 assert(inst->isLoad() || inst->isStoreConditional() || 130 inst->isAtomic()); 131 writeback(inst, state->request()->mainPacket()); 132 if (inst->isStore() || inst->isAtomic()) { 133 auto ss = dynamic_cast<SQSenderState*>(state); 134 ss->writebackDone(); 135 completeStore(ss->idx); 136 } 137 } else if (inst->isStore()) { 138 // This is a regular store (i.e., not store conditionals and 139 // atomics), so it can complete without writing back 140 completeStore(dynamic_cast<SQSenderState*>(state)->idx); 141 } 142 } 143} 144 145template <class Impl> 146LSQUnit<Impl>::LSQUnit(uint32_t lqEntries, uint32_t sqEntries) 147 : lsqID(-1), storeQueue(sqEntries+1), loadQueue(lqEntries+1), 148 loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false), 149 isStoreBlocked(false), storeInFlight(false), hasPendingRequest(false), 150 pendingRequest(nullptr) 151{ 152} 153 154template<class Impl> 155void 156LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 157 LSQ *lsq_ptr, unsigned id) 158{ 159 lsqID = id; 160 161 cpu = cpu_ptr; 162 iewStage = iew_ptr; 163 164 lsq = lsq_ptr; 165 166 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",lsqID); 167 168 depCheckShift = params->LSQDepCheckShift; 169 checkLoads = params->LSQCheckLoads; 170 needsTSO = params->needsTSO; 171 172 resetState(); 173} 174 175 176template<class Impl> 177void 178LSQUnit<Impl>::resetState() 179{ 180 loads = stores = storesToWB = 0; 181 182 183 storeWBIt = storeQueue.begin(); 184 185 retryPkt = NULL; 186 memDepViolator = NULL; 187 188 stalled = false; 189 190 cacheBlockMask = ~(cpu->cacheLineSize() - 1); 191} 192 193template<class Impl> 194std::string 195LSQUnit<Impl>::name() const 196{ 197 if (Impl::MaxThreads == 1) { 198 return iewStage->name() + ".lsq"; 199 } else { 200 return iewStage->name() + ".lsq.thread" + std::to_string(lsqID); 201 } 202} 203 204template<class Impl> 205void 206LSQUnit<Impl>::regStats() 207{ 208 lsqForwLoads 209 .name(name() + ".forwLoads") 210 .desc("Number of loads that had data forwarded from stores"); 211 212 invAddrLoads 213 .name(name() + ".invAddrLoads") 214 .desc("Number of loads ignored due to an invalid address"); 215 216 lsqSquashedLoads 217 .name(name() + ".squashedLoads") 218 .desc("Number of loads squashed"); 219 220 lsqIgnoredResponses 221 .name(name() + ".ignoredResponses") 222 .desc("Number of memory responses ignored because the instruction is squashed"); 223 224 lsqMemOrderViolation 225 .name(name() + ".memOrderViolation") 226 .desc("Number of memory ordering violations"); 227 228 lsqSquashedStores 229 .name(name() + ".squashedStores") 230 .desc("Number of stores squashed"); 231 232 invAddrSwpfs 233 .name(name() + ".invAddrSwpfs") 234 .desc("Number of software prefetches ignored due to an invalid address"); 235 236 lsqBlockedLoads 237 .name(name() + ".blockedLoads") 238 .desc("Number of blocked loads due to partial load-store forwarding"); 239 240 lsqRescheduledLoads 241 .name(name() + ".rescheduledLoads") 242 .desc("Number of loads that were rescheduled"); 243 244 lsqCacheBlocked 245 .name(name() + ".cacheBlocked") 246 .desc("Number of times an access to memory failed due to the cache being blocked"); 247} 248 249template<class Impl> 250void 251LSQUnit<Impl>::setDcachePort(MasterPort *dcache_port) 252{ 253 dcachePort = dcache_port; 254} 255 256template<class Impl> 257void 258LSQUnit<Impl>::drainSanityCheck() const 259{ 260 for (int i = 0; i < loadQueue.capacity(); ++i) 261 assert(!loadQueue[i].valid()); 262 263 assert(storesToWB == 0); 264 assert(!retryPkt); 265} 266 267template<class Impl> 268void 269LSQUnit<Impl>::takeOverFrom() 270{ 271 resetState(); 272} 273 274template <class Impl> 275void 276LSQUnit<Impl>::insert(const DynInstPtr &inst) 277{ 278 assert(inst->isMemRef()); 279 280 assert(inst->isLoad() || inst->isStore() || inst->isAtomic()); 281 282 if (inst->isLoad()) { 283 insertLoad(inst); 284 } else { 285 insertStore(inst); 286 } 287 288 inst->setInLSQ(); 289} 290 291template <class Impl> 292void 293LSQUnit<Impl>::insertLoad(const DynInstPtr &load_inst) 294{ 295 assert(!loadQueue.full()); 296 assert(loads < loadQueue.capacity()); 297 298 DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n", 299 load_inst->pcState(), loadQueue.tail(), load_inst->seqNum); 300 301 /* Grow the queue. */ 302 loadQueue.advance_tail(); 303 304 load_inst->sqIt = storeQueue.end(); 305 306 assert(!loadQueue.back().valid()); 307 loadQueue.back().set(load_inst); 308 load_inst->lqIdx = loadQueue.tail(); 309 load_inst->lqIt = loadQueue.getIterator(load_inst->lqIdx); 310 311 ++loads; 312} 313 314template <class Impl> 315void 316LSQUnit<Impl>::insertStore(const DynInstPtr& store_inst) 317{ 318 // Make sure it is not full before inserting an instruction. 319 assert(!storeQueue.full()); 320 assert(stores < storeQueue.capacity()); 321 322 DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n", 323 store_inst->pcState(), storeQueue.tail(), store_inst->seqNum); 324 storeQueue.advance_tail(); 325 326 store_inst->sqIdx = storeQueue.tail(); 327 store_inst->lqIdx = loadQueue.moduloAdd(loadQueue.tail(), 1); 328 store_inst->lqIt = loadQueue.end(); 329 330 storeQueue.back().set(store_inst); 331 332 ++stores; 333} 334 335template <class Impl> 336typename Impl::DynInstPtr 337LSQUnit<Impl>::getMemDepViolator() 338{ 339 DynInstPtr temp = memDepViolator; 340 341 memDepViolator = NULL; 342 343 return temp; 344} 345 346template <class Impl> 347unsigned 348LSQUnit<Impl>::numFreeLoadEntries() 349{ 350 //LQ has an extra dummy entry to differentiate 351 //empty/full conditions. Subtract 1 from the free entries. 352 DPRINTF(LSQUnit, "LQ size: %d, #loads occupied: %d\n", 353 1 + loadQueue.capacity(), loads); 354 return loadQueue.capacity() - loads; 355} 356 357template <class Impl> 358unsigned 359LSQUnit<Impl>::numFreeStoreEntries() 360{ 361 //SQ has an extra dummy entry to differentiate 362 //empty/full conditions. Subtract 1 from the free entries. 363 DPRINTF(LSQUnit, "SQ size: %d, #stores occupied: %d\n", 364 1 + storeQueue.capacity(), stores); 365 return storeQueue.capacity() - stores; 366 367 } 368 369template <class Impl> 370void 371LSQUnit<Impl>::checkSnoop(PacketPtr pkt) 372{ 373 // Should only ever get invalidations in here 374 assert(pkt->isInvalidate()); 375 376 DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr()); 377 378 for (int x = 0; x < cpu->numContexts(); x++) { 379 ThreadContext *tc = cpu->getContext(x); 380 bool no_squash = cpu->thread[x]->noSquashFromTC; 381 cpu->thread[x]->noSquashFromTC = true; 382 TheISA::handleLockedSnoop(tc, pkt, cacheBlockMask); 383 cpu->thread[x]->noSquashFromTC = no_squash; 384 } 385 386 if (loadQueue.empty()) 387 return; 388 389 auto iter = loadQueue.begin(); 390 391 Addr invalidate_addr = pkt->getAddr() & cacheBlockMask; 392 393 DynInstPtr ld_inst = iter->instruction(); 394 assert(ld_inst); 395 LSQRequest *req = iter->request(); 396 397 // Check that this snoop didn't just invalidate our lock flag 398 if (ld_inst->effAddrValid() && 399 req->isCacheBlockHit(invalidate_addr, cacheBlockMask) 400 && ld_inst->memReqFlags & Request::LLSC) 401 TheISA::handleLockedSnoopHit(ld_inst.get()); 402 403 bool force_squash = false; 404 405 while (++iter != loadQueue.end()) { 406 ld_inst = iter->instruction(); 407 assert(ld_inst); 408 req = iter->request(); 409 if (!ld_inst->effAddrValid() || ld_inst->strictlyOrdered()) 410 continue; 411 412 DPRINTF(LSQUnit, "-- inst [sn:%lli] to pktAddr:%#x\n", 413 ld_inst->seqNum, invalidate_addr); 414 415 if (force_squash || 416 req->isCacheBlockHit(invalidate_addr, cacheBlockMask)) { 417 if (needsTSO) { 418 // If we have a TSO system, as all loads must be ordered with 419 // all other loads, this load as well as *all* subsequent loads 420 // need to be squashed to prevent possible load reordering. 421 force_squash = true; 422 } 423 if (ld_inst->possibleLoadViolation() || force_squash) { 424 DPRINTF(LSQUnit, "Conflicting load at addr %#x [sn:%lli]\n", 425 pkt->getAddr(), ld_inst->seqNum); 426 427 // Mark the load for re-execution 428 ld_inst->fault = std::make_shared<ReExec>(); 429 } else { 430 DPRINTF(LSQUnit, "HitExternal Snoop for addr %#x [sn:%lli]\n", 431 pkt->getAddr(), ld_inst->seqNum); 432 433 // Make sure that we don't lose a snoop hitting a LOCKED 434 // address since the LOCK* flags don't get updated until 435 // commit. 436 if (ld_inst->memReqFlags & Request::LLSC) 437 TheISA::handleLockedSnoopHit(ld_inst.get()); 438 439 // If a older load checks this and it's true 440 // then we might have missed the snoop 441 // in which case we need to invalidate to be sure 442 ld_inst->hitExternalSnoop(true); 443 } 444 } 445 } 446 return; 447} 448 449template <class Impl> 450Fault 451LSQUnit<Impl>::checkViolations(typename LoadQueue::iterator& loadIt, 452 const DynInstPtr& inst) 453{ 454 Addr inst_eff_addr1 = inst->effAddr >> depCheckShift; 455 Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift; 456 457 /** @todo in theory you only need to check an instruction that has executed 458 * however, there isn't a good way in the pipeline at the moment to check 459 * all instructions that will execute before the store writes back. Thus, 460 * like the implementation that came before it, we're overly conservative. 461 */ 462 while (loadIt != loadQueue.end()) { 463 DynInstPtr ld_inst = loadIt->instruction(); 464 if (!ld_inst->effAddrValid() || ld_inst->strictlyOrdered()) { 465 ++loadIt; 466 continue; 467 } 468 469 Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift; 470 Addr ld_eff_addr2 = 471 (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift; 472 473 if (inst_eff_addr2 >= ld_eff_addr1 && inst_eff_addr1 <= ld_eff_addr2) { 474 if (inst->isLoad()) { 475 // If this load is to the same block as an external snoop 476 // invalidate that we've observed then the load needs to be 477 // squashed as it could have newer data 478 if (ld_inst->hitExternalSnoop()) { 479 if (!memDepViolator || 480 ld_inst->seqNum < memDepViolator->seqNum) { 481 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] " 482 "and [sn:%lli] at address %#x\n", 483 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 484 memDepViolator = ld_inst; 485 486 ++lsqMemOrderViolation; 487 488 return std::make_shared<GenericISA::M5PanicFault>( 489 "Detected fault with inst [sn:%lli] and " 490 "[sn:%lli] at address %#x\n", 491 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 492 } 493 } 494 495 // Otherwise, mark the load has a possible load violation 496 // and if we see a snoop before it's commited, we need to squash 497 ld_inst->possibleLoadViolation(true); 498 DPRINTF(LSQUnit, "Found possible load violation at addr: %#x" 499 " between instructions [sn:%lli] and [sn:%lli]\n", 500 inst_eff_addr1, inst->seqNum, ld_inst->seqNum); 501 } else { 502 // A load/store incorrectly passed this store. 503 // Check if we already have a violator, or if it's newer 504 // squash and refetch. 505 if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum) 506 break; 507 508 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and " 509 "[sn:%lli] at address %#x\n", 510 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 511 memDepViolator = ld_inst; 512 513 ++lsqMemOrderViolation; 514 515 return std::make_shared<GenericISA::M5PanicFault>( 516 "Detected fault with " 517 "inst [sn:%lli] and [sn:%lli] at address %#x\n", 518 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 519 } 520 } 521 522 ++loadIt; 523 } 524 return NoFault; 525} 526 527 528 529 530template <class Impl> 531Fault 532LSQUnit<Impl>::executeLoad(const DynInstPtr &inst) 533{ 534 using namespace TheISA; 535 // Execute a specific load. 536 Fault load_fault = NoFault; 537 538 DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n", 539 inst->pcState(), inst->seqNum); 540 541 assert(!inst->isSquashed()); 542 543 load_fault = inst->initiateAcc(); 544 545 if (load_fault == NoFault && !inst->readMemAccPredicate()) { 546 assert(inst->readPredicate()); 547 inst->setExecuted(); 548 inst->completeAcc(nullptr); 549 iewStage->instToCommit(inst); 550 iewStage->activityThisCycle(); 551 return NoFault; 552 } 553 554 if (inst->isTranslationDelayed() && load_fault == NoFault) 555 return load_fault; 556 557 // If the instruction faulted or predicated false, then we need to send it 558 // along to commit without the instruction completing. 559 if (load_fault != NoFault || !inst->readPredicate()) { 560 // Send this instruction to commit, also make sure iew stage 561 // realizes there is activity. Mark it as executed unless it 562 // is a strictly ordered load that needs to hit the head of 563 // commit. 564 if (!inst->readPredicate()) 565 inst->forwardOldRegs(); 566 DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", 567 inst->seqNum, 568 (load_fault != NoFault ? "fault" : "predication")); 569 if (!(inst->hasRequest() && inst->strictlyOrdered()) || 570 inst->isAtCommit()) { 571 inst->setExecuted(); 572 } 573 iewStage->instToCommit(inst); 574 iewStage->activityThisCycle(); 575 } else { 576 if (inst->effAddrValid()) { 577 auto it = inst->lqIt; 578 ++it; 579 580 if (checkLoads) 581 return checkViolations(it, inst); 582 } 583 } 584 585 return load_fault; 586} 587 588template <class Impl> 589Fault 590LSQUnit<Impl>::executeStore(const DynInstPtr &store_inst) 591{ 592 using namespace TheISA; 593 // Make sure that a store exists. 594 assert(stores != 0); 595 596 int store_idx = store_inst->sqIdx; 597 598 DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n", 599 store_inst->pcState(), store_inst->seqNum); 600 601 assert(!store_inst->isSquashed()); 602 603 // Check the recently completed loads to see if any match this store's 604 // address. If so, then we have a memory ordering violation. 605 typename LoadQueue::iterator loadIt = store_inst->lqIt; 606 607 Fault store_fault = store_inst->initiateAcc(); 608 609 if (store_inst->isTranslationDelayed() && 610 store_fault == NoFault) 611 return store_fault; 612 613 if (!store_inst->readPredicate()) { 614 DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", 615 store_inst->seqNum); 616 store_inst->forwardOldRegs(); 617 return store_fault; 618 } 619 620 if (storeQueue[store_idx].size() == 0) { 621 DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", 622 store_inst->pcState(), store_inst->seqNum); 623 624 return store_fault; 625 } 626 627 assert(store_fault == NoFault); 628 629 if (store_inst->isStoreConditional() || store_inst->isAtomic()) { 630 // Store conditionals and Atomics need to set themselves as able to 631 // writeback if we haven't had a fault by here. 632 storeQueue[store_idx].canWB() = true; 633 634 ++storesToWB; 635 } 636 637 return checkViolations(loadIt, store_inst); 638 639} 640 641template <class Impl> 642void 643LSQUnit<Impl>::commitLoad() 644{ 645 assert(loadQueue.front().valid()); 646 647 DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n", 648 loadQueue.front().instruction()->pcState()); 649 650 loadQueue.front().clear(); 651 loadQueue.pop_front(); 652 653 --loads; 654} 655 656template <class Impl> 657void 658LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 659{ 660 assert(loads == 0 || loadQueue.front().valid()); 661 662 while (loads != 0 && loadQueue.front().instruction()->seqNum 663 <= youngest_inst) { 664 commitLoad(); 665 } 666} 667 668template <class Impl> 669void 670LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 671{ 672 assert(stores == 0 || storeQueue.front().valid()); 673 674 /* Forward iterate the store queue (age order). */ 675 for (auto& x : storeQueue) { 676 assert(x.valid()); 677 // Mark any stores that are now committed and have not yet 678 // been marked as able to write back. 679 if (!x.canWB()) { 680 if (x.instruction()->seqNum > youngest_inst) { 681 break; 682 } 683 DPRINTF(LSQUnit, "Marking store as able to write back, PC " 684 "%s [sn:%lli]\n", 685 x.instruction()->pcState(), 686 x.instruction()->seqNum); 687 688 x.canWB() = true; 689 690 ++storesToWB; 691 } 692 } 693} 694 695template <class Impl> 696void 697LSQUnit<Impl>::writebackBlockedStore() 698{ 699 assert(isStoreBlocked); 700 storeWBIt->request()->sendPacketToCache(); 701 if (storeWBIt->request()->isSent()){ 702 storePostSend(); 703 } 704} 705 706template <class Impl> 707void 708LSQUnit<Impl>::writebackStores() 709{ 710 if (isStoreBlocked) { 711 DPRINTF(LSQUnit, "Writing back blocked store\n"); 712 writebackBlockedStore(); 713 } 714 715 while (storesToWB > 0 && 716 storeWBIt.dereferenceable() && 717 storeWBIt->valid() && 718 storeWBIt->canWB() && 719 ((!needsTSO) || (!storeInFlight)) && 720 lsq->cachePortAvailable(false)) { 721 722 if (isStoreBlocked) { 723 DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 724 " is blocked!\n"); 725 break; 726 } 727 728 // Store didn't write any data so no need to write it back to 729 // memory. 730 if (storeWBIt->size() == 0) { 731 /* It is important that the preincrement happens at (or before) 732 * the call, as the the code of completeStore checks 733 * storeWBIt. */ 734 completeStore(storeWBIt++); 735 continue; 736 } 737 738 if (storeWBIt->instruction()->isDataPrefetch()) { 739 storeWBIt++; 740 continue; 741 } 742 743 assert(storeWBIt->hasRequest()); 744 assert(!storeWBIt->committed()); 745 746 DynInstPtr inst = storeWBIt->instruction(); 747 LSQRequest* req = storeWBIt->request(); 748 storeWBIt->committed() = true; 749 750 assert(!inst->memData); 751 inst->memData = new uint8_t[req->_size]; 752 753 if (storeWBIt->isAllZeros()) 754 memset(inst->memData, 0, req->_size); 755 else 756 memcpy(inst->memData, storeWBIt->data(), req->_size); 757 758 759 if (req->senderState() == nullptr) { 760 SQSenderState *state = new SQSenderState(storeWBIt); 761 state->isLoad = false; 762 state->needWB = false; 763 state->inst = inst; 764 765 req->senderState(state); 766 if (inst->isStoreConditional() || inst->isAtomic()) { 767 /* Only store conditionals and atomics need a writeback. */ 768 state->needWB = true; 769 } 770 } 771 req->buildPackets(); 772 773 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s " 774 "to Addr:%#x, data:%#x [sn:%lli]\n", 775 storeWBIt.idx(), inst->pcState(), 776 req->request()->getPaddr(), (int)*(inst->memData), 777 inst->seqNum); 778 779 // @todo: Remove this SC hack once the memory system handles it. 780 if (inst->isStoreConditional()) { 781 // Disable recording the result temporarily. Writing to 782 // misc regs normally updates the result, but this is not 783 // the desired behavior when handling store conditionals. 784 inst->recordResult(false); 785 bool success = TheISA::handleLockedWrite(inst.get(), 786 req->request(), cacheBlockMask); 787 inst->recordResult(true); 788 req->packetSent(); 789 790 if (!success) { 791 req->complete(); 792 // Instantly complete this store. 793 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 794 "Instantly completing it.\n", 795 inst->seqNum); 796 PacketPtr new_pkt = new Packet(*req->packet()); 797 WritebackEvent *wb = new WritebackEvent(inst, 798 new_pkt, this); 799 cpu->schedule(wb, curTick() + 1); 800 completeStore(storeWBIt); 801 if (!storeQueue.empty()) 802 storeWBIt++; 803 else 804 storeWBIt = storeQueue.end(); 805 continue; 806 } 807 } 808 809 if (req->request()->isMmappedIpr()) { 810 assert(!inst->isStoreConditional()); 811 ThreadContext *thread = cpu->tcBase(lsqID); 812 PacketPtr main_pkt = new Packet(req->mainRequest(), 813 MemCmd::WriteReq); 814 main_pkt->dataStatic(inst->memData); 815 req->handleIprWrite(thread, main_pkt); 816 delete main_pkt; 817 completeStore(storeWBIt); 818 storeWBIt++; 819 continue; 820 } 821 /* Send to cache */ 822 req->sendPacketToCache(); 823 824 /* If successful, do the post send */ 825 if (req->isSent()) { 826 storePostSend(); 827 } else { 828 DPRINTF(LSQUnit, "D-Cache became blocked when writing [sn:%lli], " 829 "will retry later\n", 830 inst->seqNum); 831 } 832 } 833 assert(stores >= 0 && storesToWB >= 0); 834} 835 836template <class Impl> 837void 838LSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 839{ 840 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 841 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 842 843 while (loads != 0 && 844 loadQueue.back().instruction()->seqNum > squashed_num) { 845 DPRINTF(LSQUnit,"Load Instruction PC %s squashed, " 846 "[sn:%lli]\n", 847 loadQueue.back().instruction()->pcState(), 848 loadQueue.back().instruction()->seqNum); 849 850 if (isStalled() && loadQueue.tail() == stallingLoadIdx) { 851 stalled = false; 852 stallingStoreIsn = 0; 853 stallingLoadIdx = 0; 854 } 855 856 // Clear the smart pointer to make sure it is decremented. 857 loadQueue.back().instruction()->setSquashed(); 858 loadQueue.back().clear(); 859 860 --loads; 861 862 loadQueue.pop_back(); 863 ++lsqSquashedLoads; 864 } 865 866 if (memDepViolator && squashed_num < memDepViolator->seqNum) { 867 memDepViolator = NULL; 868 } 869 870 while (stores != 0 && 871 storeQueue.back().instruction()->seqNum > squashed_num) { 872 // Instructions marked as can WB are already committed. 873 if (storeQueue.back().canWB()) { 874 break; 875 } 876 877 DPRINTF(LSQUnit,"Store Instruction PC %s squashed, " 878 "idx:%i [sn:%lli]\n", 879 storeQueue.back().instruction()->pcState(), 880 storeQueue.tail(), storeQueue.back().instruction()->seqNum); 881 882 // I don't think this can happen. It should have been cleared 883 // by the stalling load. 884 if (isStalled() && 885 storeQueue.back().instruction()->seqNum == stallingStoreIsn) { 886 panic("Is stalled should have been cleared by stalling load!\n"); 887 stalled = false; 888 stallingStoreIsn = 0; 889 } 890 891 // Clear the smart pointer to make sure it is decremented. 892 storeQueue.back().instruction()->setSquashed(); 893 894 // Must delete request now that it wasn't handed off to 895 // memory. This is quite ugly. @todo: Figure out the proper 896 // place to really handle request deletes. 897 storeQueue.back().clear(); 898 --stores; 899 900 storeQueue.pop_back(); 901 ++lsqSquashedStores; 902 } 903} 904 905template <class Impl> 906void 907LSQUnit<Impl>::storePostSend() 908{ 909 if (isStalled() && 910 storeWBIt->instruction()->seqNum == stallingStoreIsn) { 911 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 912 "load idx:%i\n", 913 stallingStoreIsn, stallingLoadIdx); 914 stalled = false; 915 stallingStoreIsn = 0; 916 iewStage->replayMemInst(loadQueue[stallingLoadIdx].instruction()); 917 } 918 919 if (!storeWBIt->instruction()->isStoreConditional()) { 920 // The store is basically completed at this time. This 921 // only works so long as the checker doesn't try to 922 // verify the value in memory for stores. 923 storeWBIt->instruction()->setCompleted(); 924 925 if (cpu->checker) { 926 cpu->checker->verify(storeWBIt->instruction()); 927 } 928 } 929 930 if (needsTSO) { 931 storeInFlight = true; 932 } 933 934 storeWBIt++; 935} 936 937template <class Impl> 938void 939LSQUnit<Impl>::writeback(const DynInstPtr &inst, PacketPtr pkt) 940{ 941 iewStage->wakeCPU(); 942 943 // Squashed instructions do not need to complete their access. 944 if (inst->isSquashed()) { 945 assert(!inst->isStore()); 946 ++lsqIgnoredResponses; 947 return; 948 } 949 950 if (!inst->isExecuted()) { 951 inst->setExecuted(); 952 953 if (inst->fault == NoFault) { 954 // Complete access to copy data to proper place. 955 inst->completeAcc(pkt); 956 } else { 957 // If the instruction has an outstanding fault, we cannot complete 958 // the access as this discards the current fault. 959 960 // If we have an outstanding fault, the fault should only be of 961 // type ReExec. 962 assert(dynamic_cast<ReExec*>(inst->fault.get()) != nullptr); 963 964 DPRINTF(LSQUnit, "Not completing instruction [sn:%lli] access " 965 "due to pending fault.\n", inst->seqNum); 966 } 967 } 968 969 // Need to insert instruction into queue to commit 970 iewStage->instToCommit(inst); 971 972 iewStage->activityThisCycle(); 973 974 // see if this load changed the PC 975 iewStage->checkMisprediction(inst); 976} 977 978template <class Impl> 979void 980LSQUnit<Impl>::completeStore(typename StoreQueue::iterator store_idx) 981{ 982 assert(store_idx->valid()); 983 store_idx->completed() = true; 984 --storesToWB; 985 // A bit conservative because a store completion may not free up entries, 986 // but hopefully avoids two store completions in one cycle from making 987 // the CPU tick twice. 988 cpu->wakeCPU(); 989 cpu->activityThisCycle(); 990 991 /* We 'need' a copy here because we may clear the entry from the 992 * store queue. */ 993 DynInstPtr store_inst = store_idx->instruction(); 994 if (store_idx == storeQueue.begin()) { 995 do { 996 storeQueue.front().clear(); 997 storeQueue.pop_front(); 998 --stores; 999 } while (storeQueue.front().completed() && 1000 !storeQueue.empty()); 1001 1002 iewStage->updateLSQNextCycle = true; 1003 } 1004 1005 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 1006 "idx:%i\n", 1007 store_inst->seqNum, store_idx.idx() - 1, storeQueue.head() - 1); 1008 1009#if TRACING_ON 1010 if (DTRACE(O3PipeView)) { 1011 store_inst->storeTick = 1012 curTick() - store_inst->fetchTick; 1013 } 1014#endif 1015 1016 if (isStalled() && 1017 store_inst->seqNum == stallingStoreIsn) { 1018 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 1019 "load idx:%i\n", 1020 stallingStoreIsn, stallingLoadIdx); 1021 stalled = false; 1022 stallingStoreIsn = 0; 1023 iewStage->replayMemInst(loadQueue[stallingLoadIdx].instruction()); 1024 } 1025 1026 store_inst->setCompleted(); 1027 1028 if (needsTSO) { 1029 storeInFlight = false; 1030 } 1031 1032 // Tell the checker we've completed this instruction. Some stores 1033 // may get reported twice to the checker, but the checker can 1034 // handle that case. 1035 // Store conditionals cannot be sent to the checker yet, they have 1036 // to update the misc registers first which should take place 1037 // when they commit 1038 if (cpu->checker && !store_inst->isStoreConditional()) { 1039 cpu->checker->verify(store_inst); 1040 } 1041} 1042 1043template <class Impl> 1044bool 1045LSQUnit<Impl>::trySendPacket(bool isLoad, PacketPtr data_pkt) 1046{ 1047 bool ret = true; 1048 bool cache_got_blocked = false; 1049 1050 auto state = dynamic_cast<LSQSenderState*>(data_pkt->senderState); 1051 1052 if (!lsq->cacheBlocked() && 1053 lsq->cachePortAvailable(isLoad)) { 1054 if (!dcachePort->sendTimingReq(data_pkt)) { 1055 ret = false; 1056 cache_got_blocked = true; 1057 } 1058 } else { 1059 ret = false; 1060 } 1061 1062 if (ret) { 1063 if (!isLoad) { 1064 isStoreBlocked = false; 1065 } 1066 lsq->cachePortBusy(isLoad); 1067 state->outstanding++; 1068 state->request()->packetSent(); 1069 } else { 1070 if (cache_got_blocked) { 1071 lsq->cacheBlocked(true); 1072 ++lsqCacheBlocked; 1073 } 1074 if (!isLoad) { 1075 assert(state->request() == storeWBIt->request()); 1076 isStoreBlocked = true; 1077 } 1078 state->request()->packetNotSent(); 1079 } 1080 return ret; 1081} 1082 1083template <class Impl> 1084void 1085LSQUnit<Impl>::recvRetry() 1086{ 1087 if (isStoreBlocked) { 1088 DPRINTF(LSQUnit, "Receiving retry: blocked store\n"); 1089 writebackBlockedStore(); 1090 } 1091} 1092 1093template <class Impl> 1094void 1095LSQUnit<Impl>::dumpInsts() const 1096{ 1097 cprintf("Load store queue: Dumping instructions.\n"); 1098 cprintf("Load queue size: %i\n", loads); 1099 cprintf("Load queue: "); 1100 1101 for (const auto& e: loadQueue) { 1102 const DynInstPtr &inst(e.instruction()); 1103 cprintf("%s.[sn:%llu] ", inst->pcState(), inst->seqNum); 1104 } 1105 cprintf("\n"); 1106 1107 cprintf("Store queue size: %i\n", stores); 1108 cprintf("Store queue: "); 1109 1110 for (const auto& e: storeQueue) { 1111 const DynInstPtr &inst(e.instruction()); 1112 cprintf("%s.[sn:%llu] ", inst->pcState(), inst->seqNum); 1113 } 1114 1115 cprintf("\n"); 1116} 1117 1118template <class Impl> 1119unsigned int 1120LSQUnit<Impl>::cacheLineSize() 1121{ 1122 return cpu->cacheLineSize(); 1123} 1124 1125#endif//__CPU_O3_LSQ_UNIT_IMPL_HH__ 1126