lsq_unit_impl.hh revision 13590:d7e018859709
12315SN/A 212107SRekai.GonzalezAlberquilla@arm.com/* 39913Ssteve.reinhardt@amd.com * Copyright (c) 2010-2014, 2017-2018 ARM Limited 48733Sgeoffrey.blake@arm.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 58733Sgeoffrey.blake@arm.com * All rights reserved 68733Sgeoffrey.blake@arm.com * 78733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 88733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 98733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 108733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 118733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 128733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 138733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 148733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 152332SN/A * 162315SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 172315SN/A * All rights reserved. 182315SN/A * 192315SN/A * Redistribution and use in source and binary forms, with or without 202315SN/A * modification, are permitted provided that the following conditions are 212315SN/A * met: redistributions of source code must retain the above copyright 222315SN/A * notice, this list of conditions and the following disclaimer; 232315SN/A * redistributions in binary form must reproduce the above copyright 242315SN/A * notice, this list of conditions and the following disclaimer in the 252315SN/A * documentation and/or other materials provided with the distribution; 262315SN/A * neither the name of the copyright holders nor the names of its 272315SN/A * contributors may be used to endorse or promote products derived from 282315SN/A * this software without specific prior written permission. 292315SN/A * 302315SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 312315SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 322315SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 332315SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 342315SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 352315SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 362315SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 372315SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 382315SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 392315SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 402689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412689SN/A * 428733Sgeoffrey.blake@arm.com * Authors: Kevin Lim 432315SN/A * Korey Sewell 442315SN/A */ 459944Smatt.horsnell@ARM.com 469944Smatt.horsnell@ARM.com#ifndef __CPU_O3_LSQ_UNIT_IMPL_HH__ 479944Smatt.horsnell@ARM.com#define __CPU_O3_LSQ_UNIT_IMPL_HH__ 482315SN/A 492315SN/A#include "arch/generic/debugfaults.hh" 502315SN/A#include "arch/locked_mem.hh" 518888Sgeoffrey.blake@arm.com#include "base/str.hh" 528793Sgblack@eecs.umich.edu#include "config/the_isa.hh" 532315SN/A#include "cpu/checker/cpu.hh" 546658Snate@binkert.org#include "cpu/o3/lsq.hh" 552315SN/A#include "cpu/o3/lsq_unit.hh" 568733Sgeoffrey.blake@arm.com#include "debug/Activity.hh" 579913Ssteve.reinhardt@amd.com#include "debug/IEW.hh" 582683SN/A#include "debug/LSQUnit.hh" 598229Snate@binkert.org#include "debug/O3PipeView.hh" 602680SN/A#include "mem/packet.hh" 618733Sgeoffrey.blake@arm.com#include "mem/request.hh" 628733Sgeoffrey.blake@arm.com 638793Sgblack@eecs.umich.edutemplate<class Impl> 642315SN/ALSQUnit<Impl>::WritebackEvent::WritebackEvent(const DynInstPtr &_inst, 652315SN/A PacketPtr _pkt, LSQUnit *lsq_ptr) 662315SN/A : Event(Default_Pri, AutoDelete), 672315SN/A inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 688733Sgeoffrey.blake@arm.com{ 692315SN/A assert(_inst->savedReq); 708733Sgeoffrey.blake@arm.com _inst->savedReq->writebackScheduled(); 712315SN/A} 7210379Sandreas.hansson@arm.com 738733Sgeoffrey.blake@arm.comtemplate<class Impl> 748733Sgeoffrey.blake@arm.comvoid 758733Sgeoffrey.blake@arm.comLSQUnit<Impl>::WritebackEvent::process() 768733Sgeoffrey.blake@arm.com{ 779023Sgblack@eecs.umich.edu assert(!lsqPtr->cpu->switchedOut()); 788733Sgeoffrey.blake@arm.com 798733Sgeoffrey.blake@arm.com lsqPtr->writeback(inst, pkt); 808733Sgeoffrey.blake@arm.com 818733Sgeoffrey.blake@arm.com assert(inst->savedReq); 828733Sgeoffrey.blake@arm.com inst->savedReq->writebackDone(); 838733Sgeoffrey.blake@arm.com delete pkt; 848733Sgeoffrey.blake@arm.com} 858733Sgeoffrey.blake@arm.com 868733Sgeoffrey.blake@arm.comtemplate<class Impl> 878733Sgeoffrey.blake@arm.comconst char * 888733Sgeoffrey.blake@arm.comLSQUnit<Impl>::WritebackEvent::description() const 898733Sgeoffrey.blake@arm.com{ 908733Sgeoffrey.blake@arm.com return "Store writeback"; 918733Sgeoffrey.blake@arm.com} 928733Sgeoffrey.blake@arm.com 938733Sgeoffrey.blake@arm.comtemplate <class Impl> 948733Sgeoffrey.blake@arm.combool 958733Sgeoffrey.blake@arm.comLSQUnit<Impl>::recvTimingResp(PacketPtr pkt) 968733Sgeoffrey.blake@arm.com{ 978733Sgeoffrey.blake@arm.com auto senderState = dynamic_cast<LSQSenderState*>(pkt->senderState); 988733Sgeoffrey.blake@arm.com LSQRequest* req = senderState->request(); 998733Sgeoffrey.blake@arm.com assert(req != nullptr); 1008733Sgeoffrey.blake@arm.com bool ret = true; 1018733Sgeoffrey.blake@arm.com /* Check that the request is still alive before any further action. */ 1028733Sgeoffrey.blake@arm.com if (senderState->alive()) { 1038733Sgeoffrey.blake@arm.com ret = req->recvTimingResp(pkt); 1048733Sgeoffrey.blake@arm.com } else { 1058733Sgeoffrey.blake@arm.com senderState->outstanding--; 1068733Sgeoffrey.blake@arm.com } 1078733Sgeoffrey.blake@arm.com return ret; 1088733Sgeoffrey.blake@arm.com 1098733Sgeoffrey.blake@arm.com} 1108733Sgeoffrey.blake@arm.com 1118733Sgeoffrey.blake@arm.comtemplate<class Impl> 1128733Sgeoffrey.blake@arm.comvoid 1138733Sgeoffrey.blake@arm.comLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 1148733Sgeoffrey.blake@arm.com{ 1158733Sgeoffrey.blake@arm.com LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 1168733Sgeoffrey.blake@arm.com DynInstPtr inst = state->inst; 1178733Sgeoffrey.blake@arm.com 1188733Sgeoffrey.blake@arm.com cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt)); 1198733Sgeoffrey.blake@arm.com 1208733Sgeoffrey.blake@arm.com /* Notify the sender state that the access is complete (for ownership 1219023Sgblack@eecs.umich.edu * tracking). */ 1228733Sgeoffrey.blake@arm.com state->complete(); 1238733Sgeoffrey.blake@arm.com 1248733Sgeoffrey.blake@arm.com assert(!cpu->switchedOut()); 1258733Sgeoffrey.blake@arm.com if (!inst->isSquashed()) { 1268733Sgeoffrey.blake@arm.com if (state->needWB) { 12713429Srekai.gonzalezalberquilla@arm.com // Only loads and store conditionals perform the writeback 1282315SN/A // after receving the response from the memory 1292315SN/A assert(inst->isLoad() || inst->isStoreConditional()); 1302315SN/A writeback(inst, state->request()->mainPacket()); 1318733Sgeoffrey.blake@arm.com if (inst->isStore()) { 1328733Sgeoffrey.blake@arm.com auto ss = dynamic_cast<SQSenderState*>(state); 1338733Sgeoffrey.blake@arm.com ss->writebackDone(); 1348733Sgeoffrey.blake@arm.com completeStore(ss->idx); 1358733Sgeoffrey.blake@arm.com } 1368733Sgeoffrey.blake@arm.com } else if (inst->isStore()) { 1378733Sgeoffrey.blake@arm.com completeStore(dynamic_cast<SQSenderState*>(state)->idx); 1388733Sgeoffrey.blake@arm.com } 1398733Sgeoffrey.blake@arm.com } 1408733Sgeoffrey.blake@arm.com} 1418733Sgeoffrey.blake@arm.com 1428733Sgeoffrey.blake@arm.comtemplate <class Impl> 1432332SN/ALSQUnit<Impl>::LSQUnit(uint32_t lqEntries, uint32_t sqEntries) 1442332SN/A : lsqID(-1), storeQueue(sqEntries+1), loadQueue(lqEntries+1), 1452332SN/A loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false), 1462332SN/A isStoreBlocked(false), storeInFlight(false), hasPendingRequest(false), 1472332SN/A pendingRequest(nullptr) 1482315SN/A{ 1492315SN/A} 1508733Sgeoffrey.blake@arm.com 1518733Sgeoffrey.blake@arm.comtemplate<class Impl> 1522315SN/Avoid 1532315SN/ALSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 1542315SN/A LSQ *lsq_ptr, unsigned id) 1552315SN/A{ 1562315SN/A lsqID = id; 1572315SN/A 1582315SN/A cpu = cpu_ptr; 1592315SN/A iewStage = iew_ptr; 1602315SN/A 1612315SN/A lsq = lsq_ptr; 1622315SN/A 1632315SN/A DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",lsqID); 1642315SN/A 1658733Sgeoffrey.blake@arm.com depCheckShift = params->LSQDepCheckShift; 1668733Sgeoffrey.blake@arm.com checkLoads = params->LSQCheckLoads; 1672315SN/A needsTSO = params->needsTSO; 1682315SN/A 1692315SN/A resetState(); 1702315SN/A} 1712315SN/A 1722315SN/A 1732315SN/Atemplate<class Impl> 1742315SN/Avoid 1752315SN/ALSQUnit<Impl>::resetState() 1762315SN/A{ 1772315SN/A loads = stores = storesToWB = 0; 1782315SN/A 1792315SN/A 1802315SN/A storeWBIt = storeQueue.begin(); 1818733Sgeoffrey.blake@arm.com 1828733Sgeoffrey.blake@arm.com retryPkt = NULL; 1838733Sgeoffrey.blake@arm.com memDepViolator = NULL; 1848733Sgeoffrey.blake@arm.com 1858733Sgeoffrey.blake@arm.com stalled = false; 1868733Sgeoffrey.blake@arm.com 1878733Sgeoffrey.blake@arm.com cacheBlockMask = ~(cpu->cacheLineSize() - 1); 1882354SN/A} 1898733Sgeoffrey.blake@arm.com 1902354SN/Atemplate<class Impl> 1912332SN/Astd::string 1922332SN/ALSQUnit<Impl>::name() const 1932332SN/A{ 1942315SN/A if (Impl::MaxThreads == 1) { 1958733Sgeoffrey.blake@arm.com return iewStage->name() + ".lsq"; 1968733Sgeoffrey.blake@arm.com } else { 1978733Sgeoffrey.blake@arm.com return iewStage->name() + ".lsq.thread" + std::to_string(lsqID); 1988733Sgeoffrey.blake@arm.com } 1998733Sgeoffrey.blake@arm.com} 2008733Sgeoffrey.blake@arm.com 2018733Sgeoffrey.blake@arm.comtemplate<class Impl> 2028733Sgeoffrey.blake@arm.comvoid 2038733Sgeoffrey.blake@arm.comLSQUnit<Impl>::regStats() 2042315SN/A{ 2052315SN/A lsqForwLoads 2062315SN/A .name(name() + ".forwLoads") 2072315SN/A .desc("Number of loads that had data forwarded from stores"); 2082315SN/A 2092683SN/A invAddrLoads 2108888Sgeoffrey.blake@arm.com .name(name() + ".invAddrLoads") 21113611Sgabeblack@google.com .desc("Number of loads ignored due to an invalid address"); 2128888Sgeoffrey.blake@arm.com 2132315SN/A lsqSquashedLoads 2142332SN/A .name(name() + ".squashedLoads") 2152332SN/A .desc("Number of loads squashed"); 2162332SN/A 2172315SN/A lsqIgnoredResponses 2188733Sgeoffrey.blake@arm.com .name(name() + ".ignoredResponses") 2198733Sgeoffrey.blake@arm.com .desc("Number of memory responses ignored because the instruction is squashed"); 2202315SN/A 2218733Sgeoffrey.blake@arm.com lsqMemOrderViolation 2222315SN/A .name(name() + ".memOrderViolation") 2232315SN/A .desc("Number of memory ordering violations"); 2242332SN/A 2258733Sgeoffrey.blake@arm.com lsqSquashedStores 2268733Sgeoffrey.blake@arm.com .name(name() + ".squashedStores") 2272732SN/A .desc("Number of stores squashed"); 2282315SN/A 2292315SN/A invAddrSwpfs 2302315SN/A .name(name() + ".invAddrSwpfs") 2312315SN/A .desc("Number of software prefetches ignored due to an invalid address"); 2322315SN/A 2332315SN/A lsqBlockedLoads 2342332SN/A .name(name() + ".blockedLoads") 2358733Sgeoffrey.blake@arm.com .desc("Number of blocked loads due to partial load-store forwarding"); 2368733Sgeoffrey.blake@arm.com 2372332SN/A lsqRescheduledLoads 2388733Sgeoffrey.blake@arm.com .name(name() + ".rescheduledLoads") 2398733Sgeoffrey.blake@arm.com .desc("Number of loads that were rescheduled"); 2408733Sgeoffrey.blake@arm.com 2412332SN/A lsqCacheBlocked 2429023Sgblack@eecs.umich.edu .name(name() + ".cacheBlocked") 2439023Sgblack@eecs.umich.edu .desc("Number of times an access to memory failed due to the cache being blocked"); 2448733Sgeoffrey.blake@arm.com} 2458733Sgeoffrey.blake@arm.com 2468733Sgeoffrey.blake@arm.comtemplate<class Impl> 24712749Sgiacomo.travaglini@arm.comvoid 24812749Sgiacomo.travaglini@arm.comLSQUnit<Impl>::setDcachePort(MasterPort *dcache_port) 24912749Sgiacomo.travaglini@arm.com{ 25012749Sgiacomo.travaglini@arm.com dcachePort = dcache_port; 2512679SN/A} 25212749Sgiacomo.travaglini@arm.com 25312749Sgiacomo.travaglini@arm.comtemplate<class Impl> 25412749Sgiacomo.travaglini@arm.comvoid 2552315SN/ALSQUnit<Impl>::drainSanityCheck() const 25612749Sgiacomo.travaglini@arm.com{ 25712749Sgiacomo.travaglini@arm.com for (int i = 0; i < loadQueue.capacity(); ++i) 2582315SN/A assert(!loadQueue[i].valid()); 2598733Sgeoffrey.blake@arm.com 2608733Sgeoffrey.blake@arm.com assert(storesToWB == 0); 2618733Sgeoffrey.blake@arm.com assert(!retryPkt); 2628733Sgeoffrey.blake@arm.com} 2638733Sgeoffrey.blake@arm.com 2648733Sgeoffrey.blake@arm.comtemplate<class Impl> 2658733Sgeoffrey.blake@arm.comvoid 2668733Sgeoffrey.blake@arm.comLSQUnit<Impl>::takeOverFrom() 2678733Sgeoffrey.blake@arm.com{ 2688733Sgeoffrey.blake@arm.com resetState(); 2692315SN/A} 2708733Sgeoffrey.blake@arm.com 2718733Sgeoffrey.blake@arm.comtemplate <class Impl> 2722315SN/Avoid 2738733Sgeoffrey.blake@arm.comLSQUnit<Impl>::insert(const DynInstPtr &inst) 2748733Sgeoffrey.blake@arm.com{ 2758733Sgeoffrey.blake@arm.com assert(inst->isMemRef()); 2768733Sgeoffrey.blake@arm.com 2778733Sgeoffrey.blake@arm.com assert(inst->isLoad() || inst->isStore()); 2788733Sgeoffrey.blake@arm.com 2798733Sgeoffrey.blake@arm.com if (inst->isLoad()) { 2808733Sgeoffrey.blake@arm.com insertLoad(inst); 2818733Sgeoffrey.blake@arm.com } else { 2828733Sgeoffrey.blake@arm.com insertStore(inst); 2838733Sgeoffrey.blake@arm.com } 28412749Sgiacomo.travaglini@arm.com 2858733Sgeoffrey.blake@arm.com inst->setInLSQ(); 2868733Sgeoffrey.blake@arm.com} 2878733Sgeoffrey.blake@arm.com 2888733Sgeoffrey.blake@arm.comtemplate <class Impl> 2898733Sgeoffrey.blake@arm.comvoid 2908733Sgeoffrey.blake@arm.comLSQUnit<Impl>::insertLoad(const DynInstPtr &load_inst) 2918733Sgeoffrey.blake@arm.com{ 2928733Sgeoffrey.blake@arm.com assert(!loadQueue.full()); 2938733Sgeoffrey.blake@arm.com assert(loads < loadQueue.capacity()); 2948733Sgeoffrey.blake@arm.com 2958733Sgeoffrey.blake@arm.com DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n", 2968733Sgeoffrey.blake@arm.com load_inst->pcState(), loadQueue.tail(), load_inst->seqNum); 2978733Sgeoffrey.blake@arm.com 2988733Sgeoffrey.blake@arm.com /* Grow the queue. */ 2998733Sgeoffrey.blake@arm.com loadQueue.advance_tail(); 3008733Sgeoffrey.blake@arm.com 3018733Sgeoffrey.blake@arm.com load_inst->sqIt = storeQueue.end(); 3028733Sgeoffrey.blake@arm.com 30310417Sandreas.hansson@arm.com assert(!loadQueue.back().valid()); 3048733Sgeoffrey.blake@arm.com loadQueue.back().set(load_inst); 3058733Sgeoffrey.blake@arm.com load_inst->lqIdx = loadQueue.tail(); 3068733Sgeoffrey.blake@arm.com load_inst->lqIt = loadQueue.getIterator(load_inst->lqIdx); 3078733Sgeoffrey.blake@arm.com 3089023Sgblack@eecs.umich.edu ++loads; 3098733Sgeoffrey.blake@arm.com} 3108733Sgeoffrey.blake@arm.com 3118733Sgeoffrey.blake@arm.comtemplate <class Impl> 3128733Sgeoffrey.blake@arm.comvoid 3139023Sgblack@eecs.umich.eduLSQUnit<Impl>::insertStore(const DynInstPtr& store_inst) 3148733Sgeoffrey.blake@arm.com{ 3159023Sgblack@eecs.umich.edu // Make sure it is not full before inserting an instruction. 3168733Sgeoffrey.blake@arm.com assert(!storeQueue.full()); 3178733Sgeoffrey.blake@arm.com assert(stores < storeQueue.capacity()); 3188733Sgeoffrey.blake@arm.com 3198733Sgeoffrey.blake@arm.com DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n", 3208733Sgeoffrey.blake@arm.com store_inst->pcState(), storeQueue.tail(), store_inst->seqNum); 3218733Sgeoffrey.blake@arm.com storeQueue.advance_tail(); 3228733Sgeoffrey.blake@arm.com 3238733Sgeoffrey.blake@arm.com store_inst->sqIdx = storeQueue.tail(); 3248733Sgeoffrey.blake@arm.com store_inst->lqIdx = loadQueue.moduloAdd(loadQueue.tail(), 1); 3258733Sgeoffrey.blake@arm.com store_inst->lqIt = loadQueue.end(); 3268733Sgeoffrey.blake@arm.com 3278733Sgeoffrey.blake@arm.com storeQueue.back().set(store_inst); 3288733Sgeoffrey.blake@arm.com 3298733Sgeoffrey.blake@arm.com ++stores; 3308733Sgeoffrey.blake@arm.com} 3318733Sgeoffrey.blake@arm.com 3328733Sgeoffrey.blake@arm.comtemplate <class Impl> 3338733Sgeoffrey.blake@arm.comtypename Impl::DynInstPtr 3348733Sgeoffrey.blake@arm.comLSQUnit<Impl>::getMemDepViolator() 3358733Sgeoffrey.blake@arm.com{ 3368733Sgeoffrey.blake@arm.com DynInstPtr temp = memDepViolator; 3372323SN/A 3382315SN/A memDepViolator = NULL; 3399023Sgblack@eecs.umich.edu 3409023Sgblack@eecs.umich.edu return temp; 3412315SN/A} 3428733Sgeoffrey.blake@arm.com 3438733Sgeoffrey.blake@arm.comtemplate <class Impl> 3448733Sgeoffrey.blake@arm.comunsigned 3452323SN/ALSQUnit<Impl>::numFreeLoadEntries() 3468733Sgeoffrey.blake@arm.com{ 3472679SN/A //LQ has an extra dummy entry to differentiate 3482323SN/A //empty/full conditions. Subtract 1 from the free entries. 3492323SN/A DPRINTF(LSQUnit, "LQ size: %d, #loads occupied: %d\n", 3508733Sgeoffrey.blake@arm.com 1 + loadQueue.capacity(), loads); 3512323SN/A return loadQueue.capacity() - loads; 3522315SN/A} 3538733Sgeoffrey.blake@arm.com 3548733Sgeoffrey.blake@arm.comtemplate <class Impl> 3558733Sgeoffrey.blake@arm.comunsigned 3562679SN/ALSQUnit<Impl>::numFreeStoreEntries() 3572315SN/A{ 3582315SN/A //SQ has an extra dummy entry to differentiate 3592315SN/A //empty/full conditions. Subtract 1 from the free entries. 3602315SN/A DPRINTF(LSQUnit, "SQ size: %d, #stores occupied: %d\n", 3618733Sgeoffrey.blake@arm.com 1 + storeQueue.capacity(), stores); 3628733Sgeoffrey.blake@arm.com return storeQueue.capacity() - stores; 3638733Sgeoffrey.blake@arm.com 3648733Sgeoffrey.blake@arm.com } 3658733Sgeoffrey.blake@arm.com 3668733Sgeoffrey.blake@arm.comtemplate <class Impl> 3678733Sgeoffrey.blake@arm.comvoid 3688733Sgeoffrey.blake@arm.comLSQUnit<Impl>::checkSnoop(PacketPtr pkt) 3698733Sgeoffrey.blake@arm.com{ 3708733Sgeoffrey.blake@arm.com // Should only ever get invalidations in here 3718733Sgeoffrey.blake@arm.com assert(pkt->isInvalidate()); 3728733Sgeoffrey.blake@arm.com 3738733Sgeoffrey.blake@arm.com DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr()); 3742315SN/A 3758733Sgeoffrey.blake@arm.com for (int x = 0; x < cpu->numContexts(); x++) { 3768733Sgeoffrey.blake@arm.com ThreadContext *tc = cpu->getContext(x); 3778733Sgeoffrey.blake@arm.com bool no_squash = cpu->thread[x]->noSquashFromTC; 3788733Sgeoffrey.blake@arm.com cpu->thread[x]->noSquashFromTC = true; 3792315SN/A TheISA::handleLockedSnoop(tc, pkt, cacheBlockMask); 3808733Sgeoffrey.blake@arm.com cpu->thread[x]->noSquashFromTC = no_squash; 3818733Sgeoffrey.blake@arm.com } 3828733Sgeoffrey.blake@arm.com 3838733Sgeoffrey.blake@arm.com if (loadQueue.empty()) 3848733Sgeoffrey.blake@arm.com return; 3858733Sgeoffrey.blake@arm.com 3868733Sgeoffrey.blake@arm.com auto iter = loadQueue.begin(); 3878733Sgeoffrey.blake@arm.com 3888733Sgeoffrey.blake@arm.com Addr invalidate_addr = pkt->getAddr() & cacheBlockMask; 3898733Sgeoffrey.blake@arm.com 3908733Sgeoffrey.blake@arm.com DynInstPtr ld_inst = iter->instruction(); 3912315SN/A assert(ld_inst); 3922315SN/A LSQRequest *req = iter->request(); 3932315SN/A 3948733Sgeoffrey.blake@arm.com // Check that this snoop didn't just invalidate our lock flag 3952315SN/A if (ld_inst->effAddrValid() && 3968887Sgeoffrey.blake@arm.com req->isCacheBlockHit(invalidate_addr, cacheBlockMask) 3978887Sgeoffrey.blake@arm.com && ld_inst->memReqFlags & Request::LLSC) 3988887Sgeoffrey.blake@arm.com TheISA::handleLockedSnoopHit(ld_inst.get()); 3998887Sgeoffrey.blake@arm.com 4008887Sgeoffrey.blake@arm.com bool force_squash = false; 4018887Sgeoffrey.blake@arm.com 4028887Sgeoffrey.blake@arm.com while (++iter != loadQueue.end()) { 4032315SN/A ld_inst = iter->instruction(); 4048733Sgeoffrey.blake@arm.com assert(ld_inst); 4052315SN/A req = iter->request(); 4062315SN/A if (!ld_inst->effAddrValid() || ld_inst->strictlyOrdered()) 4078793Sgblack@eecs.umich.edu continue; 4088793Sgblack@eecs.umich.edu 4098793Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "-- inst [sn:%lli] to pktAddr:%#x\n", 41010426Smitch.hayenga@arm.com ld_inst->seqNum, invalidate_addr); 4118793Sgblack@eecs.umich.edu 4128793Sgblack@eecs.umich.edu if (force_squash || 4138793Sgblack@eecs.umich.edu req->isCacheBlockHit(invalidate_addr, cacheBlockMask)) { 4148809Sgblack@eecs.umich.edu if (needsTSO) { 4158793Sgblack@eecs.umich.edu // If we have a TSO system, as all loads must be ordered with 4168793Sgblack@eecs.umich.edu // all other loads, this load as well as *all* subsequent loads 4178809Sgblack@eecs.umich.edu // need to be squashed to prevent possible load reordering. 4188793Sgblack@eecs.umich.edu force_squash = true; 4198793Sgblack@eecs.umich.edu } 4208809Sgblack@eecs.umich.edu if (ld_inst->possibleLoadViolation() || force_squash) { 4218809Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Conflicting load at addr %#x [sn:%lli]\n", 4228793Sgblack@eecs.umich.edu pkt->getAddr(), ld_inst->seqNum); 4232315SN/A 4242315SN/A // Mark the load for re-execution 4252332SN/A ld_inst->fault = std::make_shared<ReExec>(); 4262315SN/A } else { 4272315SN/A DPRINTF(LSQUnit, "HitExternal Snoop for addr %#x [sn:%lli]\n", 4282315SN/A pkt->getAddr(), ld_inst->seqNum); 4292332SN/A 4302332SN/A // Make sure that we don't lose a snoop hitting a LOCKED 4312315SN/A // address since the LOCK* flags don't get updated until 4322315SN/A // commit. 4332315SN/A if (ld_inst->memReqFlags & Request::LLSC) 4348733Sgeoffrey.blake@arm.com TheISA::handleLockedSnoopHit(ld_inst.get()); 4358733Sgeoffrey.blake@arm.com 4362315SN/A // If a older load checks this and it's true 4372315SN/A // then we might have missed the snoop 4382315SN/A // in which case we need to invalidate to be sure 4392315SN/A ld_inst->hitExternalSnoop(true); 4402315SN/A } 4412354SN/A } 4422315SN/A } 4432315SN/A return; 4448733Sgeoffrey.blake@arm.com} 4452315SN/A 4468733Sgeoffrey.blake@arm.comtemplate <class Impl> 4472315SN/AFault 4482315SN/ALSQUnit<Impl>::checkViolations(typename LoadQueue::iterator& loadIt, 4492315SN/A const DynInstPtr& inst) 4502315SN/A{ 4518733Sgeoffrey.blake@arm.com Addr inst_eff_addr1 = inst->effAddr >> depCheckShift; 4522315SN/A Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift; 4538733Sgeoffrey.blake@arm.com 4542315SN/A /** @todo in theory you only need to check an instruction that has executed 4552315SN/A * however, there isn't a good way in the pipeline at the moment to check 4562315SN/A * all instructions that will execute before the store writes back. Thus, 4578733Sgeoffrey.blake@arm.com * like the implementation that came before it, we're overly conservative. 4582315SN/A */ 45913429Srekai.gonzalezalberquilla@arm.com while (loadIt != loadQueue.end()) { 4602315SN/A DynInstPtr ld_inst = loadIt->instruction(); 4618733Sgeoffrey.blake@arm.com if (!ld_inst->effAddrValid() || ld_inst->strictlyOrdered()) { 4628733Sgeoffrey.blake@arm.com ++loadIt; 4638733Sgeoffrey.blake@arm.com continue; 4642315SN/A } 4652332SN/A 4667823Ssteve.reinhardt@amd.com Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift; 4672315SN/A Addr ld_eff_addr2 = 4682732SN/A (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift; 4692315SN/A 4702315SN/A if (inst_eff_addr2 >= ld_eff_addr1 && inst_eff_addr1 <= ld_eff_addr2) { 4712315SN/A if (inst->isLoad()) { 4729023Sgblack@eecs.umich.edu // If this load is to the same block as an external snoop 4739023Sgblack@eecs.umich.edu // invalidate that we've observed then the load needs to be 4749023Sgblack@eecs.umich.edu // squashed as it could have newer data 4752315SN/A if (ld_inst->hitExternalSnoop()) { 4762315SN/A if (!memDepViolator || 4772315SN/A ld_inst->seqNum < memDepViolator->seqNum) { 4788733Sgeoffrey.blake@arm.com DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] " 4792315SN/A "and [sn:%lli] at address %#x\n", 48013429Srekai.gonzalezalberquilla@arm.com inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 4812315SN/A memDepViolator = ld_inst; 48212107SRekai.GonzalezAlberquilla@arm.com 48312107SRekai.GonzalezAlberquilla@arm.com ++lsqMemOrderViolation; 4848733Sgeoffrey.blake@arm.com 4852732SN/A return std::make_shared<GenericISA::M5PanicFault>( 48612107SRekai.GonzalezAlberquilla@arm.com "Detected fault with inst [sn:%lli] and " 48712109SRekai.GonzalezAlberquilla@arm.com "[sn:%lli] at address %#x\n", 4888733Sgeoffrey.blake@arm.com inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 4898733Sgeoffrey.blake@arm.com } 4908733Sgeoffrey.blake@arm.com } 4918733Sgeoffrey.blake@arm.com 4928733Sgeoffrey.blake@arm.com // Otherwise, mark the load has a possible load violation 49312107SRekai.GonzalezAlberquilla@arm.com // and if we see a snoop before it's commited, we need to squash 4948733Sgeoffrey.blake@arm.com ld_inst->possibleLoadViolation(true); 4958733Sgeoffrey.blake@arm.com DPRINTF(LSQUnit, "Found possible load violation at addr: %#x" 4968733Sgeoffrey.blake@arm.com " between instructions [sn:%lli] and [sn:%lli]\n", 4978733Sgeoffrey.blake@arm.com inst_eff_addr1, inst->seqNum, ld_inst->seqNum); 49812107SRekai.GonzalezAlberquilla@arm.com } else { 4998733Sgeoffrey.blake@arm.com // A load/store incorrectly passed this store. 50012107SRekai.GonzalezAlberquilla@arm.com // Check if we already have a violator, or if it's newer 50112107SRekai.GonzalezAlberquilla@arm.com // squash and refetch. 5028733Sgeoffrey.blake@arm.com if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum) 5038733Sgeoffrey.blake@arm.com break; 5048733Sgeoffrey.blake@arm.com 50512109SRekai.GonzalezAlberquilla@arm.com DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and " 50612109SRekai.GonzalezAlberquilla@arm.com "[sn:%lli] at address %#x\n", 50712109SRekai.GonzalezAlberquilla@arm.com inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 50812109SRekai.GonzalezAlberquilla@arm.com memDepViolator = ld_inst; 5098733Sgeoffrey.blake@arm.com 5102732SN/A ++lsqMemOrderViolation; 5118733Sgeoffrey.blake@arm.com 5128733Sgeoffrey.blake@arm.com return std::make_shared<GenericISA::M5PanicFault>( 5138733Sgeoffrey.blake@arm.com "Detected fault with " 5148733Sgeoffrey.blake@arm.com "inst [sn:%lli] and [sn:%lli] at address %#x\n", 5158733Sgeoffrey.blake@arm.com inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5162732SN/A } 5172732SN/A } 51812107SRekai.GonzalezAlberquilla@arm.com 51912107SRekai.GonzalezAlberquilla@arm.com ++loadIt; 52012107SRekai.GonzalezAlberquilla@arm.com } 52112107SRekai.GonzalezAlberquilla@arm.com return NoFault; 52212107SRekai.GonzalezAlberquilla@arm.com} 52312107SRekai.GonzalezAlberquilla@arm.com 5242732SN/A 5252732SN/A 5262732SN/A 5272732SN/Atemplate <class Impl> 5282732SN/AFault 5292732SN/ALSQUnit<Impl>::executeLoad(const DynInstPtr &inst) 5308733Sgeoffrey.blake@arm.com{ 5318733Sgeoffrey.blake@arm.com using namespace TheISA; 5322732SN/A // Execute a specific load. 53310935Snilay@cs.wisc.edu Fault load_fault = NoFault; 5342732SN/A 5352732SN/A DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n", 5362315SN/A inst->pcState(), inst->seqNum); 5372315SN/A 5382315SN/A assert(!inst->isSquashed()); 5398733Sgeoffrey.blake@arm.com 5402332SN/A load_fault = inst->initiateAcc(); 5412332SN/A 5428733Sgeoffrey.blake@arm.com if (inst->isTranslationDelayed() && load_fault == NoFault) 5432732SN/A return load_fault; 5442315SN/A 5452315SN/A // If the instruction faulted or predicated false, then we need to send it 5462315SN/A // along to commit without the instruction completing. 5472315SN/A if (load_fault != NoFault || !inst->readPredicate()) { 5482315SN/A // Send this instruction to commit, also make sure iew stage 5492315SN/A // realizes there is activity. Mark it as executed unless it 5502315SN/A // is a strictly ordered load that needs to hit the head of 5512315SN/A // commit. 5522315SN/A if (!inst->readPredicate()) 5532315SN/A inst->forwardOldRegs(); 5542315SN/A DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", 5554172Ssaidi@eecs.umich.edu inst->seqNum, 5564172Ssaidi@eecs.umich.edu (load_fault != NoFault ? "fault" : "predication")); 5572332SN/A if (!(inst->hasRequest() && inst->strictlyOrdered()) || 5582332SN/A inst->isAtCommit()) { 5597823Ssteve.reinhardt@amd.com inst->setExecuted(); 5604172Ssaidi@eecs.umich.edu } 5614172Ssaidi@eecs.umich.edu iewStage->instToCommit(inst); 5622732SN/A iewStage->activityThisCycle(); 5632315SN/A } else { 5642315SN/A if (inst->effAddrValid()) { 5652315SN/A auto it = inst->lqIt; 5662315SN/A ++it; 5678733Sgeoffrey.blake@arm.com 5688733Sgeoffrey.blake@arm.com if (checkLoads) 5698733Sgeoffrey.blake@arm.com return checkViolations(it, inst); 5708733Sgeoffrey.blake@arm.com } 5718733Sgeoffrey.blake@arm.com } 5722315SN/A 5738733Sgeoffrey.blake@arm.com return load_fault; 5742315SN/A} 5752354SN/A 5768733Sgeoffrey.blake@arm.comtemplate <class Impl> 5778733Sgeoffrey.blake@arm.comFault 5788733Sgeoffrey.blake@arm.comLSQUnit<Impl>::executeStore(const DynInstPtr &store_inst) 5798733Sgeoffrey.blake@arm.com{ 5808733Sgeoffrey.blake@arm.com using namespace TheISA; 5819382SAli.Saidi@ARM.com // Make sure that a store exists. 5829382SAli.Saidi@ARM.com assert(stores != 0); 5838733Sgeoffrey.blake@arm.com 5842354SN/A int store_idx = store_inst->sqIdx; 5853126Sktlim@umich.edu 5869382SAli.Saidi@ARM.com DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n", 5878733Sgeoffrey.blake@arm.com store_inst->pcState(), store_inst->seqNum); 5888733Sgeoffrey.blake@arm.com 5898733Sgeoffrey.blake@arm.com assert(!store_inst->isSquashed()); 5902356SN/A 5918733Sgeoffrey.blake@arm.com // Check the recently completed loads to see if any match this store's 5922354SN/A // address. If so, then we have a memory ordering violation. 5933126Sktlim@umich.edu typename LoadQueue::iterator loadIt = store_inst->lqIt; 5942315SN/A 5952315SN/A Fault store_fault = store_inst->initiateAcc(); 5968733Sgeoffrey.blake@arm.com 5972315SN/A if (store_inst->isTranslationDelayed() && 59813429Srekai.gonzalezalberquilla@arm.com store_fault == NoFault) 59913429Srekai.gonzalezalberquilla@arm.com return store_fault; 6002732SN/A 6018733Sgeoffrey.blake@arm.com if (!store_inst->readPredicate()) { 6028733Sgeoffrey.blake@arm.com DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", 6038733Sgeoffrey.blake@arm.com store_inst->seqNum); 60412106SRekai.GonzalezAlberquilla@arm.com store_inst->forwardOldRegs(); 60512106SRekai.GonzalezAlberquilla@arm.com return store_fault; 6069913Ssteve.reinhardt@amd.com } 60712107SRekai.GonzalezAlberquilla@arm.com 60812107SRekai.GonzalezAlberquilla@arm.com if (storeQueue[store_idx].size() == 0) { 6099913Ssteve.reinhardt@amd.com DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", 6109913Ssteve.reinhardt@amd.com store_inst->pcState(), store_inst->seqNum); 61112107SRekai.GonzalezAlberquilla@arm.com 61213611Sgabeblack@google.com return store_fault; 6139913Ssteve.reinhardt@amd.com } 61412109SRekai.GonzalezAlberquilla@arm.com 61512109SRekai.GonzalezAlberquilla@arm.com assert(store_fault == NoFault); 61612109SRekai.GonzalezAlberquilla@arm.com 61712109SRekai.GonzalezAlberquilla@arm.com if (store_inst->isStoreConditional()) { 61812109SRekai.GonzalezAlberquilla@arm.com // Store conditionals need to set themselves as able to 61912109SRekai.GonzalezAlberquilla@arm.com // writeback if we haven't had a fault by here. 62012109SRekai.GonzalezAlberquilla@arm.com storeQueue[store_idx].canWB() = true; 62112109SRekai.GonzalezAlberquilla@arm.com 62212109SRekai.GonzalezAlberquilla@arm.com ++storesToWB; 6239920Syasuko.eckert@amd.com } 62412107SRekai.GonzalezAlberquilla@arm.com 62512107SRekai.GonzalezAlberquilla@arm.com return checkViolations(loadIt, store_inst); 6269920Syasuko.eckert@amd.com 6279913Ssteve.reinhardt@amd.com} 62812107SRekai.GonzalezAlberquilla@arm.com 62912107SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 6309913Ssteve.reinhardt@amd.comvoid 63112109SRekai.GonzalezAlberquilla@arm.comLSQUnit<Impl>::commitLoad() 63212109SRekai.GonzalezAlberquilla@arm.com{ 6338733Sgeoffrey.blake@arm.com assert(loadQueue.front().valid()); 6348733Sgeoffrey.blake@arm.com 6358733Sgeoffrey.blake@arm.com DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n", 63612107SRekai.GonzalezAlberquilla@arm.com loadQueue.front().instruction()->pcState()); 6378733Sgeoffrey.blake@arm.com 63812106SRekai.GonzalezAlberquilla@arm.com loadQueue.front().clear(); 63912107SRekai.GonzalezAlberquilla@arm.com loadQueue.pop_front(); 64012106SRekai.GonzalezAlberquilla@arm.com 64110935Snilay@cs.wisc.edu --loads; 64212107SRekai.GonzalezAlberquilla@arm.com} 64312107SRekai.GonzalezAlberquilla@arm.com 64410935Snilay@cs.wisc.edutemplate <class Impl> 64510935Snilay@cs.wisc.eduvoid 64612107SRekai.GonzalezAlberquilla@arm.comLSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 64713611Sgabeblack@google.com{ 64810935Snilay@cs.wisc.edu assert(loads == 0 || loadQueue.front().valid()); 64912109SRekai.GonzalezAlberquilla@arm.com 65012109SRekai.GonzalezAlberquilla@arm.com while (loads != 0 && loadQueue.front().instruction()->seqNum 65112109SRekai.GonzalezAlberquilla@arm.com <= youngest_inst) { 65212109SRekai.GonzalezAlberquilla@arm.com commitLoad(); 65312109SRekai.GonzalezAlberquilla@arm.com } 65412109SRekai.GonzalezAlberquilla@arm.com} 65512109SRekai.GonzalezAlberquilla@arm.com 65612109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 65710935Snilay@cs.wisc.eduvoid 65812107SRekai.GonzalezAlberquilla@arm.comLSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 65912107SRekai.GonzalezAlberquilla@arm.com{ 66010935Snilay@cs.wisc.edu assert(stores == 0 || storeQueue.front().valid()); 66110935Snilay@cs.wisc.edu 66212107SRekai.GonzalezAlberquilla@arm.com /* Forward iterate the store queue (age order). */ 66310935Snilay@cs.wisc.edu for (auto& x : storeQueue) { 66412107SRekai.GonzalezAlberquilla@arm.com assert(x.valid()); 66510935Snilay@cs.wisc.edu // Mark any stores that are now committed and have not yet 6669913Ssteve.reinhardt@amd.com // been marked as able to write back. 66712109SRekai.GonzalezAlberquilla@arm.com if (!x.canWB()) { 66812109SRekai.GonzalezAlberquilla@arm.com if (x.instruction()->seqNum > youngest_inst) { 6699913Ssteve.reinhardt@amd.com break; 6702732SN/A } 6712732SN/A DPRINTF(LSQUnit, "Marking store as able to write back, PC " 6722732SN/A "%s [sn:%lli]\n", 6738733Sgeoffrey.blake@arm.com x.instruction()->pcState(), 6742732SN/A x.instruction()->seqNum); 67513429Srekai.gonzalezalberquilla@arm.com 6762732SN/A x.canWB() = true; 6772732SN/A 6788733Sgeoffrey.blake@arm.com ++storesToWB; 6792732SN/A } 6808733Sgeoffrey.blake@arm.com } 6818733Sgeoffrey.blake@arm.com} 6822732SN/A 6832732SN/Atemplate <class Impl> 6842732SN/Avoid 6852732SN/ALSQUnit<Impl>::writebackBlockedStore() 6862732SN/A{ 6872732SN/A assert(isStoreBlocked); 6882732SN/A storeWBIt->request()->sendPacketToCache(); 6898733Sgeoffrey.blake@arm.com if (storeWBIt->request()->isSent()){ 6902732SN/A storePostSend(); 6918733Sgeoffrey.blake@arm.com } 6922315SN/A} 6932315SN/A 6942315SN/Atemplate <class Impl> 6952315SN/Avoid 6962315SN/ALSQUnit<Impl>::writebackStores() 6972315SN/A{ 6982315SN/A if (isStoreBlocked) { 6992315SN/A DPRINTF(LSQUnit, "Writing back blocked store\n"); 7002315SN/A writebackBlockedStore(); 7012315SN/A } 7022315SN/A 7032315SN/A while (storesToWB > 0 && 7048733Sgeoffrey.blake@arm.com storeWBIt.dereferenceable() && 7052315SN/A storeWBIt->valid() && 7068733Sgeoffrey.blake@arm.com storeWBIt->canWB() && 7072315SN/A ((!needsTSO) || (!storeInFlight)) && 7082315SN/A lsq->storePortAvailable()) { 7092315SN/A 7102315SN/A if (isStoreBlocked) { 7112315SN/A DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 7122315SN/A " is blocked!\n"); 7132315SN/A break; 7142315SN/A } 7152315SN/A 7162315SN/A // Store didn't write any data so no need to write it back to 7172315SN/A // memory. 7189944Smatt.horsnell@ARM.com if (storeWBIt->size() == 0) { 7199944Smatt.horsnell@ARM.com /* It is important that the preincrement happens at (or before) 720 * the call, as the the code of completeStore checks 721 * storeWBIt. */ 722 completeStore(storeWBIt++); 723 continue; 724 } 725 726 if (storeWBIt->instruction()->isDataPrefetch()) { 727 storeWBIt++; 728 continue; 729 } 730 731 assert(storeWBIt->hasRequest()); 732 assert(!storeWBIt->committed()); 733 734 DynInstPtr inst = storeWBIt->instruction(); 735 LSQRequest* req = storeWBIt->request(); 736 storeWBIt->committed() = true; 737 738 assert(!inst->memData); 739 inst->memData = new uint8_t[req->_size]; 740 741 if (storeWBIt->isAllZeros()) 742 memset(inst->memData, 0, req->_size); 743 else 744 memcpy(inst->memData, storeWBIt->data(), req->_size); 745 746 747 if (req->senderState() == nullptr) { 748 SQSenderState *state = new SQSenderState(storeWBIt); 749 state->isLoad = false; 750 state->needWB = false; 751 state->inst = inst; 752 753 req->senderState(state); 754 if (inst->isStoreConditional()) { 755 /* Only store conditionals need a writeback. */ 756 state->needWB = true; 757 } 758 } 759 req->buildPackets(); 760 761 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s " 762 "to Addr:%#x, data:%#x [sn:%lli]\n", 763 storeWBIt.idx(), inst->pcState(), 764 req->request()->getPaddr(), (int)*(inst->memData), 765 inst->seqNum); 766 767 // @todo: Remove this SC hack once the memory system handles it. 768 if (inst->isStoreConditional()) { 769 // Disable recording the result temporarily. Writing to 770 // misc regs normally updates the result, but this is not 771 // the desired behavior when handling store conditionals. 772 inst->recordResult(false); 773 bool success = TheISA::handleLockedWrite(inst.get(), 774 req->request(), cacheBlockMask); 775 inst->recordResult(true); 776 req->packetSent(); 777 778 if (!success) { 779 req->complete(); 780 // Instantly complete this store. 781 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 782 "Instantly completing it.\n", 783 inst->seqNum); 784 PacketPtr new_pkt = new Packet(*req->packet()); 785 WritebackEvent *wb = new WritebackEvent(inst, 786 new_pkt, this); 787 cpu->schedule(wb, curTick() + 1); 788 completeStore(storeWBIt); 789 if (!storeQueue.empty()) 790 storeWBIt++; 791 else 792 storeWBIt = storeQueue.end(); 793 continue; 794 } 795 } 796 797 if (req->request()->isMmappedIpr()) { 798 assert(!inst->isStoreConditional()); 799 ThreadContext *thread = cpu->tcBase(lsqID); 800 PacketPtr main_pkt = new Packet(req->mainRequest(), 801 MemCmd::WriteReq); 802 main_pkt->dataStatic(inst->memData); 803 req->handleIprWrite(thread, main_pkt); 804 delete main_pkt; 805 completeStore(storeWBIt); 806 storeWBIt++; 807 continue; 808 } 809 /* Send to cache */ 810 req->sendPacketToCache(); 811 812 /* If successful, do the post send */ 813 if (req->isSent()) { 814 storePostSend(); 815 } else { 816 DPRINTF(LSQUnit, "D-Cache became blocked when writing [sn:%lli], " 817 "will retry later\n", 818 inst->seqNum); 819 } 820 } 821 assert(stores >= 0 && storesToWB >= 0); 822} 823 824template <class Impl> 825void 826LSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 827{ 828 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 829 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 830 831 while (loads != 0 && 832 loadQueue.back().instruction()->seqNum > squashed_num) { 833 DPRINTF(LSQUnit,"Load Instruction PC %s squashed, " 834 "[sn:%lli]\n", 835 loadQueue.back().instruction()->pcState(), 836 loadQueue.back().instruction()->seqNum); 837 838 if (isStalled() && loadQueue.tail() == stallingLoadIdx) { 839 stalled = false; 840 stallingStoreIsn = 0; 841 stallingLoadIdx = 0; 842 } 843 844 // Clear the smart pointer to make sure it is decremented. 845 loadQueue.back().instruction()->setSquashed(); 846 loadQueue.back().clear(); 847 848 --loads; 849 850 loadQueue.pop_back(); 851 ++lsqSquashedLoads; 852 } 853 854 if (memDepViolator && squashed_num < memDepViolator->seqNum) { 855 memDepViolator = NULL; 856 } 857 858 while (stores != 0 && 859 storeQueue.back().instruction()->seqNum > squashed_num) { 860 // Instructions marked as can WB are already committed. 861 if (storeQueue.back().canWB()) { 862 break; 863 } 864 865 DPRINTF(LSQUnit,"Store Instruction PC %s squashed, " 866 "idx:%i [sn:%lli]\n", 867 storeQueue.back().instruction()->pcState(), 868 storeQueue.tail(), storeQueue.back().instruction()->seqNum); 869 870 // I don't think this can happen. It should have been cleared 871 // by the stalling load. 872 if (isStalled() && 873 storeQueue.back().instruction()->seqNum == stallingStoreIsn) { 874 panic("Is stalled should have been cleared by stalling load!\n"); 875 stalled = false; 876 stallingStoreIsn = 0; 877 } 878 879 // Clear the smart pointer to make sure it is decremented. 880 storeQueue.back().instruction()->setSquashed(); 881 882 // Must delete request now that it wasn't handed off to 883 // memory. This is quite ugly. @todo: Figure out the proper 884 // place to really handle request deletes. 885 storeQueue.back().clear(); 886 --stores; 887 888 storeQueue.pop_back(); 889 ++lsqSquashedStores; 890 } 891} 892 893template <class Impl> 894void 895LSQUnit<Impl>::storePostSend() 896{ 897 if (isStalled() && 898 storeWBIt->instruction()->seqNum == stallingStoreIsn) { 899 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 900 "load idx:%i\n", 901 stallingStoreIsn, stallingLoadIdx); 902 stalled = false; 903 stallingStoreIsn = 0; 904 iewStage->replayMemInst(loadQueue[stallingLoadIdx].instruction()); 905 } 906 907 if (!storeWBIt->instruction()->isStoreConditional()) { 908 // The store is basically completed at this time. This 909 // only works so long as the checker doesn't try to 910 // verify the value in memory for stores. 911 storeWBIt->instruction()->setCompleted(); 912 913 if (cpu->checker) { 914 cpu->checker->verify(storeWBIt->instruction()); 915 } 916 } 917 918 if (needsTSO) { 919 storeInFlight = true; 920 } 921 922 storeWBIt++; 923} 924 925template <class Impl> 926void 927LSQUnit<Impl>::writeback(const DynInstPtr &inst, PacketPtr pkt) 928{ 929 iewStage->wakeCPU(); 930 931 // Squashed instructions do not need to complete their access. 932 if (inst->isSquashed()) { 933 assert(!inst->isStore()); 934 ++lsqIgnoredResponses; 935 return; 936 } 937 938 if (!inst->isExecuted()) { 939 inst->setExecuted(); 940 941 if (inst->fault == NoFault) { 942 // Complete access to copy data to proper place. 943 inst->completeAcc(pkt); 944 } else { 945 // If the instruction has an outstanding fault, we cannot complete 946 // the access as this discards the current fault. 947 948 // If we have an outstanding fault, the fault should only be of 949 // type ReExec. 950 assert(dynamic_cast<ReExec*>(inst->fault.get()) != nullptr); 951 952 DPRINTF(LSQUnit, "Not completing instruction [sn:%lli] access " 953 "due to pending fault.\n", inst->seqNum); 954 } 955 } 956 957 // Need to insert instruction into queue to commit 958 iewStage->instToCommit(inst); 959 960 iewStage->activityThisCycle(); 961 962 // see if this load changed the PC 963 iewStage->checkMisprediction(inst); 964} 965 966template <class Impl> 967void 968LSQUnit<Impl>::completeStore(typename StoreQueue::iterator store_idx) 969{ 970 assert(store_idx->valid()); 971 store_idx->completed() = true; 972 --storesToWB; 973 // A bit conservative because a store completion may not free up entries, 974 // but hopefully avoids two store completions in one cycle from making 975 // the CPU tick twice. 976 cpu->wakeCPU(); 977 cpu->activityThisCycle(); 978 979 /* We 'need' a copy here because we may clear the entry from the 980 * store queue. */ 981 DynInstPtr store_inst = store_idx->instruction(); 982 if (store_idx == storeQueue.begin()) { 983 do { 984 storeQueue.front().clear(); 985 storeQueue.pop_front(); 986 --stores; 987 } while (storeQueue.front().completed() && 988 !storeQueue.empty()); 989 990 iewStage->updateLSQNextCycle = true; 991 } 992 993 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 994 "idx:%i\n", 995 store_inst->seqNum, store_idx.idx() - 1, storeQueue.head() - 1); 996 997#if TRACING_ON 998 if (DTRACE(O3PipeView)) { 999 store_idx->instruction()->storeTick = 1000 curTick() - store_idx->instruction()->fetchTick; 1001 } 1002#endif 1003 1004 if (isStalled() && 1005 store_inst->seqNum == stallingStoreIsn) { 1006 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 1007 "load idx:%i\n", 1008 stallingStoreIsn, stallingLoadIdx); 1009 stalled = false; 1010 stallingStoreIsn = 0; 1011 iewStage->replayMemInst(loadQueue[stallingLoadIdx].instruction()); 1012 } 1013 1014 store_inst->setCompleted(); 1015 1016 if (needsTSO) { 1017 storeInFlight = false; 1018 } 1019 1020 // Tell the checker we've completed this instruction. Some stores 1021 // may get reported twice to the checker, but the checker can 1022 // handle that case. 1023 // Store conditionals cannot be sent to the checker yet, they have 1024 // to update the misc registers first which should take place 1025 // when they commit 1026 if (cpu->checker && !store_inst->isStoreConditional()) { 1027 cpu->checker->verify(store_inst); 1028 } 1029} 1030 1031template <class Impl> 1032bool 1033LSQUnit<Impl>::trySendPacket(bool isLoad, PacketPtr data_pkt) 1034{ 1035 bool ret = true; 1036 bool cache_got_blocked = false; 1037 1038 auto state = dynamic_cast<LSQSenderState*>(data_pkt->senderState); 1039 1040 if (!lsq->cacheBlocked() && (isLoad || lsq->storePortAvailable())) { 1041 if (!dcachePort->sendTimingReq(data_pkt)) { 1042 ret = false; 1043 cache_got_blocked = true; 1044 } 1045 } else { 1046 ret = false; 1047 } 1048 1049 if (ret) { 1050 if (!isLoad) { 1051 lsq->storePortBusy(); 1052 isStoreBlocked = false; 1053 } 1054 state->outstanding++; 1055 state->request()->packetSent(); 1056 } else { 1057 if (cache_got_blocked) { 1058 lsq->cacheBlocked(true); 1059 ++lsqCacheBlocked; 1060 } 1061 if (!isLoad) { 1062 assert(state->request() == storeWBIt->request()); 1063 isStoreBlocked = true; 1064 } 1065 state->request()->packetNotSent(); 1066 } 1067 1068 return ret; 1069} 1070 1071template <class Impl> 1072void 1073LSQUnit<Impl>::recvRetry() 1074{ 1075 if (isStoreBlocked) { 1076 DPRINTF(LSQUnit, "Receiving retry: blocked store\n"); 1077 writebackBlockedStore(); 1078 } 1079} 1080 1081template <class Impl> 1082void 1083LSQUnit<Impl>::dumpInsts() const 1084{ 1085 cprintf("Load store queue: Dumping instructions.\n"); 1086 cprintf("Load queue size: %i\n", loads); 1087 cprintf("Load queue: "); 1088 1089 for (const auto& e: loadQueue) { 1090 const DynInstPtr &inst(e.instruction()); 1091 cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum); 1092 } 1093 cprintf("\n"); 1094 1095 cprintf("Store queue size: %i\n", stores); 1096 cprintf("Store queue: "); 1097 1098 for (const auto& e: storeQueue) { 1099 const DynInstPtr &inst(e.instruction()); 1100 cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum); 1101 } 1102 1103 cprintf("\n"); 1104} 1105 1106template <class Impl> 1107unsigned int 1108LSQUnit<Impl>::cacheLineSize() 1109{ 1110 return cpu->cacheLineSize(); 1111} 1112 1113#endif//__CPU_O3_LSQ_UNIT_IMPL_HH__ 1114