lsq_unit_impl.hh revision 11356:a80884911971
11689SN/A 29444SAndreas.Sandberg@ARM.com/* 37854SAli.Saidi@ARM.com * Copyright (c) 2010-2014 ARM Limited 47854SAli.Saidi@ARM.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 57854SAli.Saidi@ARM.com * All rights reserved 67854SAli.Saidi@ARM.com * 77854SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 87854SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 97854SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 107854SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 117854SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 127854SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 137854SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 142329SN/A * modified or unmodified, in source code or in binary form. 151689SN/A * 161689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 171689SN/A * All rights reserved. 181689SN/A * 191689SN/A * Redistribution and use in source and binary forms, with or without 201689SN/A * modification, are permitted provided that the following conditions are 211689SN/A * met: redistributions of source code must retain the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer; 231689SN/A * redistributions in binary form must reproduce the above copyright 241689SN/A * notice, this list of conditions and the following disclaimer in the 251689SN/A * documentation and/or other materials provided with the distribution; 261689SN/A * neither the name of the copyright holders nor the names of its 271689SN/A * contributors may be used to endorse or promote products derived from 281689SN/A * this software without specific prior written permission. 291689SN/A * 301689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 311689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 321689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 331689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 341689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 351689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 361689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 371689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 381689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 392665Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 402665Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412935Sksewell@umich.edu * 421689SN/A * Authors: Kevin Lim 431689SN/A * Korey Sewell 441060SN/A */ 451060SN/A 463773Sgblack@eecs.umich.edu#ifndef __CPU_O3_LSQ_UNIT_IMPL_HH__ 476329Sgblack@eecs.umich.edu#define __CPU_O3_LSQ_UNIT_IMPL_HH__ 486658Snate@binkert.org 491717SN/A#include "arch/generic/debugfaults.hh" 508232Snate@binkert.org#include "arch/locked_mem.hh" 518232Snate@binkert.org#include "base/str.hh" 525529Snate@binkert.org#include "config/the_isa.hh" 531060SN/A#include "cpu/checker/cpu.hh" 546221Snate@binkert.org#include "cpu/o3/lsq.hh" 556221Snate@binkert.org#include "cpu/o3/lsq_unit.hh" 561061SN/A#include "debug/Activity.hh" 575529Snate@binkert.org#include "debug/IEW.hh" 584329Sktlim@umich.edu#include "debug/LSQUnit.hh" 594329Sktlim@umich.edu#include "debug/O3PipeView.hh" 602292SN/A#include "mem/packet.hh" 612292SN/A#include "mem/request.hh" 622292SN/A 632292SN/Atemplate<class Impl> 645529Snate@binkert.orgLSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 652361SN/A LSQUnit *lsq_ptr) 661060SN/A : Event(Default_Pri, AutoDelete), 672292SN/A inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 688907Slukefahr@umich.edu{ 692292SN/A} 702292SN/A 712292SN/Atemplate<class Impl> 722292SN/Avoid 732292SN/ALSQUnit<Impl>::WritebackEvent::process() 742292SN/A{ 752292SN/A assert(!lsqPtr->cpu->switchedOut()); 761060SN/A 771060SN/A lsqPtr->writeback(inst, pkt); 781061SN/A 791060SN/A if (pkt->senderState) 802292SN/A delete pkt->senderState; 811062SN/A 821062SN/A delete pkt->req; 838240Snate@binkert.org delete pkt; 841062SN/A} 851062SN/A 861062SN/Atemplate<class Impl> 878240Snate@binkert.orgconst char * 881062SN/ALSQUnit<Impl>::WritebackEvent::description() const 891062SN/A{ 901062SN/A return "Store writeback"; 918240Snate@binkert.org} 921062SN/A 931062SN/Atemplate<class Impl> 942301SN/Avoid 958240Snate@binkert.orgLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 962301SN/A{ 972301SN/A LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 982292SN/A DynInstPtr inst = state->inst; 998240Snate@binkert.org DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum); 1002292SN/A DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum); 1012292SN/A 1021062SN/A if (state->cacheBlocked) { 1038240Snate@binkert.org // This is the first half of a previous split load, 1041062SN/A // where the 2nd half blocked, ignore this response 1051062SN/A DPRINTF(IEW, "[sn:%lli]: Response from first half of earlier " 1061062SN/A "blocked split load recieved. Ignoring.\n", inst->seqNum); 1078240Snate@binkert.org delete state; 1081062SN/A return; 1091062SN/A } 1101062SN/A 1118240Snate@binkert.org // If this is a split access, wait until all packets are received. 1121062SN/A if (TheISA::HasUnalignedMemAcc && !state->complete()) { 1131062SN/A return; 1141062SN/A } 1158240Snate@binkert.org 1162292SN/A assert(!cpu->switchedOut()); 1171062SN/A if (!inst->isSquashed()) { 1181062SN/A if (!state->noWB) { 1198240Snate@binkert.org if (!TheISA::HasUnalignedMemAcc || !state->isSplit || 1202292SN/A !state->isLoad) { 1211062SN/A writeback(inst, pkt); 1222292SN/A } else { 1238240Snate@binkert.org writeback(inst, state->mainPkt); 1242292SN/A } 1252292SN/A } 1261062SN/A 1278240Snate@binkert.org if (inst->isStore()) { 1281062SN/A completeStore(state->idx); 1291062SN/A } 1301062SN/A } 1318240Snate@binkert.org 1321062SN/A if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) { 1331062SN/A delete state->mainPkt->req; 1341062SN/A delete state->mainPkt; 1358240Snate@binkert.org } 1361062SN/A 1371062SN/A pkt->req->setAccessLatency(); 1381062SN/A cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt)); 1398240Snate@binkert.org 1401062SN/A delete state; 1411062SN/A} 1421062SN/A 1438240Snate@binkert.orgtemplate <class Impl> 1441062SN/ALSQUnit<Impl>::LSQUnit() 1451062SN/A : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false), 1462301SN/A isStoreBlocked(false), storeInFlight(false), hasPendingPkt(false), 1478240Snate@binkert.org pendingPkt(nullptr) 1482301SN/A{ 1492301SN/A} 1502301SN/A 1512301SN/Atemplate<class Impl> 1528240Snate@binkert.orgvoid 1532301SN/ALSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 1542301SN/A LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 1552301SN/A unsigned id) 1562307SN/A{ 1578240Snate@binkert.org cpu = cpu_ptr; 1582307SN/A iewStage = iew_ptr; 1592307SN/A 1602307SN/A lsq = lsq_ptr; 1617897Shestness@cs.utexas.edu 1628240Snate@binkert.org lsqID = id; 1637897Shestness@cs.utexas.edu 1647897Shestness@cs.utexas.edu DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 1657897Shestness@cs.utexas.edu 1668240Snate@binkert.org // Add 1 for the sentinel entry (they are circular queues). 1677897Shestness@cs.utexas.edu LQEntries = maxLQEntries + 1; 1687897Shestness@cs.utexas.edu SQEntries = maxSQEntries + 1; 1691062SN/A 1701062SN/A //Due to uint8_t index in LSQSenderState 1711062SN/A assert(LQEntries <= 256); 1721062SN/A assert(SQEntries <= 256); 1732292SN/A 1741060SN/A loadQueue.resize(LQEntries); 1751060SN/A storeQueue.resize(SQEntries); 1761060SN/A 1771060SN/A depCheckShift = params->LSQDepCheckShift; 1781060SN/A checkLoads = params->LSQCheckLoads; 1791060SN/A cachePorts = params->cachePorts; 1801060SN/A needsTSO = params->needsTSO; 1811060SN/A 1821060SN/A resetState(); 1831060SN/A} 1841060SN/A 1851060SN/A 1861060SN/Atemplate<class Impl> 1871061SN/Avoid 1881060SN/ALSQUnit<Impl>::resetState() 1892292SN/A{ 1901060SN/A loads = stores = storesToWB = 0; 1911060SN/A 1921060SN/A loadHead = loadTail = 0; 1931060SN/A 1941060SN/A storeHead = storeWBIdx = storeTail = 0; 1951060SN/A 1961060SN/A usedPorts = 0; 1971061SN/A 1981060SN/A retryPkt = NULL; 1992292SN/A memDepViolator = NULL; 2001060SN/A 2011060SN/A stalled = false; 2021060SN/A 2031060SN/A cacheBlockMask = ~(cpu->cacheLineSize() - 1); 2041060SN/A} 2051060SN/A 2061060SN/Atemplate<class Impl> 2071061SN/Astd::string 2081060SN/ALSQUnit<Impl>::name() const 2099427SAndreas.Sandberg@ARM.com{ 2101060SN/A if (Impl::MaxThreads == 1) { 2119444SAndreas.Sandberg@ARM.com return iewStage->name() + ".lsq"; 2129444SAndreas.Sandberg@ARM.com } else { 2139444SAndreas.Sandberg@ARM.com return iewStage->name() + ".lsq.thread" + std::to_string(lsqID); 2149444SAndreas.Sandberg@ARM.com } 2159444SAndreas.Sandberg@ARM.com} 2169444SAndreas.Sandberg@ARM.com 2179444SAndreas.Sandberg@ARM.comtemplate<class Impl> 2189444SAndreas.Sandberg@ARM.comvoid 2199444SAndreas.Sandberg@ARM.comLSQUnit<Impl>::regStats() 2209444SAndreas.Sandberg@ARM.com{ 2219444SAndreas.Sandberg@ARM.com lsqForwLoads 2229444SAndreas.Sandberg@ARM.com .name(name() + ".forwLoads") 2232329SN/A .desc("Number of loads that had data forwarded from stores"); 2246221Snate@binkert.org 2259444SAndreas.Sandberg@ARM.com invAddrLoads 2269444SAndreas.Sandberg@ARM.com .name(name() + ".invAddrLoads") 2272292SN/A .desc("Number of loads ignored due to an invalid address"); 2282292SN/A 2292292SN/A lsqSquashedLoads 2302292SN/A .name(name() + ".squashedLoads") 2319444SAndreas.Sandberg@ARM.com .desc("Number of loads squashed"); 2329444SAndreas.Sandberg@ARM.com 2339444SAndreas.Sandberg@ARM.com lsqIgnoredResponses 2349444SAndreas.Sandberg@ARM.com .name(name() + ".ignoredResponses") 2359444SAndreas.Sandberg@ARM.com .desc("Number of memory responses ignored because the instruction is squashed"); 2369444SAndreas.Sandberg@ARM.com 2379444SAndreas.Sandberg@ARM.com lsqMemOrderViolation 2389444SAndreas.Sandberg@ARM.com .name(name() + ".memOrderViolation") 2392292SN/A .desc("Number of memory ordering violations"); 2401060SN/A 2411060SN/A lsqSquashedStores 2422292SN/A .name(name() + ".squashedStores") 2432292SN/A .desc("Number of stores squashed"); 2446221Snate@binkert.org 2452292SN/A invAddrSwpfs 2462292SN/A .name(name() + ".invAddrSwpfs") 2472292SN/A .desc("Number of software prefetches ignored due to an invalid address"); 2482292SN/A 2492292SN/A lsqBlockedLoads 2501061SN/A .name(name() + ".blockedLoads") 2511060SN/A .desc("Number of blocked loads due to partial load-store forwarding"); 2522292SN/A 2531060SN/A lsqRescheduledLoads 2546221Snate@binkert.org .name(name() + ".rescheduledLoads") 2556221Snate@binkert.org .desc("Number of loads that were rescheduled"); 2561060SN/A 2571060SN/A lsqCacheBlocked 2581061SN/A .name(name() + ".cacheBlocked") 2591060SN/A .desc("Number of times an access to memory failed due to the cache being blocked"); 2602292SN/A} 2611060SN/A 2622292SN/Atemplate<class Impl> 2632292SN/Avoid 2641060SN/ALSQUnit<Impl>::setDcachePort(MasterPort *dcache_port) 2652292SN/A{ 2662292SN/A dcachePort = dcache_port; 2672292SN/A} 2682292SN/A 2692292SN/Atemplate<class Impl> 2701060SN/Avoid 2711060SN/ALSQUnit<Impl>::clearLQ() 2721061SN/A{ 2732863Sktlim@umich.edu loadQueue.clear(); 2749444SAndreas.Sandberg@ARM.com} 2751060SN/A 2769444SAndreas.Sandberg@ARM.comtemplate<class Impl> 2779444SAndreas.Sandberg@ARM.comvoid 2789444SAndreas.Sandberg@ARM.comLSQUnit<Impl>::clearSQ() 2799444SAndreas.Sandberg@ARM.com{ 2809444SAndreas.Sandberg@ARM.com storeQueue.clear(); 2819444SAndreas.Sandberg@ARM.com} 2829444SAndreas.Sandberg@ARM.com 2832863Sktlim@umich.edutemplate<class Impl> 2842316SN/Avoid 2851060SN/ALSQUnit<Impl>::drainSanityCheck() const 2862316SN/A{ 2872316SN/A for (int i = 0; i < loadQueue.size(); ++i) 2882307SN/A assert(!loadQueue[i]); 2891060SN/A 2909444SAndreas.Sandberg@ARM.com assert(storesToWB == 0); 2919444SAndreas.Sandberg@ARM.com assert(!retryPkt); 2921060SN/A} 2939444SAndreas.Sandberg@ARM.com 2949444SAndreas.Sandberg@ARM.comtemplate<class Impl> 2959444SAndreas.Sandberg@ARM.comvoid 2969444SAndreas.Sandberg@ARM.comLSQUnit<Impl>::takeOverFrom() 2976221Snate@binkert.org{ 2989444SAndreas.Sandberg@ARM.com resetState(); 2999444SAndreas.Sandberg@ARM.com} 3009444SAndreas.Sandberg@ARM.com 3019444SAndreas.Sandberg@ARM.comtemplate<class Impl> 3022307SN/Avoid 3032307SN/ALSQUnit<Impl>::resizeLQ(unsigned size) 3042307SN/A{ 3052307SN/A unsigned size_plus_sentinel = size + 1; 3062307SN/A assert(size_plus_sentinel >= LQEntries); 3076221Snate@binkert.org 3081858SN/A if (size_plus_sentinel > LQEntries) { 3092292SN/A while (size_plus_sentinel > loadQueue.size()) { 3101858SN/A DynInstPtr dummy; 3112292SN/A loadQueue.push_back(dummy); 3122292SN/A LQEntries++; 3132292SN/A } 3142292SN/A } else { 3153788Sgblack@eecs.umich.edu LQEntries = size_plus_sentinel; 3162292SN/A } 3172698Sktlim@umich.edu 3183788Sgblack@eecs.umich.edu assert(LQEntries <= 256); 3192301SN/A} 3203788Sgblack@eecs.umich.edu 3213788Sgblack@eecs.umich.edutemplate<class Impl> 3223788Sgblack@eecs.umich.eduvoid 3233788Sgblack@eecs.umich.eduLSQUnit<Impl>::resizeSQ(unsigned size) 3243788Sgblack@eecs.umich.edu{ 3253788Sgblack@eecs.umich.edu unsigned size_plus_sentinel = size + 1; 3263788Sgblack@eecs.umich.edu if (size_plus_sentinel > SQEntries) { 3273788Sgblack@eecs.umich.edu while (size_plus_sentinel > storeQueue.size()) { 3283788Sgblack@eecs.umich.edu SQEntry dummy; 3293788Sgblack@eecs.umich.edu storeQueue.push_back(dummy); 3303788Sgblack@eecs.umich.edu SQEntries++; 3312292SN/A } 3322292SN/A } else { 3332292SN/A SQEntries = size_plus_sentinel; 3342292SN/A } 3352292SN/A 3362329SN/A assert(SQEntries <= 256); 3372292SN/A} 3382292SN/A 3392292SN/Atemplate <class Impl> 3402935Sksewell@umich.eduvoid 3412935Sksewell@umich.eduLSQUnit<Impl>::insert(DynInstPtr &inst) 3422731Sktlim@umich.edu{ 3432292SN/A assert(inst->isMemRef()); 3442292SN/A 3452292SN/A assert(inst->isLoad() || inst->isStore()); 3462935Sksewell@umich.edu 3472292SN/A if (inst->isLoad()) { 3482292SN/A insertLoad(inst); 3492935Sksewell@umich.edu } else { 3504632Sgblack@eecs.umich.edu insertStore(inst); 3513093Sksewell@umich.edu } 3522292SN/A 3532292SN/A inst->setInLSQ(); 3543093Sksewell@umich.edu} 3554632Sgblack@eecs.umich.edu 3562935Sksewell@umich.edutemplate <class Impl> 3572292SN/Avoid 3582292SN/ALSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 3592292SN/A{ 3602292SN/A assert((loadTail + 1) % LQEntries != loadHead); 3612292SN/A assert(loads < LQEntries); 3622292SN/A 3632292SN/A DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n", 3642292SN/A load_inst->pcState(), loadTail, load_inst->seqNum); 3652292SN/A 3662292SN/A load_inst->lqIdx = loadTail; 3672292SN/A 3682292SN/A if (stores == 0) { 3692292SN/A load_inst->sqIdx = -1; 3702292SN/A } else { 3712292SN/A load_inst->sqIdx = storeTail; 3722292SN/A } 3736221Snate@binkert.org 3746221Snate@binkert.org loadQueue[loadTail] = load_inst; 3752292SN/A 3762292SN/A incrLdIdx(loadTail); 3773867Sbinkertn@umich.edu 3786221Snate@binkert.org ++loads; 3792292SN/A} 3802292SN/A 3812292SN/Atemplate <class Impl> 3822292SN/Avoid 3832292SN/ALSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 3842292SN/A{ 3852292SN/A // Make sure it is not full before inserting an instruction. 3862292SN/A assert((storeTail + 1) % SQEntries != storeHead); 3872292SN/A assert(stores < SQEntries); 3882292SN/A 3892292SN/A DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n", 3902292SN/A store_inst->pcState(), storeTail, store_inst->seqNum); 3912292SN/A 3922292SN/A store_inst->sqIdx = storeTail; 3932292SN/A store_inst->lqIdx = loadTail; 3942292SN/A 3952292SN/A storeQueue[storeTail] = SQEntry(store_inst); 3963867Sbinkertn@umich.edu 3972292SN/A incrStIdx(storeTail); 3983867Sbinkertn@umich.edu 3996221Snate@binkert.org ++stores; 4002292SN/A} 4012292SN/A 4022292SN/Atemplate <class Impl> 4032292SN/Atypename Impl::DynInstPtr 4042292SN/ALSQUnit<Impl>::getMemDepViolator() 4052292SN/A{ 4062292SN/A DynInstPtr temp = memDepViolator; 4072292SN/A 4082292SN/A memDepViolator = NULL; 4092292SN/A 4102292SN/A return temp; 4112292SN/A} 4126221Snate@binkert.org 4132292SN/Atemplate <class Impl> 4142292SN/Aunsigned 4152292SN/ALSQUnit<Impl>::numFreeLoadEntries() 4162292SN/A{ 4172292SN/A //LQ has an extra dummy entry to differentiate 4182292SN/A //empty/full conditions. Subtract 1 from the free entries. 4192292SN/A DPRINTF(LSQUnit, "LQ size: %d, #loads occupied: %d\n", LQEntries, loads); 4202292SN/A return LQEntries - loads - 1; 4212292SN/A} 4226221Snate@binkert.org 4232292SN/Atemplate <class Impl> 4242292SN/Aunsigned 4252292SN/ALSQUnit<Impl>::numFreeStoreEntries() 4262292SN/A{ 4272292SN/A //SQ has an extra dummy entry to differentiate 4282292SN/A //empty/full conditions. Subtract 1 from the free entries. 4292292SN/A DPRINTF(LSQUnit, "SQ size: %d, #stores occupied: %d\n", SQEntries, stores); 4302292SN/A return SQEntries - stores - 1; 4312292SN/A 4322292SN/A } 4332292SN/A 4342292SN/Atemplate <class Impl> 4352301SN/Avoid 4362301SN/ALSQUnit<Impl>::checkSnoop(PacketPtr pkt) 4373788Sgblack@eecs.umich.edu{ 4383788Sgblack@eecs.umich.edu int load_idx = loadHead; 4393788Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr()); 4403788Sgblack@eecs.umich.edu 4413788Sgblack@eecs.umich.edu // Only Invalidate packet calls checkSnoop 4423788Sgblack@eecs.umich.edu assert(pkt->isInvalidate()); 4433788Sgblack@eecs.umich.edu for (int x = 0; x < cpu->numContexts(); x++) { 4443788Sgblack@eecs.umich.edu ThreadContext *tc = cpu->getContext(x); 4453798Sgblack@eecs.umich.edu bool no_squash = cpu->thread[x]->noSquashFromTC; 4463798Sgblack@eecs.umich.edu cpu->thread[x]->noSquashFromTC = true; 4473798Sgblack@eecs.umich.edu TheISA::handleLockedSnoop(tc, pkt, cacheBlockMask); 4483798Sgblack@eecs.umich.edu cpu->thread[x]->noSquashFromTC = no_squash; 4493798Sgblack@eecs.umich.edu } 4503798Sgblack@eecs.umich.edu 4512292SN/A Addr invalidate_addr = pkt->getAddr() & cacheBlockMask; 4522292SN/A 4532292SN/A DynInstPtr ld_inst = loadQueue[load_idx]; 4542292SN/A if (ld_inst) { 4552292SN/A Addr load_addr_low = ld_inst->physEffAddrLow & cacheBlockMask; 4562292SN/A Addr load_addr_high = ld_inst->physEffAddrHigh & cacheBlockMask; 4572292SN/A 4582292SN/A // Check that this snoop didn't just invalidate our lock flag 4592292SN/A if (ld_inst->effAddrValid() && (load_addr_low == invalidate_addr 4602292SN/A || load_addr_high == invalidate_addr) 4612292SN/A && ld_inst->memReqFlags & Request::LLSC) 4622292SN/A TheISA::handleLockedSnoopHit(ld_inst.get()); 4632292SN/A } 4642292SN/A 4652292SN/A // If this is the only load in the LSQ we don't care 4662292SN/A if (load_idx == loadTail) 4672292SN/A return; 4682292SN/A 4692292SN/A incrLdIdx(load_idx); 4702292SN/A 4711858SN/A bool force_squash = false; 4721858SN/A 4731858SN/A while (load_idx != loadTail) { 4741858SN/A DynInstPtr ld_inst = loadQueue[load_idx]; 4751858SN/A 4766221Snate@binkert.org if (!ld_inst->effAddrValid() || ld_inst->strictlyOrdered()) { 4771858SN/A incrLdIdx(load_idx); 4782292SN/A continue; 4792292SN/A } 4802292SN/A 4812292SN/A Addr load_addr_low = ld_inst->physEffAddrLow & cacheBlockMask; 4821858SN/A Addr load_addr_high = ld_inst->physEffAddrHigh & cacheBlockMask; 4832292SN/A 4842292SN/A DPRINTF(LSQUnit, "-- inst [sn:%lli] load_addr: %#x to pktAddr:%#x\n", 4852292SN/A ld_inst->seqNum, load_addr_low, invalidate_addr); 4862292SN/A 4872292SN/A if ((load_addr_low == invalidate_addr 4882292SN/A || load_addr_high == invalidate_addr) || force_squash) { 4892292SN/A if (needsTSO) { 4902292SN/A // If we have a TSO system, as all loads must be ordered with 4912292SN/A // all other loads, this load as well as *all* subsequent loads 4922292SN/A // need to be squashed to prevent possible load reordering. 4932292SN/A force_squash = true; 4942292SN/A } 4952292SN/A if (ld_inst->possibleLoadViolation() || force_squash) { 4961858SN/A DPRINTF(LSQUnit, "Conflicting load at addr %#x [sn:%lli]\n", 4972292SN/A pkt->getAddr(), ld_inst->seqNum); 4982292SN/A 4992292SN/A // Mark the load for re-execution 5002292SN/A ld_inst->fault = std::make_shared<ReExec>(); 5012292SN/A } else { 5022292SN/A DPRINTF(LSQUnit, "HitExternal Snoop for addr %#x [sn:%lli]\n", 5032292SN/A pkt->getAddr(), ld_inst->seqNum); 5042292SN/A 5052292SN/A // Make sure that we don't lose a snoop hitting a LOCKED 5062292SN/A // address since the LOCK* flags don't get updated until 5072292SN/A // commit. 5082292SN/A if (ld_inst->memReqFlags & Request::LLSC) 5092292SN/A TheISA::handleLockedSnoopHit(ld_inst.get()); 5102292SN/A 5112292SN/A // If a older load checks this and it's true 5122292SN/A // then we might have missed the snoop 5132292SN/A // in which case we need to invalidate to be sure 5142292SN/A ld_inst->hitExternalSnoop(true); 5152292SN/A } 5162292SN/A } 5172292SN/A incrLdIdx(load_idx); 5182292SN/A } 5192292SN/A return; 5202292SN/A} 5212292SN/A 5222292SN/Atemplate <class Impl> 5232292SN/AFault 5242292SN/ALSQUnit<Impl>::checkViolations(int load_idx, DynInstPtr &inst) 5252292SN/A{ 5262292SN/A Addr inst_eff_addr1 = inst->effAddr >> depCheckShift; 5272292SN/A Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift; 5282292SN/A 5292292SN/A /** @todo in theory you only need to check an instruction that has executed 5302292SN/A * however, there isn't a good way in the pipeline at the moment to check 5312292SN/A * all instructions that will execute before the store writes back. Thus, 5322292SN/A * like the implementation that came before it, we're overly conservative. 5332292SN/A */ 5342292SN/A while (load_idx != loadTail) { 5352292SN/A DynInstPtr ld_inst = loadQueue[load_idx]; 5362292SN/A if (!ld_inst->effAddrValid() || ld_inst->strictlyOrdered()) { 5372292SN/A incrLdIdx(load_idx); 5382292SN/A continue; 5392292SN/A } 5402292SN/A 5412292SN/A Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift; 5422292SN/A Addr ld_eff_addr2 = 5432292SN/A (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift; 5442292SN/A 5452292SN/A if (inst_eff_addr2 >= ld_eff_addr1 && inst_eff_addr1 <= ld_eff_addr2) { 5462292SN/A if (inst->isLoad()) { 5472292SN/A // If this load is to the same block as an external snoop 5482292SN/A // invalidate that we've observed then the load needs to be 5492292SN/A // squashed as it could have newer data 5502292SN/A if (ld_inst->hitExternalSnoop()) { 5512292SN/A if (!memDepViolator || 5522292SN/A ld_inst->seqNum < memDepViolator->seqNum) { 5532292SN/A DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] " 5542292SN/A "and [sn:%lli] at address %#x\n", 5552292SN/A inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5562292SN/A memDepViolator = ld_inst; 5572292SN/A 5582292SN/A ++lsqMemOrderViolation; 5592292SN/A 5602292SN/A return std::make_shared<GenericISA::M5PanicFault>( 5612292SN/A "Detected fault with inst [sn:%lli] and " 5622292SN/A "[sn:%lli] at address %#x\n", 5632292SN/A inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5642292SN/A } 5652292SN/A } 5662292SN/A 5672292SN/A // Otherwise, mark the load has a possible load violation 5682292SN/A // and if we see a snoop before it's commited, we need to squash 5692292SN/A ld_inst->possibleLoadViolation(true); 5702292SN/A DPRINTF(LSQUnit, "Found possible load violation at addr: %#x" 5712292SN/A " between instructions [sn:%lli] and [sn:%lli]\n", 5722292SN/A inst_eff_addr1, inst->seqNum, ld_inst->seqNum); 5732292SN/A } else { 5742292SN/A // A load/store incorrectly passed this store. 5752292SN/A // Check if we already have a violator, or if it's newer 5762292SN/A // squash and refetch. 5772292SN/A if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum) 5782292SN/A break; 5792292SN/A 5802292SN/A DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and " 5812292SN/A "[sn:%lli] at address %#x\n", 5827720Sgblack@eecs.umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5837720Sgblack@eecs.umich.edu memDepViolator = ld_inst; 5842292SN/A 5852292SN/A ++lsqMemOrderViolation; 5862292SN/A 5877720Sgblack@eecs.umich.edu return std::make_shared<GenericISA::M5PanicFault>( 5887720Sgblack@eecs.umich.edu "Detected fault with " 5897720Sgblack@eecs.umich.edu "inst [sn:%lli] and [sn:%lli] at address %#x\n", 5902292SN/A inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5912292SN/A } 5922292SN/A } 5932292SN/A 5942292SN/A incrLdIdx(load_idx); 5952292SN/A } 5962292SN/A return NoFault; 5972292SN/A} 5982292SN/A 5992292SN/A 6007720Sgblack@eecs.umich.edu 6012292SN/A 6022292SN/Atemplate <class Impl> 6032292SN/AFault 6042292SN/ALSQUnit<Impl>::executeLoad(DynInstPtr &inst) 6052292SN/A{ 6062336SN/A using namespace TheISA; 6072336SN/A // Execute a specific load. 6082336SN/A Fault load_fault = NoFault; 6092336SN/A 6102336SN/A DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n", 6112336SN/A inst->pcState(), inst->seqNum); 6122336SN/A 6132336SN/A assert(!inst->isSquashed()); 6142292SN/A 6152292SN/A load_fault = inst->initiateAcc(); 6162301SN/A 6172301SN/A if (inst->isTranslationDelayed() && 6182292SN/A load_fault == NoFault) 6192301SN/A return load_fault; 6202301SN/A 6212301SN/A // If the instruction faulted or predicated false, then we need to send it 6222292SN/A // along to commit without the instruction completing. 6232301SN/A if (load_fault != NoFault || !inst->readPredicate()) { 6242292SN/A // Send this instruction to commit, also make sure iew stage 6252301SN/A // realizes there is activity. Mark it as executed unless it 6262292SN/A // is a strictly ordered load that needs to hit the head of 6272301SN/A // commit. 6282292SN/A if (!inst->readPredicate()) 6292292SN/A inst->forwardOldRegs(); 6302292SN/A DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", 6312292SN/A inst->seqNum, 6322336SN/A (load_fault != NoFault ? "fault" : "predication")); 6332336SN/A if (!(inst->hasRequest() && inst->strictlyOrdered()) || 6342292SN/A inst->isAtCommit()) { 6352292SN/A inst->setExecuted(); 6362307SN/A } 6372307SN/A iewStage->instToCommit(inst); 6382292SN/A iewStage->activityThisCycle(); 6392292SN/A } else { 6402292SN/A assert(inst->effAddrValid()); 6412292SN/A int load_idx = inst->lqIdx; 6422292SN/A incrLdIdx(load_idx); 6432292SN/A 6442292SN/A if (checkLoads) 6452292SN/A return checkViolations(load_idx, inst); 6462292SN/A } 6472292SN/A 6482292SN/A return load_fault; 6494345Sktlim@umich.edu} 6502292SN/A 6512292SN/Atemplate <class Impl> 6522292SN/AFault 6532292SN/ALSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 6542292SN/A{ 6552292SN/A using namespace TheISA; 6562292SN/A // Make sure that a store exists. 6572292SN/A assert(stores != 0); 6582292SN/A 6592292SN/A int store_idx = store_inst->sqIdx; 6602292SN/A 6618471SGiacomo.Gabrielli@arm.com DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n", 6629046SAli.Saidi@ARM.com store_inst->pcState(), store_inst->seqNum); 6638471SGiacomo.Gabrielli@arm.com 6648471SGiacomo.Gabrielli@arm.com assert(!store_inst->isSquashed()); 6652292SN/A 6662292SN/A // Check the recently completed loads to see if any match this store's 6672292SN/A // address. If so, then we have a memory ordering violation. 6682292SN/A int load_idx = store_inst->lqIdx; 6692292SN/A 6702292SN/A Fault store_fault = store_inst->initiateAcc(); 6712292SN/A 6722292SN/A if (store_inst->isTranslationDelayed() && 6732292SN/A store_fault == NoFault) 6742292SN/A return store_fault; 6752292SN/A 6762292SN/A if (!store_inst->readPredicate()) 6772307SN/A store_inst->forwardOldRegs(); 6782292SN/A 6792292SN/A if (storeQueue[store_idx].size == 0) { 6802292SN/A DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", 6812292SN/A store_inst->pcState(), store_inst->seqNum); 6822292SN/A 6832292SN/A return store_fault; 6842292SN/A } else if (!store_inst->readPredicate()) { 6852292SN/A DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", 6862292SN/A store_inst->seqNum); 6872292SN/A return store_fault; 6882292SN/A } 6892292SN/A 6902292SN/A assert(store_fault == NoFault); 6912292SN/A 6922292SN/A if (store_inst->isStoreConditional()) { 6932292SN/A // Store conditionals need to set themselves as able to 6942292SN/A // writeback if we haven't had a fault by here. 6952292SN/A storeQueue[store_idx].canWB = true; 6962292SN/A 6972292SN/A ++storesToWB; 6986221Snate@binkert.org } 6992292SN/A 7002292SN/A return checkViolations(load_idx, store_inst); 7012292SN/A 7022292SN/A} 7032292SN/A 7042292SN/Atemplate <class Impl> 7052292SN/Avoid 7062292SN/ALSQUnit<Impl>::commitLoad() 7072292SN/A{ 7082292SN/A assert(loadQueue[loadHead]); 7097720Sgblack@eecs.umich.edu 7107720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n", 7112292SN/A loadQueue[loadHead]->pcState()); 7122307SN/A 7132307SN/A loadQueue[loadHead] = NULL; 7142292SN/A 7152292SN/A incrLdIdx(loadHead); 7162292SN/A 7172292SN/A --loads; 7183798Sgblack@eecs.umich.edu} 7193798Sgblack@eecs.umich.edu 7203798Sgblack@eecs.umich.edutemplate <class Impl> 7213798Sgblack@eecs.umich.eduvoid 7223798Sgblack@eecs.umich.eduLSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 7233798Sgblack@eecs.umich.edu{ 7247720Sgblack@eecs.umich.edu assert(loads == 0 || loadQueue[loadHead]); 7253798Sgblack@eecs.umich.edu 7263798Sgblack@eecs.umich.edu while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 7272292SN/A commitLoad(); 7283798Sgblack@eecs.umich.edu } 7292292SN/A} 7302292SN/A 7312292SN/Atemplate <class Impl> 7322292SN/Avoid 7332292SN/ALSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 7342292SN/A{ 7352292SN/A assert(stores == 0 || storeQueue[storeHead].inst); 7362292SN/A 7372292SN/A int store_idx = storeHead; 7382292SN/A 7392292SN/A while (store_idx != storeTail) { 7402292SN/A assert(storeQueue[store_idx].inst); 7412292SN/A // Mark any stores that are now committed and have not yet 7422292SN/A // been marked as able to write back. 7432292SN/A if (!storeQueue[store_idx].canWB) { 7442292SN/A if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 7452292SN/A break; 7466221Snate@binkert.org } 7476221Snate@binkert.org DPRINTF(LSQUnit, "Marking store as able to write back, PC " 7482292SN/A "%s [sn:%lli]\n", 7493867Sbinkertn@umich.edu storeQueue[store_idx].inst->pcState(), 7506221Snate@binkert.org storeQueue[store_idx].inst->seqNum); 7513867Sbinkertn@umich.edu 7523867Sbinkertn@umich.edu storeQueue[store_idx].canWB = true; 7532292SN/A 7542292SN/A ++storesToWB; 7552292SN/A } 7562292SN/A 7572292SN/A incrStIdx(store_idx); 7582292SN/A } 7592292SN/A} 7602292SN/A 7612292SN/Atemplate <class Impl> 7622292SN/Avoid 7632292SN/ALSQUnit<Impl>::writebackPendingStore() 7642292SN/A{ 7656221Snate@binkert.org if (hasPendingPkt) { 7666221Snate@binkert.org assert(pendingPkt != NULL); 7672292SN/A 7683867Sbinkertn@umich.edu // If the cache is blocked, this will store the packet for retry. 7696221Snate@binkert.org if (sendStore(pendingPkt)) { 7702292SN/A storePostSend(pendingPkt); 7712292SN/A } 7722292SN/A pendingPkt = NULL; 7732292SN/A hasPendingPkt = false; 7742292SN/A } 7752292SN/A} 7762292SN/A 7772292SN/Atemplate <class Impl> 7782292SN/Avoid 7792292SN/ALSQUnit<Impl>::writebackStores() 7802292SN/A{ 7812292SN/A // First writeback the second packet from any split store that didn't 7822292SN/A // complete last cycle because there weren't enough cache ports available. 7832292SN/A if (TheISA::HasUnalignedMemAcc) { 7842733Sktlim@umich.edu writebackPendingStore(); 7852292SN/A } 7862292SN/A 7872292SN/A while (storesToWB > 0 && 7882292SN/A storeWBIdx != storeTail && 7892292SN/A storeQueue[storeWBIdx].inst && 7902292SN/A storeQueue[storeWBIdx].canWB && 7912292SN/A ((!needsTSO) || (!storeInFlight)) && 7922292SN/A usedPorts < cachePorts) { 7932733Sktlim@umich.edu 7942292SN/A if (isStoreBlocked) { 7952292SN/A DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 7962292SN/A " is blocked!\n"); 7972292SN/A break; 7982292SN/A } 7992292SN/A 8006221Snate@binkert.org // Store didn't write any data so no need to write it back to 8012292SN/A // memory. 8022292SN/A if (storeQueue[storeWBIdx].size == 0) { 8032292SN/A completeStore(storeWBIdx); 8042292SN/A 8052292SN/A incrStIdx(storeWBIdx); 8062292SN/A 8072292SN/A continue; 8082292SN/A } 8092292SN/A 8102292SN/A ++usedPorts; 8113798Sgblack@eecs.umich.edu 8123798Sgblack@eecs.umich.edu if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 8133798Sgblack@eecs.umich.edu incrStIdx(storeWBIdx); 8143798Sgblack@eecs.umich.edu 8152292SN/A continue; 8162292SN/A } 8172292SN/A 8182292SN/A assert(storeQueue[storeWBIdx].req); 8192292SN/A assert(!storeQueue[storeWBIdx].committed); 8202329SN/A 8212329SN/A if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 8222301SN/A assert(storeQueue[storeWBIdx].sreqLow); 8232292SN/A assert(storeQueue[storeWBIdx].sreqHigh); 8242292SN/A } 8252292SN/A 8262292SN/A DynInstPtr inst = storeQueue[storeWBIdx].inst; 8272292SN/A 8282292SN/A Request *req = storeQueue[storeWBIdx].req; 8292292SN/A RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow; 8302292SN/A RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh; 8312292SN/A 8322292SN/A storeQueue[storeWBIdx].committed = true; 8332292SN/A 8346221Snate@binkert.org assert(!inst->memData); 8352292SN/A inst->memData = new uint8_t[req->getSize()]; 8362292SN/A 8372292SN/A if (storeQueue[storeWBIdx].isAllZeros) 8382292SN/A memset(inst->memData, 0, req->getSize()); 8392301SN/A else 8402292SN/A memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); 8412292SN/A 8422292SN/A PacketPtr data_pkt; 8432292SN/A PacketPtr snd_data_pkt = NULL; 8442292SN/A 8452292SN/A LSQSenderState *state = new LSQSenderState; 8462292SN/A state->isLoad = false; 8472292SN/A state->idx = storeWBIdx; 8482292SN/A state->inst = inst; 8492292SN/A 8502292SN/A if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) { 8512292SN/A 8522292SN/A // Build a single data packet if the store isn't split. 8532292SN/A data_pkt = Packet::createWrite(req); 8542292SN/A data_pkt->dataStatic(inst->memData); 8556221Snate@binkert.org data_pkt->senderState = state; 8562292SN/A } else { 8572980Sgblack@eecs.umich.edu // Create two packets if the store is split in two. 8582980Sgblack@eecs.umich.edu data_pkt = Packet::createWrite(sreqLow); 8592292SN/A snd_data_pkt = Packet::createWrite(sreqHigh); 8601060SN/A 8611060SN/A data_pkt->dataStatic(inst->memData); 8622292SN/A snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize()); 8631060SN/A 8641060SN/A data_pkt->senderState = state; 8651060SN/A snd_data_pkt->senderState = state; 8661060SN/A 8671060SN/A state->isSplit = true; 8682292SN/A state->outstanding = 2; 8692292SN/A 8702292SN/A // Can delete the main request now. 8711062SN/A delete req; 8722292SN/A req = sreqLow; 8732292SN/A } 8741060SN/A 8752292SN/A DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s " 8762292SN/A "to Addr:%#x, data:%#x [sn:%lli]\n", 8772292SN/A storeWBIdx, inst->pcState(), 8781060SN/A req->getPaddr(), (int)*(inst->memData), 8792292SN/A inst->seqNum); 8802292SN/A 8811062SN/A // @todo: Remove this SC hack once the memory system handles it. 8822367SN/A if (inst->isStoreConditional()) { 8832367SN/A assert(!storeQueue[storeWBIdx].isSplit); 8842367SN/A // Disable recording the result temporarily. Writing to 8852367SN/A // misc regs normally updates the result, but this is not 8862367SN/A // the desired behavior when handling store conditionals. 8872292SN/A inst->recordResult(false); 8881061SN/A bool success = TheISA::handleLockedWrite(inst.get(), req, cacheBlockMask); 8891062SN/A inst->recordResult(true); 8901060SN/A 8911060SN/A if (!success) { 8921060SN/A // Instantly complete this store. 8931060SN/A DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 8941060SN/A "Instantly completing it.\n", 8956221Snate@binkert.org inst->seqNum); 8961060SN/A WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 8972292SN/A cpu->schedule(wb, curTick() + 1); 8982292SN/A if (cpu->checker) { 8992292SN/A // Make sure to set the LLSC data for verification 9002292SN/A // if checker is loaded 9012980Sgblack@eecs.umich.edu inst->reqToVerify->setExtraData(0); 9022980Sgblack@eecs.umich.edu inst->completeAcc(data_pkt); 9031060SN/A } 9041061SN/A completeStore(storeWBIdx); 9051060SN/A incrStIdx(storeWBIdx); 9062292SN/A continue; 9072292SN/A } 9082292SN/A } else { 9092292SN/A // Non-store conditionals do not need a writeback. 9102292SN/A state->noWB = true; 9112292SN/A } 9121060SN/A 9131060SN/A bool split = 9141060SN/A TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit; 9152292SN/A 9162292SN/A ThreadContext *thread = cpu->tcBase(lsqID); 9172292SN/A 9182292SN/A if (req->isMmappedIpr()) { 9192292SN/A assert(!inst->isStoreConditional()); 9202292SN/A TheISA::handleIprWrite(thread, data_pkt); 9212292SN/A delete data_pkt; 9221060SN/A if (split) { 9232329SN/A assert(snd_data_pkt->req->isMmappedIpr()); 9242329SN/A TheISA::handleIprWrite(thread, snd_data_pkt); 9252292SN/A delete snd_data_pkt; 9261061SN/A delete sreqLow; 9272292SN/A delete sreqHigh; 9282292SN/A } 9291061SN/A delete state; 9302292SN/A delete req; 9311060SN/A completeStore(storeWBIdx); 9321060SN/A incrStIdx(storeWBIdx); 9331060SN/A } else if (!sendStore(data_pkt)) { 9341061SN/A DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 9351061SN/A "retry later\n", 9366221Snate@binkert.org inst->seqNum); 9371061SN/A 9382292SN/A // Need to store the second packet, if split. 9392292SN/A if (split) { 9401061SN/A state->pktToSend = true; 9411061SN/A state->pendingPacket = snd_data_pkt; 9421061SN/A } 9431061SN/A } else { 9441061SN/A 9452292SN/A // If split, try to send the second packet too 9461061SN/A if (split) { 9473773Sgblack@eecs.umich.edu assert(snd_data_pkt); 9483773Sgblack@eecs.umich.edu 9496313Sgblack@eecs.umich.edu // Ensure there are enough ports to use. 9507767Sgblack@eecs.umich.edu if (usedPorts < cachePorts) { 9517767Sgblack@eecs.umich.edu ++usedPorts; 9525082Sgblack@eecs.umich.edu if (sendStore(snd_data_pkt)) { 9535082Sgblack@eecs.umich.edu storePostSend(snd_data_pkt); 9546313Sgblack@eecs.umich.edu } else { 9557767Sgblack@eecs.umich.edu DPRINTF(IEW, "D-Cache became blocked when writing" 9567767Sgblack@eecs.umich.edu " [sn:%lli] second packet, will retry later\n", 9575082Sgblack@eecs.umich.edu inst->seqNum); 9587649Sminkyu.jeong@arm.com } 9597767Sgblack@eecs.umich.edu } else { 9607767Sgblack@eecs.umich.edu 9617767Sgblack@eecs.umich.edu // Store the packet for when there's free ports. 9627767Sgblack@eecs.umich.edu assert(pendingPkt == NULL); 9637649Sminkyu.jeong@arm.com pendingPkt = snd_data_pkt; 9647649Sminkyu.jeong@arm.com hasPendingPkt = true; 9653773Sgblack@eecs.umich.edu } 9664352Sgblack@eecs.umich.edu } else { 9671061SN/A 9681061SN/A // Not a split store. 9693773Sgblack@eecs.umich.edu storePostSend(data_pkt); 9701061SN/A } 9712292SN/A } 9723773Sgblack@eecs.umich.edu } 9732292SN/A 9741061SN/A // Not sure this should set it to 0. 9751061SN/A usedPorts = 0; 9761061SN/A 9772292SN/A assert(stores >= 0 && storesToWB >= 0); 9782292SN/A} 9797767Sgblack@eecs.umich.edu 9807767Sgblack@eecs.umich.edu/*template <class Impl> 9811061SN/Avoid 9821061SN/ALSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 9834636Sgblack@eecs.umich.edu{ 9847767Sgblack@eecs.umich.edu list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 9857767Sgblack@eecs.umich.edu mshrSeqNums.end(), 9861061SN/A seqNum); 9871062SN/A 9881062SN/A if (mshr_it != mshrSeqNums.end()) { 9897897Shestness@cs.utexas.edu mshrSeqNums.erase(mshr_it); 9901061SN/A DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 9911061SN/A } 9921061SN/A}*/ 9931061SN/A 9941061SN/Atemplate <class Impl> 9956221Snate@binkert.orgvoid 9961061SN/ALSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 9972292SN/A{ 9981061SN/A DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 9991061SN/A "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 10001061SN/A 10012292SN/A int load_idx = loadTail; 10022292SN/A decrLdIdx(load_idx); 10032292SN/A 10043773Sgblack@eecs.umich.edu while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 10053773Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"Load Instruction PC %s squashed, " 10064352Sgblack@eecs.umich.edu "[sn:%lli]\n", 10076313Sgblack@eecs.umich.edu loadQueue[load_idx]->pcState(), 10087767Sgblack@eecs.umich.edu loadQueue[load_idx]->seqNum); 10097767Sgblack@eecs.umich.edu 10107767Sgblack@eecs.umich.edu if (isStalled() && load_idx == stallingLoadIdx) { 10117767Sgblack@eecs.umich.edu stalled = false; 10127767Sgblack@eecs.umich.edu stallingStoreIsn = 0; 10137767Sgblack@eecs.umich.edu stallingLoadIdx = 0; 10147767Sgblack@eecs.umich.edu } 10157767Sgblack@eecs.umich.edu 10167649Sminkyu.jeong@arm.com // Clear the smart pointer to make sure it is decremented. 10174352Sgblack@eecs.umich.edu loadQueue[load_idx]->setSquashed(); 10184352Sgblack@eecs.umich.edu loadQueue[load_idx] = NULL; 10197767Sgblack@eecs.umich.edu --loads; 10207767Sgblack@eecs.umich.edu 10217767Sgblack@eecs.umich.edu // Inefficient! 10227767Sgblack@eecs.umich.edu loadTail = load_idx; 10237649Sminkyu.jeong@arm.com 10247649Sminkyu.jeong@arm.com decrLdIdx(load_idx); 10253773Sgblack@eecs.umich.edu ++lsqSquashedLoads; 10263773Sgblack@eecs.umich.edu } 10273773Sgblack@eecs.umich.edu 10281061SN/A if (memDepViolator && squashed_num < memDepViolator->seqNum) { 10292292SN/A memDepViolator = NULL; 10302292SN/A } 10313773Sgblack@eecs.umich.edu 10321061SN/A int store_idx = storeTail; 10332292SN/A decrStIdx(store_idx); 10347854SAli.Saidi@ARM.com 10357854SAli.Saidi@ARM.com while (stores != 0 && 10361062SN/A storeQueue[store_idx].inst->seqNum > squashed_num) { 10372292SN/A // Instructions marked as can WB are already committed. 10383773Sgblack@eecs.umich.edu if (storeQueue[store_idx].canWB) { 10392292SN/A break; 10401062SN/A } 10412292SN/A 10423773Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"Store Instruction PC %s squashed, " 10432292SN/A "idx:%i [sn:%lli]\n", 10442292SN/A storeQueue[store_idx].inst->pcState(), 10451062SN/A store_idx, storeQueue[store_idx].inst->seqNum); 10462292SN/A 10471062SN/A // I don't think this can happen. It should have been cleared 10482935Sksewell@umich.edu // by the stalling load. 10492935Sksewell@umich.edu if (isStalled() && 10502935Sksewell@umich.edu storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 10512292SN/A panic("Is stalled should have been cleared by stalling load!\n"); 10521062SN/A stalled = false; 10532292SN/A stallingStoreIsn = 0; 10542292SN/A } 10552292SN/A 10562292SN/A // Clear the smart pointer to make sure it is decremented. 10572292SN/A storeQueue[store_idx].inst->setSquashed(); 10582292SN/A storeQueue[store_idx].inst = NULL; 10592292SN/A storeQueue[store_idx].canWB = 0; 10602292SN/A 10611062SN/A // Must delete request now that it wasn't handed off to 10622292SN/A // memory. This is quite ugly. @todo: Figure out the proper 10631061SN/A // place to really handle request deletes. 10641061SN/A delete storeQueue[store_idx].req; 10651061SN/A if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) { 10661061SN/A delete storeQueue[store_idx].sreqLow; 10671061SN/A delete storeQueue[store_idx].sreqHigh; 10686221Snate@binkert.org 10691061SN/A storeQueue[store_idx].sreqLow = NULL; 10702292SN/A storeQueue[store_idx].sreqHigh = NULL; 10712292SN/A } 10722292SN/A 10732292SN/A storeQueue[store_idx].req = NULL; 10742292SN/A --stores; 10752292SN/A 10761061SN/A // Inefficient! 10771061SN/A storeTail = store_idx; 10781061SN/A 10791061SN/A decrStIdx(store_idx); 10806221Snate@binkert.org ++lsqSquashedStores; 10811061SN/A } 10822292SN/A} 10832292SN/A 10842292SN/Atemplate <class Impl> 10852292SN/Avoid 10862292SN/ALSQUnit<Impl>::storePostSend(PacketPtr pkt) 10872292SN/A{ 10882292SN/A if (isStalled() && 10892292SN/A storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 10902292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 10912292SN/A "load idx:%i\n", 10926221Snate@binkert.org stallingStoreIsn, stallingLoadIdx); 10932292SN/A stalled = false; 10942292SN/A stallingStoreIsn = 0; 10952292SN/A iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 10962292SN/A } 10972292SN/A 10982292SN/A if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 10992292SN/A // The store is basically completed at this time. This 11002292SN/A // only works so long as the checker doesn't try to 11012292SN/A // verify the value in memory for stores. 11022292SN/A storeQueue[storeWBIdx].inst->setCompleted(); 11032292SN/A 11042292SN/A if (cpu->checker) { 11052292SN/A cpu->checker->verify(storeQueue[storeWBIdx].inst); 11062292SN/A } 11072292SN/A } 11082292SN/A 11092731Sktlim@umich.edu if (needsTSO) { 11102292SN/A storeInFlight = true; 11112292SN/A } 11122292SN/A 11132292SN/A incrStIdx(storeWBIdx); 11142292SN/A} 11152292SN/A 11162292SN/Atemplate <class Impl> 11172292SN/Avoid 11186221Snate@binkert.orgLSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 11192292SN/A{ 11202292SN/A iewStage->wakeCPU(); 11212292SN/A 11222292SN/A // Squashed instructions do not need to complete their access. 11232292SN/A if (inst->isSquashed()) { 11242292SN/A assert(!inst->isStore()); 11252292SN/A ++lsqIgnoredResponses; 11262292SN/A return; 11272292SN/A } 11282292SN/A 11292292SN/A if (!inst->isExecuted()) { 11302292SN/A inst->setExecuted(); 11312292SN/A 11322292SN/A if (inst->fault == NoFault) { 11332292SN/A // Complete access to copy data to proper place. 11342292SN/A inst->completeAcc(pkt); 11352292SN/A } else { 11362292SN/A // If the instruction has an outstanding fault, we cannot complete 11372292SN/A // the access as this discards the current fault. 11382292SN/A 11392292SN/A // If we have an outstanding fault, the fault should only be of 11402292SN/A // type ReExec. 11416221Snate@binkert.org assert(dynamic_cast<ReExec*>(inst->fault.get()) != nullptr); 11422292SN/A 11432292SN/A DPRINTF(LSQUnit, "Not completing instruction [sn:%lli] access " 11442292SN/A "due to pending fault.\n", inst->seqNum); 11452292SN/A } 11462292SN/A } 11472292SN/A 11482292SN/A // Need to insert instruction into queue to commit 11492292SN/A iewStage->instToCommit(inst); 11502292SN/A 11512292SN/A iewStage->activityThisCycle(); 11522292SN/A 11532292SN/A // see if this load changed the PC 11542292SN/A iewStage->checkMisprediction(inst); 11552292SN/A} 11562292SN/A 11572292SN/Atemplate <class Impl> 11582292SN/Avoid 11592292SN/ALSQUnit<Impl>::completeStore(int store_idx) 11602292SN/A{ 11612292SN/A assert(storeQueue[store_idx].inst); 11622292SN/A storeQueue[store_idx].completed = true; 11632301SN/A --storesToWB; 11642292SN/A // A bit conservative because a store completion may not free up entries, 11652301SN/A // but hopefully avoids two store completions in one cycle from making 11662292SN/A // the CPU tick twice. 11672292SN/A cpu->wakeCPU(); 11682292SN/A cpu->activityThisCycle(); 11692292SN/A 11702292SN/A if (store_idx == storeHead) { 11712292SN/A do { 11722292SN/A incrStIdx(storeHead); 11732292SN/A 11742292SN/A --stores; 11752292SN/A } while (storeQueue[storeHead].completed && 11766221Snate@binkert.org storeHead != storeTail); 11772292SN/A 11788607Sgblack@eecs.umich.edu iewStage->updateLSQNextCycle = true; 11798607Sgblack@eecs.umich.edu } 11802292SN/A 11818607Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 11828607Sgblack@eecs.umich.edu "idx:%i\n", 11832292SN/A storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 11842292SN/A 11852292SN/A#if TRACING_ON 11862292SN/A if (DTRACE(O3PipeView)) { 11872292SN/A storeQueue[store_idx].inst->storeTick = 11882292SN/A curTick() - storeQueue[store_idx].inst->fetchTick; 11892292SN/A } 11902292SN/A#endif 11912292SN/A 11922292SN/A if (isStalled() && 11932292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 11942292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 11952292SN/A "load idx:%i\n", 11962292SN/A stallingStoreIsn, stallingLoadIdx); 11972292SN/A stalled = false; 11982292SN/A stallingStoreIsn = 0; 11992292SN/A iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 12002292SN/A } 12012292SN/A 12026221Snate@binkert.org storeQueue[store_idx].inst->setCompleted(); 12032292SN/A 12042292SN/A if (needsTSO) { 12052292SN/A storeInFlight = false; 12062292SN/A } 12072292SN/A 12082292SN/A // Tell the checker we've completed this instruction. Some stores 12092292SN/A // may get reported twice to the checker, but the checker can 12102292SN/A // handle that case. 12112301SN/A if (cpu->checker) { 12122292SN/A cpu->checker->verify(storeQueue[store_idx].inst); 12132292SN/A } 12142292SN/A} 12152292SN/A 12162292SN/Atemplate <class Impl> 12172292SN/Abool 12182292SN/ALSQUnit<Impl>::sendStore(PacketPtr data_pkt) 12192292SN/A{ 12202292SN/A if (!dcachePort->sendTimingReq(data_pkt)) { 12214632Sgblack@eecs.umich.edu // Need to handle becoming blocked on a store. 12222292SN/A isStoreBlocked = true; 12232292SN/A ++lsqCacheBlocked; 12242292SN/A assert(retryPkt == NULL); 12252292SN/A retryPkt = data_pkt; 12262292SN/A return false; 12272292SN/A } 12282292SN/A return true; 12292292SN/A} 12302292SN/A 12312292SN/Atemplate <class Impl> 12322292SN/Avoid 12332292SN/ALSQUnit<Impl>::recvRetry() 12342292SN/A{ 12352292SN/A if (isStoreBlocked) { 12362292SN/A DPRINTF(LSQUnit, "Receiving retry: store blocked\n"); 12372292SN/A assert(retryPkt != NULL); 12382292SN/A 12392292SN/A LSQSenderState *state = 12402292SN/A dynamic_cast<LSQSenderState *>(retryPkt->senderState); 12412292SN/A 12422292SN/A if (dcachePort->sendTimingReq(retryPkt)) { 12432292SN/A // Don't finish the store unless this is the last packet. 12442292SN/A if (!TheISA::HasUnalignedMemAcc || !state->pktToSend || 12452292SN/A state->pendingPacket == retryPkt) { 12462292SN/A state->pktToSend = false; 12472292SN/A storePostSend(retryPkt); 12482292SN/A } 12492292SN/A retryPkt = NULL; 12502292SN/A isStoreBlocked = false; 12512292SN/A 12523798Sgblack@eecs.umich.edu // Send any outstanding packet. 12533798Sgblack@eecs.umich.edu if (TheISA::HasUnalignedMemAcc && state->pktToSend) { 12543798Sgblack@eecs.umich.edu assert(state->pendingPacket); 12552292SN/A if (sendStore(state->pendingPacket)) { 12563798Sgblack@eecs.umich.edu storePostSend(state->pendingPacket); 12573798Sgblack@eecs.umich.edu } 12583798Sgblack@eecs.umich.edu } 12593798Sgblack@eecs.umich.edu } else { 12603798Sgblack@eecs.umich.edu // Still blocked! 12613798Sgblack@eecs.umich.edu ++lsqCacheBlocked; 12623798Sgblack@eecs.umich.edu } 12633798Sgblack@eecs.umich.edu } 12643788Sgblack@eecs.umich.edu} 12653788Sgblack@eecs.umich.edu 12662292SN/Atemplate <class Impl> 12673788Sgblack@eecs.umich.eduinline void 12683788Sgblack@eecs.umich.eduLSQUnit<Impl>::incrStIdx(int &store_idx) const 12693788Sgblack@eecs.umich.edu{ 12702292SN/A if (++store_idx >= SQEntries) 12712292SN/A store_idx = 0; 12722301SN/A} 12732292SN/A 12742301SN/Atemplate <class Impl> 12752292SN/Ainline void 12762292SN/ALSQUnit<Impl>::decrStIdx(int &store_idx) const 12772301SN/A{ 12782292SN/A if (--store_idx < 0) 12792292SN/A store_idx += SQEntries; 12802292SN/A} 12812292SN/A 12822292SN/Atemplate <class Impl> 12832292SN/Ainline void 12847720Sgblack@eecs.umich.eduLSQUnit<Impl>::incrLdIdx(int &load_idx) const 12852292SN/A{ 12862292SN/A if (++load_idx >= LQEntries) 12872301SN/A load_idx = 0; 12882292SN/A} 12892292SN/A 12902301SN/Atemplate <class Impl> 12912292SN/Ainline void 12922301SN/ALSQUnit<Impl>::decrLdIdx(int &load_idx) const 12932292SN/A{ 12942292SN/A if (--load_idx < 0) 12952292SN/A load_idx += LQEntries; 12962703Sktlim@umich.edu} 12972292SN/A 12982301SN/Atemplate <class Impl> 12992292SN/Avoid 13002292SN/ALSQUnit<Impl>::dumpInsts() const 13012292SN/A{ 13022292SN/A cprintf("Load store queue: Dumping instructions.\n"); 13032292SN/A cprintf("Load queue size: %i\n", loads); 13042292SN/A cprintf("Load queue: "); 13052292SN/A 13061061SN/A int load_idx = loadHead; 13071061SN/A 13081060SN/A while (load_idx != loadTail && loadQueue[load_idx]) { 13091060SN/A const DynInstPtr &inst(loadQueue[load_idx]); 13106221Snate@binkert.org cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum); 13111060SN/A 13122292SN/A incrLdIdx(load_idx); 13132292SN/A } 13142292SN/A cprintf("\n"); 13151060SN/A 13161060SN/A cprintf("Store queue size: %i\n", stores); 13171060SN/A cprintf("Store queue: "); 13182292SN/A 13192292SN/A int store_idx = storeHead; 13202292SN/A 13212292SN/A while (store_idx != storeTail && storeQueue[store_idx].inst) { 13222292SN/A const DynInstPtr &inst(storeQueue[store_idx].inst); 13232292SN/A cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum); 13242292SN/A 13252292SN/A incrStIdx(store_idx); 13262292SN/A } 13272292SN/A 13282292SN/A cprintf("\n"); 13292292SN/A} 13302292SN/A 13312292SN/A#endif//__CPU_O3_LSQ_UNIT_IMPL_HH__ 13322292SN/A