lsq_unit_impl.hh revision 8587
12292SN/A/* 27597Sminkyu.jeong@arm.com * Copyright (c) 2010 ARM Limited 37597Sminkyu.jeong@arm.com * All rights reserved 47597Sminkyu.jeong@arm.com * 57597Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 67597Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 77597Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 87597Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 97597Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 107597Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 117597Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 127597Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 137597Sminkyu.jeong@arm.com * 142292SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 152292SN/A * All rights reserved. 162292SN/A * 172292SN/A * Redistribution and use in source and binary forms, with or without 182292SN/A * modification, are permitted provided that the following conditions are 192292SN/A * met: redistributions of source code must retain the above copyright 202292SN/A * notice, this list of conditions and the following disclaimer; 212292SN/A * redistributions in binary form must reproduce the above copyright 222292SN/A * notice, this list of conditions and the following disclaimer in the 232292SN/A * documentation and/or other materials provided with the distribution; 242292SN/A * neither the name of the copyright holders nor the names of its 252292SN/A * contributors may be used to endorse or promote products derived from 262292SN/A * this software without specific prior written permission. 272292SN/A * 282292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392689Sktlim@umich.edu * 402689Sktlim@umich.edu * Authors: Kevin Lim 412689Sktlim@umich.edu * Korey Sewell 422292SN/A */ 432292SN/A 443326Sktlim@umich.edu#include "arch/locked_mem.hh" 458229Snate@binkert.org#include "base/str.hh" 466658Snate@binkert.org#include "config/the_isa.hh" 472733Sktlim@umich.edu#include "config/use_checker.hh" 482907Sktlim@umich.edu#include "cpu/o3/lsq.hh" 492292SN/A#include "cpu/o3/lsq_unit.hh" 508232Snate@binkert.org#include "debug/Activity.hh" 518232Snate@binkert.org#include "debug/IEW.hh" 528232Snate@binkert.org#include "debug/LSQUnit.hh" 532722Sktlim@umich.edu#include "mem/packet.hh" 542669Sktlim@umich.edu#include "mem/request.hh" 552292SN/A 562790Sktlim@umich.edu#if USE_CHECKER 572790Sktlim@umich.edu#include "cpu/checker/cpu.hh" 582790Sktlim@umich.edu#endif 592790Sktlim@umich.edu 602669Sktlim@umich.edutemplate<class Impl> 612678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 622678Sktlim@umich.edu LSQUnit *lsq_ptr) 638581Ssteve.reinhardt@amd.com : Event(Default_Pri, AutoDelete), 648581Ssteve.reinhardt@amd.com inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 652292SN/A{ 662292SN/A} 672292SN/A 682669Sktlim@umich.edutemplate<class Impl> 692292SN/Avoid 702678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::process() 712292SN/A{ 722678Sktlim@umich.edu if (!lsqPtr->isSwitchedOut()) { 732678Sktlim@umich.edu lsqPtr->writeback(inst, pkt); 742678Sktlim@umich.edu } 754319Sktlim@umich.edu 764319Sktlim@umich.edu if (pkt->senderState) 774319Sktlim@umich.edu delete pkt->senderState; 784319Sktlim@umich.edu 794319Sktlim@umich.edu delete pkt->req; 802678Sktlim@umich.edu delete pkt; 812678Sktlim@umich.edu} 822292SN/A 832678Sktlim@umich.edutemplate<class Impl> 842678Sktlim@umich.educonst char * 855336Shines@cs.fsu.eduLSQUnit<Impl>::WritebackEvent::description() const 862678Sktlim@umich.edu{ 874873Sstever@eecs.umich.edu return "Store writeback"; 882678Sktlim@umich.edu} 892292SN/A 902678Sktlim@umich.edutemplate<class Impl> 912678Sktlim@umich.eduvoid 922678Sktlim@umich.eduLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 932678Sktlim@umich.edu{ 942678Sktlim@umich.edu LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 952678Sktlim@umich.edu DynInstPtr inst = state->inst; 967852SMatt.Horsnell@arm.com DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum); 977852SMatt.Horsnell@arm.com DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum); 982344SN/A 992678Sktlim@umich.edu //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 1002678Sktlim@umich.edu 1014986Ssaidi@eecs.umich.edu assert(!pkt->wasNacked()); 1024986Ssaidi@eecs.umich.edu 1036974Stjones1@inf.ed.ac.uk // If this is a split access, wait until all packets are received. 1046974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && !state->complete()) { 1056974Stjones1@inf.ed.ac.uk delete pkt->req; 1066974Stjones1@inf.ed.ac.uk delete pkt; 1076974Stjones1@inf.ed.ac.uk return; 1086974Stjones1@inf.ed.ac.uk } 1096974Stjones1@inf.ed.ac.uk 1102678Sktlim@umich.edu if (isSwitchedOut() || inst->isSquashed()) { 1112820Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 1122678Sktlim@umich.edu } else { 1132678Sktlim@umich.edu if (!state->noWB) { 1146974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || !state->isSplit || 1156974Stjones1@inf.ed.ac.uk !state->isLoad) { 1166974Stjones1@inf.ed.ac.uk writeback(inst, pkt); 1176974Stjones1@inf.ed.ac.uk } else { 1186974Stjones1@inf.ed.ac.uk writeback(inst, state->mainPkt); 1196974Stjones1@inf.ed.ac.uk } 1202678Sktlim@umich.edu } 1212678Sktlim@umich.edu 1222678Sktlim@umich.edu if (inst->isStore()) { 1232678Sktlim@umich.edu completeStore(state->idx); 1242678Sktlim@umich.edu } 1252344SN/A } 1262307SN/A 1276974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) { 1286974Stjones1@inf.ed.ac.uk delete state->mainPkt->req; 1296974Stjones1@inf.ed.ac.uk delete state->mainPkt; 1306974Stjones1@inf.ed.ac.uk } 1312678Sktlim@umich.edu delete state; 1324032Sktlim@umich.edu delete pkt->req; 1332678Sktlim@umich.edu delete pkt; 1342292SN/A} 1352292SN/A 1362292SN/Atemplate <class Impl> 1372292SN/ALSQUnit<Impl>::LSQUnit() 1388545Ssaidi@eecs.umich.edu : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false), 1392678Sktlim@umich.edu isStoreBlocked(false), isLoadBlocked(false), 1406974Stjones1@inf.ed.ac.uk loadBlockedHandled(false), hasPendingPkt(false) 1412292SN/A{ 1422292SN/A} 1432292SN/A 1442292SN/Atemplate<class Impl> 1452292SN/Avoid 1465529Snate@binkert.orgLSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 1475529Snate@binkert.org LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 1485529Snate@binkert.org unsigned id) 1492292SN/A{ 1504329Sktlim@umich.edu cpu = cpu_ptr; 1514329Sktlim@umich.edu iewStage = iew_ptr; 1524329Sktlim@umich.edu 1534329Sktlim@umich.edu DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 1542292SN/A 1552307SN/A switchedOut = false; 1562307SN/A 1578545Ssaidi@eecs.umich.edu cacheBlockMask = 0; 1588545Ssaidi@eecs.umich.edu 1592907Sktlim@umich.edu lsq = lsq_ptr; 1602907Sktlim@umich.edu 1612292SN/A lsqID = id; 1622292SN/A 1632329SN/A // Add 1 for the sentinel entry (they are circular queues). 1642329SN/A LQEntries = maxLQEntries + 1; 1652329SN/A SQEntries = maxSQEntries + 1; 1662292SN/A 1672292SN/A loadQueue.resize(LQEntries); 1682292SN/A storeQueue.resize(SQEntries); 1692292SN/A 1708199SAli.Saidi@ARM.com depCheckShift = params->LSQDepCheckShift; 1718199SAli.Saidi@ARM.com checkLoads = params->LSQCheckLoads; 1728199SAli.Saidi@ARM.com 1732292SN/A loadHead = loadTail = 0; 1742292SN/A 1752292SN/A storeHead = storeWBIdx = storeTail = 0; 1762292SN/A 1772292SN/A usedPorts = 0; 1782292SN/A cachePorts = params->cachePorts; 1792292SN/A 1803492Sktlim@umich.edu retryPkt = NULL; 1812329SN/A memDepViolator = NULL; 1822292SN/A 1832292SN/A blockedLoadSeqNum = 0; 1842292SN/A} 1852292SN/A 1862292SN/Atemplate<class Impl> 1872292SN/Astd::string 1882292SN/ALSQUnit<Impl>::name() const 1892292SN/A{ 1902292SN/A if (Impl::MaxThreads == 1) { 1912292SN/A return iewStage->name() + ".lsq"; 1922292SN/A } else { 1938247Snate@binkert.org return iewStage->name() + ".lsq.thread" + to_string(lsqID); 1942292SN/A } 1952292SN/A} 1962292SN/A 1972292SN/Atemplate<class Impl> 1982292SN/Avoid 1992727Sktlim@umich.eduLSQUnit<Impl>::regStats() 2002727Sktlim@umich.edu{ 2012727Sktlim@umich.edu lsqForwLoads 2022727Sktlim@umich.edu .name(name() + ".forwLoads") 2032727Sktlim@umich.edu .desc("Number of loads that had data forwarded from stores"); 2042727Sktlim@umich.edu 2052727Sktlim@umich.edu invAddrLoads 2062727Sktlim@umich.edu .name(name() + ".invAddrLoads") 2072727Sktlim@umich.edu .desc("Number of loads ignored due to an invalid address"); 2082727Sktlim@umich.edu 2092727Sktlim@umich.edu lsqSquashedLoads 2102727Sktlim@umich.edu .name(name() + ".squashedLoads") 2112727Sktlim@umich.edu .desc("Number of loads squashed"); 2122727Sktlim@umich.edu 2132727Sktlim@umich.edu lsqIgnoredResponses 2142727Sktlim@umich.edu .name(name() + ".ignoredResponses") 2152727Sktlim@umich.edu .desc("Number of memory responses ignored because the instruction is squashed"); 2162727Sktlim@umich.edu 2172361SN/A lsqMemOrderViolation 2182361SN/A .name(name() + ".memOrderViolation") 2192361SN/A .desc("Number of memory ordering violations"); 2202361SN/A 2212727Sktlim@umich.edu lsqSquashedStores 2222727Sktlim@umich.edu .name(name() + ".squashedStores") 2232727Sktlim@umich.edu .desc("Number of stores squashed"); 2242727Sktlim@umich.edu 2252727Sktlim@umich.edu invAddrSwpfs 2262727Sktlim@umich.edu .name(name() + ".invAddrSwpfs") 2272727Sktlim@umich.edu .desc("Number of software prefetches ignored due to an invalid address"); 2282727Sktlim@umich.edu 2292727Sktlim@umich.edu lsqBlockedLoads 2302727Sktlim@umich.edu .name(name() + ".blockedLoads") 2312727Sktlim@umich.edu .desc("Number of blocked loads due to partial load-store forwarding"); 2322727Sktlim@umich.edu 2332727Sktlim@umich.edu lsqRescheduledLoads 2342727Sktlim@umich.edu .name(name() + ".rescheduledLoads") 2352727Sktlim@umich.edu .desc("Number of loads that were rescheduled"); 2362727Sktlim@umich.edu 2372727Sktlim@umich.edu lsqCacheBlocked 2382727Sktlim@umich.edu .name(name() + ".cacheBlocked") 2392727Sktlim@umich.edu .desc("Number of times an access to memory failed due to the cache being blocked"); 2402727Sktlim@umich.edu} 2412727Sktlim@umich.edu 2422727Sktlim@umich.edutemplate<class Impl> 2432727Sktlim@umich.eduvoid 2444329Sktlim@umich.eduLSQUnit<Impl>::setDcachePort(Port *dcache_port) 2454329Sktlim@umich.edu{ 2464329Sktlim@umich.edu dcachePort = dcache_port; 2474329Sktlim@umich.edu 2484329Sktlim@umich.edu#if USE_CHECKER 2494329Sktlim@umich.edu if (cpu->checker) { 2504329Sktlim@umich.edu cpu->checker->setDcachePort(dcachePort); 2514329Sktlim@umich.edu } 2524329Sktlim@umich.edu#endif 2534329Sktlim@umich.edu} 2544329Sktlim@umich.edu 2554329Sktlim@umich.edutemplate<class Impl> 2564329Sktlim@umich.eduvoid 2572292SN/ALSQUnit<Impl>::clearLQ() 2582292SN/A{ 2592292SN/A loadQueue.clear(); 2602292SN/A} 2612292SN/A 2622292SN/Atemplate<class Impl> 2632292SN/Avoid 2642292SN/ALSQUnit<Impl>::clearSQ() 2652292SN/A{ 2662292SN/A storeQueue.clear(); 2672292SN/A} 2682292SN/A 2692292SN/Atemplate<class Impl> 2702292SN/Avoid 2712307SN/ALSQUnit<Impl>::switchOut() 2722307SN/A{ 2732307SN/A switchedOut = true; 2742367SN/A for (int i = 0; i < loadQueue.size(); ++i) { 2752367SN/A assert(!loadQueue[i]); 2762307SN/A loadQueue[i] = NULL; 2772367SN/A } 2782307SN/A 2792329SN/A assert(storesToWB == 0); 2802307SN/A} 2812307SN/A 2822307SN/Atemplate<class Impl> 2832307SN/Avoid 2842307SN/ALSQUnit<Impl>::takeOverFrom() 2852307SN/A{ 2862307SN/A switchedOut = false; 2872307SN/A loads = stores = storesToWB = 0; 2882307SN/A 2892307SN/A loadHead = loadTail = 0; 2902307SN/A 2912307SN/A storeHead = storeWBIdx = storeTail = 0; 2922307SN/A 2932307SN/A usedPorts = 0; 2942307SN/A 2952329SN/A memDepViolator = NULL; 2962307SN/A 2972307SN/A blockedLoadSeqNum = 0; 2982307SN/A 2992307SN/A stalled = false; 3002307SN/A isLoadBlocked = false; 3012307SN/A loadBlockedHandled = false; 3028545Ssaidi@eecs.umich.edu 3038545Ssaidi@eecs.umich.edu // Just incase the memory system changed out from under us 3048545Ssaidi@eecs.umich.edu cacheBlockMask = 0; 3052307SN/A} 3062307SN/A 3072307SN/Atemplate<class Impl> 3082307SN/Avoid 3092292SN/ALSQUnit<Impl>::resizeLQ(unsigned size) 3102292SN/A{ 3112329SN/A unsigned size_plus_sentinel = size + 1; 3122329SN/A assert(size_plus_sentinel >= LQEntries); 3132292SN/A 3142329SN/A if (size_plus_sentinel > LQEntries) { 3152329SN/A while (size_plus_sentinel > loadQueue.size()) { 3162292SN/A DynInstPtr dummy; 3172292SN/A loadQueue.push_back(dummy); 3182292SN/A LQEntries++; 3192292SN/A } 3202292SN/A } else { 3212329SN/A LQEntries = size_plus_sentinel; 3222292SN/A } 3232292SN/A 3242292SN/A} 3252292SN/A 3262292SN/Atemplate<class Impl> 3272292SN/Avoid 3282292SN/ALSQUnit<Impl>::resizeSQ(unsigned size) 3292292SN/A{ 3302329SN/A unsigned size_plus_sentinel = size + 1; 3312329SN/A if (size_plus_sentinel > SQEntries) { 3322329SN/A while (size_plus_sentinel > storeQueue.size()) { 3332292SN/A SQEntry dummy; 3342292SN/A storeQueue.push_back(dummy); 3352292SN/A SQEntries++; 3362292SN/A } 3372292SN/A } else { 3382329SN/A SQEntries = size_plus_sentinel; 3392292SN/A } 3402292SN/A} 3412292SN/A 3422292SN/Atemplate <class Impl> 3432292SN/Avoid 3442292SN/ALSQUnit<Impl>::insert(DynInstPtr &inst) 3452292SN/A{ 3462292SN/A assert(inst->isMemRef()); 3472292SN/A 3482292SN/A assert(inst->isLoad() || inst->isStore()); 3492292SN/A 3502292SN/A if (inst->isLoad()) { 3512292SN/A insertLoad(inst); 3522292SN/A } else { 3532292SN/A insertStore(inst); 3542292SN/A } 3552292SN/A 3562292SN/A inst->setInLSQ(); 3572292SN/A} 3582292SN/A 3592292SN/Atemplate <class Impl> 3602292SN/Avoid 3612292SN/ALSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 3622292SN/A{ 3632329SN/A assert((loadTail + 1) % LQEntries != loadHead); 3642329SN/A assert(loads < LQEntries); 3652292SN/A 3667720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n", 3677720Sgblack@eecs.umich.edu load_inst->pcState(), loadTail, load_inst->seqNum); 3682292SN/A 3692292SN/A load_inst->lqIdx = loadTail; 3702292SN/A 3712292SN/A if (stores == 0) { 3722292SN/A load_inst->sqIdx = -1; 3732292SN/A } else { 3742292SN/A load_inst->sqIdx = storeTail; 3752292SN/A } 3762292SN/A 3772292SN/A loadQueue[loadTail] = load_inst; 3782292SN/A 3792292SN/A incrLdIdx(loadTail); 3802292SN/A 3812292SN/A ++loads; 3822292SN/A} 3832292SN/A 3842292SN/Atemplate <class Impl> 3852292SN/Avoid 3862292SN/ALSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 3872292SN/A{ 3882292SN/A // Make sure it is not full before inserting an instruction. 3892292SN/A assert((storeTail + 1) % SQEntries != storeHead); 3902292SN/A assert(stores < SQEntries); 3912292SN/A 3927720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n", 3937720Sgblack@eecs.umich.edu store_inst->pcState(), storeTail, store_inst->seqNum); 3942292SN/A 3952292SN/A store_inst->sqIdx = storeTail; 3962292SN/A store_inst->lqIdx = loadTail; 3972292SN/A 3982292SN/A storeQueue[storeTail] = SQEntry(store_inst); 3992292SN/A 4002292SN/A incrStIdx(storeTail); 4012292SN/A 4022292SN/A ++stores; 4032292SN/A} 4042292SN/A 4052292SN/Atemplate <class Impl> 4062292SN/Atypename Impl::DynInstPtr 4072292SN/ALSQUnit<Impl>::getMemDepViolator() 4082292SN/A{ 4092292SN/A DynInstPtr temp = memDepViolator; 4102292SN/A 4112292SN/A memDepViolator = NULL; 4122292SN/A 4132292SN/A return temp; 4142292SN/A} 4152292SN/A 4162292SN/Atemplate <class Impl> 4172292SN/Aunsigned 4182292SN/ALSQUnit<Impl>::numFreeEntries() 4192292SN/A{ 4202292SN/A unsigned free_lq_entries = LQEntries - loads; 4212292SN/A unsigned free_sq_entries = SQEntries - stores; 4222292SN/A 4232292SN/A // Both the LQ and SQ entries have an extra dummy entry to differentiate 4242292SN/A // empty/full conditions. Subtract 1 from the free entries. 4252292SN/A if (free_lq_entries < free_sq_entries) { 4262292SN/A return free_lq_entries - 1; 4272292SN/A } else { 4282292SN/A return free_sq_entries - 1; 4292292SN/A } 4302292SN/A} 4312292SN/A 4322292SN/Atemplate <class Impl> 4332292SN/Aint 4342292SN/ALSQUnit<Impl>::numLoadsReady() 4352292SN/A{ 4362292SN/A int load_idx = loadHead; 4372292SN/A int retval = 0; 4382292SN/A 4392292SN/A while (load_idx != loadTail) { 4402292SN/A assert(loadQueue[load_idx]); 4412292SN/A 4422292SN/A if (loadQueue[load_idx]->readyToIssue()) { 4432292SN/A ++retval; 4442292SN/A } 4452292SN/A } 4462292SN/A 4472292SN/A return retval; 4482292SN/A} 4492292SN/A 4502292SN/Atemplate <class Impl> 4518545Ssaidi@eecs.umich.eduvoid 4528545Ssaidi@eecs.umich.eduLSQUnit<Impl>::checkSnoop(PacketPtr pkt) 4538545Ssaidi@eecs.umich.edu{ 4548545Ssaidi@eecs.umich.edu int load_idx = loadHead; 4558545Ssaidi@eecs.umich.edu 4568545Ssaidi@eecs.umich.edu if (!cacheBlockMask) { 4578545Ssaidi@eecs.umich.edu assert(dcachePort); 4588545Ssaidi@eecs.umich.edu Addr bs = dcachePort->peerBlockSize(); 4598545Ssaidi@eecs.umich.edu 4608545Ssaidi@eecs.umich.edu // Make sure we actually got a size 4618545Ssaidi@eecs.umich.edu assert(bs != 0); 4628545Ssaidi@eecs.umich.edu 4638545Ssaidi@eecs.umich.edu cacheBlockMask = ~(bs - 1); 4648545Ssaidi@eecs.umich.edu } 4658545Ssaidi@eecs.umich.edu 4668545Ssaidi@eecs.umich.edu // If this is the only load in the LSQ we don't care 4678545Ssaidi@eecs.umich.edu if (load_idx == loadTail) 4688545Ssaidi@eecs.umich.edu return; 4698545Ssaidi@eecs.umich.edu incrLdIdx(load_idx); 4708545Ssaidi@eecs.umich.edu 4718545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr()); 4728545Ssaidi@eecs.umich.edu Addr invalidate_addr = pkt->getAddr() & cacheBlockMask; 4738545Ssaidi@eecs.umich.edu while (load_idx != loadTail) { 4748545Ssaidi@eecs.umich.edu DynInstPtr ld_inst = loadQueue[load_idx]; 4758545Ssaidi@eecs.umich.edu 4768545Ssaidi@eecs.umich.edu if (!ld_inst->effAddrValid || ld_inst->uncacheable()) { 4778545Ssaidi@eecs.umich.edu incrLdIdx(load_idx); 4788545Ssaidi@eecs.umich.edu continue; 4798545Ssaidi@eecs.umich.edu } 4808545Ssaidi@eecs.umich.edu 4818545Ssaidi@eecs.umich.edu Addr load_addr = ld_inst->physEffAddr & cacheBlockMask; 4828545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "-- inst [sn:%lli] load_addr: %#x to pktAddr:%#x\n", 4838545Ssaidi@eecs.umich.edu ld_inst->seqNum, load_addr, invalidate_addr); 4848545Ssaidi@eecs.umich.edu 4858545Ssaidi@eecs.umich.edu if (load_addr == invalidate_addr) { 4868545Ssaidi@eecs.umich.edu if (ld_inst->possibleLoadViolation) { 4878545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Conflicting load at addr %#x [sn:%lli]\n", 4888545Ssaidi@eecs.umich.edu ld_inst->physEffAddr, pkt->getAddr(), ld_inst->seqNum); 4898545Ssaidi@eecs.umich.edu 4908545Ssaidi@eecs.umich.edu // Mark the load for re-execution 4918545Ssaidi@eecs.umich.edu ld_inst->fault = new ReExec; 4928545Ssaidi@eecs.umich.edu } else { 4938545Ssaidi@eecs.umich.edu // If a older load checks this and it's true 4948545Ssaidi@eecs.umich.edu // then we might have missed the snoop 4958545Ssaidi@eecs.umich.edu // in which case we need to invalidate to be sure 4968545Ssaidi@eecs.umich.edu ld_inst->hitExternalSnoop = true; 4978545Ssaidi@eecs.umich.edu } 4988545Ssaidi@eecs.umich.edu } 4998545Ssaidi@eecs.umich.edu incrLdIdx(load_idx); 5008545Ssaidi@eecs.umich.edu } 5018545Ssaidi@eecs.umich.edu return; 5028545Ssaidi@eecs.umich.edu} 5038545Ssaidi@eecs.umich.edu 5048545Ssaidi@eecs.umich.edutemplate <class Impl> 5052292SN/AFault 5068199SAli.Saidi@ARM.comLSQUnit<Impl>::checkViolations(int load_idx, DynInstPtr &inst) 5078199SAli.Saidi@ARM.com{ 5088199SAli.Saidi@ARM.com Addr inst_eff_addr1 = inst->effAddr >> depCheckShift; 5098199SAli.Saidi@ARM.com Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift; 5108199SAli.Saidi@ARM.com 5118199SAli.Saidi@ARM.com /** @todo in theory you only need to check an instruction that has executed 5128199SAli.Saidi@ARM.com * however, there isn't a good way in the pipeline at the moment to check 5138199SAli.Saidi@ARM.com * all instructions that will execute before the store writes back. Thus, 5148199SAli.Saidi@ARM.com * like the implementation that came before it, we're overly conservative. 5158199SAli.Saidi@ARM.com */ 5168199SAli.Saidi@ARM.com while (load_idx != loadTail) { 5178199SAli.Saidi@ARM.com DynInstPtr ld_inst = loadQueue[load_idx]; 5188199SAli.Saidi@ARM.com if (!ld_inst->effAddrValid || ld_inst->uncacheable()) { 5198199SAli.Saidi@ARM.com incrLdIdx(load_idx); 5208199SAli.Saidi@ARM.com continue; 5218199SAli.Saidi@ARM.com } 5228199SAli.Saidi@ARM.com 5238199SAli.Saidi@ARM.com Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift; 5248199SAli.Saidi@ARM.com Addr ld_eff_addr2 = 5258199SAli.Saidi@ARM.com (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift; 5268199SAli.Saidi@ARM.com 5278272SAli.Saidi@ARM.com if (inst_eff_addr2 >= ld_eff_addr1 && inst_eff_addr1 <= ld_eff_addr2) { 5288545Ssaidi@eecs.umich.edu if (inst->isLoad()) { 5298545Ssaidi@eecs.umich.edu // If this load is to the same block as an external snoop 5308545Ssaidi@eecs.umich.edu // invalidate that we've observed then the load needs to be 5318545Ssaidi@eecs.umich.edu // squashed as it could have newer data 5328545Ssaidi@eecs.umich.edu if (ld_inst->hitExternalSnoop) { 5338545Ssaidi@eecs.umich.edu if (!memDepViolator || 5348545Ssaidi@eecs.umich.edu ld_inst->seqNum < memDepViolator->seqNum) { 5358545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] " 5368545Ssaidi@eecs.umich.edu " and [sn:%lli] at address %#x\n", inst->seqNum, 5378545Ssaidi@eecs.umich.edu ld_inst->seqNum, ld_eff_addr1); 5388545Ssaidi@eecs.umich.edu memDepViolator = ld_inst; 5398199SAli.Saidi@ARM.com 5408545Ssaidi@eecs.umich.edu ++lsqMemOrderViolation; 5418199SAli.Saidi@ARM.com 5428545Ssaidi@eecs.umich.edu return TheISA::genMachineCheckFault(); 5438545Ssaidi@eecs.umich.edu } 5448545Ssaidi@eecs.umich.edu } 5458199SAli.Saidi@ARM.com 5468545Ssaidi@eecs.umich.edu // Otherwise, mark the load has a possible load violation 5478545Ssaidi@eecs.umich.edu // and if we see a snoop before it's commited, we need to squash 5488545Ssaidi@eecs.umich.edu ld_inst->possibleLoadViolation = true; 5498545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Found possible load violaiton at addr: %#x" 5508545Ssaidi@eecs.umich.edu " between instructions [sn:%lli] and [sn:%lli]\n", 5518545Ssaidi@eecs.umich.edu inst_eff_addr1, inst->seqNum, ld_inst->seqNum); 5528545Ssaidi@eecs.umich.edu } else { 5538545Ssaidi@eecs.umich.edu // A load/store incorrectly passed this store. 5548545Ssaidi@eecs.umich.edu // Check if we already have a violator, or if it's newer 5558545Ssaidi@eecs.umich.edu // squash and refetch. 5568545Ssaidi@eecs.umich.edu if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum) 5578545Ssaidi@eecs.umich.edu break; 5588545Ssaidi@eecs.umich.edu 5598545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and [sn:%lli]" 5608545Ssaidi@eecs.umich.edu " at address %#x\n", inst->seqNum, ld_inst->seqNum, 5618545Ssaidi@eecs.umich.edu ld_eff_addr1); 5628545Ssaidi@eecs.umich.edu memDepViolator = ld_inst; 5638545Ssaidi@eecs.umich.edu 5648545Ssaidi@eecs.umich.edu ++lsqMemOrderViolation; 5658545Ssaidi@eecs.umich.edu 5668545Ssaidi@eecs.umich.edu return TheISA::genMachineCheckFault(); 5678545Ssaidi@eecs.umich.edu } 5688199SAli.Saidi@ARM.com } 5698199SAli.Saidi@ARM.com 5708199SAli.Saidi@ARM.com incrLdIdx(load_idx); 5718199SAli.Saidi@ARM.com } 5728199SAli.Saidi@ARM.com return NoFault; 5738199SAli.Saidi@ARM.com} 5748199SAli.Saidi@ARM.com 5758199SAli.Saidi@ARM.com 5768199SAli.Saidi@ARM.com 5778199SAli.Saidi@ARM.com 5788199SAli.Saidi@ARM.comtemplate <class Impl> 5798199SAli.Saidi@ARM.comFault 5802292SN/ALSQUnit<Impl>::executeLoad(DynInstPtr &inst) 5812292SN/A{ 5824032Sktlim@umich.edu using namespace TheISA; 5832292SN/A // Execute a specific load. 5842292SN/A Fault load_fault = NoFault; 5852292SN/A 5867720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n", 5877944SGiacomo.Gabrielli@arm.com inst->pcState(), inst->seqNum); 5882292SN/A 5894032Sktlim@umich.edu assert(!inst->isSquashed()); 5904032Sktlim@umich.edu 5912669Sktlim@umich.edu load_fault = inst->initiateAcc(); 5922292SN/A 5937944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 5947944SGiacomo.Gabrielli@arm.com load_fault == NoFault) 5957944SGiacomo.Gabrielli@arm.com return load_fault; 5967944SGiacomo.Gabrielli@arm.com 5977597Sminkyu.jeong@arm.com // If the instruction faulted or predicated false, then we need to send it 5987597Sminkyu.jeong@arm.com // along to commit without the instruction completing. 5997597Sminkyu.jeong@arm.com if (load_fault != NoFault || inst->readPredicate() == false) { 6002329SN/A // Send this instruction to commit, also make sure iew stage 6012329SN/A // realizes there is activity. 6022367SN/A // Mark it as executed unless it is an uncached load that 6032367SN/A // needs to hit the head of commit. 6047848SAli.Saidi@ARM.com if (inst->readPredicate() == false) 6057848SAli.Saidi@ARM.com inst->forwardOldRegs(); 6067600Sminkyu.jeong@arm.com DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", 6077600Sminkyu.jeong@arm.com inst->seqNum, 6087600Sminkyu.jeong@arm.com (load_fault != NoFault ? "fault" : "predication")); 6094032Sktlim@umich.edu if (!(inst->hasRequest() && inst->uncacheable()) || 6103731Sktlim@umich.edu inst->isAtCommit()) { 6112367SN/A inst->setExecuted(); 6122367SN/A } 6132292SN/A iewStage->instToCommit(inst); 6142292SN/A iewStage->activityThisCycle(); 6154032Sktlim@umich.edu } else if (!loadBlocked()) { 6164032Sktlim@umich.edu assert(inst->effAddrValid); 6174032Sktlim@umich.edu int load_idx = inst->lqIdx; 6184032Sktlim@umich.edu incrLdIdx(load_idx); 6194032Sktlim@umich.edu 6208199SAli.Saidi@ARM.com if (checkLoads) 6218199SAli.Saidi@ARM.com return checkViolations(load_idx, inst); 6222292SN/A } 6232292SN/A 6242292SN/A return load_fault; 6252292SN/A} 6262292SN/A 6272292SN/Atemplate <class Impl> 6282292SN/AFault 6292292SN/ALSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 6302292SN/A{ 6312292SN/A using namespace TheISA; 6322292SN/A // Make sure that a store exists. 6332292SN/A assert(stores != 0); 6342292SN/A 6352292SN/A int store_idx = store_inst->sqIdx; 6362292SN/A 6377720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n", 6387720Sgblack@eecs.umich.edu store_inst->pcState(), store_inst->seqNum); 6392292SN/A 6404032Sktlim@umich.edu assert(!store_inst->isSquashed()); 6414032Sktlim@umich.edu 6422292SN/A // Check the recently completed loads to see if any match this store's 6432292SN/A // address. If so, then we have a memory ordering violation. 6442292SN/A int load_idx = store_inst->lqIdx; 6452292SN/A 6462292SN/A Fault store_fault = store_inst->initiateAcc(); 6472292SN/A 6487944SGiacomo.Gabrielli@arm.com if (store_inst->isTranslationDelayed() && 6497944SGiacomo.Gabrielli@arm.com store_fault == NoFault) 6507944SGiacomo.Gabrielli@arm.com return store_fault; 6517944SGiacomo.Gabrielli@arm.com 6527848SAli.Saidi@ARM.com if (store_inst->readPredicate() == false) 6537848SAli.Saidi@ARM.com store_inst->forwardOldRegs(); 6547848SAli.Saidi@ARM.com 6552329SN/A if (storeQueue[store_idx].size == 0) { 6567782Sminkyu.jeong@arm.com DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", 6577720Sgblack@eecs.umich.edu store_inst->pcState(), store_inst->seqNum); 6582292SN/A 6592292SN/A return store_fault; 6607782Sminkyu.jeong@arm.com } else if (store_inst->readPredicate() == false) { 6617782Sminkyu.jeong@arm.com DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", 6627782Sminkyu.jeong@arm.com store_inst->seqNum); 6637782Sminkyu.jeong@arm.com return store_fault; 6642292SN/A } 6652292SN/A 6662292SN/A assert(store_fault == NoFault); 6672292SN/A 6682336SN/A if (store_inst->isStoreConditional()) { 6692336SN/A // Store conditionals need to set themselves as able to 6702336SN/A // writeback if we haven't had a fault by here. 6712329SN/A storeQueue[store_idx].canWB = true; 6722292SN/A 6732329SN/A ++storesToWB; 6742292SN/A } 6752292SN/A 6768199SAli.Saidi@ARM.com return checkViolations(load_idx, store_inst); 6772292SN/A 6782292SN/A} 6792292SN/A 6802292SN/Atemplate <class Impl> 6812292SN/Avoid 6822292SN/ALSQUnit<Impl>::commitLoad() 6832292SN/A{ 6842292SN/A assert(loadQueue[loadHead]); 6852292SN/A 6867720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n", 6877720Sgblack@eecs.umich.edu loadQueue[loadHead]->pcState()); 6882292SN/A 6892292SN/A loadQueue[loadHead] = NULL; 6902292SN/A 6912292SN/A incrLdIdx(loadHead); 6922292SN/A 6932292SN/A --loads; 6942292SN/A} 6952292SN/A 6962292SN/Atemplate <class Impl> 6972292SN/Avoid 6982292SN/ALSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 6992292SN/A{ 7002292SN/A assert(loads == 0 || loadQueue[loadHead]); 7012292SN/A 7022292SN/A while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 7032292SN/A commitLoad(); 7042292SN/A } 7052292SN/A} 7062292SN/A 7072292SN/Atemplate <class Impl> 7082292SN/Avoid 7092292SN/ALSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 7102292SN/A{ 7112292SN/A assert(stores == 0 || storeQueue[storeHead].inst); 7122292SN/A 7132292SN/A int store_idx = storeHead; 7142292SN/A 7152292SN/A while (store_idx != storeTail) { 7162292SN/A assert(storeQueue[store_idx].inst); 7172329SN/A // Mark any stores that are now committed and have not yet 7182329SN/A // been marked as able to write back. 7192292SN/A if (!storeQueue[store_idx].canWB) { 7202292SN/A if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 7212292SN/A break; 7222292SN/A } 7232292SN/A DPRINTF(LSQUnit, "Marking store as able to write back, PC " 7247720Sgblack@eecs.umich.edu "%s [sn:%lli]\n", 7257720Sgblack@eecs.umich.edu storeQueue[store_idx].inst->pcState(), 7262292SN/A storeQueue[store_idx].inst->seqNum); 7272292SN/A 7282292SN/A storeQueue[store_idx].canWB = true; 7292292SN/A 7302292SN/A ++storesToWB; 7312292SN/A } 7322292SN/A 7332292SN/A incrStIdx(store_idx); 7342292SN/A } 7352292SN/A} 7362292SN/A 7372292SN/Atemplate <class Impl> 7382292SN/Avoid 7396974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::writebackPendingStore() 7406974Stjones1@inf.ed.ac.uk{ 7416974Stjones1@inf.ed.ac.uk if (hasPendingPkt) { 7426974Stjones1@inf.ed.ac.uk assert(pendingPkt != NULL); 7436974Stjones1@inf.ed.ac.uk 7446974Stjones1@inf.ed.ac.uk // If the cache is blocked, this will store the packet for retry. 7456974Stjones1@inf.ed.ac.uk if (sendStore(pendingPkt)) { 7466974Stjones1@inf.ed.ac.uk storePostSend(pendingPkt); 7476974Stjones1@inf.ed.ac.uk } 7486974Stjones1@inf.ed.ac.uk pendingPkt = NULL; 7496974Stjones1@inf.ed.ac.uk hasPendingPkt = false; 7506974Stjones1@inf.ed.ac.uk } 7516974Stjones1@inf.ed.ac.uk} 7526974Stjones1@inf.ed.ac.uk 7536974Stjones1@inf.ed.ac.uktemplate <class Impl> 7546974Stjones1@inf.ed.ac.ukvoid 7552292SN/ALSQUnit<Impl>::writebackStores() 7562292SN/A{ 7576974Stjones1@inf.ed.ac.uk // First writeback the second packet from any split store that didn't 7586974Stjones1@inf.ed.ac.uk // complete last cycle because there weren't enough cache ports available. 7596974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc) { 7606974Stjones1@inf.ed.ac.uk writebackPendingStore(); 7616974Stjones1@inf.ed.ac.uk } 7626974Stjones1@inf.ed.ac.uk 7632292SN/A while (storesToWB > 0 && 7642292SN/A storeWBIdx != storeTail && 7652292SN/A storeQueue[storeWBIdx].inst && 7662292SN/A storeQueue[storeWBIdx].canWB && 7672292SN/A usedPorts < cachePorts) { 7682292SN/A 7692907Sktlim@umich.edu if (isStoreBlocked || lsq->cacheBlocked()) { 7702678Sktlim@umich.edu DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 7712678Sktlim@umich.edu " is blocked!\n"); 7722678Sktlim@umich.edu break; 7732678Sktlim@umich.edu } 7742678Sktlim@umich.edu 7752329SN/A // Store didn't write any data so no need to write it back to 7762329SN/A // memory. 7772292SN/A if (storeQueue[storeWBIdx].size == 0) { 7782292SN/A completeStore(storeWBIdx); 7792292SN/A 7802292SN/A incrStIdx(storeWBIdx); 7812292SN/A 7822292SN/A continue; 7832292SN/A } 7842678Sktlim@umich.edu 7852292SN/A ++usedPorts; 7862292SN/A 7872292SN/A if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 7882292SN/A incrStIdx(storeWBIdx); 7892292SN/A 7902292SN/A continue; 7912292SN/A } 7922292SN/A 7932292SN/A assert(storeQueue[storeWBIdx].req); 7942292SN/A assert(!storeQueue[storeWBIdx].committed); 7952292SN/A 7966974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 7976974Stjones1@inf.ed.ac.uk assert(storeQueue[storeWBIdx].sreqLow); 7986974Stjones1@inf.ed.ac.uk assert(storeQueue[storeWBIdx].sreqHigh); 7996974Stjones1@inf.ed.ac.uk } 8006974Stjones1@inf.ed.ac.uk 8012669Sktlim@umich.edu DynInstPtr inst = storeQueue[storeWBIdx].inst; 8022669Sktlim@umich.edu 8032669Sktlim@umich.edu Request *req = storeQueue[storeWBIdx].req; 8048481Sgblack@eecs.umich.edu RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow; 8058481Sgblack@eecs.umich.edu RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh; 8068481Sgblack@eecs.umich.edu 8072292SN/A storeQueue[storeWBIdx].committed = true; 8082292SN/A 8092669Sktlim@umich.edu assert(!inst->memData); 8102669Sktlim@umich.edu inst->memData = new uint8_t[64]; 8113772Sgblack@eecs.umich.edu 8124326Sgblack@eecs.umich.edu memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); 8132669Sktlim@umich.edu 8144878Sstever@eecs.umich.edu MemCmd command = 8154878Sstever@eecs.umich.edu req->isSwap() ? MemCmd::SwapReq : 8166102Sgblack@eecs.umich.edu (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq); 8176974Stjones1@inf.ed.ac.uk PacketPtr data_pkt; 8186974Stjones1@inf.ed.ac.uk PacketPtr snd_data_pkt = NULL; 8192292SN/A 8202678Sktlim@umich.edu LSQSenderState *state = new LSQSenderState; 8212678Sktlim@umich.edu state->isLoad = false; 8222678Sktlim@umich.edu state->idx = storeWBIdx; 8232678Sktlim@umich.edu state->inst = inst; 8246974Stjones1@inf.ed.ac.uk 8256974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) { 8266974Stjones1@inf.ed.ac.uk 8276974Stjones1@inf.ed.ac.uk // Build a single data packet if the store isn't split. 8286974Stjones1@inf.ed.ac.uk data_pkt = new Packet(req, command, Packet::Broadcast); 8296974Stjones1@inf.ed.ac.uk data_pkt->dataStatic(inst->memData); 8306974Stjones1@inf.ed.ac.uk data_pkt->senderState = state; 8316974Stjones1@inf.ed.ac.uk } else { 8326974Stjones1@inf.ed.ac.uk // Create two packets if the store is split in two. 8336974Stjones1@inf.ed.ac.uk data_pkt = new Packet(sreqLow, command, Packet::Broadcast); 8346974Stjones1@inf.ed.ac.uk snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast); 8356974Stjones1@inf.ed.ac.uk 8366974Stjones1@inf.ed.ac.uk data_pkt->dataStatic(inst->memData); 8376974Stjones1@inf.ed.ac.uk snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize()); 8386974Stjones1@inf.ed.ac.uk 8396974Stjones1@inf.ed.ac.uk data_pkt->senderState = state; 8406974Stjones1@inf.ed.ac.uk snd_data_pkt->senderState = state; 8416974Stjones1@inf.ed.ac.uk 8426974Stjones1@inf.ed.ac.uk state->isSplit = true; 8436974Stjones1@inf.ed.ac.uk state->outstanding = 2; 8446974Stjones1@inf.ed.ac.uk 8456974Stjones1@inf.ed.ac.uk // Can delete the main request now. 8466974Stjones1@inf.ed.ac.uk delete req; 8476974Stjones1@inf.ed.ac.uk req = sreqLow; 8486974Stjones1@inf.ed.ac.uk } 8492678Sktlim@umich.edu 8507720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s " 8512292SN/A "to Addr:%#x, data:%#x [sn:%lli]\n", 8527720Sgblack@eecs.umich.edu storeWBIdx, inst->pcState(), 8533797Sgblack@eecs.umich.edu req->getPaddr(), (int)*(inst->memData), 8543221Sktlim@umich.edu inst->seqNum); 8552292SN/A 8562693Sktlim@umich.edu // @todo: Remove this SC hack once the memory system handles it. 8574350Sgblack@eecs.umich.edu if (inst->isStoreConditional()) { 8586974Stjones1@inf.ed.ac.uk assert(!storeQueue[storeWBIdx].isSplit); 8593326Sktlim@umich.edu // Disable recording the result temporarily. Writing to 8603326Sktlim@umich.edu // misc regs normally updates the result, but this is not 8613326Sktlim@umich.edu // the desired behavior when handling store conditionals. 8623326Sktlim@umich.edu inst->recordResult = false; 8633326Sktlim@umich.edu bool success = TheISA::handleLockedWrite(inst.get(), req); 8643326Sktlim@umich.edu inst->recordResult = true; 8653326Sktlim@umich.edu 8663326Sktlim@umich.edu if (!success) { 8673326Sktlim@umich.edu // Instantly complete this store. 8683326Sktlim@umich.edu DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 8693326Sktlim@umich.edu "Instantly completing it.\n", 8703326Sktlim@umich.edu inst->seqNum); 8713326Sktlim@umich.edu WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 8727823Ssteve.reinhardt@amd.com cpu->schedule(wb, curTick() + 1); 8733326Sktlim@umich.edu completeStore(storeWBIdx); 8743326Sktlim@umich.edu incrStIdx(storeWBIdx); 8753326Sktlim@umich.edu continue; 8762693Sktlim@umich.edu } 8772693Sktlim@umich.edu } else { 8782693Sktlim@umich.edu // Non-store conditionals do not need a writeback. 8792693Sktlim@umich.edu state->noWB = true; 8802693Sktlim@umich.edu } 8812693Sktlim@umich.edu 8828481Sgblack@eecs.umich.edu bool split = 8838481Sgblack@eecs.umich.edu TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit; 8848481Sgblack@eecs.umich.edu 8858481Sgblack@eecs.umich.edu ThreadContext *thread = cpu->tcBase(lsqID); 8868481Sgblack@eecs.umich.edu 8878481Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 8888481Sgblack@eecs.umich.edu assert(!inst->isStoreConditional()); 8898481Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread, data_pkt); 8908481Sgblack@eecs.umich.edu delete data_pkt; 8918481Sgblack@eecs.umich.edu if (split) { 8928481Sgblack@eecs.umich.edu assert(snd_data_pkt->req->isMmappedIpr()); 8938481Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread, snd_data_pkt); 8948481Sgblack@eecs.umich.edu delete snd_data_pkt; 8958481Sgblack@eecs.umich.edu delete sreqLow; 8968481Sgblack@eecs.umich.edu delete sreqHigh; 8978481Sgblack@eecs.umich.edu } 8988481Sgblack@eecs.umich.edu delete state; 8998481Sgblack@eecs.umich.edu delete req; 9008481Sgblack@eecs.umich.edu completeStore(storeWBIdx); 9018481Sgblack@eecs.umich.edu incrStIdx(storeWBIdx); 9028481Sgblack@eecs.umich.edu } else if (!sendStore(data_pkt)) { 9034032Sktlim@umich.edu DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 9043221Sktlim@umich.edu "retry later\n", 9053221Sktlim@umich.edu inst->seqNum); 9066974Stjones1@inf.ed.ac.uk 9076974Stjones1@inf.ed.ac.uk // Need to store the second packet, if split. 9088481Sgblack@eecs.umich.edu if (split) { 9096974Stjones1@inf.ed.ac.uk state->pktToSend = true; 9106974Stjones1@inf.ed.ac.uk state->pendingPacket = snd_data_pkt; 9116974Stjones1@inf.ed.ac.uk } 9122669Sktlim@umich.edu } else { 9136974Stjones1@inf.ed.ac.uk 9146974Stjones1@inf.ed.ac.uk // If split, try to send the second packet too 9158481Sgblack@eecs.umich.edu if (split) { 9166974Stjones1@inf.ed.ac.uk assert(snd_data_pkt); 9176974Stjones1@inf.ed.ac.uk 9186974Stjones1@inf.ed.ac.uk // Ensure there are enough ports to use. 9196974Stjones1@inf.ed.ac.uk if (usedPorts < cachePorts) { 9206974Stjones1@inf.ed.ac.uk ++usedPorts; 9216974Stjones1@inf.ed.ac.uk if (sendStore(snd_data_pkt)) { 9226974Stjones1@inf.ed.ac.uk storePostSend(snd_data_pkt); 9236974Stjones1@inf.ed.ac.uk } else { 9246974Stjones1@inf.ed.ac.uk DPRINTF(IEW, "D-Cache became blocked when writing" 9256974Stjones1@inf.ed.ac.uk " [sn:%lli] second packet, will retry later\n", 9266974Stjones1@inf.ed.ac.uk inst->seqNum); 9276974Stjones1@inf.ed.ac.uk } 9286974Stjones1@inf.ed.ac.uk } else { 9296974Stjones1@inf.ed.ac.uk 9306974Stjones1@inf.ed.ac.uk // Store the packet for when there's free ports. 9316974Stjones1@inf.ed.ac.uk assert(pendingPkt == NULL); 9326974Stjones1@inf.ed.ac.uk pendingPkt = snd_data_pkt; 9336974Stjones1@inf.ed.ac.uk hasPendingPkt = true; 9346974Stjones1@inf.ed.ac.uk } 9356974Stjones1@inf.ed.ac.uk } else { 9366974Stjones1@inf.ed.ac.uk 9376974Stjones1@inf.ed.ac.uk // Not a split store. 9386974Stjones1@inf.ed.ac.uk storePostSend(data_pkt); 9396974Stjones1@inf.ed.ac.uk } 9402292SN/A } 9412292SN/A } 9422292SN/A 9432292SN/A // Not sure this should set it to 0. 9442292SN/A usedPorts = 0; 9452292SN/A 9462292SN/A assert(stores >= 0 && storesToWB >= 0); 9472292SN/A} 9482292SN/A 9492292SN/A/*template <class Impl> 9502292SN/Avoid 9512292SN/ALSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 9522292SN/A{ 9532292SN/A list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 9542292SN/A mshrSeqNums.end(), 9552292SN/A seqNum); 9562292SN/A 9572292SN/A if (mshr_it != mshrSeqNums.end()) { 9582292SN/A mshrSeqNums.erase(mshr_it); 9592292SN/A DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 9602292SN/A } 9612292SN/A}*/ 9622292SN/A 9632292SN/Atemplate <class Impl> 9642292SN/Avoid 9652292SN/ALSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 9662292SN/A{ 9672292SN/A DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 9682329SN/A "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 9692292SN/A 9702292SN/A int load_idx = loadTail; 9712292SN/A decrLdIdx(load_idx); 9722292SN/A 9732292SN/A while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 9747720Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"Load Instruction PC %s squashed, " 9752292SN/A "[sn:%lli]\n", 9767720Sgblack@eecs.umich.edu loadQueue[load_idx]->pcState(), 9772292SN/A loadQueue[load_idx]->seqNum); 9782292SN/A 9792292SN/A if (isStalled() && load_idx == stallingLoadIdx) { 9802292SN/A stalled = false; 9812292SN/A stallingStoreIsn = 0; 9822292SN/A stallingLoadIdx = 0; 9832292SN/A } 9842292SN/A 9852329SN/A // Clear the smart pointer to make sure it is decremented. 9862731Sktlim@umich.edu loadQueue[load_idx]->setSquashed(); 9872292SN/A loadQueue[load_idx] = NULL; 9882292SN/A --loads; 9892292SN/A 9902292SN/A // Inefficient! 9912292SN/A loadTail = load_idx; 9922292SN/A 9932292SN/A decrLdIdx(load_idx); 9942727Sktlim@umich.edu ++lsqSquashedLoads; 9952292SN/A } 9962292SN/A 9972292SN/A if (isLoadBlocked) { 9982292SN/A if (squashed_num < blockedLoadSeqNum) { 9992292SN/A isLoadBlocked = false; 10002292SN/A loadBlockedHandled = false; 10012292SN/A blockedLoadSeqNum = 0; 10022292SN/A } 10032292SN/A } 10042292SN/A 10054032Sktlim@umich.edu if (memDepViolator && squashed_num < memDepViolator->seqNum) { 10064032Sktlim@umich.edu memDepViolator = NULL; 10074032Sktlim@umich.edu } 10084032Sktlim@umich.edu 10092292SN/A int store_idx = storeTail; 10102292SN/A decrStIdx(store_idx); 10112292SN/A 10122292SN/A while (stores != 0 && 10132292SN/A storeQueue[store_idx].inst->seqNum > squashed_num) { 10142329SN/A // Instructions marked as can WB are already committed. 10152292SN/A if (storeQueue[store_idx].canWB) { 10162292SN/A break; 10172292SN/A } 10182292SN/A 10197720Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"Store Instruction PC %s squashed, " 10202292SN/A "idx:%i [sn:%lli]\n", 10217720Sgblack@eecs.umich.edu storeQueue[store_idx].inst->pcState(), 10222292SN/A store_idx, storeQueue[store_idx].inst->seqNum); 10232292SN/A 10242329SN/A // I don't think this can happen. It should have been cleared 10252329SN/A // by the stalling load. 10262292SN/A if (isStalled() && 10272292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 10282292SN/A panic("Is stalled should have been cleared by stalling load!\n"); 10292292SN/A stalled = false; 10302292SN/A stallingStoreIsn = 0; 10312292SN/A } 10322292SN/A 10332329SN/A // Clear the smart pointer to make sure it is decremented. 10342731Sktlim@umich.edu storeQueue[store_idx].inst->setSquashed(); 10352292SN/A storeQueue[store_idx].inst = NULL; 10362292SN/A storeQueue[store_idx].canWB = 0; 10372292SN/A 10384032Sktlim@umich.edu // Must delete request now that it wasn't handed off to 10394032Sktlim@umich.edu // memory. This is quite ugly. @todo: Figure out the proper 10404032Sktlim@umich.edu // place to really handle request deletes. 10414032Sktlim@umich.edu delete storeQueue[store_idx].req; 10426974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) { 10436974Stjones1@inf.ed.ac.uk delete storeQueue[store_idx].sreqLow; 10446974Stjones1@inf.ed.ac.uk delete storeQueue[store_idx].sreqHigh; 10456974Stjones1@inf.ed.ac.uk 10466974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqLow = NULL; 10476974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqHigh = NULL; 10486974Stjones1@inf.ed.ac.uk } 10494032Sktlim@umich.edu 10502292SN/A storeQueue[store_idx].req = NULL; 10512292SN/A --stores; 10522292SN/A 10532292SN/A // Inefficient! 10542292SN/A storeTail = store_idx; 10552292SN/A 10562292SN/A decrStIdx(store_idx); 10572727Sktlim@umich.edu ++lsqSquashedStores; 10582292SN/A } 10592292SN/A} 10602292SN/A 10612292SN/Atemplate <class Impl> 10622292SN/Avoid 10633349Sbinkertn@umich.eduLSQUnit<Impl>::storePostSend(PacketPtr pkt) 10642693Sktlim@umich.edu{ 10652693Sktlim@umich.edu if (isStalled() && 10662693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 10672693Sktlim@umich.edu DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 10682693Sktlim@umich.edu "load idx:%i\n", 10692693Sktlim@umich.edu stallingStoreIsn, stallingLoadIdx); 10702693Sktlim@umich.edu stalled = false; 10712693Sktlim@umich.edu stallingStoreIsn = 0; 10722693Sktlim@umich.edu iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 10732693Sktlim@umich.edu } 10742693Sktlim@umich.edu 10752693Sktlim@umich.edu if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 10762693Sktlim@umich.edu // The store is basically completed at this time. This 10772693Sktlim@umich.edu // only works so long as the checker doesn't try to 10782693Sktlim@umich.edu // verify the value in memory for stores. 10792693Sktlim@umich.edu storeQueue[storeWBIdx].inst->setCompleted(); 10802733Sktlim@umich.edu#if USE_CHECKER 10812693Sktlim@umich.edu if (cpu->checker) { 10822732Sktlim@umich.edu cpu->checker->verify(storeQueue[storeWBIdx].inst); 10832693Sktlim@umich.edu } 10842733Sktlim@umich.edu#endif 10852693Sktlim@umich.edu } 10862693Sktlim@umich.edu 10872693Sktlim@umich.edu incrStIdx(storeWBIdx); 10882693Sktlim@umich.edu} 10892693Sktlim@umich.edu 10902693Sktlim@umich.edutemplate <class Impl> 10912693Sktlim@umich.eduvoid 10922678Sktlim@umich.eduLSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 10932678Sktlim@umich.edu{ 10942678Sktlim@umich.edu iewStage->wakeCPU(); 10952678Sktlim@umich.edu 10962678Sktlim@umich.edu // Squashed instructions do not need to complete their access. 10972678Sktlim@umich.edu if (inst->isSquashed()) { 10982927Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 10992678Sktlim@umich.edu assert(!inst->isStore()); 11002727Sktlim@umich.edu ++lsqIgnoredResponses; 11012678Sktlim@umich.edu return; 11022678Sktlim@umich.edu } 11032678Sktlim@umich.edu 11042678Sktlim@umich.edu if (!inst->isExecuted()) { 11052678Sktlim@umich.edu inst->setExecuted(); 11062678Sktlim@umich.edu 11072678Sktlim@umich.edu // Complete access to copy data to proper place. 11082678Sktlim@umich.edu inst->completeAcc(pkt); 11092678Sktlim@umich.edu } 11102678Sktlim@umich.edu 11112678Sktlim@umich.edu // Need to insert instruction into queue to commit 11122678Sktlim@umich.edu iewStage->instToCommit(inst); 11132678Sktlim@umich.edu 11142678Sktlim@umich.edu iewStage->activityThisCycle(); 11157598Sminkyu.jeong@arm.com 11167598Sminkyu.jeong@arm.com // see if this load changed the PC 11177598Sminkyu.jeong@arm.com iewStage->checkMisprediction(inst); 11182678Sktlim@umich.edu} 11192678Sktlim@umich.edu 11202678Sktlim@umich.edutemplate <class Impl> 11212678Sktlim@umich.eduvoid 11222292SN/ALSQUnit<Impl>::completeStore(int store_idx) 11232292SN/A{ 11242292SN/A assert(storeQueue[store_idx].inst); 11252292SN/A storeQueue[store_idx].completed = true; 11262292SN/A --storesToWB; 11272292SN/A // A bit conservative because a store completion may not free up entries, 11282292SN/A // but hopefully avoids two store completions in one cycle from making 11292292SN/A // the CPU tick twice. 11303126Sktlim@umich.edu cpu->wakeCPU(); 11312292SN/A cpu->activityThisCycle(); 11322292SN/A 11332292SN/A if (store_idx == storeHead) { 11342292SN/A do { 11352292SN/A incrStIdx(storeHead); 11362292SN/A 11372292SN/A --stores; 11382292SN/A } while (storeQueue[storeHead].completed && 11392292SN/A storeHead != storeTail); 11402292SN/A 11412292SN/A iewStage->updateLSQNextCycle = true; 11422292SN/A } 11432292SN/A 11442329SN/A DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 11452329SN/A "idx:%i\n", 11462329SN/A storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 11472292SN/A 11482292SN/A if (isStalled() && 11492292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 11502292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 11512292SN/A "load idx:%i\n", 11522292SN/A stallingStoreIsn, stallingLoadIdx); 11532292SN/A stalled = false; 11542292SN/A stallingStoreIsn = 0; 11552292SN/A iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 11562292SN/A } 11572316SN/A 11582316SN/A storeQueue[store_idx].inst->setCompleted(); 11592329SN/A 11602329SN/A // Tell the checker we've completed this instruction. Some stores 11612329SN/A // may get reported twice to the checker, but the checker can 11622329SN/A // handle that case. 11632733Sktlim@umich.edu#if USE_CHECKER 11642316SN/A if (cpu->checker) { 11652732Sktlim@umich.edu cpu->checker->verify(storeQueue[store_idx].inst); 11662316SN/A } 11672733Sktlim@umich.edu#endif 11682292SN/A} 11692292SN/A 11702292SN/Atemplate <class Impl> 11716974Stjones1@inf.ed.ac.ukbool 11726974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::sendStore(PacketPtr data_pkt) 11736974Stjones1@inf.ed.ac.uk{ 11746974Stjones1@inf.ed.ac.uk if (!dcachePort->sendTiming(data_pkt)) { 11756974Stjones1@inf.ed.ac.uk // Need to handle becoming blocked on a store. 11766974Stjones1@inf.ed.ac.uk isStoreBlocked = true; 11776974Stjones1@inf.ed.ac.uk ++lsqCacheBlocked; 11786974Stjones1@inf.ed.ac.uk assert(retryPkt == NULL); 11796974Stjones1@inf.ed.ac.uk retryPkt = data_pkt; 11806974Stjones1@inf.ed.ac.uk lsq->setRetryTid(lsqID); 11816974Stjones1@inf.ed.ac.uk return false; 11826974Stjones1@inf.ed.ac.uk } 11836974Stjones1@inf.ed.ac.uk return true; 11846974Stjones1@inf.ed.ac.uk} 11856974Stjones1@inf.ed.ac.uk 11866974Stjones1@inf.ed.ac.uktemplate <class Impl> 11872693Sktlim@umich.eduvoid 11882693Sktlim@umich.eduLSQUnit<Impl>::recvRetry() 11892693Sktlim@umich.edu{ 11902698Sktlim@umich.edu if (isStoreBlocked) { 11914985Sktlim@umich.edu DPRINTF(LSQUnit, "Receiving retry: store blocked\n"); 11922698Sktlim@umich.edu assert(retryPkt != NULL); 11932693Sktlim@umich.edu 11948587Snilay@cs.wisc.edu LSQSenderState *state = 11958587Snilay@cs.wisc.edu dynamic_cast<LSQSenderState *>(retryPkt->senderState); 11968587Snilay@cs.wisc.edu 11972698Sktlim@umich.edu if (dcachePort->sendTiming(retryPkt)) { 11986974Stjones1@inf.ed.ac.uk // Don't finish the store unless this is the last packet. 11998133SAli.Saidi@ARM.com if (!TheISA::HasUnalignedMemAcc || !state->pktToSend || 12008133SAli.Saidi@ARM.com state->pendingPacket == retryPkt) { 12018133SAli.Saidi@ARM.com state->pktToSend = false; 12026974Stjones1@inf.ed.ac.uk storePostSend(retryPkt); 12036974Stjones1@inf.ed.ac.uk } 12042699Sktlim@umich.edu retryPkt = NULL; 12052693Sktlim@umich.edu isStoreBlocked = false; 12066221Snate@binkert.org lsq->setRetryTid(InvalidThreadID); 12076974Stjones1@inf.ed.ac.uk 12086974Stjones1@inf.ed.ac.uk // Send any outstanding packet. 12096974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && state->pktToSend) { 12106974Stjones1@inf.ed.ac.uk assert(state->pendingPacket); 12116974Stjones1@inf.ed.ac.uk if (sendStore(state->pendingPacket)) { 12126974Stjones1@inf.ed.ac.uk storePostSend(state->pendingPacket); 12136974Stjones1@inf.ed.ac.uk } 12146974Stjones1@inf.ed.ac.uk } 12152693Sktlim@umich.edu } else { 12162693Sktlim@umich.edu // Still blocked! 12172727Sktlim@umich.edu ++lsqCacheBlocked; 12182907Sktlim@umich.edu lsq->setRetryTid(lsqID); 12192693Sktlim@umich.edu } 12202693Sktlim@umich.edu } else if (isLoadBlocked) { 12212693Sktlim@umich.edu DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 12222693Sktlim@umich.edu "no need to resend packet.\n"); 12232693Sktlim@umich.edu } else { 12242693Sktlim@umich.edu DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 12252693Sktlim@umich.edu } 12262693Sktlim@umich.edu} 12272693Sktlim@umich.edu 12282693Sktlim@umich.edutemplate <class Impl> 12292292SN/Ainline void 12302292SN/ALSQUnit<Impl>::incrStIdx(int &store_idx) 12312292SN/A{ 12322292SN/A if (++store_idx >= SQEntries) 12332292SN/A store_idx = 0; 12342292SN/A} 12352292SN/A 12362292SN/Atemplate <class Impl> 12372292SN/Ainline void 12382292SN/ALSQUnit<Impl>::decrStIdx(int &store_idx) 12392292SN/A{ 12402292SN/A if (--store_idx < 0) 12412292SN/A store_idx += SQEntries; 12422292SN/A} 12432292SN/A 12442292SN/Atemplate <class Impl> 12452292SN/Ainline void 12462292SN/ALSQUnit<Impl>::incrLdIdx(int &load_idx) 12472292SN/A{ 12482292SN/A if (++load_idx >= LQEntries) 12492292SN/A load_idx = 0; 12502292SN/A} 12512292SN/A 12522292SN/Atemplate <class Impl> 12532292SN/Ainline void 12542292SN/ALSQUnit<Impl>::decrLdIdx(int &load_idx) 12552292SN/A{ 12562292SN/A if (--load_idx < 0) 12572292SN/A load_idx += LQEntries; 12582292SN/A} 12592329SN/A 12602329SN/Atemplate <class Impl> 12612329SN/Avoid 12622329SN/ALSQUnit<Impl>::dumpInsts() 12632329SN/A{ 12642329SN/A cprintf("Load store queue: Dumping instructions.\n"); 12652329SN/A cprintf("Load queue size: %i\n", loads); 12662329SN/A cprintf("Load queue: "); 12672329SN/A 12682329SN/A int load_idx = loadHead; 12692329SN/A 12702329SN/A while (load_idx != loadTail && loadQueue[load_idx]) { 12717720Sgblack@eecs.umich.edu cprintf("%s ", loadQueue[load_idx]->pcState()); 12722329SN/A 12732329SN/A incrLdIdx(load_idx); 12742329SN/A } 12752329SN/A 12762329SN/A cprintf("Store queue size: %i\n", stores); 12772329SN/A cprintf("Store queue: "); 12782329SN/A 12792329SN/A int store_idx = storeHead; 12802329SN/A 12812329SN/A while (store_idx != storeTail && storeQueue[store_idx].inst) { 12827720Sgblack@eecs.umich.edu cprintf("%s ", storeQueue[store_idx].inst->pcState()); 12832329SN/A 12842329SN/A incrStIdx(store_idx); 12852329SN/A } 12862329SN/A 12872329SN/A cprintf("\n"); 12882329SN/A} 1289