lsq_unit_impl.hh revision 4318
12292SN/A/* 22292SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32292SN/A * All rights reserved. 42292SN/A * 52292SN/A * Redistribution and use in source and binary forms, with or without 62292SN/A * modification, are permitted provided that the following conditions are 72292SN/A * met: redistributions of source code must retain the above copyright 82292SN/A * notice, this list of conditions and the following disclaimer; 92292SN/A * redistributions in binary form must reproduce the above copyright 102292SN/A * notice, this list of conditions and the following disclaimer in the 112292SN/A * documentation and/or other materials provided with the distribution; 122292SN/A * neither the name of the copyright holders nor the names of its 132292SN/A * contributors may be used to endorse or promote products derived from 142292SN/A * this software without specific prior written permission. 152292SN/A * 162292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292689Sktlim@umich.edu * Korey Sewell 302292SN/A */ 312292SN/A 323326Sktlim@umich.edu#include "arch/locked_mem.hh" 332733Sktlim@umich.edu#include "config/use_checker.hh" 342733Sktlim@umich.edu 352907Sktlim@umich.edu#include "cpu/o3/lsq.hh" 362292SN/A#include "cpu/o3/lsq_unit.hh" 372292SN/A#include "base/str.hh" 382722Sktlim@umich.edu#include "mem/packet.hh" 392669Sktlim@umich.edu#include "mem/request.hh" 402292SN/A 412790Sktlim@umich.edu#if USE_CHECKER 422790Sktlim@umich.edu#include "cpu/checker/cpu.hh" 432790Sktlim@umich.edu#endif 442790Sktlim@umich.edu 452669Sktlim@umich.edutemplate<class Impl> 462678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 472678Sktlim@umich.edu LSQUnit *lsq_ptr) 482678Sktlim@umich.edu : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 492292SN/A{ 502678Sktlim@umich.edu this->setFlags(Event::AutoDelete); 512292SN/A} 522292SN/A 532669Sktlim@umich.edutemplate<class Impl> 542292SN/Avoid 552678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::process() 562292SN/A{ 572678Sktlim@umich.edu if (!lsqPtr->isSwitchedOut()) { 582678Sktlim@umich.edu lsqPtr->writeback(inst, pkt); 592678Sktlim@umich.edu } 602678Sktlim@umich.edu delete pkt; 612678Sktlim@umich.edu} 622292SN/A 632678Sktlim@umich.edutemplate<class Impl> 642678Sktlim@umich.educonst char * 652678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::description() 662678Sktlim@umich.edu{ 672678Sktlim@umich.edu return "Store writeback event"; 682678Sktlim@umich.edu} 692292SN/A 702678Sktlim@umich.edutemplate<class Impl> 712678Sktlim@umich.eduvoid 722678Sktlim@umich.eduLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 732678Sktlim@umich.edu{ 742678Sktlim@umich.edu LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 752678Sktlim@umich.edu DynInstPtr inst = state->inst; 762678Sktlim@umich.edu DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum); 772698Sktlim@umich.edu DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum); 782344SN/A 792678Sktlim@umich.edu //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 802678Sktlim@umich.edu 812678Sktlim@umich.edu if (isSwitchedOut() || inst->isSquashed()) { 822820Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 832678Sktlim@umich.edu delete state; 844032Sktlim@umich.edu delete pkt->req; 852678Sktlim@umich.edu delete pkt; 862307SN/A return; 872678Sktlim@umich.edu } else { 882678Sktlim@umich.edu if (!state->noWB) { 892678Sktlim@umich.edu writeback(inst, pkt); 902678Sktlim@umich.edu } 912678Sktlim@umich.edu 922678Sktlim@umich.edu if (inst->isStore()) { 932678Sktlim@umich.edu completeStore(state->idx); 942678Sktlim@umich.edu } 952344SN/A } 962307SN/A 972678Sktlim@umich.edu delete state; 984032Sktlim@umich.edu delete pkt->req; 992678Sktlim@umich.edu delete pkt; 1002292SN/A} 1012292SN/A 1022292SN/Atemplate <class Impl> 1032292SN/ALSQUnit<Impl>::LSQUnit() 1042678Sktlim@umich.edu : loads(0), stores(0), storesToWB(0), stalled(false), 1052678Sktlim@umich.edu isStoreBlocked(false), isLoadBlocked(false), 1062292SN/A loadBlockedHandled(false) 1072292SN/A{ 1082292SN/A} 1092292SN/A 1102292SN/Atemplate<class Impl> 1112292SN/Avoid 1122907Sktlim@umich.eduLSQUnit<Impl>::init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries, 1132292SN/A unsigned maxSQEntries, unsigned id) 1142292SN/A{ 1154318Sktlim@umich.edu// DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 1162292SN/A 1172307SN/A switchedOut = false; 1182307SN/A 1192907Sktlim@umich.edu lsq = lsq_ptr; 1202907Sktlim@umich.edu 1212292SN/A lsqID = id; 1222292SN/A 1232329SN/A // Add 1 for the sentinel entry (they are circular queues). 1242329SN/A LQEntries = maxLQEntries + 1; 1252329SN/A SQEntries = maxSQEntries + 1; 1262292SN/A 1272292SN/A loadQueue.resize(LQEntries); 1282292SN/A storeQueue.resize(SQEntries); 1292292SN/A 1302292SN/A loadHead = loadTail = 0; 1312292SN/A 1322292SN/A storeHead = storeWBIdx = storeTail = 0; 1332292SN/A 1342292SN/A usedPorts = 0; 1352292SN/A cachePorts = params->cachePorts; 1362292SN/A 1373492Sktlim@umich.edu retryPkt = NULL; 1382329SN/A memDepViolator = NULL; 1392292SN/A 1402292SN/A blockedLoadSeqNum = 0; 1412292SN/A} 1422292SN/A 1432292SN/Atemplate<class Impl> 1442669Sktlim@umich.eduvoid 1452733Sktlim@umich.eduLSQUnit<Impl>::setCPU(O3CPU *cpu_ptr) 1462669Sktlim@umich.edu{ 1472669Sktlim@umich.edu cpu = cpu_ptr; 1482678Sktlim@umich.edu 1492733Sktlim@umich.edu#if USE_CHECKER 1502679Sktlim@umich.edu if (cpu->checker) { 1512679Sktlim@umich.edu cpu->checker->setDcachePort(dcachePort); 1522679Sktlim@umich.edu } 1532733Sktlim@umich.edu#endif 1542669Sktlim@umich.edu} 1552669Sktlim@umich.edu 1562669Sktlim@umich.edutemplate<class Impl> 1572292SN/Astd::string 1582292SN/ALSQUnit<Impl>::name() const 1592292SN/A{ 1602292SN/A if (Impl::MaxThreads == 1) { 1612292SN/A return iewStage->name() + ".lsq"; 1622292SN/A } else { 1632292SN/A return iewStage->name() + ".lsq.thread." + to_string(lsqID); 1642292SN/A } 1652292SN/A} 1662292SN/A 1672292SN/Atemplate<class Impl> 1682292SN/Avoid 1692727Sktlim@umich.eduLSQUnit<Impl>::regStats() 1702727Sktlim@umich.edu{ 1712727Sktlim@umich.edu lsqForwLoads 1722727Sktlim@umich.edu .name(name() + ".forwLoads") 1732727Sktlim@umich.edu .desc("Number of loads that had data forwarded from stores"); 1742727Sktlim@umich.edu 1752727Sktlim@umich.edu invAddrLoads 1762727Sktlim@umich.edu .name(name() + ".invAddrLoads") 1772727Sktlim@umich.edu .desc("Number of loads ignored due to an invalid address"); 1782727Sktlim@umich.edu 1792727Sktlim@umich.edu lsqSquashedLoads 1802727Sktlim@umich.edu .name(name() + ".squashedLoads") 1812727Sktlim@umich.edu .desc("Number of loads squashed"); 1822727Sktlim@umich.edu 1832727Sktlim@umich.edu lsqIgnoredResponses 1842727Sktlim@umich.edu .name(name() + ".ignoredResponses") 1852727Sktlim@umich.edu .desc("Number of memory responses ignored because the instruction is squashed"); 1862727Sktlim@umich.edu 1872361SN/A lsqMemOrderViolation 1882361SN/A .name(name() + ".memOrderViolation") 1892361SN/A .desc("Number of memory ordering violations"); 1902361SN/A 1912727Sktlim@umich.edu lsqSquashedStores 1922727Sktlim@umich.edu .name(name() + ".squashedStores") 1932727Sktlim@umich.edu .desc("Number of stores squashed"); 1942727Sktlim@umich.edu 1952727Sktlim@umich.edu invAddrSwpfs 1962727Sktlim@umich.edu .name(name() + ".invAddrSwpfs") 1972727Sktlim@umich.edu .desc("Number of software prefetches ignored due to an invalid address"); 1982727Sktlim@umich.edu 1992727Sktlim@umich.edu lsqBlockedLoads 2002727Sktlim@umich.edu .name(name() + ".blockedLoads") 2012727Sktlim@umich.edu .desc("Number of blocked loads due to partial load-store forwarding"); 2022727Sktlim@umich.edu 2032727Sktlim@umich.edu lsqRescheduledLoads 2042727Sktlim@umich.edu .name(name() + ".rescheduledLoads") 2052727Sktlim@umich.edu .desc("Number of loads that were rescheduled"); 2062727Sktlim@umich.edu 2072727Sktlim@umich.edu lsqCacheBlocked 2082727Sktlim@umich.edu .name(name() + ".cacheBlocked") 2092727Sktlim@umich.edu .desc("Number of times an access to memory failed due to the cache being blocked"); 2102727Sktlim@umich.edu} 2112727Sktlim@umich.edu 2122727Sktlim@umich.edutemplate<class Impl> 2132727Sktlim@umich.eduvoid 2142292SN/ALSQUnit<Impl>::clearLQ() 2152292SN/A{ 2162292SN/A loadQueue.clear(); 2172292SN/A} 2182292SN/A 2192292SN/Atemplate<class Impl> 2202292SN/Avoid 2212292SN/ALSQUnit<Impl>::clearSQ() 2222292SN/A{ 2232292SN/A storeQueue.clear(); 2242292SN/A} 2252292SN/A 2262292SN/Atemplate<class Impl> 2272292SN/Avoid 2282307SN/ALSQUnit<Impl>::switchOut() 2292307SN/A{ 2302307SN/A switchedOut = true; 2312367SN/A for (int i = 0; i < loadQueue.size(); ++i) { 2322367SN/A assert(!loadQueue[i]); 2332307SN/A loadQueue[i] = NULL; 2342367SN/A } 2352307SN/A 2362329SN/A assert(storesToWB == 0); 2372307SN/A} 2382307SN/A 2392307SN/Atemplate<class Impl> 2402307SN/Avoid 2412307SN/ALSQUnit<Impl>::takeOverFrom() 2422307SN/A{ 2432307SN/A switchedOut = false; 2442307SN/A loads = stores = storesToWB = 0; 2452307SN/A 2462307SN/A loadHead = loadTail = 0; 2472307SN/A 2482307SN/A storeHead = storeWBIdx = storeTail = 0; 2492307SN/A 2502307SN/A usedPorts = 0; 2512307SN/A 2522329SN/A memDepViolator = NULL; 2532307SN/A 2542307SN/A blockedLoadSeqNum = 0; 2552307SN/A 2562307SN/A stalled = false; 2572307SN/A isLoadBlocked = false; 2582307SN/A loadBlockedHandled = false; 2592307SN/A} 2602307SN/A 2612307SN/Atemplate<class Impl> 2622307SN/Avoid 2632292SN/ALSQUnit<Impl>::resizeLQ(unsigned size) 2642292SN/A{ 2652329SN/A unsigned size_plus_sentinel = size + 1; 2662329SN/A assert(size_plus_sentinel >= LQEntries); 2672292SN/A 2682329SN/A if (size_plus_sentinel > LQEntries) { 2692329SN/A while (size_plus_sentinel > loadQueue.size()) { 2702292SN/A DynInstPtr dummy; 2712292SN/A loadQueue.push_back(dummy); 2722292SN/A LQEntries++; 2732292SN/A } 2742292SN/A } else { 2752329SN/A LQEntries = size_plus_sentinel; 2762292SN/A } 2772292SN/A 2782292SN/A} 2792292SN/A 2802292SN/Atemplate<class Impl> 2812292SN/Avoid 2822292SN/ALSQUnit<Impl>::resizeSQ(unsigned size) 2832292SN/A{ 2842329SN/A unsigned size_plus_sentinel = size + 1; 2852329SN/A if (size_plus_sentinel > SQEntries) { 2862329SN/A while (size_plus_sentinel > storeQueue.size()) { 2872292SN/A SQEntry dummy; 2882292SN/A storeQueue.push_back(dummy); 2892292SN/A SQEntries++; 2902292SN/A } 2912292SN/A } else { 2922329SN/A SQEntries = size_plus_sentinel; 2932292SN/A } 2942292SN/A} 2952292SN/A 2962292SN/Atemplate <class Impl> 2972292SN/Avoid 2982292SN/ALSQUnit<Impl>::insert(DynInstPtr &inst) 2992292SN/A{ 3002292SN/A assert(inst->isMemRef()); 3012292SN/A 3022292SN/A assert(inst->isLoad() || inst->isStore()); 3032292SN/A 3042292SN/A if (inst->isLoad()) { 3052292SN/A insertLoad(inst); 3062292SN/A } else { 3072292SN/A insertStore(inst); 3082292SN/A } 3092292SN/A 3102292SN/A inst->setInLSQ(); 3112292SN/A} 3122292SN/A 3132292SN/Atemplate <class Impl> 3142292SN/Avoid 3152292SN/ALSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 3162292SN/A{ 3172329SN/A assert((loadTail + 1) % LQEntries != loadHead); 3182329SN/A assert(loads < LQEntries); 3192292SN/A 3202292SN/A DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n", 3212292SN/A load_inst->readPC(), loadTail, load_inst->seqNum); 3222292SN/A 3232292SN/A load_inst->lqIdx = loadTail; 3242292SN/A 3252292SN/A if (stores == 0) { 3262292SN/A load_inst->sqIdx = -1; 3272292SN/A } else { 3282292SN/A load_inst->sqIdx = storeTail; 3292292SN/A } 3302292SN/A 3312292SN/A loadQueue[loadTail] = load_inst; 3322292SN/A 3332292SN/A incrLdIdx(loadTail); 3342292SN/A 3352292SN/A ++loads; 3362292SN/A} 3372292SN/A 3382292SN/Atemplate <class Impl> 3392292SN/Avoid 3402292SN/ALSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 3412292SN/A{ 3422292SN/A // Make sure it is not full before inserting an instruction. 3432292SN/A assert((storeTail + 1) % SQEntries != storeHead); 3442292SN/A assert(stores < SQEntries); 3452292SN/A 3462292SN/A DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n", 3472292SN/A store_inst->readPC(), storeTail, store_inst->seqNum); 3482292SN/A 3492292SN/A store_inst->sqIdx = storeTail; 3502292SN/A store_inst->lqIdx = loadTail; 3512292SN/A 3522292SN/A storeQueue[storeTail] = SQEntry(store_inst); 3532292SN/A 3542292SN/A incrStIdx(storeTail); 3552292SN/A 3562292SN/A ++stores; 3572292SN/A} 3582292SN/A 3592292SN/Atemplate <class Impl> 3602292SN/Atypename Impl::DynInstPtr 3612292SN/ALSQUnit<Impl>::getMemDepViolator() 3622292SN/A{ 3632292SN/A DynInstPtr temp = memDepViolator; 3642292SN/A 3652292SN/A memDepViolator = NULL; 3662292SN/A 3672292SN/A return temp; 3682292SN/A} 3692292SN/A 3702292SN/Atemplate <class Impl> 3712292SN/Aunsigned 3722292SN/ALSQUnit<Impl>::numFreeEntries() 3732292SN/A{ 3742292SN/A unsigned free_lq_entries = LQEntries - loads; 3752292SN/A unsigned free_sq_entries = SQEntries - stores; 3762292SN/A 3772292SN/A // Both the LQ and SQ entries have an extra dummy entry to differentiate 3782292SN/A // empty/full conditions. Subtract 1 from the free entries. 3792292SN/A if (free_lq_entries < free_sq_entries) { 3802292SN/A return free_lq_entries - 1; 3812292SN/A } else { 3822292SN/A return free_sq_entries - 1; 3832292SN/A } 3842292SN/A} 3852292SN/A 3862292SN/Atemplate <class Impl> 3872292SN/Aint 3882292SN/ALSQUnit<Impl>::numLoadsReady() 3892292SN/A{ 3902292SN/A int load_idx = loadHead; 3912292SN/A int retval = 0; 3922292SN/A 3932292SN/A while (load_idx != loadTail) { 3942292SN/A assert(loadQueue[load_idx]); 3952292SN/A 3962292SN/A if (loadQueue[load_idx]->readyToIssue()) { 3972292SN/A ++retval; 3982292SN/A } 3992292SN/A } 4002292SN/A 4012292SN/A return retval; 4022292SN/A} 4032292SN/A 4042292SN/Atemplate <class Impl> 4052292SN/AFault 4062292SN/ALSQUnit<Impl>::executeLoad(DynInstPtr &inst) 4072292SN/A{ 4084032Sktlim@umich.edu using namespace TheISA; 4092292SN/A // Execute a specific load. 4102292SN/A Fault load_fault = NoFault; 4112292SN/A 4122292SN/A DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n", 4132292SN/A inst->readPC(),inst->seqNum); 4142292SN/A 4154032Sktlim@umich.edu assert(!inst->isSquashed()); 4164032Sktlim@umich.edu 4172669Sktlim@umich.edu load_fault = inst->initiateAcc(); 4182292SN/A 4192292SN/A // If the instruction faulted, then we need to send it along to commit 4202292SN/A // without the instruction completing. 4212292SN/A if (load_fault != NoFault) { 4222329SN/A // Send this instruction to commit, also make sure iew stage 4232329SN/A // realizes there is activity. 4242367SN/A // Mark it as executed unless it is an uncached load that 4252367SN/A // needs to hit the head of commit. 4264032Sktlim@umich.edu if (!(inst->hasRequest() && inst->uncacheable()) || 4273731Sktlim@umich.edu inst->isAtCommit()) { 4282367SN/A inst->setExecuted(); 4292367SN/A } 4302292SN/A iewStage->instToCommit(inst); 4312292SN/A iewStage->activityThisCycle(); 4324032Sktlim@umich.edu } else if (!loadBlocked()) { 4334032Sktlim@umich.edu assert(inst->effAddrValid); 4344032Sktlim@umich.edu int load_idx = inst->lqIdx; 4354032Sktlim@umich.edu incrLdIdx(load_idx); 4364032Sktlim@umich.edu while (load_idx != loadTail) { 4374032Sktlim@umich.edu // Really only need to check loads that have actually executed 4384032Sktlim@umich.edu 4394032Sktlim@umich.edu // @todo: For now this is extra conservative, detecting a 4404032Sktlim@umich.edu // violation if the addresses match assuming all accesses 4414032Sktlim@umich.edu // are quad word accesses. 4424032Sktlim@umich.edu 4434032Sktlim@umich.edu // @todo: Fix this, magic number being used here 4444032Sktlim@umich.edu if (loadQueue[load_idx]->effAddrValid && 4454032Sktlim@umich.edu (loadQueue[load_idx]->effAddr >> 8) == 4464032Sktlim@umich.edu (inst->effAddr >> 8)) { 4474032Sktlim@umich.edu // A load incorrectly passed this load. Squash and refetch. 4484032Sktlim@umich.edu // For now return a fault to show that it was unsuccessful. 4494032Sktlim@umich.edu DynInstPtr violator = loadQueue[load_idx]; 4504032Sktlim@umich.edu if (!memDepViolator || 4514032Sktlim@umich.edu (violator->seqNum < memDepViolator->seqNum)) { 4524032Sktlim@umich.edu memDepViolator = violator; 4534032Sktlim@umich.edu } else { 4544032Sktlim@umich.edu break; 4554032Sktlim@umich.edu } 4564032Sktlim@umich.edu 4574032Sktlim@umich.edu ++lsqMemOrderViolation; 4584032Sktlim@umich.edu 4594032Sktlim@umich.edu return genMachineCheckFault(); 4604032Sktlim@umich.edu } 4614032Sktlim@umich.edu 4624032Sktlim@umich.edu incrLdIdx(load_idx); 4634032Sktlim@umich.edu } 4642292SN/A } 4652292SN/A 4662292SN/A return load_fault; 4672292SN/A} 4682292SN/A 4692292SN/Atemplate <class Impl> 4702292SN/AFault 4712292SN/ALSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 4722292SN/A{ 4732292SN/A using namespace TheISA; 4742292SN/A // Make sure that a store exists. 4752292SN/A assert(stores != 0); 4762292SN/A 4772292SN/A int store_idx = store_inst->sqIdx; 4782292SN/A 4792292SN/A DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n", 4802292SN/A store_inst->readPC(), store_inst->seqNum); 4812292SN/A 4824032Sktlim@umich.edu assert(!store_inst->isSquashed()); 4834032Sktlim@umich.edu 4842292SN/A // Check the recently completed loads to see if any match this store's 4852292SN/A // address. If so, then we have a memory ordering violation. 4862292SN/A int load_idx = store_inst->lqIdx; 4872292SN/A 4882292SN/A Fault store_fault = store_inst->initiateAcc(); 4892292SN/A 4902329SN/A if (storeQueue[store_idx].size == 0) { 4912292SN/A DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n", 4922292SN/A store_inst->readPC(),store_inst->seqNum); 4932292SN/A 4942292SN/A return store_fault; 4952292SN/A } 4962292SN/A 4972292SN/A assert(store_fault == NoFault); 4982292SN/A 4992336SN/A if (store_inst->isStoreConditional()) { 5002336SN/A // Store conditionals need to set themselves as able to 5012336SN/A // writeback if we haven't had a fault by here. 5022329SN/A storeQueue[store_idx].canWB = true; 5032292SN/A 5042329SN/A ++storesToWB; 5052292SN/A } 5062292SN/A 5074032Sktlim@umich.edu assert(store_inst->effAddrValid); 5084032Sktlim@umich.edu while (load_idx != loadTail) { 5094032Sktlim@umich.edu // Really only need to check loads that have actually executed 5104032Sktlim@umich.edu // It's safe to check all loads because effAddr is set to 5114032Sktlim@umich.edu // InvalAddr when the dyn inst is created. 5122292SN/A 5134032Sktlim@umich.edu // @todo: For now this is extra conservative, detecting a 5144032Sktlim@umich.edu // violation if the addresses match assuming all accesses 5154032Sktlim@umich.edu // are quad word accesses. 5162329SN/A 5174032Sktlim@umich.edu // @todo: Fix this, magic number being used here 5184032Sktlim@umich.edu if (loadQueue[load_idx]->effAddrValid && 5194032Sktlim@umich.edu (loadQueue[load_idx]->effAddr >> 8) == 5204032Sktlim@umich.edu (store_inst->effAddr >> 8)) { 5214032Sktlim@umich.edu // A load incorrectly passed this store. Squash and refetch. 5224032Sktlim@umich.edu // For now return a fault to show that it was unsuccessful. 5234032Sktlim@umich.edu DynInstPtr violator = loadQueue[load_idx]; 5244032Sktlim@umich.edu if (!memDepViolator || 5254032Sktlim@umich.edu (violator->seqNum < memDepViolator->seqNum)) { 5264032Sktlim@umich.edu memDepViolator = violator; 5274032Sktlim@umich.edu } else { 5284032Sktlim@umich.edu break; 5292292SN/A } 5302292SN/A 5314032Sktlim@umich.edu ++lsqMemOrderViolation; 5324032Sktlim@umich.edu 5334032Sktlim@umich.edu return genMachineCheckFault(); 5342292SN/A } 5352292SN/A 5364032Sktlim@umich.edu incrLdIdx(load_idx); 5372292SN/A } 5382292SN/A 5392292SN/A return store_fault; 5402292SN/A} 5412292SN/A 5422292SN/Atemplate <class Impl> 5432292SN/Avoid 5442292SN/ALSQUnit<Impl>::commitLoad() 5452292SN/A{ 5462292SN/A assert(loadQueue[loadHead]); 5472292SN/A 5482292SN/A DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n", 5492292SN/A loadQueue[loadHead]->readPC()); 5502292SN/A 5512292SN/A loadQueue[loadHead] = NULL; 5522292SN/A 5532292SN/A incrLdIdx(loadHead); 5542292SN/A 5552292SN/A --loads; 5562292SN/A} 5572292SN/A 5582292SN/Atemplate <class Impl> 5592292SN/Avoid 5602292SN/ALSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 5612292SN/A{ 5622292SN/A assert(loads == 0 || loadQueue[loadHead]); 5632292SN/A 5642292SN/A while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 5652292SN/A commitLoad(); 5662292SN/A } 5672292SN/A} 5682292SN/A 5692292SN/Atemplate <class Impl> 5702292SN/Avoid 5712292SN/ALSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 5722292SN/A{ 5732292SN/A assert(stores == 0 || storeQueue[storeHead].inst); 5742292SN/A 5752292SN/A int store_idx = storeHead; 5762292SN/A 5772292SN/A while (store_idx != storeTail) { 5782292SN/A assert(storeQueue[store_idx].inst); 5792329SN/A // Mark any stores that are now committed and have not yet 5802329SN/A // been marked as able to write back. 5812292SN/A if (!storeQueue[store_idx].canWB) { 5822292SN/A if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 5832292SN/A break; 5842292SN/A } 5852292SN/A DPRINTF(LSQUnit, "Marking store as able to write back, PC " 5862292SN/A "%#x [sn:%lli]\n", 5872292SN/A storeQueue[store_idx].inst->readPC(), 5882292SN/A storeQueue[store_idx].inst->seqNum); 5892292SN/A 5902292SN/A storeQueue[store_idx].canWB = true; 5912292SN/A 5922292SN/A ++storesToWB; 5932292SN/A } 5942292SN/A 5952292SN/A incrStIdx(store_idx); 5962292SN/A } 5972292SN/A} 5982292SN/A 5992292SN/Atemplate <class Impl> 6002292SN/Avoid 6012292SN/ALSQUnit<Impl>::writebackStores() 6022292SN/A{ 6032292SN/A while (storesToWB > 0 && 6042292SN/A storeWBIdx != storeTail && 6052292SN/A storeQueue[storeWBIdx].inst && 6062292SN/A storeQueue[storeWBIdx].canWB && 6072292SN/A usedPorts < cachePorts) { 6082292SN/A 6092907Sktlim@umich.edu if (isStoreBlocked || lsq->cacheBlocked()) { 6102678Sktlim@umich.edu DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 6112678Sktlim@umich.edu " is blocked!\n"); 6122678Sktlim@umich.edu break; 6132678Sktlim@umich.edu } 6142678Sktlim@umich.edu 6152329SN/A // Store didn't write any data so no need to write it back to 6162329SN/A // memory. 6172292SN/A if (storeQueue[storeWBIdx].size == 0) { 6182292SN/A completeStore(storeWBIdx); 6192292SN/A 6202292SN/A incrStIdx(storeWBIdx); 6212292SN/A 6222292SN/A continue; 6232292SN/A } 6242678Sktlim@umich.edu 6252292SN/A ++usedPorts; 6262292SN/A 6272292SN/A if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 6282292SN/A incrStIdx(storeWBIdx); 6292292SN/A 6302292SN/A continue; 6312292SN/A } 6322292SN/A 6332292SN/A assert(storeQueue[storeWBIdx].req); 6342292SN/A assert(!storeQueue[storeWBIdx].committed); 6352292SN/A 6362669Sktlim@umich.edu DynInstPtr inst = storeQueue[storeWBIdx].inst; 6372669Sktlim@umich.edu 6382669Sktlim@umich.edu Request *req = storeQueue[storeWBIdx].req; 6392292SN/A storeQueue[storeWBIdx].committed = true; 6402292SN/A 6412669Sktlim@umich.edu assert(!inst->memData); 6422669Sktlim@umich.edu inst->memData = new uint8_t[64]; 6433772Sgblack@eecs.umich.edu 6443772Sgblack@eecs.umich.edu TheISA::IntReg convertedData = 6453772Sgblack@eecs.umich.edu TheISA::htog(storeQueue[storeWBIdx].data); 6463772Sgblack@eecs.umich.edu 6473797Sgblack@eecs.umich.edu //FIXME This is a hack to get SPARC working. It, along with endianness 6483797Sgblack@eecs.umich.edu //in the memory system in general, need to be straightened out more 6493797Sgblack@eecs.umich.edu //formally. The problem is that the data's endianness is swapped when 6503797Sgblack@eecs.umich.edu //it's in the 64 bit data field in the store queue. The data that you 6513797Sgblack@eecs.umich.edu //want won't start at the beginning of the field anymore unless it was 6523797Sgblack@eecs.umich.edu //a 64 bit access. 6533797Sgblack@eecs.umich.edu memcpy(inst->memData, 6543797Sgblack@eecs.umich.edu (uint8_t *)&convertedData + 6553797Sgblack@eecs.umich.edu (TheISA::ByteOrderDiffers ? 6563797Sgblack@eecs.umich.edu (sizeof(TheISA::IntReg) - req->getSize()) : 0), 6573797Sgblack@eecs.umich.edu req->getSize()); 6582669Sktlim@umich.edu 6594022Sstever@eecs.umich.edu PacketPtr data_pkt = new Packet(req, MemCmd::WriteReq, 6604022Sstever@eecs.umich.edu Packet::Broadcast); 6612669Sktlim@umich.edu data_pkt->dataStatic(inst->memData); 6622292SN/A 6632678Sktlim@umich.edu LSQSenderState *state = new LSQSenderState; 6642678Sktlim@umich.edu state->isLoad = false; 6652678Sktlim@umich.edu state->idx = storeWBIdx; 6662678Sktlim@umich.edu state->inst = inst; 6672678Sktlim@umich.edu data_pkt->senderState = state; 6682678Sktlim@umich.edu 6692292SN/A DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x " 6702292SN/A "to Addr:%#x, data:%#x [sn:%lli]\n", 6713221Sktlim@umich.edu storeWBIdx, inst->readPC(), 6723797Sgblack@eecs.umich.edu req->getPaddr(), (int)*(inst->memData), 6733221Sktlim@umich.edu inst->seqNum); 6742292SN/A 6752693Sktlim@umich.edu // @todo: Remove this SC hack once the memory system handles it. 6763172Sstever@eecs.umich.edu if (req->isLocked()) { 6773326Sktlim@umich.edu // Disable recording the result temporarily. Writing to 6783326Sktlim@umich.edu // misc regs normally updates the result, but this is not 6793326Sktlim@umich.edu // the desired behavior when handling store conditionals. 6803326Sktlim@umich.edu inst->recordResult = false; 6813326Sktlim@umich.edu bool success = TheISA::handleLockedWrite(inst.get(), req); 6823326Sktlim@umich.edu inst->recordResult = true; 6833326Sktlim@umich.edu 6843326Sktlim@umich.edu if (!success) { 6853326Sktlim@umich.edu // Instantly complete this store. 6863326Sktlim@umich.edu DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 6873326Sktlim@umich.edu "Instantly completing it.\n", 6883326Sktlim@umich.edu inst->seqNum); 6893326Sktlim@umich.edu WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 6903326Sktlim@umich.edu wb->schedule(curTick + 1); 6913326Sktlim@umich.edu delete state; 6923326Sktlim@umich.edu completeStore(storeWBIdx); 6933326Sktlim@umich.edu incrStIdx(storeWBIdx); 6943326Sktlim@umich.edu continue; 6952693Sktlim@umich.edu } 6962693Sktlim@umich.edu } else { 6972693Sktlim@umich.edu // Non-store conditionals do not need a writeback. 6982693Sktlim@umich.edu state->noWB = true; 6992693Sktlim@umich.edu } 7002693Sktlim@umich.edu 7012669Sktlim@umich.edu if (!dcachePort->sendTiming(data_pkt)) { 7023221Sktlim@umich.edu if (data_pkt->result == Packet::BadAddress) { 7033221Sktlim@umich.edu panic("LSQ sent out a bad address for a completed store!"); 7043221Sktlim@umich.edu } 7052669Sktlim@umich.edu // Need to handle becoming blocked on a store. 7064032Sktlim@umich.edu DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 7073221Sktlim@umich.edu "retry later\n", 7083221Sktlim@umich.edu inst->seqNum); 7092678Sktlim@umich.edu isStoreBlocked = true; 7102727Sktlim@umich.edu ++lsqCacheBlocked; 7112698Sktlim@umich.edu assert(retryPkt == NULL); 7122698Sktlim@umich.edu retryPkt = data_pkt; 7133014Srdreslin@umich.edu lsq->setRetryTid(lsqID); 7142669Sktlim@umich.edu } else { 7152693Sktlim@umich.edu storePostSend(data_pkt); 7162292SN/A } 7172292SN/A } 7182292SN/A 7192292SN/A // Not sure this should set it to 0. 7202292SN/A usedPorts = 0; 7212292SN/A 7222292SN/A assert(stores >= 0 && storesToWB >= 0); 7232292SN/A} 7242292SN/A 7252292SN/A/*template <class Impl> 7262292SN/Avoid 7272292SN/ALSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 7282292SN/A{ 7292292SN/A list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 7302292SN/A mshrSeqNums.end(), 7312292SN/A seqNum); 7322292SN/A 7332292SN/A if (mshr_it != mshrSeqNums.end()) { 7342292SN/A mshrSeqNums.erase(mshr_it); 7352292SN/A DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 7362292SN/A } 7372292SN/A}*/ 7382292SN/A 7392292SN/Atemplate <class Impl> 7402292SN/Avoid 7412292SN/ALSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 7422292SN/A{ 7432292SN/A DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 7442329SN/A "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 7452292SN/A 7462292SN/A int load_idx = loadTail; 7472292SN/A decrLdIdx(load_idx); 7482292SN/A 7492292SN/A while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 7502292SN/A DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, " 7512292SN/A "[sn:%lli]\n", 7522292SN/A loadQueue[load_idx]->readPC(), 7532292SN/A loadQueue[load_idx]->seqNum); 7542292SN/A 7552292SN/A if (isStalled() && load_idx == stallingLoadIdx) { 7562292SN/A stalled = false; 7572292SN/A stallingStoreIsn = 0; 7582292SN/A stallingLoadIdx = 0; 7592292SN/A } 7602292SN/A 7612329SN/A // Clear the smart pointer to make sure it is decremented. 7622731Sktlim@umich.edu loadQueue[load_idx]->setSquashed(); 7632292SN/A loadQueue[load_idx] = NULL; 7642292SN/A --loads; 7652292SN/A 7662292SN/A // Inefficient! 7672292SN/A loadTail = load_idx; 7682292SN/A 7692292SN/A decrLdIdx(load_idx); 7702727Sktlim@umich.edu ++lsqSquashedLoads; 7712292SN/A } 7722292SN/A 7732292SN/A if (isLoadBlocked) { 7742292SN/A if (squashed_num < blockedLoadSeqNum) { 7752292SN/A isLoadBlocked = false; 7762292SN/A loadBlockedHandled = false; 7772292SN/A blockedLoadSeqNum = 0; 7782292SN/A } 7792292SN/A } 7802292SN/A 7814032Sktlim@umich.edu if (memDepViolator && squashed_num < memDepViolator->seqNum) { 7824032Sktlim@umich.edu memDepViolator = NULL; 7834032Sktlim@umich.edu } 7844032Sktlim@umich.edu 7852292SN/A int store_idx = storeTail; 7862292SN/A decrStIdx(store_idx); 7872292SN/A 7882292SN/A while (stores != 0 && 7892292SN/A storeQueue[store_idx].inst->seqNum > squashed_num) { 7902329SN/A // Instructions marked as can WB are already committed. 7912292SN/A if (storeQueue[store_idx].canWB) { 7922292SN/A break; 7932292SN/A } 7942292SN/A 7952292SN/A DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, " 7962292SN/A "idx:%i [sn:%lli]\n", 7972292SN/A storeQueue[store_idx].inst->readPC(), 7982292SN/A store_idx, storeQueue[store_idx].inst->seqNum); 7992292SN/A 8002329SN/A // I don't think this can happen. It should have been cleared 8012329SN/A // by the stalling load. 8022292SN/A if (isStalled() && 8032292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 8042292SN/A panic("Is stalled should have been cleared by stalling load!\n"); 8052292SN/A stalled = false; 8062292SN/A stallingStoreIsn = 0; 8072292SN/A } 8082292SN/A 8092329SN/A // Clear the smart pointer to make sure it is decremented. 8102731Sktlim@umich.edu storeQueue[store_idx].inst->setSquashed(); 8112292SN/A storeQueue[store_idx].inst = NULL; 8122292SN/A storeQueue[store_idx].canWB = 0; 8132292SN/A 8144032Sktlim@umich.edu // Must delete request now that it wasn't handed off to 8154032Sktlim@umich.edu // memory. This is quite ugly. @todo: Figure out the proper 8164032Sktlim@umich.edu // place to really handle request deletes. 8174032Sktlim@umich.edu delete storeQueue[store_idx].req; 8184032Sktlim@umich.edu 8192292SN/A storeQueue[store_idx].req = NULL; 8202292SN/A --stores; 8212292SN/A 8222292SN/A // Inefficient! 8232292SN/A storeTail = store_idx; 8242292SN/A 8252292SN/A decrStIdx(store_idx); 8262727Sktlim@umich.edu ++lsqSquashedStores; 8272292SN/A } 8282292SN/A} 8292292SN/A 8302292SN/Atemplate <class Impl> 8312292SN/Avoid 8323349Sbinkertn@umich.eduLSQUnit<Impl>::storePostSend(PacketPtr pkt) 8332693Sktlim@umich.edu{ 8342693Sktlim@umich.edu if (isStalled() && 8352693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 8362693Sktlim@umich.edu DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 8372693Sktlim@umich.edu "load idx:%i\n", 8382693Sktlim@umich.edu stallingStoreIsn, stallingLoadIdx); 8392693Sktlim@umich.edu stalled = false; 8402693Sktlim@umich.edu stallingStoreIsn = 0; 8412693Sktlim@umich.edu iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 8422693Sktlim@umich.edu } 8432693Sktlim@umich.edu 8442693Sktlim@umich.edu if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 8452693Sktlim@umich.edu // The store is basically completed at this time. This 8462693Sktlim@umich.edu // only works so long as the checker doesn't try to 8472693Sktlim@umich.edu // verify the value in memory for stores. 8482693Sktlim@umich.edu storeQueue[storeWBIdx].inst->setCompleted(); 8492733Sktlim@umich.edu#if USE_CHECKER 8502693Sktlim@umich.edu if (cpu->checker) { 8512732Sktlim@umich.edu cpu->checker->verify(storeQueue[storeWBIdx].inst); 8522693Sktlim@umich.edu } 8532733Sktlim@umich.edu#endif 8542693Sktlim@umich.edu } 8552693Sktlim@umich.edu 8562693Sktlim@umich.edu if (pkt->result != Packet::Success) { 8572693Sktlim@umich.edu DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n", 8582693Sktlim@umich.edu storeWBIdx); 8592693Sktlim@umich.edu 8602693Sktlim@umich.edu DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n", 8612693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum); 8622693Sktlim@umich.edu 8632693Sktlim@umich.edu //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum); 8642693Sktlim@umich.edu 8652693Sktlim@umich.edu //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size()); 8662693Sktlim@umich.edu 8672693Sktlim@umich.edu // @todo: Increment stat here. 8682693Sktlim@umich.edu } else { 8692693Sktlim@umich.edu DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n", 8702693Sktlim@umich.edu storeWBIdx); 8712693Sktlim@umich.edu 8722693Sktlim@umich.edu DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n", 8732693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum); 8742693Sktlim@umich.edu } 8752693Sktlim@umich.edu 8762693Sktlim@umich.edu incrStIdx(storeWBIdx); 8772693Sktlim@umich.edu} 8782693Sktlim@umich.edu 8792693Sktlim@umich.edutemplate <class Impl> 8802693Sktlim@umich.eduvoid 8812678Sktlim@umich.eduLSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 8822678Sktlim@umich.edu{ 8832678Sktlim@umich.edu iewStage->wakeCPU(); 8842678Sktlim@umich.edu 8852678Sktlim@umich.edu // Squashed instructions do not need to complete their access. 8862678Sktlim@umich.edu if (inst->isSquashed()) { 8872927Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 8882678Sktlim@umich.edu assert(!inst->isStore()); 8892727Sktlim@umich.edu ++lsqIgnoredResponses; 8902678Sktlim@umich.edu return; 8912678Sktlim@umich.edu } 8922678Sktlim@umich.edu 8932678Sktlim@umich.edu if (!inst->isExecuted()) { 8942678Sktlim@umich.edu inst->setExecuted(); 8952678Sktlim@umich.edu 8962678Sktlim@umich.edu // Complete access to copy data to proper place. 8972678Sktlim@umich.edu inst->completeAcc(pkt); 8982678Sktlim@umich.edu } 8992678Sktlim@umich.edu 9002678Sktlim@umich.edu // Need to insert instruction into queue to commit 9012678Sktlim@umich.edu iewStage->instToCommit(inst); 9022678Sktlim@umich.edu 9032678Sktlim@umich.edu iewStage->activityThisCycle(); 9042678Sktlim@umich.edu} 9052678Sktlim@umich.edu 9062678Sktlim@umich.edutemplate <class Impl> 9072678Sktlim@umich.eduvoid 9082292SN/ALSQUnit<Impl>::completeStore(int store_idx) 9092292SN/A{ 9102292SN/A assert(storeQueue[store_idx].inst); 9112292SN/A storeQueue[store_idx].completed = true; 9122292SN/A --storesToWB; 9132292SN/A // A bit conservative because a store completion may not free up entries, 9142292SN/A // but hopefully avoids two store completions in one cycle from making 9152292SN/A // the CPU tick twice. 9163126Sktlim@umich.edu cpu->wakeCPU(); 9172292SN/A cpu->activityThisCycle(); 9182292SN/A 9192292SN/A if (store_idx == storeHead) { 9202292SN/A do { 9212292SN/A incrStIdx(storeHead); 9222292SN/A 9232292SN/A --stores; 9242292SN/A } while (storeQueue[storeHead].completed && 9252292SN/A storeHead != storeTail); 9262292SN/A 9272292SN/A iewStage->updateLSQNextCycle = true; 9282292SN/A } 9292292SN/A 9302329SN/A DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 9312329SN/A "idx:%i\n", 9322329SN/A storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 9332292SN/A 9342292SN/A if (isStalled() && 9352292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 9362292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 9372292SN/A "load idx:%i\n", 9382292SN/A stallingStoreIsn, stallingLoadIdx); 9392292SN/A stalled = false; 9402292SN/A stallingStoreIsn = 0; 9412292SN/A iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 9422292SN/A } 9432316SN/A 9442316SN/A storeQueue[store_idx].inst->setCompleted(); 9452329SN/A 9462329SN/A // Tell the checker we've completed this instruction. Some stores 9472329SN/A // may get reported twice to the checker, but the checker can 9482329SN/A // handle that case. 9492733Sktlim@umich.edu#if USE_CHECKER 9502316SN/A if (cpu->checker) { 9512732Sktlim@umich.edu cpu->checker->verify(storeQueue[store_idx].inst); 9522316SN/A } 9532733Sktlim@umich.edu#endif 9542292SN/A} 9552292SN/A 9562292SN/Atemplate <class Impl> 9572693Sktlim@umich.eduvoid 9582693Sktlim@umich.eduLSQUnit<Impl>::recvRetry() 9592693Sktlim@umich.edu{ 9602698Sktlim@umich.edu if (isStoreBlocked) { 9612698Sktlim@umich.edu assert(retryPkt != NULL); 9622693Sktlim@umich.edu 9632698Sktlim@umich.edu if (dcachePort->sendTiming(retryPkt)) { 9643221Sktlim@umich.edu if (retryPkt->result == Packet::BadAddress) { 9653221Sktlim@umich.edu panic("LSQ sent out a bad address for a completed store!"); 9663221Sktlim@umich.edu } 9672698Sktlim@umich.edu storePostSend(retryPkt); 9682699Sktlim@umich.edu retryPkt = NULL; 9692693Sktlim@umich.edu isStoreBlocked = false; 9703014Srdreslin@umich.edu lsq->setRetryTid(-1); 9712693Sktlim@umich.edu } else { 9722693Sktlim@umich.edu // Still blocked! 9732727Sktlim@umich.edu ++lsqCacheBlocked; 9742907Sktlim@umich.edu lsq->setRetryTid(lsqID); 9752693Sktlim@umich.edu } 9762693Sktlim@umich.edu } else if (isLoadBlocked) { 9772693Sktlim@umich.edu DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 9782693Sktlim@umich.edu "no need to resend packet.\n"); 9792693Sktlim@umich.edu } else { 9802693Sktlim@umich.edu DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 9812693Sktlim@umich.edu } 9822693Sktlim@umich.edu} 9832693Sktlim@umich.edu 9842693Sktlim@umich.edutemplate <class Impl> 9852292SN/Ainline void 9862292SN/ALSQUnit<Impl>::incrStIdx(int &store_idx) 9872292SN/A{ 9882292SN/A if (++store_idx >= SQEntries) 9892292SN/A store_idx = 0; 9902292SN/A} 9912292SN/A 9922292SN/Atemplate <class Impl> 9932292SN/Ainline void 9942292SN/ALSQUnit<Impl>::decrStIdx(int &store_idx) 9952292SN/A{ 9962292SN/A if (--store_idx < 0) 9972292SN/A store_idx += SQEntries; 9982292SN/A} 9992292SN/A 10002292SN/Atemplate <class Impl> 10012292SN/Ainline void 10022292SN/ALSQUnit<Impl>::incrLdIdx(int &load_idx) 10032292SN/A{ 10042292SN/A if (++load_idx >= LQEntries) 10052292SN/A load_idx = 0; 10062292SN/A} 10072292SN/A 10082292SN/Atemplate <class Impl> 10092292SN/Ainline void 10102292SN/ALSQUnit<Impl>::decrLdIdx(int &load_idx) 10112292SN/A{ 10122292SN/A if (--load_idx < 0) 10132292SN/A load_idx += LQEntries; 10142292SN/A} 10152329SN/A 10162329SN/Atemplate <class Impl> 10172329SN/Avoid 10182329SN/ALSQUnit<Impl>::dumpInsts() 10192329SN/A{ 10202329SN/A cprintf("Load store queue: Dumping instructions.\n"); 10212329SN/A cprintf("Load queue size: %i\n", loads); 10222329SN/A cprintf("Load queue: "); 10232329SN/A 10242329SN/A int load_idx = loadHead; 10252329SN/A 10262329SN/A while (load_idx != loadTail && loadQueue[load_idx]) { 10272329SN/A cprintf("%#x ", loadQueue[load_idx]->readPC()); 10282329SN/A 10292329SN/A incrLdIdx(load_idx); 10302329SN/A } 10312329SN/A 10322329SN/A cprintf("Store queue size: %i\n", stores); 10332329SN/A cprintf("Store queue: "); 10342329SN/A 10352329SN/A int store_idx = storeHead; 10362329SN/A 10372329SN/A while (store_idx != storeTail && storeQueue[store_idx].inst) { 10382329SN/A cprintf("%#x ", storeQueue[store_idx].inst->readPC()); 10392329SN/A 10402329SN/A incrStIdx(store_idx); 10412329SN/A } 10422329SN/A 10432329SN/A cprintf("\n"); 10442329SN/A} 1045