lsq_unit_impl.hh revision 4032
17119Sgblack@eecs.umich.edu/* 27119Sgblack@eecs.umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 310037SARM gem5 Developers * All rights reserved. 47120Sgblack@eecs.umich.edu * 57120Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 67120Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 77120Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 87120Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 97120Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 107120Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 117120Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 127120Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 137120Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 147120Sgblack@eecs.umich.edu * this software without specific prior written permission. 157119Sgblack@eecs.umich.edu * 167119Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177119Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187119Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197119Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207119Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217119Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227119Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237119Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247119Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257119Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267119Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277119Sgblack@eecs.umich.edu * 287119Sgblack@eecs.umich.edu * Authors: Kevin Lim 297119Sgblack@eecs.umich.edu * Korey Sewell 307119Sgblack@eecs.umich.edu */ 317119Sgblack@eecs.umich.edu 327119Sgblack@eecs.umich.edu#include "arch/locked_mem.hh" 337119Sgblack@eecs.umich.edu#include "config/use_checker.hh" 347119Sgblack@eecs.umich.edu 357119Sgblack@eecs.umich.edu#include "cpu/o3/lsq.hh" 367119Sgblack@eecs.umich.edu#include "cpu/o3/lsq_unit.hh" 377119Sgblack@eecs.umich.edu#include "base/str.hh" 387119Sgblack@eecs.umich.edu#include "mem/packet.hh" 397119Sgblack@eecs.umich.edu#include "mem/request.hh" 407119Sgblack@eecs.umich.edu 417119Sgblack@eecs.umich.edu#if USE_CHECKER 427119Sgblack@eecs.umich.edu#include "cpu/checker/cpu.hh" 437119Sgblack@eecs.umich.edu#endif 447646Sgene.wu@arm.com 457646Sgene.wu@arm.comtemplate<class Impl> 467646Sgene.wu@arm.comLSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 477646Sgene.wu@arm.com LSQUnit *lsq_ptr) 487646Sgene.wu@arm.com : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 497646Sgene.wu@arm.com{ 507646Sgene.wu@arm.com this->setFlags(Event::AutoDelete); 517646Sgene.wu@arm.com} 527646Sgene.wu@arm.com 537646Sgene.wu@arm.comtemplate<class Impl> 547646Sgene.wu@arm.comvoid 557646Sgene.wu@arm.comLSQUnit<Impl>::WritebackEvent::process() 567646Sgene.wu@arm.com{ 577646Sgene.wu@arm.com if (!lsqPtr->isSwitchedOut()) { 587646Sgene.wu@arm.com lsqPtr->writeback(inst, pkt); 597646Sgene.wu@arm.com } 607646Sgene.wu@arm.com delete pkt; 617646Sgene.wu@arm.com} 627646Sgene.wu@arm.com 637646Sgene.wu@arm.comtemplate<class Impl> 647646Sgene.wu@arm.comconst char * 657646Sgene.wu@arm.comLSQUnit<Impl>::WritebackEvent::description() 667646Sgene.wu@arm.com{ 677646Sgene.wu@arm.com return "Store writeback event"; 687646Sgene.wu@arm.com} 697646Sgene.wu@arm.com 707646Sgene.wu@arm.comtemplate<class Impl> 717646Sgene.wu@arm.comvoid 727646Sgene.wu@arm.comLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 737205Sgblack@eecs.umich.edu{ 747205Sgblack@eecs.umich.edu LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 757205Sgblack@eecs.umich.edu DynInstPtr inst = state->inst; 767205Sgblack@eecs.umich.edu DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum); 777205Sgblack@eecs.umich.edu DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum); 787205Sgblack@eecs.umich.edu 797205Sgblack@eecs.umich.edu //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 807205Sgblack@eecs.umich.edu 817205Sgblack@eecs.umich.edu if (isSwitchedOut() || inst->isSquashed()) { 827205Sgblack@eecs.umich.edu iewStage->decrWb(inst->seqNum); 837205Sgblack@eecs.umich.edu delete state; 847205Sgblack@eecs.umich.edu delete pkt->req; 857205Sgblack@eecs.umich.edu delete pkt; 867205Sgblack@eecs.umich.edu return; 877205Sgblack@eecs.umich.edu } else { 887205Sgblack@eecs.umich.edu if (!state->noWB) { 897205Sgblack@eecs.umich.edu writeback(inst, pkt); 908442Sgblack@eecs.umich.edu } 918442Sgblack@eecs.umich.edu 927205Sgblack@eecs.umich.edu if (inst->isStore()) { 937205Sgblack@eecs.umich.edu completeStore(state->idx); 947205Sgblack@eecs.umich.edu } 957205Sgblack@eecs.umich.edu } 967205Sgblack@eecs.umich.edu 977205Sgblack@eecs.umich.edu delete state; 987205Sgblack@eecs.umich.edu delete pkt->req; 997205Sgblack@eecs.umich.edu delete pkt; 1007205Sgblack@eecs.umich.edu} 1017597Sminkyu.jeong@arm.com 1027597Sminkyu.jeong@arm.comtemplate <class Impl> 1037205Sgblack@eecs.umich.eduLSQUnit<Impl>::LSQUnit() 1047205Sgblack@eecs.umich.edu : loads(0), stores(0), storesToWB(0), stalled(false), 1057205Sgblack@eecs.umich.edu isStoreBlocked(false), isLoadBlocked(false), 1067205Sgblack@eecs.umich.edu loadBlockedHandled(false) 1077205Sgblack@eecs.umich.edu{ 1087205Sgblack@eecs.umich.edu} 1097205Sgblack@eecs.umich.edu 1107205Sgblack@eecs.umich.edutemplate<class Impl> 1117205Sgblack@eecs.umich.eduvoid 1127205Sgblack@eecs.umich.eduLSQUnit<Impl>::init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries, 1137205Sgblack@eecs.umich.edu unsigned maxSQEntries, unsigned id) 1147205Sgblack@eecs.umich.edu{ 1157205Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 1167205Sgblack@eecs.umich.edu 1177205Sgblack@eecs.umich.edu switchedOut = false; 1187205Sgblack@eecs.umich.edu 1197205Sgblack@eecs.umich.edu lsq = lsq_ptr; 1207205Sgblack@eecs.umich.edu 1217205Sgblack@eecs.umich.edu lsqID = id; 1227205Sgblack@eecs.umich.edu 1237205Sgblack@eecs.umich.edu // Add 1 for the sentinel entry (they are circular queues). 1247205Sgblack@eecs.umich.edu LQEntries = maxLQEntries + 1; 1257205Sgblack@eecs.umich.edu SQEntries = maxSQEntries + 1; 1268442Sgblack@eecs.umich.edu 1278442Sgblack@eecs.umich.edu loadQueue.resize(LQEntries); 1287205Sgblack@eecs.umich.edu storeQueue.resize(SQEntries); 1297597Sminkyu.jeong@arm.com 1307597Sminkyu.jeong@arm.com loadHead = loadTail = 0; 1317205Sgblack@eecs.umich.edu 1327205Sgblack@eecs.umich.edu storeHead = storeWBIdx = storeTail = 0; 1337205Sgblack@eecs.umich.edu 1347205Sgblack@eecs.umich.edu usedPorts = 0; 1357205Sgblack@eecs.umich.edu cachePorts = params->cachePorts; 1367205Sgblack@eecs.umich.edu 1377205Sgblack@eecs.umich.edu retryPkt = NULL; 1387205Sgblack@eecs.umich.edu memDepViolator = NULL; 1397205Sgblack@eecs.umich.edu 1407205Sgblack@eecs.umich.edu blockedLoadSeqNum = 0; 1417205Sgblack@eecs.umich.edu} 1427205Sgblack@eecs.umich.edu 1437205Sgblack@eecs.umich.edutemplate<class Impl> 1447205Sgblack@eecs.umich.eduvoid 1457205Sgblack@eecs.umich.eduLSQUnit<Impl>::setCPU(O3CPU *cpu_ptr) 1467205Sgblack@eecs.umich.edu{ 1477205Sgblack@eecs.umich.edu cpu = cpu_ptr; 1487205Sgblack@eecs.umich.edu 1497205Sgblack@eecs.umich.edu#if USE_CHECKER 1508442Sgblack@eecs.umich.edu if (cpu->checker) { 1518442Sgblack@eecs.umich.edu cpu->checker->setDcachePort(dcachePort); 1527205Sgblack@eecs.umich.edu } 1537205Sgblack@eecs.umich.edu#endif 1547205Sgblack@eecs.umich.edu} 1557205Sgblack@eecs.umich.edu 1567205Sgblack@eecs.umich.edutemplate<class Impl> 1577205Sgblack@eecs.umich.edustd::string 1587205Sgblack@eecs.umich.eduLSQUnit<Impl>::name() const 1597205Sgblack@eecs.umich.edu{ 1607205Sgblack@eecs.umich.edu if (Impl::MaxThreads == 1) { 1617205Sgblack@eecs.umich.edu return iewStage->name() + ".lsq"; 1627205Sgblack@eecs.umich.edu } else { 1637205Sgblack@eecs.umich.edu return iewStage->name() + ".lsq.thread." + to_string(lsqID); 1647119Sgblack@eecs.umich.edu } 1657119Sgblack@eecs.umich.edu} 1667119Sgblack@eecs.umich.edu 1677119Sgblack@eecs.umich.edutemplate<class Impl> 1687119Sgblack@eecs.umich.eduvoid 1697119Sgblack@eecs.umich.eduLSQUnit<Impl>::regStats() 1707119Sgblack@eecs.umich.edu{ 1717119Sgblack@eecs.umich.edu lsqForwLoads 1727119Sgblack@eecs.umich.edu .name(name() + ".forwLoads") 1737119Sgblack@eecs.umich.edu .desc("Number of loads that had data forwarded from stores"); 1747119Sgblack@eecs.umich.edu 1757119Sgblack@eecs.umich.edu invAddrLoads 1767119Sgblack@eecs.umich.edu .name(name() + ".invAddrLoads") 1777119Sgblack@eecs.umich.edu .desc("Number of loads ignored due to an invalid address"); 1788442Sgblack@eecs.umich.edu 1797119Sgblack@eecs.umich.edu lsqSquashedLoads 1807119Sgblack@eecs.umich.edu .name(name() + ".squashedLoads") 1817119Sgblack@eecs.umich.edu .desc("Number of loads squashed"); 1827119Sgblack@eecs.umich.edu 1837119Sgblack@eecs.umich.edu lsqIgnoredResponses 1847119Sgblack@eecs.umich.edu .name(name() + ".ignoredResponses") 1857597Sminkyu.jeong@arm.com .desc("Number of memory responses ignored because the instruction is squashed"); 1867597Sminkyu.jeong@arm.com 1877119Sgblack@eecs.umich.edu lsqMemOrderViolation 1887119Sgblack@eecs.umich.edu .name(name() + ".memOrderViolation") 1897119Sgblack@eecs.umich.edu .desc("Number of memory ordering violations"); 1907119Sgblack@eecs.umich.edu 1917119Sgblack@eecs.umich.edu lsqSquashedStores 1927119Sgblack@eecs.umich.edu .name(name() + ".squashedStores") 1937639Sgblack@eecs.umich.edu .desc("Number of stores squashed"); 1947639Sgblack@eecs.umich.edu 1957639Sgblack@eecs.umich.edu invAddrSwpfs 1967639Sgblack@eecs.umich.edu .name(name() + ".invAddrSwpfs") 1977639Sgblack@eecs.umich.edu .desc("Number of software prefetches ignored due to an invalid address"); 1987639Sgblack@eecs.umich.edu 1997639Sgblack@eecs.umich.edu lsqBlockedLoads 2007639Sgblack@eecs.umich.edu .name(name() + ".blockedLoads") 2017639Sgblack@eecs.umich.edu .desc("Number of blocked loads due to partial load-store forwarding"); 2027639Sgblack@eecs.umich.edu 2037639Sgblack@eecs.umich.edu lsqRescheduledLoads 2047639Sgblack@eecs.umich.edu .name(name() + ".rescheduledLoads") 2057639Sgblack@eecs.umich.edu .desc("Number of loads that were rescheduled"); 2067639Sgblack@eecs.umich.edu 2077639Sgblack@eecs.umich.edu lsqCacheBlocked 2087639Sgblack@eecs.umich.edu .name(name() + ".cacheBlocked") 2097639Sgblack@eecs.umich.edu .desc("Number of times an access to memory failed due to the cache being blocked"); 2107639Sgblack@eecs.umich.edu} 2117639Sgblack@eecs.umich.edu 2128444Sgblack@eecs.umich.edutemplate<class Impl> 2137639Sgblack@eecs.umich.eduvoid 2147639Sgblack@eecs.umich.eduLSQUnit<Impl>::clearLQ() 2157639Sgblack@eecs.umich.edu{ 2167639Sgblack@eecs.umich.edu loadQueue.clear(); 2177639Sgblack@eecs.umich.edu} 2187639Sgblack@eecs.umich.edu 2198072SGiacomo.Gabrielli@arm.comtemplate<class Impl> 2208072SGiacomo.Gabrielli@arm.comvoid 2217639Sgblack@eecs.umich.eduLSQUnit<Impl>::clearSQ() 2227639Sgblack@eecs.umich.edu{ 2237639Sgblack@eecs.umich.edu storeQueue.clear(); 2247639Sgblack@eecs.umich.edu} 2257639Sgblack@eecs.umich.edu 2267639Sgblack@eecs.umich.edutemplate<class Impl> 2277120Sgblack@eecs.umich.eduvoid 2287120Sgblack@eecs.umich.eduLSQUnit<Impl>::switchOut() 2297120Sgblack@eecs.umich.edu{ 2307120Sgblack@eecs.umich.edu switchedOut = true; 2317120Sgblack@eecs.umich.edu for (int i = 0; i < loadQueue.size(); ++i) { 2327120Sgblack@eecs.umich.edu assert(!loadQueue[i]); 2337120Sgblack@eecs.umich.edu loadQueue[i] = NULL; 2347120Sgblack@eecs.umich.edu } 2357120Sgblack@eecs.umich.edu 2367120Sgblack@eecs.umich.edu assert(storesToWB == 0); 2377120Sgblack@eecs.umich.edu} 2387120Sgblack@eecs.umich.edu 2397120Sgblack@eecs.umich.edutemplate<class Impl> 2407120Sgblack@eecs.umich.eduvoid 2417120Sgblack@eecs.umich.eduLSQUnit<Impl>::takeOverFrom() 2427120Sgblack@eecs.umich.edu{ 2437120Sgblack@eecs.umich.edu switchedOut = false; 2447120Sgblack@eecs.umich.edu loads = stores = storesToWB = 0; 2458442Sgblack@eecs.umich.edu 2468442Sgblack@eecs.umich.edu loadHead = loadTail = 0; 2477120Sgblack@eecs.umich.edu 2487120Sgblack@eecs.umich.edu storeHead = storeWBIdx = storeTail = 0; 2497120Sgblack@eecs.umich.edu 2507120Sgblack@eecs.umich.edu usedPorts = 0; 2517120Sgblack@eecs.umich.edu 2527597Sminkyu.jeong@arm.com memDepViolator = NULL; 2537597Sminkyu.jeong@arm.com 2547120Sgblack@eecs.umich.edu blockedLoadSeqNum = 0; 2557120Sgblack@eecs.umich.edu 2567120Sgblack@eecs.umich.edu stalled = false; 2577120Sgblack@eecs.umich.edu isLoadBlocked = false; 2587120Sgblack@eecs.umich.edu loadBlockedHandled = false; 2597120Sgblack@eecs.umich.edu} 2607639Sgblack@eecs.umich.edu 2617639Sgblack@eecs.umich.edutemplate<class Impl> 2627639Sgblack@eecs.umich.eduvoid 2637639Sgblack@eecs.umich.eduLSQUnit<Impl>::resizeLQ(unsigned size) 2647639Sgblack@eecs.umich.edu{ 2657639Sgblack@eecs.umich.edu unsigned size_plus_sentinel = size + 1; 2667639Sgblack@eecs.umich.edu assert(size_plus_sentinel >= LQEntries); 2677639Sgblack@eecs.umich.edu 2687639Sgblack@eecs.umich.edu if (size_plus_sentinel > LQEntries) { 2697639Sgblack@eecs.umich.edu while (size_plus_sentinel > loadQueue.size()) { 2707639Sgblack@eecs.umich.edu DynInstPtr dummy; 2717639Sgblack@eecs.umich.edu loadQueue.push_back(dummy); 2727639Sgblack@eecs.umich.edu LQEntries++; 2737639Sgblack@eecs.umich.edu } 2747639Sgblack@eecs.umich.edu } else { 2757639Sgblack@eecs.umich.edu LQEntries = size_plus_sentinel; 2767639Sgblack@eecs.umich.edu } 2777639Sgblack@eecs.umich.edu 2787639Sgblack@eecs.umich.edu} 2797639Sgblack@eecs.umich.edu 2807639Sgblack@eecs.umich.edutemplate<class Impl> 2817639Sgblack@eecs.umich.eduvoid 2827639Sgblack@eecs.umich.eduLSQUnit<Impl>::resizeSQ(unsigned size) 2838444Sgblack@eecs.umich.edu{ 2848444Sgblack@eecs.umich.edu unsigned size_plus_sentinel = size + 1; 2857639Sgblack@eecs.umich.edu if (size_plus_sentinel > SQEntries) { 2867639Sgblack@eecs.umich.edu while (size_plus_sentinel > storeQueue.size()) { 2877639Sgblack@eecs.umich.edu SQEntry dummy; 2887639Sgblack@eecs.umich.edu storeQueue.push_back(dummy); 2897639Sgblack@eecs.umich.edu SQEntries++; 2908072SGiacomo.Gabrielli@arm.com } 2918072SGiacomo.Gabrielli@arm.com } else { 2927639Sgblack@eecs.umich.edu SQEntries = size_plus_sentinel; 2937639Sgblack@eecs.umich.edu } 2947639Sgblack@eecs.umich.edu} 2957639Sgblack@eecs.umich.edu 2967639Sgblack@eecs.umich.edutemplate <class Impl> 2977639Sgblack@eecs.umich.eduvoid 2987303Sgblack@eecs.umich.eduLSQUnit<Impl>::insert(DynInstPtr &inst) 2997303Sgblack@eecs.umich.edu{ 3007303Sgblack@eecs.umich.edu assert(inst->isMemRef()); 3017303Sgblack@eecs.umich.edu 3027303Sgblack@eecs.umich.edu assert(inst->isLoad() || inst->isStore()); 3037303Sgblack@eecs.umich.edu 3047303Sgblack@eecs.umich.edu if (inst->isLoad()) { 3057303Sgblack@eecs.umich.edu insertLoad(inst); 3067303Sgblack@eecs.umich.edu } else { 3077303Sgblack@eecs.umich.edu insertStore(inst); 3087303Sgblack@eecs.umich.edu } 3097303Sgblack@eecs.umich.edu 3107303Sgblack@eecs.umich.edu inst->setInLSQ(); 3117303Sgblack@eecs.umich.edu} 3127303Sgblack@eecs.umich.edu 3137303Sgblack@eecs.umich.edutemplate <class Impl> 3147303Sgblack@eecs.umich.eduvoid 3157303Sgblack@eecs.umich.eduLSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 3167303Sgblack@eecs.umich.edu{ 3177303Sgblack@eecs.umich.edu assert((loadTail + 1) % LQEntries != loadHead); 3188442Sgblack@eecs.umich.edu assert(loads < LQEntries); 3198442Sgblack@eecs.umich.edu 3207303Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n", 3217303Sgblack@eecs.umich.edu load_inst->readPC(), loadTail, load_inst->seqNum); 3227303Sgblack@eecs.umich.edu 3237303Sgblack@eecs.umich.edu load_inst->lqIdx = loadTail; 3247303Sgblack@eecs.umich.edu 3257303Sgblack@eecs.umich.edu if (stores == 0) { 3267303Sgblack@eecs.umich.edu load_inst->sqIdx = -1; 3277303Sgblack@eecs.umich.edu } else { 3287303Sgblack@eecs.umich.edu load_inst->sqIdx = storeTail; 3297597Sminkyu.jeong@arm.com } 3307597Sminkyu.jeong@arm.com 3317303Sgblack@eecs.umich.edu loadQueue[loadTail] = load_inst; 3327303Sgblack@eecs.umich.edu 3337303Sgblack@eecs.umich.edu incrLdIdx(loadTail); 3347303Sgblack@eecs.umich.edu 3357303Sgblack@eecs.umich.edu ++loads; 3367303Sgblack@eecs.umich.edu} 3377303Sgblack@eecs.umich.edu 3387303Sgblack@eecs.umich.edutemplate <class Impl> 3397303Sgblack@eecs.umich.eduvoid 3407303Sgblack@eecs.umich.eduLSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 3417303Sgblack@eecs.umich.edu{ 3427303Sgblack@eecs.umich.edu // Make sure it is not full before inserting an instruction. 3437303Sgblack@eecs.umich.edu assert((storeTail + 1) % SQEntries != storeHead); 3447303Sgblack@eecs.umich.edu assert(stores < SQEntries); 3457303Sgblack@eecs.umich.edu 3467303Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n", 3477303Sgblack@eecs.umich.edu store_inst->readPC(), storeTail, store_inst->seqNum); 3487303Sgblack@eecs.umich.edu 3497303Sgblack@eecs.umich.edu store_inst->sqIdx = storeTail; 3507303Sgblack@eecs.umich.edu store_inst->lqIdx = loadTail; 3517303Sgblack@eecs.umich.edu 3527303Sgblack@eecs.umich.edu storeQueue[storeTail] = SQEntry(store_inst); 3537303Sgblack@eecs.umich.edu 3547303Sgblack@eecs.umich.edu incrStIdx(storeTail); 3558442Sgblack@eecs.umich.edu 3568442Sgblack@eecs.umich.edu ++stores; 3577303Sgblack@eecs.umich.edu} 3587597Sminkyu.jeong@arm.com 3597597Sminkyu.jeong@arm.comtemplate <class Impl> 3607303Sgblack@eecs.umich.edutypename Impl::DynInstPtr 3617408Sgblack@eecs.umich.eduLSQUnit<Impl>::getMemDepViolator() 3627303Sgblack@eecs.umich.edu{ 3637303Sgblack@eecs.umich.edu DynInstPtr temp = memDepViolator; 3647303Sgblack@eecs.umich.edu 3657303Sgblack@eecs.umich.edu memDepViolator = NULL; 3667120Sgblack@eecs.umich.edu 3677120Sgblack@eecs.umich.edu return temp; 3687120Sgblack@eecs.umich.edu} 3697120Sgblack@eecs.umich.edu 3707120Sgblack@eecs.umich.edutemplate <class Impl> 3717120Sgblack@eecs.umich.eduunsigned 3727120Sgblack@eecs.umich.eduLSQUnit<Impl>::numFreeEntries() 3737120Sgblack@eecs.umich.edu{ 3747120Sgblack@eecs.umich.edu unsigned free_lq_entries = LQEntries - loads; 3757120Sgblack@eecs.umich.edu unsigned free_sq_entries = SQEntries - stores; 3767120Sgblack@eecs.umich.edu 3777120Sgblack@eecs.umich.edu // Both the LQ and SQ entries have an extra dummy entry to differentiate 3787120Sgblack@eecs.umich.edu // empty/full conditions. Subtract 1 from the free entries. 3797120Sgblack@eecs.umich.edu if (free_lq_entries < free_sq_entries) { 3807120Sgblack@eecs.umich.edu return free_lq_entries - 1; 3817120Sgblack@eecs.umich.edu } else { 3827120Sgblack@eecs.umich.edu return free_sq_entries - 1; 3837120Sgblack@eecs.umich.edu } 3848442Sgblack@eecs.umich.edu} 3858442Sgblack@eecs.umich.edu 3867120Sgblack@eecs.umich.edutemplate <class Impl> 3877597Sminkyu.jeong@arm.comint 3887597Sminkyu.jeong@arm.comLSQUnit<Impl>::numLoadsReady() 3897120Sgblack@eecs.umich.edu{ 3907120Sgblack@eecs.umich.edu int load_idx = loadHead; 3917120Sgblack@eecs.umich.edu int retval = 0; 3927120Sgblack@eecs.umich.edu 3937120Sgblack@eecs.umich.edu while (load_idx != loadTail) { 3947120Sgblack@eecs.umich.edu assert(loadQueue[load_idx]); 3957639Sgblack@eecs.umich.edu 3967639Sgblack@eecs.umich.edu if (loadQueue[load_idx]->readyToIssue()) { 3977639Sgblack@eecs.umich.edu ++retval; 3987639Sgblack@eecs.umich.edu } 3997639Sgblack@eecs.umich.edu } 4007639Sgblack@eecs.umich.edu 4017639Sgblack@eecs.umich.edu return retval; 4027639Sgblack@eecs.umich.edu} 4037639Sgblack@eecs.umich.edu 4047639Sgblack@eecs.umich.edutemplate <class Impl> 4057639Sgblack@eecs.umich.eduFault 4067639Sgblack@eecs.umich.eduLSQUnit<Impl>::executeLoad(DynInstPtr &inst) 4077639Sgblack@eecs.umich.edu{ 4087639Sgblack@eecs.umich.edu using namespace TheISA; 4097639Sgblack@eecs.umich.edu // Execute a specific load. 4107639Sgblack@eecs.umich.edu Fault load_fault = NoFault; 4117639Sgblack@eecs.umich.edu 4127639Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n", 4137639Sgblack@eecs.umich.edu inst->readPC(),inst->seqNum); 4147639Sgblack@eecs.umich.edu 4157639Sgblack@eecs.umich.edu assert(!inst->isSquashed()); 4168444Sgblack@eecs.umich.edu 4178444Sgblack@eecs.umich.edu load_fault = inst->initiateAcc(); 4187639Sgblack@eecs.umich.edu 4198072SGiacomo.Gabrielli@arm.com // If the instruction faulted, then we need to send it along to commit 4208072SGiacomo.Gabrielli@arm.com // without the instruction completing. 4217639Sgblack@eecs.umich.edu if (load_fault != NoFault) { 4227639Sgblack@eecs.umich.edu // Send this instruction to commit, also make sure iew stage 4237639Sgblack@eecs.umich.edu // realizes there is activity. 4247639Sgblack@eecs.umich.edu // Mark it as executed unless it is an uncached load that 4257639Sgblack@eecs.umich.edu // needs to hit the head of commit. 4267639Sgblack@eecs.umich.edu if (!(inst->hasRequest() && inst->uncacheable()) || 4277119Sgblack@eecs.umich.edu inst->isAtCommit()) { 4287119Sgblack@eecs.umich.edu inst->setExecuted(); 4297119Sgblack@eecs.umich.edu } 4307119Sgblack@eecs.umich.edu iewStage->instToCommit(inst); 4317119Sgblack@eecs.umich.edu iewStage->activityThisCycle(); 4327119Sgblack@eecs.umich.edu } else if (!loadBlocked()) { 4337119Sgblack@eecs.umich.edu assert(inst->effAddrValid); 4347119Sgblack@eecs.umich.edu int load_idx = inst->lqIdx; 4357119Sgblack@eecs.umich.edu incrLdIdx(load_idx); 4367119Sgblack@eecs.umich.edu while (load_idx != loadTail) { 4377119Sgblack@eecs.umich.edu // Really only need to check loads that have actually executed 4387119Sgblack@eecs.umich.edu 4397119Sgblack@eecs.umich.edu // @todo: For now this is extra conservative, detecting a 4407119Sgblack@eecs.umich.edu // violation if the addresses match assuming all accesses 4418442Sgblack@eecs.umich.edu // are quad word accesses. 4427119Sgblack@eecs.umich.edu 4437597Sminkyu.jeong@arm.com // @todo: Fix this, magic number being used here 4447597Sminkyu.jeong@arm.com if (loadQueue[load_idx]->effAddrValid && 4457119Sgblack@eecs.umich.edu (loadQueue[load_idx]->effAddr >> 8) == 4467119Sgblack@eecs.umich.edu (inst->effAddr >> 8)) { 4477119Sgblack@eecs.umich.edu // A load incorrectly passed this load. Squash and refetch. 4487119Sgblack@eecs.umich.edu // For now return a fault to show that it was unsuccessful. 4497119Sgblack@eecs.umich.edu DynInstPtr violator = loadQueue[load_idx]; 4507119Sgblack@eecs.umich.edu if (!memDepViolator || 4517639Sgblack@eecs.umich.edu (violator->seqNum < memDepViolator->seqNum)) { 4527639Sgblack@eecs.umich.edu memDepViolator = violator; 4537639Sgblack@eecs.umich.edu } else { 4547639Sgblack@eecs.umich.edu break; 4557639Sgblack@eecs.umich.edu } 4567639Sgblack@eecs.umich.edu 4577639Sgblack@eecs.umich.edu ++lsqMemOrderViolation; 4587639Sgblack@eecs.umich.edu 4598207SAli.Saidi@ARM.com return genMachineCheckFault(); 4608207SAli.Saidi@ARM.com } 4617639Sgblack@eecs.umich.edu 4627639Sgblack@eecs.umich.edu incrLdIdx(load_idx); 4637639Sgblack@eecs.umich.edu } 4648207SAli.Saidi@ARM.com } 4658207SAli.Saidi@ARM.com 4668207SAli.Saidi@ARM.com return load_fault; 4677639Sgblack@eecs.umich.edu} 4687639Sgblack@eecs.umich.edu 4697639Sgblack@eecs.umich.edutemplate <class Impl> 4708444Sgblack@eecs.umich.eduFault 4717639Sgblack@eecs.umich.eduLSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 4728072SGiacomo.Gabrielli@arm.com{ 4738072SGiacomo.Gabrielli@arm.com using namespace TheISA; 4747639Sgblack@eecs.umich.edu // Make sure that a store exists. 4757639Sgblack@eecs.umich.edu assert(stores != 0); 4767639Sgblack@eecs.umich.edu 4777639Sgblack@eecs.umich.edu int store_idx = store_inst->sqIdx; 4787639Sgblack@eecs.umich.edu 4797639Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n", 4807119Sgblack@eecs.umich.edu store_inst->readPC(), store_inst->seqNum); 4817119Sgblack@eecs.umich.edu 4827119Sgblack@eecs.umich.edu assert(!store_inst->isSquashed()); 4837119Sgblack@eecs.umich.edu 4847119Sgblack@eecs.umich.edu // Check the recently completed loads to see if any match this store's 4857119Sgblack@eecs.umich.edu // address. If so, then we have a memory ordering violation. 4867119Sgblack@eecs.umich.edu int load_idx = store_inst->lqIdx; 4877119Sgblack@eecs.umich.edu 4887119Sgblack@eecs.umich.edu Fault store_fault = store_inst->initiateAcc(); 4897119Sgblack@eecs.umich.edu 4907119Sgblack@eecs.umich.edu if (storeQueue[store_idx].size == 0) { 4917119Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n", 4927119Sgblack@eecs.umich.edu store_inst->readPC(),store_inst->seqNum); 4938442Sgblack@eecs.umich.edu 4947119Sgblack@eecs.umich.edu return store_fault; 4957119Sgblack@eecs.umich.edu } 4967119Sgblack@eecs.umich.edu 4977119Sgblack@eecs.umich.edu assert(store_fault == NoFault); 4987119Sgblack@eecs.umich.edu 4997119Sgblack@eecs.umich.edu if (store_inst->isStoreConditional()) { 5007119Sgblack@eecs.umich.edu // Store conditionals need to set themselves as able to 5017119Sgblack@eecs.umich.edu // writeback if we haven't had a fault by here. 5027119Sgblack@eecs.umich.edu storeQueue[store_idx].canWB = true; 5037119Sgblack@eecs.umich.edu 5047119Sgblack@eecs.umich.edu ++storesToWB; 5057119Sgblack@eecs.umich.edu } 5067119Sgblack@eecs.umich.edu 5077119Sgblack@eecs.umich.edu assert(store_inst->effAddrValid); 5087639Sgblack@eecs.umich.edu while (load_idx != loadTail) { 5097639Sgblack@eecs.umich.edu // Really only need to check loads that have actually executed 5107639Sgblack@eecs.umich.edu // It's safe to check all loads because effAddr is set to 5117639Sgblack@eecs.umich.edu // InvalAddr when the dyn inst is created. 5127639Sgblack@eecs.umich.edu 5137639Sgblack@eecs.umich.edu // @todo: For now this is extra conservative, detecting a 5147639Sgblack@eecs.umich.edu // violation if the addresses match assuming all accesses 5157639Sgblack@eecs.umich.edu // are quad word accesses. 5167639Sgblack@eecs.umich.edu 5177639Sgblack@eecs.umich.edu // @todo: Fix this, magic number being used here 5187639Sgblack@eecs.umich.edu if (loadQueue[load_idx]->effAddrValid && 5197639Sgblack@eecs.umich.edu (loadQueue[load_idx]->effAddr >> 8) == 5207639Sgblack@eecs.umich.edu (store_inst->effAddr >> 8)) { 5217639Sgblack@eecs.umich.edu // A load incorrectly passed this store. Squash and refetch. 5227639Sgblack@eecs.umich.edu // For now return a fault to show that it was unsuccessful. 5237639Sgblack@eecs.umich.edu DynInstPtr violator = loadQueue[load_idx]; 5247639Sgblack@eecs.umich.edu if (!memDepViolator || 5257639Sgblack@eecs.umich.edu (violator->seqNum < memDepViolator->seqNum)) { 5267639Sgblack@eecs.umich.edu memDepViolator = violator; 5277639Sgblack@eecs.umich.edu } else { 5287639Sgblack@eecs.umich.edu break; 5297639Sgblack@eecs.umich.edu } 5307639Sgblack@eecs.umich.edu 5317639Sgblack@eecs.umich.edu ++lsqMemOrderViolation; 5327639Sgblack@eecs.umich.edu 5337639Sgblack@eecs.umich.edu return genMachineCheckFault(); 5347639Sgblack@eecs.umich.edu } 5357639Sgblack@eecs.umich.edu 5367639Sgblack@eecs.umich.edu incrLdIdx(load_idx); 5377639Sgblack@eecs.umich.edu } 5387120Sgblack@eecs.umich.edu 5397120Sgblack@eecs.umich.edu return store_fault; 5407120Sgblack@eecs.umich.edu} 5417120Sgblack@eecs.umich.edu 5427120Sgblack@eecs.umich.edutemplate <class Impl> 5437712Sgblack@eecs.umich.eduvoid 5447120Sgblack@eecs.umich.eduLSQUnit<Impl>::commitLoad() 5457120Sgblack@eecs.umich.edu{ 5467120Sgblack@eecs.umich.edu assert(loadQueue[loadHead]); 5477639Sgblack@eecs.umich.edu 5487639Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n", 5497639Sgblack@eecs.umich.edu loadQueue[loadHead]->readPC()); 5507639Sgblack@eecs.umich.edu 5517639Sgblack@eecs.umich.edu loadQueue[loadHead] = NULL; 5527639Sgblack@eecs.umich.edu 5537712Sgblack@eecs.umich.edu incrLdIdx(loadHead); 5547639Sgblack@eecs.umich.edu 5557639Sgblack@eecs.umich.edu --loads; 5567639Sgblack@eecs.umich.edu} 5577303Sgblack@eecs.umich.edu 5587303Sgblack@eecs.umich.edutemplate <class Impl> 5597303Sgblack@eecs.umich.eduvoid 5607303Sgblack@eecs.umich.eduLSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 5617303Sgblack@eecs.umich.edu{ 5627303Sgblack@eecs.umich.edu assert(loads == 0 || loadQueue[loadHead]); 5637303Sgblack@eecs.umich.edu 5647303Sgblack@eecs.umich.edu while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 5657303Sgblack@eecs.umich.edu commitLoad(); 5667303Sgblack@eecs.umich.edu } 5677303Sgblack@eecs.umich.edu} 5687303Sgblack@eecs.umich.edu 5697303Sgblack@eecs.umich.edutemplate <class Impl> 5707303Sgblack@eecs.umich.eduvoid 5717303Sgblack@eecs.umich.eduLSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 5727303Sgblack@eecs.umich.edu{ 5737303Sgblack@eecs.umich.edu assert(stores == 0 || storeQueue[storeHead].inst); 5747303Sgblack@eecs.umich.edu 5757303Sgblack@eecs.umich.edu int store_idx = storeHead; 5767303Sgblack@eecs.umich.edu 5777303Sgblack@eecs.umich.edu while (store_idx != storeTail) { 5787303Sgblack@eecs.umich.edu assert(storeQueue[store_idx].inst); 5797303Sgblack@eecs.umich.edu // Mark any stores that are now committed and have not yet 5807303Sgblack@eecs.umich.edu // been marked as able to write back. 5817291Sgblack@eecs.umich.edu if (!storeQueue[store_idx].canWB) { 5827291Sgblack@eecs.umich.edu if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 5837291Sgblack@eecs.umich.edu break; 5847291Sgblack@eecs.umich.edu } 5857291Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Marking store as able to write back, PC " 5867291Sgblack@eecs.umich.edu "%#x [sn:%lli]\n", 5877291Sgblack@eecs.umich.edu storeQueue[store_idx].inst->readPC(), 5887291Sgblack@eecs.umich.edu storeQueue[store_idx].inst->seqNum); 5897291Sgblack@eecs.umich.edu 5907291Sgblack@eecs.umich.edu storeQueue[store_idx].canWB = true; 5917291Sgblack@eecs.umich.edu 5927291Sgblack@eecs.umich.edu ++storesToWB; 5937291Sgblack@eecs.umich.edu } 5947291Sgblack@eecs.umich.edu 5957291Sgblack@eecs.umich.edu incrStIdx(store_idx); 5967291Sgblack@eecs.umich.edu } 5977291Sgblack@eecs.umich.edu} 5987291Sgblack@eecs.umich.edu 5997291Sgblack@eecs.umich.edutemplate <class Impl> 6007291Sgblack@eecs.umich.eduvoid 6017312Sgblack@eecs.umich.eduLSQUnit<Impl>::writebackStores() 6027312Sgblack@eecs.umich.edu{ 6037312Sgblack@eecs.umich.edu while (storesToWB > 0 && 6047312Sgblack@eecs.umich.edu storeWBIdx != storeTail && 6057312Sgblack@eecs.umich.edu storeQueue[storeWBIdx].inst && 6067312Sgblack@eecs.umich.edu storeQueue[storeWBIdx].canWB && 6077312Sgblack@eecs.umich.edu usedPorts < cachePorts) { 6087312Sgblack@eecs.umich.edu 6097312Sgblack@eecs.umich.edu if (isStoreBlocked || lsq->cacheBlocked()) { 6107312Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 6117312Sgblack@eecs.umich.edu " is blocked!\n"); 6127312Sgblack@eecs.umich.edu break; 6137312Sgblack@eecs.umich.edu } 6147312Sgblack@eecs.umich.edu 6157312Sgblack@eecs.umich.edu // Store didn't write any data so no need to write it back to 6167312Sgblack@eecs.umich.edu // memory. 6177312Sgblack@eecs.umich.edu if (storeQueue[storeWBIdx].size == 0) { 6187312Sgblack@eecs.umich.edu completeStore(storeWBIdx); 6197312Sgblack@eecs.umich.edu 6207312Sgblack@eecs.umich.edu incrStIdx(storeWBIdx); 6217205Sgblack@eecs.umich.edu 6227205Sgblack@eecs.umich.edu continue; 6237205Sgblack@eecs.umich.edu } 6247205Sgblack@eecs.umich.edu 6257205Sgblack@eecs.umich.edu ++usedPorts; 6267205Sgblack@eecs.umich.edu 6277205Sgblack@eecs.umich.edu if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 6287205Sgblack@eecs.umich.edu incrStIdx(storeWBIdx); 6297205Sgblack@eecs.umich.edu 6307205Sgblack@eecs.umich.edu continue; 6317205Sgblack@eecs.umich.edu } 6327205Sgblack@eecs.umich.edu 6337205Sgblack@eecs.umich.edu assert(storeQueue[storeWBIdx].req); 6347205Sgblack@eecs.umich.edu assert(!storeQueue[storeWBIdx].committed); 6357205Sgblack@eecs.umich.edu 6367205Sgblack@eecs.umich.edu DynInstPtr inst = storeQueue[storeWBIdx].inst; 6377205Sgblack@eecs.umich.edu 6387205Sgblack@eecs.umich.edu Request *req = storeQueue[storeWBIdx].req; 6397205Sgblack@eecs.umich.edu storeQueue[storeWBIdx].committed = true; 6407205Sgblack@eecs.umich.edu 6417279Sgblack@eecs.umich.edu assert(!inst->memData); 6427279Sgblack@eecs.umich.edu inst->memData = new uint8_t[64]; 6437279Sgblack@eecs.umich.edu 6447279Sgblack@eecs.umich.edu TheISA::IntReg convertedData = 6457279Sgblack@eecs.umich.edu TheISA::htog(storeQueue[storeWBIdx].data); 6467279Sgblack@eecs.umich.edu 6477279Sgblack@eecs.umich.edu //FIXME This is a hack to get SPARC working. It, along with endianness 6487279Sgblack@eecs.umich.edu //in the memory system in general, need to be straightened out more 6497279Sgblack@eecs.umich.edu //formally. The problem is that the data's endianness is swapped when 6507279Sgblack@eecs.umich.edu //it's in the 64 bit data field in the store queue. The data that you 6517279Sgblack@eecs.umich.edu //want won't start at the beginning of the field anymore unless it was 6527279Sgblack@eecs.umich.edu //a 64 bit access. 6537279Sgblack@eecs.umich.edu memcpy(inst->memData, 6547279Sgblack@eecs.umich.edu (uint8_t *)&convertedData + 6557279Sgblack@eecs.umich.edu (TheISA::ByteOrderDiffers ? 6567279Sgblack@eecs.umich.edu (sizeof(TheISA::IntReg) - req->getSize()) : 0), 6577279Sgblack@eecs.umich.edu req->getSize()); 6587279Sgblack@eecs.umich.edu 6597279Sgblack@eecs.umich.edu PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast); 6607279Sgblack@eecs.umich.edu data_pkt->dataStatic(inst->memData); 6617279Sgblack@eecs.umich.edu 6627303Sgblack@eecs.umich.edu LSQSenderState *state = new LSQSenderState; 6637303Sgblack@eecs.umich.edu state->isLoad = false; 6647303Sgblack@eecs.umich.edu state->idx = storeWBIdx; 6657303Sgblack@eecs.umich.edu state->inst = inst; 6667303Sgblack@eecs.umich.edu data_pkt->senderState = state; 6677303Sgblack@eecs.umich.edu 6687303Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x " 6697303Sgblack@eecs.umich.edu "to Addr:%#x, data:%#x [sn:%lli]\n", 6707303Sgblack@eecs.umich.edu storeWBIdx, inst->readPC(), 6717303Sgblack@eecs.umich.edu req->getPaddr(), (int)*(inst->memData), 6727303Sgblack@eecs.umich.edu inst->seqNum); 6737303Sgblack@eecs.umich.edu 6747303Sgblack@eecs.umich.edu // @todo: Remove this SC hack once the memory system handles it. 6757303Sgblack@eecs.umich.edu if (req->isLocked()) { 6767303Sgblack@eecs.umich.edu // Disable recording the result temporarily. Writing to 6777303Sgblack@eecs.umich.edu // misc regs normally updates the result, but this is not 6787303Sgblack@eecs.umich.edu // the desired behavior when handling store conditionals. 6797303Sgblack@eecs.umich.edu inst->recordResult = false; 6807303Sgblack@eecs.umich.edu bool success = TheISA::handleLockedWrite(inst.get(), req); 6817303Sgblack@eecs.umich.edu inst->recordResult = true; 6827303Sgblack@eecs.umich.edu 6837119Sgblack@eecs.umich.edu if (!success) { 6847119Sgblack@eecs.umich.edu // Instantly complete this store. 6857119Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 6867119Sgblack@eecs.umich.edu "Instantly completing it.\n", 6877119Sgblack@eecs.umich.edu inst->seqNum); 6887119Sgblack@eecs.umich.edu WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 6897119Sgblack@eecs.umich.edu wb->schedule(curTick + 1); 6907119Sgblack@eecs.umich.edu delete state; 6917119Sgblack@eecs.umich.edu completeStore(storeWBIdx); 6927119Sgblack@eecs.umich.edu incrStIdx(storeWBIdx); 6937119Sgblack@eecs.umich.edu continue; 6947119Sgblack@eecs.umich.edu } 6957119Sgblack@eecs.umich.edu } else { 6967119Sgblack@eecs.umich.edu // Non-store conditionals do not need a writeback. 6977119Sgblack@eecs.umich.edu state->noWB = true; 6987119Sgblack@eecs.umich.edu } 6997119Sgblack@eecs.umich.edu 70010037SARM gem5 Developers if (!dcachePort->sendTiming(data_pkt)) { 70110037SARM gem5 Developers if (data_pkt->result == Packet::BadAddress) { 70210037SARM gem5 Developers panic("LSQ sent out a bad address for a completed store!"); 70310037SARM gem5 Developers } 70410037SARM gem5 Developers // Need to handle becoming blocked on a store. 7057119Sgblack@eecs.umich.edu DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 7067119Sgblack@eecs.umich.edu "retry later\n", 7077119Sgblack@eecs.umich.edu inst->seqNum); 7087303Sgblack@eecs.umich.edu isStoreBlocked = true; 7097303Sgblack@eecs.umich.edu ++lsqCacheBlocked; 7107303Sgblack@eecs.umich.edu assert(retryPkt == NULL); 7117303Sgblack@eecs.umich.edu retryPkt = data_pkt; 7127303Sgblack@eecs.umich.edu lsq->setRetryTid(lsqID); 7137303Sgblack@eecs.umich.edu } else { 7147303Sgblack@eecs.umich.edu storePostSend(data_pkt); 7157303Sgblack@eecs.umich.edu } 7167303Sgblack@eecs.umich.edu } 7177303Sgblack@eecs.umich.edu 7187303Sgblack@eecs.umich.edu // Not sure this should set it to 0. 7197303Sgblack@eecs.umich.edu usedPorts = 0; 7207303Sgblack@eecs.umich.edu 7217303Sgblack@eecs.umich.edu assert(stores >= 0 && storesToWB >= 0); 7227303Sgblack@eecs.umich.edu} 7237303Sgblack@eecs.umich.edu 7247303Sgblack@eecs.umich.edu/*template <class Impl> 7257303Sgblack@eecs.umich.eduvoid 7267303Sgblack@eecs.umich.eduLSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 7277303Sgblack@eecs.umich.edu{ 7287303Sgblack@eecs.umich.edu list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 7297646Sgene.wu@arm.com mshrSeqNums.end(), 7307279Sgblack@eecs.umich.edu seqNum); 7317279Sgblack@eecs.umich.edu 7327279Sgblack@eecs.umich.edu if (mshr_it != mshrSeqNums.end()) { 7337279Sgblack@eecs.umich.edu mshrSeqNums.erase(mshr_it); 7347279Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 7357279Sgblack@eecs.umich.edu } 7367279Sgblack@eecs.umich.edu}*/ 7377279Sgblack@eecs.umich.edu 7387279Sgblack@eecs.umich.edutemplate <class Impl> 7397279Sgblack@eecs.umich.eduvoid 7407279Sgblack@eecs.umich.eduLSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 7417279Sgblack@eecs.umich.edu{ 7427279Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 7437279Sgblack@eecs.umich.edu "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 7447279Sgblack@eecs.umich.edu 7457279Sgblack@eecs.umich.edu int load_idx = loadTail; 7467279Sgblack@eecs.umich.edu decrLdIdx(load_idx); 7477279Sgblack@eecs.umich.edu 7487279Sgblack@eecs.umich.edu while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 7497279Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, " 7507279Sgblack@eecs.umich.edu "[sn:%lli]\n", 7517279Sgblack@eecs.umich.edu loadQueue[load_idx]->readPC(), 7527646Sgene.wu@arm.com loadQueue[load_idx]->seqNum); 7537119Sgblack@eecs.umich.edu 7547119Sgblack@eecs.umich.edu if (isStalled() && load_idx == stallingLoadIdx) { 7557119Sgblack@eecs.umich.edu stalled = false; 7567119Sgblack@eecs.umich.edu stallingStoreIsn = 0; 7577119Sgblack@eecs.umich.edu stallingLoadIdx = 0; 7587119Sgblack@eecs.umich.edu } 7597119Sgblack@eecs.umich.edu 7607119Sgblack@eecs.umich.edu // Clear the smart pointer to make sure it is decremented. 7617119Sgblack@eecs.umich.edu loadQueue[load_idx]->setSquashed(); 7627119Sgblack@eecs.umich.edu loadQueue[load_idx] = NULL; 7637119Sgblack@eecs.umich.edu --loads; 7647119Sgblack@eecs.umich.edu 7657119Sgblack@eecs.umich.edu // Inefficient! 7667119Sgblack@eecs.umich.edu loadTail = load_idx; 7677119Sgblack@eecs.umich.edu 7687119Sgblack@eecs.umich.edu decrLdIdx(load_idx); 7697119Sgblack@eecs.umich.edu ++lsqSquashedLoads; 7707119Sgblack@eecs.umich.edu } 77110037SARM gem5 Developers 77210037SARM gem5 Developers if (isLoadBlocked) { 77310037SARM gem5 Developers if (squashed_num < blockedLoadSeqNum) { 77410037SARM gem5 Developers isLoadBlocked = false; 77510037SARM gem5 Developers loadBlockedHandled = false; 7767119Sgblack@eecs.umich.edu blockedLoadSeqNum = 0; 7777119Sgblack@eecs.umich.edu } 7787119Sgblack@eecs.umich.edu } 7797646Sgene.wu@arm.com 7807646Sgene.wu@arm.com if (memDepViolator && squashed_num < memDepViolator->seqNum) { 7817646Sgene.wu@arm.com memDepViolator = NULL; 7827646Sgene.wu@arm.com } 7837646Sgene.wu@arm.com 7847646Sgene.wu@arm.com int store_idx = storeTail; 7857646Sgene.wu@arm.com decrStIdx(store_idx); 7867646Sgene.wu@arm.com 7877646Sgene.wu@arm.com while (stores != 0 && 7887646Sgene.wu@arm.com storeQueue[store_idx].inst->seqNum > squashed_num) { 7897646Sgene.wu@arm.com // Instructions marked as can WB are already committed. 7907646Sgene.wu@arm.com if (storeQueue[store_idx].canWB) { 7917646Sgene.wu@arm.com break; 7927646Sgene.wu@arm.com } 7937646Sgene.wu@arm.com 7947646Sgene.wu@arm.com DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, " 7957646Sgene.wu@arm.com "idx:%i [sn:%lli]\n", 7967646Sgene.wu@arm.com storeQueue[store_idx].inst->readPC(), 7977646Sgene.wu@arm.com store_idx, storeQueue[store_idx].inst->seqNum); 7987646Sgene.wu@arm.com 7997646Sgene.wu@arm.com // I don't think this can happen. It should have been cleared 8007646Sgene.wu@arm.com // by the stalling load. 8017646Sgene.wu@arm.com if (isStalled() && 8027646Sgene.wu@arm.com storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 8037646Sgene.wu@arm.com panic("Is stalled should have been cleared by stalling load!\n"); 8047646Sgene.wu@arm.com stalled = false; 8057646Sgene.wu@arm.com stallingStoreIsn = 0; 8067646Sgene.wu@arm.com } 8077646Sgene.wu@arm.com 8087646Sgene.wu@arm.com // Clear the smart pointer to make sure it is decremented. 8097646Sgene.wu@arm.com storeQueue[store_idx].inst->setSquashed(); 8107646Sgene.wu@arm.com storeQueue[store_idx].inst = NULL; 8117646Sgene.wu@arm.com storeQueue[store_idx].canWB = 0; 8127646Sgene.wu@arm.com 8137646Sgene.wu@arm.com // Must delete request now that it wasn't handed off to 8147646Sgene.wu@arm.com // memory. This is quite ugly. @todo: Figure out the proper 8157646Sgene.wu@arm.com // place to really handle request deletes. 8167646Sgene.wu@arm.com delete storeQueue[store_idx].req; 8177646Sgene.wu@arm.com 8187646Sgene.wu@arm.com storeQueue[store_idx].req = NULL; 8197646Sgene.wu@arm.com --stores; 8207646Sgene.wu@arm.com 82110037SARM gem5 Developers // Inefficient! 82210037SARM gem5 Developers storeTail = store_idx; 82310037SARM gem5 Developers 82410037SARM gem5 Developers decrStIdx(store_idx); 82510037SARM gem5 Developers ++lsqSquashedStores; 8267646Sgene.wu@arm.com } 8277646Sgene.wu@arm.com} 8287646Sgene.wu@arm.com 8297646Sgene.wu@arm.comtemplate <class Impl> 8307646Sgene.wu@arm.comvoid 8317646Sgene.wu@arm.comLSQUnit<Impl>::storePostSend(PacketPtr pkt) 8327646Sgene.wu@arm.com{ 8337646Sgene.wu@arm.com if (isStalled() && 8347646Sgene.wu@arm.com storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 8357646Sgene.wu@arm.com DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 8367646Sgene.wu@arm.com "load idx:%i\n", 8377646Sgene.wu@arm.com stallingStoreIsn, stallingLoadIdx); 8387646Sgene.wu@arm.com stalled = false; 8397646Sgene.wu@arm.com stallingStoreIsn = 0; 8407646Sgene.wu@arm.com iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 8417646Sgene.wu@arm.com } 8427646Sgene.wu@arm.com 8437646Sgene.wu@arm.com if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 8447646Sgene.wu@arm.com // The store is basically completed at this time. This 8457646Sgene.wu@arm.com // only works so long as the checker doesn't try to 84610037SARM gem5 Developers // verify the value in memory for stores. 84710037SARM gem5 Developers storeQueue[storeWBIdx].inst->setCompleted(); 84810037SARM gem5 Developers#if USE_CHECKER 84910037SARM gem5 Developers if (cpu->checker) { 85010037SARM gem5 Developers cpu->checker->verify(storeQueue[storeWBIdx].inst); 8517646Sgene.wu@arm.com } 8527646Sgene.wu@arm.com#endif 8537646Sgene.wu@arm.com } 8547119Sgblack@eecs.umich.edu 8557119Sgblack@eecs.umich.edu if (pkt->result != Packet::Success) { 8567119Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n", 8577119Sgblack@eecs.umich.edu storeWBIdx); 8587119Sgblack@eecs.umich.edu 8597119Sgblack@eecs.umich.edu DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n", 8607119Sgblack@eecs.umich.edu storeQueue[storeWBIdx].inst->seqNum); 8617119Sgblack@eecs.umich.edu 8627291Sgblack@eecs.umich.edu //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum); 86310184SCurtis.Dunham@arm.com 8648140SMatt.Horsnell@arm.com //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size()); 8658140SMatt.Horsnell@arm.com 8668140SMatt.Horsnell@arm.com // @todo: Increment stat here. 8677291Sgblack@eecs.umich.edu } else { 8687291Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n", 8697848SAli.Saidi@ARM.com storeWBIdx); 8707848SAli.Saidi@ARM.com 8717848SAli.Saidi@ARM.com DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n", 8727848SAli.Saidi@ARM.com storeQueue[storeWBIdx].inst->seqNum); 8737848SAli.Saidi@ARM.com } 8747646Sgene.wu@arm.com 8758140SMatt.Horsnell@arm.com incrStIdx(storeWBIdx); 8768140SMatt.Horsnell@arm.com} 8778140SMatt.Horsnell@arm.com 8788140SMatt.Horsnell@arm.comtemplate <class Impl> 8798140SMatt.Horsnell@arm.comvoid 8808140SMatt.Horsnell@arm.comLSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 8818140SMatt.Horsnell@arm.com{ 8828140SMatt.Horsnell@arm.com iewStage->wakeCPU(); 8838140SMatt.Horsnell@arm.com 8848140SMatt.Horsnell@arm.com // Squashed instructions do not need to complete their access. 8858140SMatt.Horsnell@arm.com if (inst->isSquashed()) { 8868140SMatt.Horsnell@arm.com iewStage->decrWb(inst->seqNum); 8877646Sgene.wu@arm.com assert(!inst->isStore()); 8887291Sgblack@eecs.umich.edu ++lsqIgnoredResponses; 8897291Sgblack@eecs.umich.edu return; 8907291Sgblack@eecs.umich.edu } 8917312Sgblack@eecs.umich.edu 89210184SCurtis.Dunham@arm.com if (!inst->isExecuted()) { 8937312Sgblack@eecs.umich.edu inst->setExecuted(); 8947312Sgblack@eecs.umich.edu 8957312Sgblack@eecs.umich.edu // Complete access to copy data to proper place. 8967312Sgblack@eecs.umich.edu inst->completeAcc(pkt); 8977312Sgblack@eecs.umich.edu } 8987848SAli.Saidi@ARM.com 8997848SAli.Saidi@ARM.com // Need to insert instruction into queue to commit 9007848SAli.Saidi@ARM.com iewStage->instToCommit(inst); 9017848SAli.Saidi@ARM.com 9027848SAli.Saidi@ARM.com iewStage->activityThisCycle(); 9037646Sgene.wu@arm.com} 9047646Sgene.wu@arm.com 9057646Sgene.wu@arm.comtemplate <class Impl> 9067646Sgene.wu@arm.comvoid 9077724SAli.Saidi@ARM.comLSQUnit<Impl>::completeStore(int store_idx) 9087646Sgene.wu@arm.com{ 9097646Sgene.wu@arm.com assert(storeQueue[store_idx].inst); 9107646Sgene.wu@arm.com storeQueue[store_idx].completed = true; 9117312Sgblack@eecs.umich.edu --storesToWB; 9127312Sgblack@eecs.umich.edu // A bit conservative because a store completion may not free up entries, 9137312Sgblack@eecs.umich.edu // but hopefully avoids two store completions in one cycle from making 9147205Sgblack@eecs.umich.edu // the CPU tick twice. 91510184SCurtis.Dunham@arm.com cpu->wakeCPU(); 9167205Sgblack@eecs.umich.edu cpu->activityThisCycle(); 9177205Sgblack@eecs.umich.edu 9187205Sgblack@eecs.umich.edu if (store_idx == storeHead) { 9197205Sgblack@eecs.umich.edu do { 9207205Sgblack@eecs.umich.edu incrStIdx(storeHead); 9217848SAli.Saidi@ARM.com 9227848SAli.Saidi@ARM.com --stores; 9237848SAli.Saidi@ARM.com } while (storeQueue[storeHead].completed && 9247848SAli.Saidi@ARM.com storeHead != storeTail); 9257848SAli.Saidi@ARM.com 9267205Sgblack@eecs.umich.edu iewStage->updateLSQNextCycle = true; 9277205Sgblack@eecs.umich.edu } 9287205Sgblack@eecs.umich.edu 9297279Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 93010184SCurtis.Dunham@arm.com "idx:%i\n", 9317279Sgblack@eecs.umich.edu storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 9327279Sgblack@eecs.umich.edu 9337279Sgblack@eecs.umich.edu if (isStalled() && 9347279Sgblack@eecs.umich.edu storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 9357279Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 9367279Sgblack@eecs.umich.edu "load idx:%i\n", 9377279Sgblack@eecs.umich.edu stallingStoreIsn, stallingLoadIdx); 9387848SAli.Saidi@ARM.com stalled = false; 9397848SAli.Saidi@ARM.com stallingStoreIsn = 0; 9407848SAli.Saidi@ARM.com iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 9417848SAli.Saidi@ARM.com } 9427848SAli.Saidi@ARM.com 9437646Sgene.wu@arm.com storeQueue[store_idx].inst->setCompleted(); 9447646Sgene.wu@arm.com 9457646Sgene.wu@arm.com // Tell the checker we've completed this instruction. Some stores 9467646Sgene.wu@arm.com // may get reported twice to the checker, but the checker can 9477724SAli.Saidi@ARM.com // handle that case. 9487646Sgene.wu@arm.com#if USE_CHECKER 9497646Sgene.wu@arm.com if (cpu->checker) { 9507646Sgene.wu@arm.com cpu->checker->verify(storeQueue[store_idx].inst); 9517279Sgblack@eecs.umich.edu } 9527279Sgblack@eecs.umich.edu#endif 9537279Sgblack@eecs.umich.edu} 9547303Sgblack@eecs.umich.edu 95510184SCurtis.Dunham@arm.comtemplate <class Impl> 9567303Sgblack@eecs.umich.eduvoid 9577303Sgblack@eecs.umich.eduLSQUnit<Impl>::recvRetry() 9587303Sgblack@eecs.umich.edu{ 9597303Sgblack@eecs.umich.edu if (isStoreBlocked) { 9607303Sgblack@eecs.umich.edu assert(retryPkt != NULL); 9617303Sgblack@eecs.umich.edu 9627303Sgblack@eecs.umich.edu if (dcachePort->sendTiming(retryPkt)) { 9637303Sgblack@eecs.umich.edu if (retryPkt->result == Packet::BadAddress) { 9647848SAli.Saidi@ARM.com panic("LSQ sent out a bad address for a completed store!"); 9657848SAli.Saidi@ARM.com } 9667848SAli.Saidi@ARM.com storePostSend(retryPkt); 9677848SAli.Saidi@ARM.com retryPkt = NULL; 9687848SAli.Saidi@ARM.com isStoreBlocked = false; 9697646Sgene.wu@arm.com lsq->setRetryTid(-1); 9707646Sgene.wu@arm.com } else { 9717646Sgene.wu@arm.com // Still blocked! 9727646Sgene.wu@arm.com ++lsqCacheBlocked; 9737646Sgene.wu@arm.com lsq->setRetryTid(lsqID); 9747724SAli.Saidi@ARM.com } 9757646Sgene.wu@arm.com } else if (isLoadBlocked) { 9767646Sgene.wu@arm.com DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 9777646Sgene.wu@arm.com "no need to resend packet.\n"); 9787303Sgblack@eecs.umich.edu } else { 9797303Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 9807303Sgblack@eecs.umich.edu } 9817119Sgblack@eecs.umich.edu} 98210184SCurtis.Dunham@arm.com 9837119Sgblack@eecs.umich.edutemplate <class Impl> 9847119Sgblack@eecs.umich.eduinline void 9857119Sgblack@eecs.umich.eduLSQUnit<Impl>::incrStIdx(int &store_idx) 9867119Sgblack@eecs.umich.edu{ 9877119Sgblack@eecs.umich.edu if (++store_idx >= SQEntries) 9887848SAli.Saidi@ARM.com store_idx = 0; 9897848SAli.Saidi@ARM.com} 9907848SAli.Saidi@ARM.com 9917848SAli.Saidi@ARM.comtemplate <class Impl> 9927848SAli.Saidi@ARM.cominline void 9937646Sgene.wu@arm.comLSQUnit<Impl>::decrStIdx(int &store_idx) 9947646Sgene.wu@arm.com{ 9957646Sgene.wu@arm.com if (--store_idx < 0) 9967646Sgene.wu@arm.com store_idx += SQEntries; 9977724SAli.Saidi@ARM.com} 9987646Sgene.wu@arm.com 9997646Sgene.wu@arm.comtemplate <class Impl> 10007646Sgene.wu@arm.cominline void 10017119Sgblack@eecs.umich.eduLSQUnit<Impl>::incrLdIdx(int &load_idx) 10027119Sgblack@eecs.umich.edu{ 10037119Sgblack@eecs.umich.edu if (++load_idx >= LQEntries) 10047303Sgblack@eecs.umich.edu load_idx = 0; 100510184SCurtis.Dunham@arm.com} 10067303Sgblack@eecs.umich.edu 10077303Sgblack@eecs.umich.edutemplate <class Impl> 10087303Sgblack@eecs.umich.eduinline void 10097303Sgblack@eecs.umich.eduLSQUnit<Impl>::decrLdIdx(int &load_idx) 10107303Sgblack@eecs.umich.edu{ 10117303Sgblack@eecs.umich.edu if (--load_idx < 0) 10127303Sgblack@eecs.umich.edu load_idx += LQEntries; 10137848SAli.Saidi@ARM.com} 10147848SAli.Saidi@ARM.com 10157848SAli.Saidi@ARM.comtemplate <class Impl> 10167848SAli.Saidi@ARM.comvoid 10177848SAli.Saidi@ARM.comLSQUnit<Impl>::dumpInsts() 10187646Sgene.wu@arm.com{ 10197646Sgene.wu@arm.com cprintf("Load store queue: Dumping instructions.\n"); 10207646Sgene.wu@arm.com cprintf("Load queue size: %i\n", loads); 10217646Sgene.wu@arm.com cprintf("Load queue: "); 10227646Sgene.wu@arm.com 10237724SAli.Saidi@ARM.com int load_idx = loadHead; 10247646Sgene.wu@arm.com 10257646Sgene.wu@arm.com while (load_idx != loadTail && loadQueue[load_idx]) { 10267646Sgene.wu@arm.com cprintf("%#x ", loadQueue[load_idx]->readPC()); 10277303Sgblack@eecs.umich.edu 10287303Sgblack@eecs.umich.edu incrLdIdx(load_idx); 10297303Sgblack@eecs.umich.edu } 10307646Sgene.wu@arm.com 103110184SCurtis.Dunham@arm.com cprintf("Store queue size: %i\n", stores); 10327279Sgblack@eecs.umich.edu cprintf("Store queue: "); 10337279Sgblack@eecs.umich.edu 10347279Sgblack@eecs.umich.edu int store_idx = storeHead; 10357279Sgblack@eecs.umich.edu 10367279Sgblack@eecs.umich.edu while (store_idx != storeTail && storeQueue[store_idx].inst) { 10377279Sgblack@eecs.umich.edu cprintf("%#x ", storeQueue[store_idx].inst->readPC()); 10387279Sgblack@eecs.umich.edu 10397279Sgblack@eecs.umich.edu incrStIdx(store_idx); 10407279Sgblack@eecs.umich.edu } 10417848SAli.Saidi@ARM.com 10427848SAli.Saidi@ARM.com cprintf("\n"); 10437848SAli.Saidi@ARM.com} 10447848SAli.Saidi@ARM.com