lsq_unit_impl.hh revision 2927
14276Sgblack@eecs.umich.edu/* 24276Sgblack@eecs.umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 34276Sgblack@eecs.umich.edu * All rights reserved. 44276Sgblack@eecs.umich.edu * 54276Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 64276Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 74276Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 84276Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 94276Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 104276Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 114276Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 124276Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 134276Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 144276Sgblack@eecs.umich.edu * this software without specific prior written permission. 154276Sgblack@eecs.umich.edu * 164276Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174276Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184276Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194276Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204276Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214276Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224276Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234276Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244276Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254276Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264276Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274276Sgblack@eecs.umich.edu * 284276Sgblack@eecs.umich.edu * Authors: Kevin Lim 294276Sgblack@eecs.umich.edu * Korey Sewell 304276Sgblack@eecs.umich.edu */ 314276Sgblack@eecs.umich.edu 324276Sgblack@eecs.umich.edu#include "config/use_checker.hh" 334276Sgblack@eecs.umich.edu 344276Sgblack@eecs.umich.edu#include "cpu/o3/lsq.hh" 354276Sgblack@eecs.umich.edu#include "cpu/o3/lsq_unit.hh" 364276Sgblack@eecs.umich.edu#include "base/str.hh" 374276Sgblack@eecs.umich.edu#include "mem/packet.hh" 384276Sgblack@eecs.umich.edu#include "mem/request.hh" 394276Sgblack@eecs.umich.edu 404276Sgblack@eecs.umich.edu#if USE_CHECKER 414276Sgblack@eecs.umich.edu#include "cpu/checker/cpu.hh" 424276Sgblack@eecs.umich.edu#endif 434276Sgblack@eecs.umich.edu 444276Sgblack@eecs.umich.edutemplate<class Impl> 454276Sgblack@eecs.umich.eduLSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 464276Sgblack@eecs.umich.edu LSQUnit *lsq_ptr) 474276Sgblack@eecs.umich.edu : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 484276Sgblack@eecs.umich.edu{ 494276Sgblack@eecs.umich.edu this->setFlags(Event::AutoDelete); 504276Sgblack@eecs.umich.edu} 514276Sgblack@eecs.umich.edu 524276Sgblack@eecs.umich.edutemplate<class Impl> 534276Sgblack@eecs.umich.eduvoid 544276Sgblack@eecs.umich.eduLSQUnit<Impl>::WritebackEvent::process() 554276Sgblack@eecs.umich.edu{ 564276Sgblack@eecs.umich.edu if (!lsqPtr->isSwitchedOut()) { 574276Sgblack@eecs.umich.edu lsqPtr->writeback(inst, pkt); 584276Sgblack@eecs.umich.edu } 594276Sgblack@eecs.umich.edu delete pkt; 604276Sgblack@eecs.umich.edu} 614276Sgblack@eecs.umich.edu 624276Sgblack@eecs.umich.edutemplate<class Impl> 634276Sgblack@eecs.umich.educonst char * 644519Sgblack@eecs.umich.eduLSQUnit<Impl>::WritebackEvent::description() 654519Sgblack@eecs.umich.edu{ 664276Sgblack@eecs.umich.edu return "Store writeback event"; 674276Sgblack@eecs.umich.edu} 684519Sgblack@eecs.umich.edu 694276Sgblack@eecs.umich.edutemplate<class Impl> 704276Sgblack@eecs.umich.eduvoid 714276Sgblack@eecs.umich.eduLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 724276Sgblack@eecs.umich.edu{ 734276Sgblack@eecs.umich.edu LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 744276Sgblack@eecs.umich.edu DynInstPtr inst = state->inst; 754276Sgblack@eecs.umich.edu DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum); 764276Sgblack@eecs.umich.edu DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum); 774276Sgblack@eecs.umich.edu 784276Sgblack@eecs.umich.edu //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 794276Sgblack@eecs.umich.edu 804276Sgblack@eecs.umich.edu if (isSwitchedOut() || inst->isSquashed()) { 814276Sgblack@eecs.umich.edu iewStage->decrWb(inst->seqNum); 824276Sgblack@eecs.umich.edu delete state; 834276Sgblack@eecs.umich.edu delete pkt; 844276Sgblack@eecs.umich.edu return; 854276Sgblack@eecs.umich.edu } else { 864276Sgblack@eecs.umich.edu if (!state->noWB) { 874276Sgblack@eecs.umich.edu writeback(inst, pkt); 884276Sgblack@eecs.umich.edu } 894276Sgblack@eecs.umich.edu 904276Sgblack@eecs.umich.edu if (inst->isStore()) { 914276Sgblack@eecs.umich.edu completeStore(state->idx); 924276Sgblack@eecs.umich.edu } 934276Sgblack@eecs.umich.edu } 944276Sgblack@eecs.umich.edu 954276Sgblack@eecs.umich.edu delete state; 964276Sgblack@eecs.umich.edu delete pkt; 974276Sgblack@eecs.umich.edu} 984276Sgblack@eecs.umich.edu 994276Sgblack@eecs.umich.edutemplate <class Impl> 1004276Sgblack@eecs.umich.eduLSQUnit<Impl>::LSQUnit() 1014276Sgblack@eecs.umich.edu : loads(0), stores(0), storesToWB(0), stalled(false), 1024276Sgblack@eecs.umich.edu isStoreBlocked(false), isLoadBlocked(false), 1034276Sgblack@eecs.umich.edu loadBlockedHandled(false) 1044276Sgblack@eecs.umich.edu{ 1054276Sgblack@eecs.umich.edu} 1064276Sgblack@eecs.umich.edu 1074276Sgblack@eecs.umich.edutemplate<class Impl> 1084276Sgblack@eecs.umich.eduvoid 1094276Sgblack@eecs.umich.eduLSQUnit<Impl>::init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries, 1104276Sgblack@eecs.umich.edu unsigned maxSQEntries, unsigned id) 1114276Sgblack@eecs.umich.edu{ 1124276Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 1134276Sgblack@eecs.umich.edu 1144276Sgblack@eecs.umich.edu switchedOut = false; 1154276Sgblack@eecs.umich.edu 1164276Sgblack@eecs.umich.edu lsq = lsq_ptr; 1174276Sgblack@eecs.umich.edu 1184276Sgblack@eecs.umich.edu lsqID = id; 1194276Sgblack@eecs.umich.edu 1204276Sgblack@eecs.umich.edu // Add 1 for the sentinel entry (they are circular queues). 1214276Sgblack@eecs.umich.edu LQEntries = maxLQEntries + 1; 1224276Sgblack@eecs.umich.edu SQEntries = maxSQEntries + 1; 1234276Sgblack@eecs.umich.edu 1244276Sgblack@eecs.umich.edu loadQueue.resize(LQEntries); 1254527Sgblack@eecs.umich.edu storeQueue.resize(SQEntries); 1264527Sgblack@eecs.umich.edu 1274276Sgblack@eecs.umich.edu loadHead = loadTail = 0; 1284276Sgblack@eecs.umich.edu 1294276Sgblack@eecs.umich.edu storeHead = storeWBIdx = storeTail = 0; 1304527Sgblack@eecs.umich.edu 1314527Sgblack@eecs.umich.edu usedPorts = 0; 1324527Sgblack@eecs.umich.edu cachePorts = params->cachePorts; 1334276Sgblack@eecs.umich.edu 1344276Sgblack@eecs.umich.edu memDepViolator = NULL; 1354276Sgblack@eecs.umich.edu 1364276Sgblack@eecs.umich.edu blockedLoadSeqNum = 0; 1374276Sgblack@eecs.umich.edu} 1384276Sgblack@eecs.umich.edu 1394276Sgblack@eecs.umich.edutemplate<class Impl> 1404276Sgblack@eecs.umich.eduvoid 1414276Sgblack@eecs.umich.eduLSQUnit<Impl>::setCPU(O3CPU *cpu_ptr) 1424276Sgblack@eecs.umich.edu{ 1434276Sgblack@eecs.umich.edu cpu = cpu_ptr; 1444276Sgblack@eecs.umich.edu 1454276Sgblack@eecs.umich.edu#if USE_CHECKER 1464276Sgblack@eecs.umich.edu if (cpu->checker) { 1474276Sgblack@eecs.umich.edu cpu->checker->setDcachePort(dcachePort); 1484276Sgblack@eecs.umich.edu } 1494276Sgblack@eecs.umich.edu#endif 1504276Sgblack@eecs.umich.edu} 1514276Sgblack@eecs.umich.edu 1524276Sgblack@eecs.umich.edutemplate<class Impl> 1534276Sgblack@eecs.umich.edustd::string 1544276Sgblack@eecs.umich.eduLSQUnit<Impl>::name() const 1554276Sgblack@eecs.umich.edu{ 1564276Sgblack@eecs.umich.edu if (Impl::MaxThreads == 1) { 1574276Sgblack@eecs.umich.edu return iewStage->name() + ".lsq"; 1584276Sgblack@eecs.umich.edu } else { 1594276Sgblack@eecs.umich.edu return iewStage->name() + ".lsq.thread." + to_string(lsqID); 1604276Sgblack@eecs.umich.edu } 1614276Sgblack@eecs.umich.edu} 1624276Sgblack@eecs.umich.edu 1634276Sgblack@eecs.umich.edutemplate<class Impl> 1644276Sgblack@eecs.umich.eduvoid 1654276Sgblack@eecs.umich.eduLSQUnit<Impl>::regStats() 1664276Sgblack@eecs.umich.edu{ 1674276Sgblack@eecs.umich.edu lsqForwLoads 1684276Sgblack@eecs.umich.edu .name(name() + ".forwLoads") 1694276Sgblack@eecs.umich.edu .desc("Number of loads that had data forwarded from stores"); 1704276Sgblack@eecs.umich.edu 1714276Sgblack@eecs.umich.edu invAddrLoads 1724276Sgblack@eecs.umich.edu .name(name() + ".invAddrLoads") 1734276Sgblack@eecs.umich.edu .desc("Number of loads ignored due to an invalid address"); 1744276Sgblack@eecs.umich.edu 1754276Sgblack@eecs.umich.edu lsqSquashedLoads 1764276Sgblack@eecs.umich.edu .name(name() + ".squashedLoads") 1774276Sgblack@eecs.umich.edu .desc("Number of loads squashed"); 1784276Sgblack@eecs.umich.edu 1794276Sgblack@eecs.umich.edu lsqIgnoredResponses 1804276Sgblack@eecs.umich.edu .name(name() + ".ignoredResponses") 1814276Sgblack@eecs.umich.edu .desc("Number of memory responses ignored because the instruction is squashed"); 1824562Sgblack@eecs.umich.edu 1834276Sgblack@eecs.umich.edu lsqSquashedStores 1844276Sgblack@eecs.umich.edu .name(name() + ".squashedStores") 1854276Sgblack@eecs.umich.edu .desc("Number of stores squashed"); 1864276Sgblack@eecs.umich.edu 1874276Sgblack@eecs.umich.edu invAddrSwpfs 1884276Sgblack@eecs.umich.edu .name(name() + ".invAddrSwpfs") 1894276Sgblack@eecs.umich.edu .desc("Number of software prefetches ignored due to an invalid address"); 1904276Sgblack@eecs.umich.edu 1914276Sgblack@eecs.umich.edu lsqBlockedLoads 1924276Sgblack@eecs.umich.edu .name(name() + ".blockedLoads") 1934276Sgblack@eecs.umich.edu .desc("Number of blocked loads due to partial load-store forwarding"); 1944276Sgblack@eecs.umich.edu 1954276Sgblack@eecs.umich.edu lsqRescheduledLoads 1964276Sgblack@eecs.umich.edu .name(name() + ".rescheduledLoads") 1974276Sgblack@eecs.umich.edu .desc("Number of loads that were rescheduled"); 1984276Sgblack@eecs.umich.edu 1994276Sgblack@eecs.umich.edu lsqCacheBlocked 2004276Sgblack@eecs.umich.edu .name(name() + ".cacheBlocked") 2014276Sgblack@eecs.umich.edu .desc("Number of times an access to memory failed due to the cache being blocked"); 2024276Sgblack@eecs.umich.edu} 2034276Sgblack@eecs.umich.edu 2044276Sgblack@eecs.umich.edutemplate<class Impl> 2054276Sgblack@eecs.umich.eduvoid 2064276Sgblack@eecs.umich.eduLSQUnit<Impl>::clearLQ() 2074276Sgblack@eecs.umich.edu{ 2084276Sgblack@eecs.umich.edu loadQueue.clear(); 2094276Sgblack@eecs.umich.edu} 2104276Sgblack@eecs.umich.edu 2114276Sgblack@eecs.umich.edutemplate<class Impl> 2124276Sgblack@eecs.umich.eduvoid 2134276Sgblack@eecs.umich.eduLSQUnit<Impl>::clearSQ() 2144276Sgblack@eecs.umich.edu{ 2154276Sgblack@eecs.umich.edu storeQueue.clear(); 2164276Sgblack@eecs.umich.edu} 2174276Sgblack@eecs.umich.edu 2184276Sgblack@eecs.umich.edutemplate<class Impl> 2194276Sgblack@eecs.umich.eduvoid 2204276Sgblack@eecs.umich.eduLSQUnit<Impl>::switchOut() 2214276Sgblack@eecs.umich.edu{ 2224276Sgblack@eecs.umich.edu switchedOut = true; 2234276Sgblack@eecs.umich.edu for (int i = 0; i < loadQueue.size(); ++i) 2244276Sgblack@eecs.umich.edu loadQueue[i] = NULL; 2254276Sgblack@eecs.umich.edu 2264276Sgblack@eecs.umich.edu assert(storesToWB == 0); 2274276Sgblack@eecs.umich.edu} 2284276Sgblack@eecs.umich.edu 2294276Sgblack@eecs.umich.edutemplate<class Impl> 2304276Sgblack@eecs.umich.eduvoid 2314276Sgblack@eecs.umich.eduLSQUnit<Impl>::takeOverFrom() 2324276Sgblack@eecs.umich.edu{ 2334276Sgblack@eecs.umich.edu switchedOut = false; 2344276Sgblack@eecs.umich.edu loads = stores = storesToWB = 0; 2354276Sgblack@eecs.umich.edu 2364276Sgblack@eecs.umich.edu loadHead = loadTail = 0; 2374276Sgblack@eecs.umich.edu 2384276Sgblack@eecs.umich.edu storeHead = storeWBIdx = storeTail = 0; 2394276Sgblack@eecs.umich.edu 2404545Sgblack@eecs.umich.edu usedPorts = 0; 2414545Sgblack@eecs.umich.edu 2424545Sgblack@eecs.umich.edu memDepViolator = NULL; 2434545Sgblack@eecs.umich.edu 2444482Sgblack@eecs.umich.edu blockedLoadSeqNum = 0; 2454276Sgblack@eecs.umich.edu 2464276Sgblack@eecs.umich.edu stalled = false; 2474276Sgblack@eecs.umich.edu isLoadBlocked = false; 2484276Sgblack@eecs.umich.edu loadBlockedHandled = false; 2494276Sgblack@eecs.umich.edu} 2504276Sgblack@eecs.umich.edu 2514276Sgblack@eecs.umich.edutemplate<class Impl> 2524276Sgblack@eecs.umich.eduvoid 2534276Sgblack@eecs.umich.eduLSQUnit<Impl>::resizeLQ(unsigned size) 2544276Sgblack@eecs.umich.edu{ 2554276Sgblack@eecs.umich.edu unsigned size_plus_sentinel = size + 1; 2564276Sgblack@eecs.umich.edu assert(size_plus_sentinel >= LQEntries); 2574276Sgblack@eecs.umich.edu 2584276Sgblack@eecs.umich.edu if (size_plus_sentinel > LQEntries) { 2594276Sgblack@eecs.umich.edu while (size_plus_sentinel > loadQueue.size()) { 2604276Sgblack@eecs.umich.edu DynInstPtr dummy; 2614276Sgblack@eecs.umich.edu loadQueue.push_back(dummy); 2624276Sgblack@eecs.umich.edu LQEntries++; 2634276Sgblack@eecs.umich.edu } 2644276Sgblack@eecs.umich.edu } else { 2654276Sgblack@eecs.umich.edu LQEntries = size_plus_sentinel; 2664276Sgblack@eecs.umich.edu } 2674276Sgblack@eecs.umich.edu 2684276Sgblack@eecs.umich.edu} 2694276Sgblack@eecs.umich.edu 2704276Sgblack@eecs.umich.edutemplate<class Impl> 2714276Sgblack@eecs.umich.eduvoid 2724276Sgblack@eecs.umich.eduLSQUnit<Impl>::resizeSQ(unsigned size) 2734276Sgblack@eecs.umich.edu{ 2744276Sgblack@eecs.umich.edu unsigned size_plus_sentinel = size + 1; 2754276Sgblack@eecs.umich.edu if (size_plus_sentinel > SQEntries) { 2764276Sgblack@eecs.umich.edu while (size_plus_sentinel > storeQueue.size()) { 2774276Sgblack@eecs.umich.edu SQEntry dummy; 2784276Sgblack@eecs.umich.edu storeQueue.push_back(dummy); 2794276Sgblack@eecs.umich.edu SQEntries++; 2804276Sgblack@eecs.umich.edu } 2814276Sgblack@eecs.umich.edu } else { 2824276Sgblack@eecs.umich.edu SQEntries = size_plus_sentinel; 2834276Sgblack@eecs.umich.edu } 2844276Sgblack@eecs.umich.edu} 2854276Sgblack@eecs.umich.edu 2864276Sgblack@eecs.umich.edutemplate <class Impl> 2874276Sgblack@eecs.umich.eduvoid 2884276Sgblack@eecs.umich.eduLSQUnit<Impl>::insert(DynInstPtr &inst) 2894276Sgblack@eecs.umich.edu{ 2904276Sgblack@eecs.umich.edu assert(inst->isMemRef()); 2914276Sgblack@eecs.umich.edu 2924276Sgblack@eecs.umich.edu assert(inst->isLoad() || inst->isStore()); 2934276Sgblack@eecs.umich.edu 2944276Sgblack@eecs.umich.edu if (inst->isLoad()) { 2954276Sgblack@eecs.umich.edu insertLoad(inst); 2964276Sgblack@eecs.umich.edu } else { 2974276Sgblack@eecs.umich.edu insertStore(inst); 2984276Sgblack@eecs.umich.edu } 2994276Sgblack@eecs.umich.edu 3004276Sgblack@eecs.umich.edu inst->setInLSQ(); 3014276Sgblack@eecs.umich.edu} 3024276Sgblack@eecs.umich.edu 3034276Sgblack@eecs.umich.edutemplate <class Impl> 3044276Sgblack@eecs.umich.eduvoid 3054276Sgblack@eecs.umich.eduLSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 3064276Sgblack@eecs.umich.edu{ 3074276Sgblack@eecs.umich.edu assert((loadTail + 1) % LQEntries != loadHead); 3084276Sgblack@eecs.umich.edu assert(loads < LQEntries); 3094276Sgblack@eecs.umich.edu 3104276Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n", 3114276Sgblack@eecs.umich.edu load_inst->readPC(), loadTail, load_inst->seqNum); 3124276Sgblack@eecs.umich.edu 3134276Sgblack@eecs.umich.edu load_inst->lqIdx = loadTail; 3144276Sgblack@eecs.umich.edu 3154276Sgblack@eecs.umich.edu if (stores == 0) { 3164276Sgblack@eecs.umich.edu load_inst->sqIdx = -1; 3174276Sgblack@eecs.umich.edu } else { 3184276Sgblack@eecs.umich.edu load_inst->sqIdx = storeTail; 3194276Sgblack@eecs.umich.edu } 3204276Sgblack@eecs.umich.edu 3214276Sgblack@eecs.umich.edu loadQueue[loadTail] = load_inst; 3224276Sgblack@eecs.umich.edu 3234276Sgblack@eecs.umich.edu incrLdIdx(loadTail); 3244276Sgblack@eecs.umich.edu 3254276Sgblack@eecs.umich.edu ++loads; 3264276Sgblack@eecs.umich.edu} 3274276Sgblack@eecs.umich.edu 3284276Sgblack@eecs.umich.edutemplate <class Impl> 3294276Sgblack@eecs.umich.eduvoid 3304276Sgblack@eecs.umich.eduLSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 3314276Sgblack@eecs.umich.edu{ 3324276Sgblack@eecs.umich.edu // Make sure it is not full before inserting an instruction. 3334276Sgblack@eecs.umich.edu assert((storeTail + 1) % SQEntries != storeHead); 3344276Sgblack@eecs.umich.edu assert(stores < SQEntries); 3354276Sgblack@eecs.umich.edu 3364276Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n", 3374276Sgblack@eecs.umich.edu store_inst->readPC(), storeTail, store_inst->seqNum); 3384276Sgblack@eecs.umich.edu 3394276Sgblack@eecs.umich.edu store_inst->sqIdx = storeTail; 3404276Sgblack@eecs.umich.edu store_inst->lqIdx = loadTail; 3414276Sgblack@eecs.umich.edu 3424276Sgblack@eecs.umich.edu storeQueue[storeTail] = SQEntry(store_inst); 3434276Sgblack@eecs.umich.edu 3444276Sgblack@eecs.umich.edu incrStIdx(storeTail); 3454276Sgblack@eecs.umich.edu 3464276Sgblack@eecs.umich.edu ++stores; 3474276Sgblack@eecs.umich.edu} 3484276Sgblack@eecs.umich.edu 3494276Sgblack@eecs.umich.edutemplate <class Impl> 3504276Sgblack@eecs.umich.edutypename Impl::DynInstPtr 3514276Sgblack@eecs.umich.eduLSQUnit<Impl>::getMemDepViolator() 3524276Sgblack@eecs.umich.edu{ 3534276Sgblack@eecs.umich.edu DynInstPtr temp = memDepViolator; 3544276Sgblack@eecs.umich.edu 3554276Sgblack@eecs.umich.edu memDepViolator = NULL; 3564276Sgblack@eecs.umich.edu 3574276Sgblack@eecs.umich.edu return temp; 3584276Sgblack@eecs.umich.edu} 3594276Sgblack@eecs.umich.edu 3604276Sgblack@eecs.umich.edutemplate <class Impl> 3614276Sgblack@eecs.umich.eduunsigned 3624276Sgblack@eecs.umich.eduLSQUnit<Impl>::numFreeEntries() 3634276Sgblack@eecs.umich.edu{ 3644276Sgblack@eecs.umich.edu unsigned free_lq_entries = LQEntries - loads; 3654276Sgblack@eecs.umich.edu unsigned free_sq_entries = SQEntries - stores; 3664276Sgblack@eecs.umich.edu 3674276Sgblack@eecs.umich.edu // Both the LQ and SQ entries have an extra dummy entry to differentiate 3684276Sgblack@eecs.umich.edu // empty/full conditions. Subtract 1 from the free entries. 3694276Sgblack@eecs.umich.edu if (free_lq_entries < free_sq_entries) { 3704276Sgblack@eecs.umich.edu return free_lq_entries - 1; 3714276Sgblack@eecs.umich.edu } else { 3724276Sgblack@eecs.umich.edu return free_sq_entries - 1; 3734276Sgblack@eecs.umich.edu } 3744276Sgblack@eecs.umich.edu} 3754276Sgblack@eecs.umich.edu 3764276Sgblack@eecs.umich.edutemplate <class Impl> 3774276Sgblack@eecs.umich.eduint 3784276Sgblack@eecs.umich.eduLSQUnit<Impl>::numLoadsReady() 3794276Sgblack@eecs.umich.edu{ 3804276Sgblack@eecs.umich.edu int load_idx = loadHead; 3814276Sgblack@eecs.umich.edu int retval = 0; 3824276Sgblack@eecs.umich.edu 3834276Sgblack@eecs.umich.edu while (load_idx != loadTail) { 3844276Sgblack@eecs.umich.edu assert(loadQueue[load_idx]); 3854276Sgblack@eecs.umich.edu 3864276Sgblack@eecs.umich.edu if (loadQueue[load_idx]->readyToIssue()) { 3874276Sgblack@eecs.umich.edu ++retval; 3884276Sgblack@eecs.umich.edu } 3894276Sgblack@eecs.umich.edu } 3904276Sgblack@eecs.umich.edu 3914276Sgblack@eecs.umich.edu return retval; 3924276Sgblack@eecs.umich.edu} 3934276Sgblack@eecs.umich.edu 3944276Sgblack@eecs.umich.edutemplate <class Impl> 395Fault 396LSQUnit<Impl>::executeLoad(DynInstPtr &inst) 397{ 398 // Execute a specific load. 399 Fault load_fault = NoFault; 400 401 DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n", 402 inst->readPC(),inst->seqNum); 403 404 load_fault = inst->initiateAcc(); 405 406 // If the instruction faulted, then we need to send it along to commit 407 // without the instruction completing. 408 if (load_fault != NoFault) { 409 // Send this instruction to commit, also make sure iew stage 410 // realizes there is activity. 411 iewStage->instToCommit(inst); 412 iewStage->activityThisCycle(); 413 } 414 415 return load_fault; 416} 417 418template <class Impl> 419Fault 420LSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 421{ 422 using namespace TheISA; 423 // Make sure that a store exists. 424 assert(stores != 0); 425 426 int store_idx = store_inst->sqIdx; 427 428 DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n", 429 store_inst->readPC(), store_inst->seqNum); 430 431 // Check the recently completed loads to see if any match this store's 432 // address. If so, then we have a memory ordering violation. 433 int load_idx = store_inst->lqIdx; 434 435 Fault store_fault = store_inst->initiateAcc(); 436 437 if (storeQueue[store_idx].size == 0) { 438 DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n", 439 store_inst->readPC(),store_inst->seqNum); 440 441 return store_fault; 442 } 443 444 assert(store_fault == NoFault); 445 446 if (store_inst->isStoreConditional()) { 447 // Store conditionals need to set themselves as able to 448 // writeback if we haven't had a fault by here. 449 storeQueue[store_idx].canWB = true; 450 451 ++storesToWB; 452 } 453 454 if (!memDepViolator) { 455 while (load_idx != loadTail) { 456 // Really only need to check loads that have actually executed 457 // It's safe to check all loads because effAddr is set to 458 // InvalAddr when the dyn inst is created. 459 460 // @todo: For now this is extra conservative, detecting a 461 // violation if the addresses match assuming all accesses 462 // are quad word accesses. 463 464 // @todo: Fix this, magic number being used here 465 if ((loadQueue[load_idx]->effAddr >> 8) == 466 (store_inst->effAddr >> 8)) { 467 // A load incorrectly passed this store. Squash and refetch. 468 // For now return a fault to show that it was unsuccessful. 469 memDepViolator = loadQueue[load_idx]; 470 471 return genMachineCheckFault(); 472 } 473 474 incrLdIdx(load_idx); 475 } 476 477 // If we've reached this point, there was no violation. 478 memDepViolator = NULL; 479 } 480 481 return store_fault; 482} 483 484template <class Impl> 485void 486LSQUnit<Impl>::commitLoad() 487{ 488 assert(loadQueue[loadHead]); 489 490 DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n", 491 loadQueue[loadHead]->readPC()); 492 493 loadQueue[loadHead] = NULL; 494 495 incrLdIdx(loadHead); 496 497 --loads; 498} 499 500template <class Impl> 501void 502LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 503{ 504 assert(loads == 0 || loadQueue[loadHead]); 505 506 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 507 commitLoad(); 508 } 509} 510 511template <class Impl> 512void 513LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 514{ 515 assert(stores == 0 || storeQueue[storeHead].inst); 516 517 int store_idx = storeHead; 518 519 while (store_idx != storeTail) { 520 assert(storeQueue[store_idx].inst); 521 // Mark any stores that are now committed and have not yet 522 // been marked as able to write back. 523 if (!storeQueue[store_idx].canWB) { 524 if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 525 break; 526 } 527 DPRINTF(LSQUnit, "Marking store as able to write back, PC " 528 "%#x [sn:%lli]\n", 529 storeQueue[store_idx].inst->readPC(), 530 storeQueue[store_idx].inst->seqNum); 531 532 storeQueue[store_idx].canWB = true; 533 534 ++storesToWB; 535 } 536 537 incrStIdx(store_idx); 538 } 539} 540 541template <class Impl> 542void 543LSQUnit<Impl>::writebackStores() 544{ 545 while (storesToWB > 0 && 546 storeWBIdx != storeTail && 547 storeQueue[storeWBIdx].inst && 548 storeQueue[storeWBIdx].canWB && 549 usedPorts < cachePorts) { 550 551 if (isStoreBlocked || lsq->cacheBlocked()) { 552 DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 553 " is blocked!\n"); 554 break; 555 } 556 557 // Store didn't write any data so no need to write it back to 558 // memory. 559 if (storeQueue[storeWBIdx].size == 0) { 560 completeStore(storeWBIdx); 561 562 incrStIdx(storeWBIdx); 563 564 continue; 565 } 566 567 ++usedPorts; 568 569 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 570 incrStIdx(storeWBIdx); 571 572 continue; 573 } 574 575 assert(storeQueue[storeWBIdx].req); 576 assert(!storeQueue[storeWBIdx].committed); 577 578 DynInstPtr inst = storeQueue[storeWBIdx].inst; 579 580 Request *req = storeQueue[storeWBIdx].req; 581 storeQueue[storeWBIdx].committed = true; 582 583 assert(!inst->memData); 584 inst->memData = new uint8_t[64]; 585 memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data, 586 req->getSize()); 587 588 PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast); 589 data_pkt->dataStatic(inst->memData); 590 591 LSQSenderState *state = new LSQSenderState; 592 state->isLoad = false; 593 state->idx = storeWBIdx; 594 state->inst = inst; 595 data_pkt->senderState = state; 596 597 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x " 598 "to Addr:%#x, data:%#x [sn:%lli]\n", 599 storeWBIdx, storeQueue[storeWBIdx].inst->readPC(), 600 req->getPaddr(), *(inst->memData), 601 storeQueue[storeWBIdx].inst->seqNum); 602 603 // @todo: Remove this SC hack once the memory system handles it. 604 if (req->getFlags() & LOCKED) { 605 if (req->getFlags() & UNCACHEABLE) { 606 req->setScResult(2); 607 } else { 608 if (cpu->lockFlag) { 609 req->setScResult(1); 610 } else { 611 req->setScResult(0); 612 // Hack: Instantly complete this store. 613 completeDataAccess(data_pkt); 614 incrStIdx(storeWBIdx); 615 continue; 616 } 617 } 618 } else { 619 // Non-store conditionals do not need a writeback. 620 state->noWB = true; 621 } 622 623 if (!dcachePort->sendTiming(data_pkt)) { 624 // Need to handle becoming blocked on a store. 625 isStoreBlocked = true; 626 ++lsqCacheBlocked; 627 assert(retryPkt == NULL); 628 retryPkt = data_pkt; 629 } else { 630 storePostSend(data_pkt); 631 } 632 } 633 634 // Not sure this should set it to 0. 635 usedPorts = 0; 636 637 assert(stores >= 0 && storesToWB >= 0); 638} 639 640/*template <class Impl> 641void 642LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 643{ 644 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 645 mshrSeqNums.end(), 646 seqNum); 647 648 if (mshr_it != mshrSeqNums.end()) { 649 mshrSeqNums.erase(mshr_it); 650 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 651 } 652}*/ 653 654template <class Impl> 655void 656LSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 657{ 658 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 659 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 660 661 int load_idx = loadTail; 662 decrLdIdx(load_idx); 663 664 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 665 DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, " 666 "[sn:%lli]\n", 667 loadQueue[load_idx]->readPC(), 668 loadQueue[load_idx]->seqNum); 669 670 if (isStalled() && load_idx == stallingLoadIdx) { 671 stalled = false; 672 stallingStoreIsn = 0; 673 stallingLoadIdx = 0; 674 } 675 676 // Clear the smart pointer to make sure it is decremented. 677 loadQueue[load_idx]->setSquashed(); 678 loadQueue[load_idx] = NULL; 679 --loads; 680 681 // Inefficient! 682 loadTail = load_idx; 683 684 decrLdIdx(load_idx); 685 ++lsqSquashedLoads; 686 } 687 688 if (isLoadBlocked) { 689 if (squashed_num < blockedLoadSeqNum) { 690 isLoadBlocked = false; 691 loadBlockedHandled = false; 692 blockedLoadSeqNum = 0; 693 } 694 } 695 696 int store_idx = storeTail; 697 decrStIdx(store_idx); 698 699 while (stores != 0 && 700 storeQueue[store_idx].inst->seqNum > squashed_num) { 701 // Instructions marked as can WB are already committed. 702 if (storeQueue[store_idx].canWB) { 703 break; 704 } 705 706 DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, " 707 "idx:%i [sn:%lli]\n", 708 storeQueue[store_idx].inst->readPC(), 709 store_idx, storeQueue[store_idx].inst->seqNum); 710 711 // I don't think this can happen. It should have been cleared 712 // by the stalling load. 713 if (isStalled() && 714 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 715 panic("Is stalled should have been cleared by stalling load!\n"); 716 stalled = false; 717 stallingStoreIsn = 0; 718 } 719 720 // Clear the smart pointer to make sure it is decremented. 721 storeQueue[store_idx].inst->setSquashed(); 722 storeQueue[store_idx].inst = NULL; 723 storeQueue[store_idx].canWB = 0; 724 725 storeQueue[store_idx].req = NULL; 726 --stores; 727 728 // Inefficient! 729 storeTail = store_idx; 730 731 decrStIdx(store_idx); 732 ++lsqSquashedStores; 733 } 734} 735 736template <class Impl> 737void 738LSQUnit<Impl>::storePostSend(Packet *pkt) 739{ 740 if (isStalled() && 741 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 742 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 743 "load idx:%i\n", 744 stallingStoreIsn, stallingLoadIdx); 745 stalled = false; 746 stallingStoreIsn = 0; 747 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 748 } 749 750 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 751 // The store is basically completed at this time. This 752 // only works so long as the checker doesn't try to 753 // verify the value in memory for stores. 754 storeQueue[storeWBIdx].inst->setCompleted(); 755#if USE_CHECKER 756 if (cpu->checker) { 757 cpu->checker->verify(storeQueue[storeWBIdx].inst); 758 } 759#endif 760 } 761 762 if (pkt->result != Packet::Success) { 763 DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n", 764 storeWBIdx); 765 766 DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n", 767 storeQueue[storeWBIdx].inst->seqNum); 768 769 //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum); 770 771 //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size()); 772 773 // @todo: Increment stat here. 774 } else { 775 DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n", 776 storeWBIdx); 777 778 DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n", 779 storeQueue[storeWBIdx].inst->seqNum); 780 } 781 782 incrStIdx(storeWBIdx); 783} 784 785template <class Impl> 786void 787LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 788{ 789 iewStage->wakeCPU(); 790 791 // Squashed instructions do not need to complete their access. 792 if (inst->isSquashed()) { 793 iewStage->decrWb(inst->seqNum); 794 assert(!inst->isStore()); 795 ++lsqIgnoredResponses; 796 return; 797 } 798 799 if (!inst->isExecuted()) { 800 inst->setExecuted(); 801 802 // Complete access to copy data to proper place. 803 inst->completeAcc(pkt); 804 } 805 806 // Need to insert instruction into queue to commit 807 iewStage->instToCommit(inst); 808 809 iewStage->activityThisCycle(); 810} 811 812template <class Impl> 813void 814LSQUnit<Impl>::completeStore(int store_idx) 815{ 816 assert(storeQueue[store_idx].inst); 817 storeQueue[store_idx].completed = true; 818 --storesToWB; 819 // A bit conservative because a store completion may not free up entries, 820 // but hopefully avoids two store completions in one cycle from making 821 // the CPU tick twice. 822 cpu->activityThisCycle(); 823 824 if (store_idx == storeHead) { 825 do { 826 incrStIdx(storeHead); 827 828 --stores; 829 } while (storeQueue[storeHead].completed && 830 storeHead != storeTail); 831 832 iewStage->updateLSQNextCycle = true; 833 } 834 835 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 836 "idx:%i\n", 837 storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 838 839 if (isStalled() && 840 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 841 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 842 "load idx:%i\n", 843 stallingStoreIsn, stallingLoadIdx); 844 stalled = false; 845 stallingStoreIsn = 0; 846 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 847 } 848 849 storeQueue[store_idx].inst->setCompleted(); 850 851 // Tell the checker we've completed this instruction. Some stores 852 // may get reported twice to the checker, but the checker can 853 // handle that case. 854#if USE_CHECKER 855 if (cpu->checker) { 856 cpu->checker->verify(storeQueue[store_idx].inst); 857 } 858#endif 859} 860 861template <class Impl> 862void 863LSQUnit<Impl>::recvRetry() 864{ 865 if (isStoreBlocked) { 866 assert(retryPkt != NULL); 867 868 if (dcachePort->sendTiming(retryPkt)) { 869 storePostSend(retryPkt); 870 retryPkt = NULL; 871 isStoreBlocked = false; 872 } else { 873 // Still blocked! 874 ++lsqCacheBlocked; 875 lsq->setRetryTid(lsqID); 876 } 877 } else if (isLoadBlocked) { 878 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 879 "no need to resend packet.\n"); 880 } else { 881 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 882 } 883} 884 885template <class Impl> 886inline void 887LSQUnit<Impl>::incrStIdx(int &store_idx) 888{ 889 if (++store_idx >= SQEntries) 890 store_idx = 0; 891} 892 893template <class Impl> 894inline void 895LSQUnit<Impl>::decrStIdx(int &store_idx) 896{ 897 if (--store_idx < 0) 898 store_idx += SQEntries; 899} 900 901template <class Impl> 902inline void 903LSQUnit<Impl>::incrLdIdx(int &load_idx) 904{ 905 if (++load_idx >= LQEntries) 906 load_idx = 0; 907} 908 909template <class Impl> 910inline void 911LSQUnit<Impl>::decrLdIdx(int &load_idx) 912{ 913 if (--load_idx < 0) 914 load_idx += LQEntries; 915} 916 917template <class Impl> 918void 919LSQUnit<Impl>::dumpInsts() 920{ 921 cprintf("Load store queue: Dumping instructions.\n"); 922 cprintf("Load queue size: %i\n", loads); 923 cprintf("Load queue: "); 924 925 int load_idx = loadHead; 926 927 while (load_idx != loadTail && loadQueue[load_idx]) { 928 cprintf("%#x ", loadQueue[load_idx]->readPC()); 929 930 incrLdIdx(load_idx); 931 } 932 933 cprintf("Store queue size: %i\n", stores); 934 cprintf("Store queue: "); 935 936 int store_idx = storeHead; 937 938 while (store_idx != storeTail && storeQueue[store_idx].inst) { 939 cprintf("%#x ", storeQueue[store_idx].inst->readPC()); 940 941 incrStIdx(store_idx); 942 } 943 944 cprintf("\n"); 945} 946