lsq_unit_impl.hh revision 2689
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#include "cpu/checker/cpu.hh" 33#include "cpu/o3/lsq_unit.hh" 34#include "base/str.hh" 35#include "mem/request.hh" 36 37template<class Impl> 38LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 39 LSQUnit *lsq_ptr) 40 : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 41{ 42 this->setFlags(Event::AutoDelete); 43} 44 45template<class Impl> 46void 47LSQUnit<Impl>::WritebackEvent::process() 48{ 49 if (!lsqPtr->isSwitchedOut()) { 50 lsqPtr->writeback(inst, pkt); 51 } 52 delete pkt; 53} 54 55template<class Impl> 56const char * 57LSQUnit<Impl>::WritebackEvent::description() 58{ 59 return "Store writeback event"; 60} 61 62template<class Impl> 63void 64LSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 65{ 66 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 67 DynInstPtr inst = state->inst; 68 DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum); 69// DPRINTF(Activity, "Activity: Ld Writeback event [sn:%lli]\n", inst->seqNum); 70 71 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 72 73 if (isSwitchedOut() || inst->isSquashed()) { 74 delete state; 75 delete pkt; 76 return; 77 } else { 78 if (!state->noWB) { 79 writeback(inst, pkt); 80 } 81 82 if (inst->isStore()) { 83 completeStore(state->idx); 84 } 85 } 86 87 delete state; 88 delete pkt; 89} 90 91template <class Impl> 92Tick 93LSQUnit<Impl>::DcachePort::recvAtomic(PacketPtr pkt) 94{ 95 panic("O3CPU model does not work with atomic mode!"); 96 return curTick; 97} 98 99template <class Impl> 100void 101LSQUnit<Impl>::DcachePort::recvFunctional(PacketPtr pkt) 102{ 103 panic("O3CPU doesn't expect recvFunctional callback!"); 104} 105 106template <class Impl> 107void 108LSQUnit<Impl>::DcachePort::recvStatusChange(Status status) 109{ 110 if (status == RangeChange) 111 return; 112 113 panic("O3CPU doesn't expect recvStatusChange callback!"); 114} 115 116template <class Impl> 117bool 118LSQUnit<Impl>::DcachePort::recvTiming(PacketPtr pkt) 119{ 120 lsq->completeDataAccess(pkt); 121 return true; 122} 123 124template <class Impl> 125void 126LSQUnit<Impl>::DcachePort::recvRetry() 127{ 128 panic("Retry unsupported for now!"); 129 // we shouldn't get a retry unless we have a packet that we're 130 // waiting to transmit 131/* 132 assert(cpu->dcache_pkt != NULL); 133 assert(cpu->_status == DcacheRetry); 134 PacketPtr tmp = cpu->dcache_pkt; 135 if (sendTiming(tmp)) { 136 cpu->_status = DcacheWaitResponse; 137 cpu->dcache_pkt = NULL; 138 } 139*/ 140} 141 142template <class Impl> 143LSQUnit<Impl>::LSQUnit() 144 : loads(0), stores(0), storesToWB(0), stalled(false), 145 isStoreBlocked(false), isLoadBlocked(false), 146 loadBlockedHandled(false) 147{ 148} 149 150template<class Impl> 151void 152LSQUnit<Impl>::init(Params *params, unsigned maxLQEntries, 153 unsigned maxSQEntries, unsigned id) 154{ 155 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 156 157 switchedOut = false; 158 159 lsqID = id; 160 161 // Add 1 for the sentinel entry (they are circular queues). 162 LQEntries = maxLQEntries + 1; 163 SQEntries = maxSQEntries + 1; 164 165 loadQueue.resize(LQEntries); 166 storeQueue.resize(SQEntries); 167 168 loadHead = loadTail = 0; 169 170 storeHead = storeWBIdx = storeTail = 0; 171 172 usedPorts = 0; 173 cachePorts = params->cachePorts; 174 175 mem = params->mem; 176 177 memDepViolator = NULL; 178 179 blockedLoadSeqNum = 0; 180} 181 182template<class Impl> 183void 184LSQUnit<Impl>::setCPU(FullCPU *cpu_ptr) 185{ 186 cpu = cpu_ptr; 187 dcachePort = new DcachePort(cpu, this); 188 189 Port *mem_dport = mem->getPort(""); 190 dcachePort->setPeer(mem_dport); 191 mem_dport->setPeer(dcachePort); 192 193 if (cpu->checker) { 194 cpu->checker->setDcachePort(dcachePort); 195 } 196} 197 198template<class Impl> 199std::string 200LSQUnit<Impl>::name() const 201{ 202 if (Impl::MaxThreads == 1) { 203 return iewStage->name() + ".lsq"; 204 } else { 205 return iewStage->name() + ".lsq.thread." + to_string(lsqID); 206 } 207} 208 209template<class Impl> 210void 211LSQUnit<Impl>::clearLQ() 212{ 213 loadQueue.clear(); 214} 215 216template<class Impl> 217void 218LSQUnit<Impl>::clearSQ() 219{ 220 storeQueue.clear(); 221} 222 223#if 0 224template<class Impl> 225void 226LSQUnit<Impl>::setPageTable(PageTable *pt_ptr) 227{ 228 DPRINTF(LSQUnit, "Setting the page table pointer.\n"); 229 pTable = pt_ptr; 230} 231#endif 232 233template<class Impl> 234void 235LSQUnit<Impl>::switchOut() 236{ 237 switchedOut = true; 238 for (int i = 0; i < loadQueue.size(); ++i) 239 loadQueue[i] = NULL; 240 241 assert(storesToWB == 0); 242} 243 244template<class Impl> 245void 246LSQUnit<Impl>::takeOverFrom() 247{ 248 switchedOut = false; 249 loads = stores = storesToWB = 0; 250 251 loadHead = loadTail = 0; 252 253 storeHead = storeWBIdx = storeTail = 0; 254 255 usedPorts = 0; 256 257 memDepViolator = NULL; 258 259 blockedLoadSeqNum = 0; 260 261 stalled = false; 262 isLoadBlocked = false; 263 loadBlockedHandled = false; 264} 265 266template<class Impl> 267void 268LSQUnit<Impl>::resizeLQ(unsigned size) 269{ 270 unsigned size_plus_sentinel = size + 1; 271 assert(size_plus_sentinel >= LQEntries); 272 273 if (size_plus_sentinel > LQEntries) { 274 while (size_plus_sentinel > loadQueue.size()) { 275 DynInstPtr dummy; 276 loadQueue.push_back(dummy); 277 LQEntries++; 278 } 279 } else { 280 LQEntries = size_plus_sentinel; 281 } 282 283} 284 285template<class Impl> 286void 287LSQUnit<Impl>::resizeSQ(unsigned size) 288{ 289 unsigned size_plus_sentinel = size + 1; 290 if (size_plus_sentinel > SQEntries) { 291 while (size_plus_sentinel > storeQueue.size()) { 292 SQEntry dummy; 293 storeQueue.push_back(dummy); 294 SQEntries++; 295 } 296 } else { 297 SQEntries = size_plus_sentinel; 298 } 299} 300 301template <class Impl> 302void 303LSQUnit<Impl>::insert(DynInstPtr &inst) 304{ 305 assert(inst->isMemRef()); 306 307 assert(inst->isLoad() || inst->isStore()); 308 309 if (inst->isLoad()) { 310 insertLoad(inst); 311 } else { 312 insertStore(inst); 313 } 314 315 inst->setInLSQ(); 316} 317 318template <class Impl> 319void 320LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 321{ 322 assert((loadTail + 1) % LQEntries != loadHead); 323 assert(loads < LQEntries); 324 325 DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n", 326 load_inst->readPC(), loadTail, load_inst->seqNum); 327 328 load_inst->lqIdx = loadTail; 329 330 if (stores == 0) { 331 load_inst->sqIdx = -1; 332 } else { 333 load_inst->sqIdx = storeTail; 334 } 335 336 loadQueue[loadTail] = load_inst; 337 338 incrLdIdx(loadTail); 339 340 ++loads; 341} 342 343template <class Impl> 344void 345LSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 346{ 347 // Make sure it is not full before inserting an instruction. 348 assert((storeTail + 1) % SQEntries != storeHead); 349 assert(stores < SQEntries); 350 351 DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n", 352 store_inst->readPC(), storeTail, store_inst->seqNum); 353 354 store_inst->sqIdx = storeTail; 355 store_inst->lqIdx = loadTail; 356 357 storeQueue[storeTail] = SQEntry(store_inst); 358 359 incrStIdx(storeTail); 360 361 ++stores; 362} 363 364template <class Impl> 365typename Impl::DynInstPtr 366LSQUnit<Impl>::getMemDepViolator() 367{ 368 DynInstPtr temp = memDepViolator; 369 370 memDepViolator = NULL; 371 372 return temp; 373} 374 375template <class Impl> 376unsigned 377LSQUnit<Impl>::numFreeEntries() 378{ 379 unsigned free_lq_entries = LQEntries - loads; 380 unsigned free_sq_entries = SQEntries - stores; 381 382 // Both the LQ and SQ entries have an extra dummy entry to differentiate 383 // empty/full conditions. Subtract 1 from the free entries. 384 if (free_lq_entries < free_sq_entries) { 385 return free_lq_entries - 1; 386 } else { 387 return free_sq_entries - 1; 388 } 389} 390 391template <class Impl> 392int 393LSQUnit<Impl>::numLoadsReady() 394{ 395 int load_idx = loadHead; 396 int retval = 0; 397 398 while (load_idx != loadTail) { 399 assert(loadQueue[load_idx]); 400 401 if (loadQueue[load_idx]->readyToIssue()) { 402 ++retval; 403 } 404 } 405 406 return retval; 407} 408 409template <class Impl> 410Fault 411LSQUnit<Impl>::executeLoad(DynInstPtr &inst) 412{ 413 // Execute a specific load. 414 Fault load_fault = NoFault; 415 416 DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n", 417 inst->readPC(),inst->seqNum); 418 419 load_fault = inst->initiateAcc(); 420 421 // If the instruction faulted, then we need to send it along to commit 422 // without the instruction completing. 423 if (load_fault != NoFault) { 424 // Send this instruction to commit, also make sure iew stage 425 // realizes there is activity. 426 iewStage->instToCommit(inst); 427 iewStage->activityThisCycle(); 428 } 429 430 return load_fault; 431} 432 433template <class Impl> 434Fault 435LSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 436{ 437 using namespace TheISA; 438 // Make sure that a store exists. 439 assert(stores != 0); 440 441 int store_idx = store_inst->sqIdx; 442 443 DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n", 444 store_inst->readPC(), store_inst->seqNum); 445 446 // Check the recently completed loads to see if any match this store's 447 // address. If so, then we have a memory ordering violation. 448 int load_idx = store_inst->lqIdx; 449 450 Fault store_fault = store_inst->initiateAcc(); 451 452 if (storeQueue[store_idx].size == 0) { 453 DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n", 454 store_inst->readPC(),store_inst->seqNum); 455 456 return store_fault; 457 } 458 459 assert(store_fault == NoFault); 460 461 if (store_inst->isStoreConditional()) { 462 // Store conditionals need to set themselves as able to 463 // writeback if we haven't had a fault by here. 464 storeQueue[store_idx].canWB = true; 465 466 ++storesToWB; 467 } 468 469 if (!memDepViolator) { 470 while (load_idx != loadTail) { 471 // Really only need to check loads that have actually executed 472 // It's safe to check all loads because effAddr is set to 473 // InvalAddr when the dyn inst is created. 474 475 // @todo: For now this is extra conservative, detecting a 476 // violation if the addresses match assuming all accesses 477 // are quad word accesses. 478 479 // @todo: Fix this, magic number being used here 480 if ((loadQueue[load_idx]->effAddr >> 8) == 481 (store_inst->effAddr >> 8)) { 482 // A load incorrectly passed this store. Squash and refetch. 483 // For now return a fault to show that it was unsuccessful. 484 memDepViolator = loadQueue[load_idx]; 485 486 return genMachineCheckFault(); 487 } 488 489 incrLdIdx(load_idx); 490 } 491 492 // If we've reached this point, there was no violation. 493 memDepViolator = NULL; 494 } 495 496 return store_fault; 497} 498 499template <class Impl> 500void 501LSQUnit<Impl>::commitLoad() 502{ 503 assert(loadQueue[loadHead]); 504 505 DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n", 506 loadQueue[loadHead]->readPC()); 507 508 loadQueue[loadHead] = NULL; 509 510 incrLdIdx(loadHead); 511 512 --loads; 513} 514 515template <class Impl> 516void 517LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 518{ 519 assert(loads == 0 || loadQueue[loadHead]); 520 521 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 522 commitLoad(); 523 } 524} 525 526template <class Impl> 527void 528LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 529{ 530 assert(stores == 0 || storeQueue[storeHead].inst); 531 532 int store_idx = storeHead; 533 534 while (store_idx != storeTail) { 535 assert(storeQueue[store_idx].inst); 536 // Mark any stores that are now committed and have not yet 537 // been marked as able to write back. 538 if (!storeQueue[store_idx].canWB) { 539 if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 540 break; 541 } 542 DPRINTF(LSQUnit, "Marking store as able to write back, PC " 543 "%#x [sn:%lli]\n", 544 storeQueue[store_idx].inst->readPC(), 545 storeQueue[store_idx].inst->seqNum); 546 547 storeQueue[store_idx].canWB = true; 548 549 ++storesToWB; 550 } 551 552 incrStIdx(store_idx); 553 } 554} 555 556template <class Impl> 557void 558LSQUnit<Impl>::writebackStores() 559{ 560 while (storesToWB > 0 && 561 storeWBIdx != storeTail && 562 storeQueue[storeWBIdx].inst && 563 storeQueue[storeWBIdx].canWB && 564 usedPorts < cachePorts) { 565 566 if (isStoreBlocked) { 567 DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 568 " is blocked!\n"); 569 break; 570 } 571 572 // Store didn't write any data so no need to write it back to 573 // memory. 574 if (storeQueue[storeWBIdx].size == 0) { 575 completeStore(storeWBIdx); 576 577 incrStIdx(storeWBIdx); 578 579 continue; 580 } 581 582 ++usedPorts; 583 584 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 585 incrStIdx(storeWBIdx); 586 587 continue; 588 } 589 590 assert(storeQueue[storeWBIdx].req); 591 assert(!storeQueue[storeWBIdx].committed); 592 593 DynInstPtr inst = storeQueue[storeWBIdx].inst; 594 595 Request *req = storeQueue[storeWBIdx].req; 596 storeQueue[storeWBIdx].committed = true; 597 598 assert(!inst->memData); 599 inst->memData = new uint8_t[64]; 600 memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data, 601 req->getSize()); 602 603 PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast); 604 data_pkt->dataStatic(inst->memData); 605 606 LSQSenderState *state = new LSQSenderState; 607 state->isLoad = false; 608 state->idx = storeWBIdx; 609 state->inst = inst; 610 data_pkt->senderState = state; 611 612 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x " 613 "to Addr:%#x, data:%#x [sn:%lli]\n", 614 storeWBIdx, storeQueue[storeWBIdx].inst->readPC(), 615 req->getPaddr(), *(inst->memData), 616 storeQueue[storeWBIdx].inst->seqNum); 617 618 if (!dcachePort->sendTiming(data_pkt)) { 619 // Need to handle becoming blocked on a store. 620 isStoreBlocked = true; 621 } else { 622 if (isStalled() && 623 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 624 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 625 "load idx:%i\n", 626 stallingStoreIsn, stallingLoadIdx); 627 stalled = false; 628 stallingStoreIsn = 0; 629 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 630 } 631 632 if (!(req->getFlags() & LOCKED)) { 633 assert(!storeQueue[storeWBIdx].inst->isStoreConditional()); 634 // Non-store conditionals do not need a writeback. 635 state->noWB = true; 636 } 637 638 if (data_pkt->result != Packet::Success) { 639 DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n", 640 storeWBIdx); 641 642 DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n", 643 storeQueue[storeWBIdx].inst->seqNum); 644 645 //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum); 646 647 //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size()); 648 649 // @todo: Increment stat here. 650 } else { 651 DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n", 652 storeWBIdx); 653 654 DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n", 655 storeQueue[storeWBIdx].inst->seqNum); 656 } 657 658 incrStIdx(storeWBIdx); 659 } 660 } 661 662 // Not sure this should set it to 0. 663 usedPorts = 0; 664 665 assert(stores >= 0 && storesToWB >= 0); 666} 667 668/*template <class Impl> 669void 670LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 671{ 672 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 673 mshrSeqNums.end(), 674 seqNum); 675 676 if (mshr_it != mshrSeqNums.end()) { 677 mshrSeqNums.erase(mshr_it); 678 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 679 } 680}*/ 681 682template <class Impl> 683void 684LSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 685{ 686 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 687 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 688 689 int load_idx = loadTail; 690 decrLdIdx(load_idx); 691 692 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 693 DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, " 694 "[sn:%lli]\n", 695 loadQueue[load_idx]->readPC(), 696 loadQueue[load_idx]->seqNum); 697 698 if (isStalled() && load_idx == stallingLoadIdx) { 699 stalled = false; 700 stallingStoreIsn = 0; 701 stallingLoadIdx = 0; 702 } 703 704 // Clear the smart pointer to make sure it is decremented. 705 loadQueue[load_idx]->squashed = true; 706 loadQueue[load_idx] = NULL; 707 --loads; 708 709 // Inefficient! 710 loadTail = load_idx; 711 712 decrLdIdx(load_idx); 713 } 714 715 if (isLoadBlocked) { 716 if (squashed_num < blockedLoadSeqNum) { 717 isLoadBlocked = false; 718 loadBlockedHandled = false; 719 blockedLoadSeqNum = 0; 720 } 721 } 722 723 int store_idx = storeTail; 724 decrStIdx(store_idx); 725 726 while (stores != 0 && 727 storeQueue[store_idx].inst->seqNum > squashed_num) { 728 // Instructions marked as can WB are already committed. 729 if (storeQueue[store_idx].canWB) { 730 break; 731 } 732 733 DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, " 734 "idx:%i [sn:%lli]\n", 735 storeQueue[store_idx].inst->readPC(), 736 store_idx, storeQueue[store_idx].inst->seqNum); 737 738 // I don't think this can happen. It should have been cleared 739 // by the stalling load. 740 if (isStalled() && 741 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 742 panic("Is stalled should have been cleared by stalling load!\n"); 743 stalled = false; 744 stallingStoreIsn = 0; 745 } 746 747 // Clear the smart pointer to make sure it is decremented. 748 storeQueue[store_idx].inst->squashed = true; 749 storeQueue[store_idx].inst = NULL; 750 storeQueue[store_idx].canWB = 0; 751 752 storeQueue[store_idx].req = NULL; 753 --stores; 754 755 // Inefficient! 756 storeTail = store_idx; 757 758 decrStIdx(store_idx); 759 } 760} 761 762template <class Impl> 763void 764LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 765{ 766 iewStage->wakeCPU(); 767 768 // Squashed instructions do not need to complete their access. 769 if (inst->isSquashed()) { 770 assert(!inst->isStore()); 771 return; 772 } 773 774 if (!inst->isExecuted()) { 775 inst->setExecuted(); 776 777 // Complete access to copy data to proper place. 778 inst->completeAcc(pkt); 779 } 780 781 // Need to insert instruction into queue to commit 782 iewStage->instToCommit(inst); 783 784 iewStage->activityThisCycle(); 785} 786 787template <class Impl> 788void 789LSQUnit<Impl>::completeStore(int store_idx) 790{ 791 assert(storeQueue[store_idx].inst); 792 storeQueue[store_idx].completed = true; 793 --storesToWB; 794 // A bit conservative because a store completion may not free up entries, 795 // but hopefully avoids two store completions in one cycle from making 796 // the CPU tick twice. 797 cpu->activityThisCycle(); 798 799 if (store_idx == storeHead) { 800 do { 801 incrStIdx(storeHead); 802 803 --stores; 804 } while (storeQueue[storeHead].completed && 805 storeHead != storeTail); 806 807 iewStage->updateLSQNextCycle = true; 808 } 809 810 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 811 "idx:%i\n", 812 storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 813 814 if (isStalled() && 815 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 816 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 817 "load idx:%i\n", 818 stallingStoreIsn, stallingLoadIdx); 819 stalled = false; 820 stallingStoreIsn = 0; 821 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 822 } 823 824 storeQueue[store_idx].inst->setCompleted(); 825 826 // Tell the checker we've completed this instruction. Some stores 827 // may get reported twice to the checker, but the checker can 828 // handle that case. 829 if (cpu->checker) { 830 cpu->checker->tick(storeQueue[store_idx].inst); 831 } 832} 833 834template <class Impl> 835inline void 836LSQUnit<Impl>::incrStIdx(int &store_idx) 837{ 838 if (++store_idx >= SQEntries) 839 store_idx = 0; 840} 841 842template <class Impl> 843inline void 844LSQUnit<Impl>::decrStIdx(int &store_idx) 845{ 846 if (--store_idx < 0) 847 store_idx += SQEntries; 848} 849 850template <class Impl> 851inline void 852LSQUnit<Impl>::incrLdIdx(int &load_idx) 853{ 854 if (++load_idx >= LQEntries) 855 load_idx = 0; 856} 857 858template <class Impl> 859inline void 860LSQUnit<Impl>::decrLdIdx(int &load_idx) 861{ 862 if (--load_idx < 0) 863 load_idx += LQEntries; 864} 865 866template <class Impl> 867void 868LSQUnit<Impl>::dumpInsts() 869{ 870 cprintf("Load store queue: Dumping instructions.\n"); 871 cprintf("Load queue size: %i\n", loads); 872 cprintf("Load queue: "); 873 874 int load_idx = loadHead; 875 876 while (load_idx != loadTail && loadQueue[load_idx]) { 877 cprintf("%#x ", loadQueue[load_idx]->readPC()); 878 879 incrLdIdx(load_idx); 880 } 881 882 cprintf("Store queue size: %i\n", stores); 883 cprintf("Store queue: "); 884 885 int store_idx = storeHead; 886 887 while (store_idx != storeTail && storeQueue[store_idx].inst) { 888 cprintf("%#x ", storeQueue[store_idx].inst->readPC()); 889 890 incrStIdx(store_idx); 891 } 892 893 cprintf("\n"); 894} 895