lsq_unit_impl.hh revision 10231
14661Sksewell@umich.edu 25222Sksewell@umich.edu/* 34661Sksewell@umich.edu * Copyright (c) 2010-2013 ARM Limited 44661Sksewell@umich.edu * All rights reserved 54661Sksewell@umich.edu * 64661Sksewell@umich.edu * The license below extends only to copyright in the software and shall 74661Sksewell@umich.edu * not be construed as granting a license to any other intellectual 84661Sksewell@umich.edu * property including but not limited to intellectual property relating 94661Sksewell@umich.edu * to a hardware implementation of the functionality of the software 104661Sksewell@umich.edu * licensed hereunder. You may use the software subject to the license 114661Sksewell@umich.edu * terms below provided that you ensure that this notice is replicated 124661Sksewell@umich.edu * unmodified and in its entirety in all distributions of the software, 134661Sksewell@umich.edu * modified or unmodified, in source code or in binary form. 144661Sksewell@umich.edu * 154661Sksewell@umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 164661Sksewell@umich.edu * All rights reserved. 174661Sksewell@umich.edu * 184661Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 194661Sksewell@umich.edu * modification, are permitted provided that the following conditions are 204661Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 214661Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 224661Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 234661Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 244661Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 254661Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 264661Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 274661Sksewell@umich.edu * this software without specific prior written permission. 284661Sksewell@umich.edu * 294661Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 304661Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 314661Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 324661Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 334661Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 344661Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 354661Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 364661Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 374661Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 384661Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 394661Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 404661Sksewell@umich.edu * 414661Sksewell@umich.edu * Authors: Kevin Lim 424661Sksewell@umich.edu * Korey Sewell 434661Sksewell@umich.edu */ 444661Sksewell@umich.edu 454661Sksewell@umich.edu#ifndef __CPU_O3_LSQ_UNIT_IMPL_HH__ 464661Sksewell@umich.edu#define __CPU_O3_LSQ_UNIT_IMPL_HH__ 474661Sksewell@umich.edu 484661Sksewell@umich.edu#include "arch/generic/debugfaults.hh" 494661Sksewell@umich.edu#include "arch/locked_mem.hh" 504661Sksewell@umich.edu#include "base/str.hh" 514661Sksewell@umich.edu#include "config/the_isa.hh" 524661Sksewell@umich.edu#include "cpu/checker/cpu.hh" 534661Sksewell@umich.edu#include "cpu/o3/lsq.hh" 544661Sksewell@umich.edu#include "cpu/o3/lsq_unit.hh" 554661Sksewell@umich.edu#include "debug/Activity.hh" 564661Sksewell@umich.edu#include "debug/IEW.hh" 574661Sksewell@umich.edu#include "debug/LSQUnit.hh" 584661Sksewell@umich.edu#include "debug/O3PipeView.hh" 594661Sksewell@umich.edu#include "mem/packet.hh" 604661Sksewell@umich.edu#include "mem/request.hh" 614661Sksewell@umich.edu 624661Sksewell@umich.edutemplate<class Impl> 634661Sksewell@umich.eduLSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 644661Sksewell@umich.edu LSQUnit *lsq_ptr) 654661Sksewell@umich.edu : Event(Default_Pri, AutoDelete), 665222Sksewell@umich.edu inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 675222Sksewell@umich.edu{ 685222Sksewell@umich.edu} 695222Sksewell@umich.edu 705222Sksewell@umich.edutemplate<class Impl> 715222Sksewell@umich.eduvoid 724661Sksewell@umich.eduLSQUnit<Impl>::WritebackEvent::process() 734661Sksewell@umich.edu{ 744661Sksewell@umich.edu assert(!lsqPtr->cpu->switchedOut()); 754661Sksewell@umich.edu 764661Sksewell@umich.edu lsqPtr->writeback(inst, pkt); 774661Sksewell@umich.edu 785222Sksewell@umich.edu if (pkt->senderState) 795222Sksewell@umich.edu delete pkt->senderState; 805222Sksewell@umich.edu 815222Sksewell@umich.edu delete pkt->req; 825222Sksewell@umich.edu delete pkt; 835222Sksewell@umich.edu} 844661Sksewell@umich.edu 854661Sksewell@umich.edutemplate<class Impl> 864661Sksewell@umich.educonst char * 874661Sksewell@umich.eduLSQUnit<Impl>::WritebackEvent::description() const 884661Sksewell@umich.edu{ 894661Sksewell@umich.edu return "Store writeback"; 904661Sksewell@umich.edu} 914661Sksewell@umich.edu 924661Sksewell@umich.edutemplate<class Impl> 934661Sksewell@umich.eduvoid 944661Sksewell@umich.eduLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 954661Sksewell@umich.edu{ 964661Sksewell@umich.edu LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 974661Sksewell@umich.edu DynInstPtr inst = state->inst; 984661Sksewell@umich.edu DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum); 994661Sksewell@umich.edu DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum); 1004661Sksewell@umich.edu 1014661Sksewell@umich.edu //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 1024661Sksewell@umich.edu 1034661Sksewell@umich.edu // If this is a split access, wait until all packets are received. 1044661Sksewell@umich.edu if (TheISA::HasUnalignedMemAcc && !state->complete()) { 1054661Sksewell@umich.edu delete pkt->req; 1064661Sksewell@umich.edu delete pkt; 1074661Sksewell@umich.edu return; 1084661Sksewell@umich.edu } 1094661Sksewell@umich.edu 1104661Sksewell@umich.edu assert(!cpu->switchedOut()); 1114661Sksewell@umich.edu if (inst->isSquashed()) { 1124661Sksewell@umich.edu iewStage->decrWb(inst->seqNum); 1135222Sksewell@umich.edu } else { 1145222Sksewell@umich.edu if (!state->noWB) { 1154661Sksewell@umich.edu if (!TheISA::HasUnalignedMemAcc || !state->isSplit || 1164661Sksewell@umich.edu !state->isLoad) { 1174661Sksewell@umich.edu writeback(inst, pkt); 1184661Sksewell@umich.edu } else { 1194661Sksewell@umich.edu writeback(inst, state->mainPkt); 1204661Sksewell@umich.edu } 1214661Sksewell@umich.edu } 1224661Sksewell@umich.edu 1234661Sksewell@umich.edu if (inst->isStore()) { 1244661Sksewell@umich.edu completeStore(state->idx); 1254661Sksewell@umich.edu } 1264661Sksewell@umich.edu } 1274661Sksewell@umich.edu 1284661Sksewell@umich.edu if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) { 1294661Sksewell@umich.edu delete state->mainPkt->req; 1304661Sksewell@umich.edu delete state->mainPkt; 1314661Sksewell@umich.edu } 1324661Sksewell@umich.edu 1334661Sksewell@umich.edu pkt->req->setAccessLatency(); 1344661Sksewell@umich.edu cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt)); 1354661Sksewell@umich.edu 1364661Sksewell@umich.edu delete state; 1374661Sksewell@umich.edu delete pkt->req; 1384661Sksewell@umich.edu delete pkt; 1394661Sksewell@umich.edu} 1404661Sksewell@umich.edu 1415222Sksewell@umich.edutemplate <class Impl> 1425222Sksewell@umich.eduLSQUnit<Impl>::LSQUnit() 1435222Sksewell@umich.edu : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false), 1445222Sksewell@umich.edu isStoreBlocked(false), isLoadBlocked(false), 1455222Sksewell@umich.edu loadBlockedHandled(false), storeInFlight(false), hasPendingPkt(false) 1465222Sksewell@umich.edu{ 1474661Sksewell@umich.edu} 1484661Sksewell@umich.edu 1494661Sksewell@umich.edutemplate<class Impl> 1504661Sksewell@umich.eduvoid 1514661Sksewell@umich.eduLSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 1524661Sksewell@umich.edu LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 1534661Sksewell@umich.edu unsigned id) 1544661Sksewell@umich.edu{ 1554661Sksewell@umich.edu cpu = cpu_ptr; 1565222Sksewell@umich.edu iewStage = iew_ptr; 1574661Sksewell@umich.edu 1584661Sksewell@umich.edu lsq = lsq_ptr; 1594661Sksewell@umich.edu 1604661Sksewell@umich.edu lsqID = id; 1614661Sksewell@umich.edu 1624661Sksewell@umich.edu DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 1634661Sksewell@umich.edu 1644661Sksewell@umich.edu // Add 1 for the sentinel entry (they are circular queues). 1654661Sksewell@umich.edu LQEntries = maxLQEntries + 1; 1664661Sksewell@umich.edu SQEntries = maxSQEntries + 1; 1674661Sksewell@umich.edu 1684661Sksewell@umich.edu //Due to uint8_t index in LSQSenderState 1694661Sksewell@umich.edu assert(LQEntries <= 256); 1704661Sksewell@umich.edu assert(SQEntries <= 256); 1714661Sksewell@umich.edu 1724661Sksewell@umich.edu loadQueue.resize(LQEntries); 1734661Sksewell@umich.edu storeQueue.resize(SQEntries); 1744661Sksewell@umich.edu 1754661Sksewell@umich.edu depCheckShift = params->LSQDepCheckShift; 1764661Sksewell@umich.edu checkLoads = params->LSQCheckLoads; 1774661Sksewell@umich.edu cachePorts = params->cachePorts; 1784661Sksewell@umich.edu needsTSO = params->needsTSO; 1794661Sksewell@umich.edu 1804661Sksewell@umich.edu resetState(); 1814661Sksewell@umich.edu} 1824661Sksewell@umich.edu 1834661Sksewell@umich.edu 1845222Sksewell@umich.edutemplate<class Impl> 1855222Sksewell@umich.eduvoid 1864661Sksewell@umich.eduLSQUnit<Impl>::resetState() 1874661Sksewell@umich.edu{ 1884661Sksewell@umich.edu loads = stores = storesToWB = 0; 1894661Sksewell@umich.edu 1904661Sksewell@umich.edu loadHead = loadTail = 0; 1914661Sksewell@umich.edu 1924661Sksewell@umich.edu storeHead = storeWBIdx = storeTail = 0; 1934661Sksewell@umich.edu 1944661Sksewell@umich.edu usedPorts = 0; 1954661Sksewell@umich.edu 1964661Sksewell@umich.edu retryPkt = NULL; 1974661Sksewell@umich.edu memDepViolator = NULL; 1984661Sksewell@umich.edu 1994661Sksewell@umich.edu blockedLoadSeqNum = 0; 2004661Sksewell@umich.edu 2014661Sksewell@umich.edu stalled = false; 2024661Sksewell@umich.edu isLoadBlocked = false; 2034661Sksewell@umich.edu loadBlockedHandled = false; 2044661Sksewell@umich.edu 2054661Sksewell@umich.edu cacheBlockMask = ~(cpu->cacheLineSize() - 1); 2064661Sksewell@umich.edu} 2074661Sksewell@umich.edu 2084661Sksewell@umich.edutemplate<class Impl> 2094661Sksewell@umich.edustd::string 2104661Sksewell@umich.eduLSQUnit<Impl>::name() const 2114661Sksewell@umich.edu{ 2124661Sksewell@umich.edu if (Impl::MaxThreads == 1) { 2134661Sksewell@umich.edu return iewStage->name() + ".lsq"; 2144661Sksewell@umich.edu } else { 2154661Sksewell@umich.edu return iewStage->name() + ".lsq.thread" + to_string(lsqID); 2164661Sksewell@umich.edu } 2174661Sksewell@umich.edu} 2184661Sksewell@umich.edu 2194661Sksewell@umich.edutemplate<class Impl> 2204661Sksewell@umich.eduvoid 2214661Sksewell@umich.eduLSQUnit<Impl>::regStats() 2224661Sksewell@umich.edu{ 2234661Sksewell@umich.edu lsqForwLoads 2244661Sksewell@umich.edu .name(name() + ".forwLoads") 2254661Sksewell@umich.edu .desc("Number of loads that had data forwarded from stores"); 2264661Sksewell@umich.edu 2274661Sksewell@umich.edu invAddrLoads 2284661Sksewell@umich.edu .name(name() + ".invAddrLoads") 2294661Sksewell@umich.edu .desc("Number of loads ignored due to an invalid address"); 2304661Sksewell@umich.edu 2314661Sksewell@umich.edu lsqSquashedLoads 2324661Sksewell@umich.edu .name(name() + ".squashedLoads") 2334661Sksewell@umich.edu .desc("Number of loads squashed"); 2344661Sksewell@umich.edu 2354661Sksewell@umich.edu lsqIgnoredResponses 2364661Sksewell@umich.edu .name(name() + ".ignoredResponses") 2374661Sksewell@umich.edu .desc("Number of memory responses ignored because the instruction is squashed"); 2384661Sksewell@umich.edu 2394661Sksewell@umich.edu lsqMemOrderViolation 2404661Sksewell@umich.edu .name(name() + ".memOrderViolation") 2414661Sksewell@umich.edu .desc("Number of memory ordering violations"); 2424661Sksewell@umich.edu 2435222Sksewell@umich.edu lsqSquashedStores 2445222Sksewell@umich.edu .name(name() + ".squashedStores") 2455222Sksewell@umich.edu .desc("Number of stores squashed"); 2465222Sksewell@umich.edu 2474661Sksewell@umich.edu invAddrSwpfs 2484661Sksewell@umich.edu .name(name() + ".invAddrSwpfs") 2494661Sksewell@umich.edu .desc("Number of software prefetches ignored due to an invalid address"); 2504661Sksewell@umich.edu 2514661Sksewell@umich.edu lsqBlockedLoads 2524661Sksewell@umich.edu .name(name() + ".blockedLoads") 2534661Sksewell@umich.edu .desc("Number of blocked loads due to partial load-store forwarding"); 2544661Sksewell@umich.edu 2554661Sksewell@umich.edu lsqRescheduledLoads 2564661Sksewell@umich.edu .name(name() + ".rescheduledLoads") 2574661Sksewell@umich.edu .desc("Number of loads that were rescheduled"); 2584661Sksewell@umich.edu 2594661Sksewell@umich.edu lsqCacheBlocked 2604661Sksewell@umich.edu .name(name() + ".cacheBlocked") 2614661Sksewell@umich.edu .desc("Number of times an access to memory failed due to the cache being blocked"); 2624661Sksewell@umich.edu} 2634661Sksewell@umich.edu 2644661Sksewell@umich.edutemplate<class Impl> 2654661Sksewell@umich.eduvoid 2664661Sksewell@umich.eduLSQUnit<Impl>::setDcachePort(MasterPort *dcache_port) 2674661Sksewell@umich.edu{ 2684661Sksewell@umich.edu dcachePort = dcache_port; 2694661Sksewell@umich.edu} 2704661Sksewell@umich.edu 2714661Sksewell@umich.edutemplate<class Impl> 2724661Sksewell@umich.eduvoid 2734661Sksewell@umich.eduLSQUnit<Impl>::clearLQ() 2744661Sksewell@umich.edu{ 2754661Sksewell@umich.edu loadQueue.clear(); 2764661Sksewell@umich.edu} 2774661Sksewell@umich.edu 2784661Sksewell@umich.edutemplate<class Impl> 2794661Sksewell@umich.eduvoid 2804661Sksewell@umich.eduLSQUnit<Impl>::clearSQ() 2814661Sksewell@umich.edu{ 2824661Sksewell@umich.edu storeQueue.clear(); 2834661Sksewell@umich.edu} 2844661Sksewell@umich.edu 2854661Sksewell@umich.edutemplate<class Impl> 2864661Sksewell@umich.eduvoid 2874661Sksewell@umich.eduLSQUnit<Impl>::drainSanityCheck() const 2884661Sksewell@umich.edu{ 2894661Sksewell@umich.edu for (int i = 0; i < loadQueue.size(); ++i) 2904661Sksewell@umich.edu assert(!loadQueue[i]); 2914661Sksewell@umich.edu 2924661Sksewell@umich.edu assert(storesToWB == 0); 2934661Sksewell@umich.edu assert(!retryPkt); 2944661Sksewell@umich.edu} 2954661Sksewell@umich.edu 2964661Sksewell@umich.edutemplate<class Impl> 2974661Sksewell@umich.eduvoid 2984661Sksewell@umich.eduLSQUnit<Impl>::takeOverFrom() 2994661Sksewell@umich.edu{ 3004661Sksewell@umich.edu resetState(); 3014661Sksewell@umich.edu} 3025222Sksewell@umich.edu 3035222Sksewell@umich.edutemplate<class Impl> 3044661Sksewell@umich.eduvoid 3054661Sksewell@umich.eduLSQUnit<Impl>::resizeLQ(unsigned size) 3064661Sksewell@umich.edu{ 3074661Sksewell@umich.edu unsigned size_plus_sentinel = size + 1; 3084661Sksewell@umich.edu assert(size_plus_sentinel >= LQEntries); 3094661Sksewell@umich.edu 3105222Sksewell@umich.edu if (size_plus_sentinel > LQEntries) { 3115222Sksewell@umich.edu while (size_plus_sentinel > loadQueue.size()) { 3124661Sksewell@umich.edu DynInstPtr dummy; 3134661Sksewell@umich.edu loadQueue.push_back(dummy); 3144661Sksewell@umich.edu LQEntries++; 3154661Sksewell@umich.edu } 3164661Sksewell@umich.edu } else { 3174661Sksewell@umich.edu LQEntries = size_plus_sentinel; 3184661Sksewell@umich.edu } 3194661Sksewell@umich.edu 3204661Sksewell@umich.edu assert(LQEntries <= 256); 3214661Sksewell@umich.edu} 3224661Sksewell@umich.edu 3234661Sksewell@umich.edutemplate<class Impl> 3244661Sksewell@umich.eduvoid 3254661Sksewell@umich.eduLSQUnit<Impl>::resizeSQ(unsigned size) 3264661Sksewell@umich.edu{ 3274661Sksewell@umich.edu unsigned size_plus_sentinel = size + 1; 3284661Sksewell@umich.edu if (size_plus_sentinel > SQEntries) { 3294661Sksewell@umich.edu while (size_plus_sentinel > storeQueue.size()) { 3304661Sksewell@umich.edu SQEntry dummy; 3315222Sksewell@umich.edu storeQueue.push_back(dummy); 3325222Sksewell@umich.edu SQEntries++; 3335222Sksewell@umich.edu } 3345222Sksewell@umich.edu } else { 3355222Sksewell@umich.edu SQEntries = size_plus_sentinel; 3365222Sksewell@umich.edu } 3375222Sksewell@umich.edu 3385222Sksewell@umich.edu assert(SQEntries <= 256); 3395222Sksewell@umich.edu} 3405222Sksewell@umich.edu 3415222Sksewell@umich.edutemplate <class Impl> 3425222Sksewell@umich.eduvoid 3435222Sksewell@umich.eduLSQUnit<Impl>::insert(DynInstPtr &inst) 3445222Sksewell@umich.edu{ 3454661Sksewell@umich.edu assert(inst->isMemRef()); 3464661Sksewell@umich.edu 3474661Sksewell@umich.edu assert(inst->isLoad() || inst->isStore()); 3484661Sksewell@umich.edu 3494661Sksewell@umich.edu if (inst->isLoad()) { 3504661Sksewell@umich.edu insertLoad(inst); 3514661Sksewell@umich.edu } else { 3524661Sksewell@umich.edu insertStore(inst); 3534661Sksewell@umich.edu } 3544661Sksewell@umich.edu 3554661Sksewell@umich.edu inst->setInLSQ(); 3564661Sksewell@umich.edu} 3574661Sksewell@umich.edu 3584661Sksewell@umich.edutemplate <class Impl> 3594661Sksewell@umich.eduvoid 3604661Sksewell@umich.eduLSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 3614661Sksewell@umich.edu{ 3624661Sksewell@umich.edu assert((loadTail + 1) % LQEntries != loadHead); 3634661Sksewell@umich.edu assert(loads < LQEntries); 3644661Sksewell@umich.edu 3654661Sksewell@umich.edu DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n", 3664661Sksewell@umich.edu load_inst->pcState(), loadTail, load_inst->seqNum); 3674661Sksewell@umich.edu 3685222Sksewell@umich.edu load_inst->lqIdx = loadTail; 3695222Sksewell@umich.edu 3705222Sksewell@umich.edu if (stores == 0) { 3715222Sksewell@umich.edu load_inst->sqIdx = -1; 3725222Sksewell@umich.edu } else { 3735222Sksewell@umich.edu load_inst->sqIdx = storeTail; 3745222Sksewell@umich.edu } 3755222Sksewell@umich.edu 3764661Sksewell@umich.edu loadQueue[loadTail] = load_inst; 3775222Sksewell@umich.edu 3785222Sksewell@umich.edu incrLdIdx(loadTail); 3795222Sksewell@umich.edu 3805222Sksewell@umich.edu ++loads; 3815222Sksewell@umich.edu} 3825222Sksewell@umich.edu 3835222Sksewell@umich.edutemplate <class Impl> 3845222Sksewell@umich.eduvoid 3854661Sksewell@umich.eduLSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 3864661Sksewell@umich.edu{ 3874661Sksewell@umich.edu // Make sure it is not full before inserting an instruction. 3884661Sksewell@umich.edu assert((storeTail + 1) % SQEntries != storeHead); 3894661Sksewell@umich.edu assert(stores < SQEntries); 3904661Sksewell@umich.edu 3914661Sksewell@umich.edu DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n", 3924661Sksewell@umich.edu store_inst->pcState(), storeTail, store_inst->seqNum); 3934661Sksewell@umich.edu 3944661Sksewell@umich.edu store_inst->sqIdx = storeTail; 3954661Sksewell@umich.edu store_inst->lqIdx = loadTail; 3964661Sksewell@umich.edu 3974661Sksewell@umich.edu storeQueue[storeTail] = SQEntry(store_inst); 3984661Sksewell@umich.edu 3994661Sksewell@umich.edu incrStIdx(storeTail); 4004661Sksewell@umich.edu 4014661Sksewell@umich.edu ++stores; 4024661Sksewell@umich.edu} 4034661Sksewell@umich.edu 4044661Sksewell@umich.edutemplate <class Impl> 4054661Sksewell@umich.edutypename Impl::DynInstPtr 4064661Sksewell@umich.eduLSQUnit<Impl>::getMemDepViolator() 4074661Sksewell@umich.edu{ 4084661Sksewell@umich.edu DynInstPtr temp = memDepViolator; 4094661Sksewell@umich.edu 4104661Sksewell@umich.edu memDepViolator = NULL; 4114661Sksewell@umich.edu 4124661Sksewell@umich.edu return temp; 4134661Sksewell@umich.edu} 4144661Sksewell@umich.edu 4154661Sksewell@umich.edutemplate <class Impl> 4164661Sksewell@umich.eduunsigned 4174661Sksewell@umich.eduLSQUnit<Impl>::numFreeEntries() 4184661Sksewell@umich.edu{ 4194661Sksewell@umich.edu unsigned free_lq_entries = LQEntries - loads; 4204661Sksewell@umich.edu unsigned free_sq_entries = SQEntries - stores; 4214661Sksewell@umich.edu 4224661Sksewell@umich.edu // Both the LQ and SQ entries have an extra dummy entry to differentiate 4234661Sksewell@umich.edu // empty/full conditions. Subtract 1 from the free entries. 4244661Sksewell@umich.edu if (free_lq_entries < free_sq_entries) { 4254661Sksewell@umich.edu return free_lq_entries - 1; 4264661Sksewell@umich.edu } else { 4274661Sksewell@umich.edu return free_sq_entries - 1; 4284661Sksewell@umich.edu } 4294661Sksewell@umich.edu} 4304661Sksewell@umich.edu 4314661Sksewell@umich.edutemplate <class Impl> 4324661Sksewell@umich.eduvoid 4334661Sksewell@umich.eduLSQUnit<Impl>::checkSnoop(PacketPtr pkt) 4344661Sksewell@umich.edu{ 4354661Sksewell@umich.edu int load_idx = loadHead; 4364661Sksewell@umich.edu DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr()); 4374661Sksewell@umich.edu 4384661Sksewell@umich.edu // Unlock the cpu-local monitor when the CPU sees a snoop to a locked 4394661Sksewell@umich.edu // address. The CPU can speculatively execute a LL operation after a pending 4404661Sksewell@umich.edu // SC operation in the pipeline and that can make the cache monitor the CPU 4414661Sksewell@umich.edu // is connected to valid while it really shouldn't be. 4424661Sksewell@umich.edu for (int x = 0; x < cpu->numContexts(); x++) { 4434661Sksewell@umich.edu ThreadContext *tc = cpu->getContext(x); 4444661Sksewell@umich.edu bool no_squash = cpu->thread[x]->noSquashFromTC; 4454661Sksewell@umich.edu cpu->thread[x]->noSquashFromTC = true; 4464661Sksewell@umich.edu TheISA::handleLockedSnoop(tc, pkt, cacheBlockMask); 4474661Sksewell@umich.edu cpu->thread[x]->noSquashFromTC = no_squash; 4484661Sksewell@umich.edu } 4494661Sksewell@umich.edu 4504661Sksewell@umich.edu Addr invalidate_addr = pkt->getAddr() & cacheBlockMask; 4514661Sksewell@umich.edu 4524661Sksewell@umich.edu DynInstPtr ld_inst = loadQueue[load_idx]; 4534661Sksewell@umich.edu if (ld_inst) { 4544661Sksewell@umich.edu Addr load_addr = ld_inst->physEffAddr & cacheBlockMask; 4554661Sksewell@umich.edu // Check that this snoop didn't just invalidate our lock flag 4564661Sksewell@umich.edu if (ld_inst->effAddrValid() && load_addr == invalidate_addr && 4574661Sksewell@umich.edu ld_inst->memReqFlags & Request::LLSC) 4584661Sksewell@umich.edu TheISA::handleLockedSnoopHit(ld_inst.get()); 4594661Sksewell@umich.edu } 4604661Sksewell@umich.edu 4614661Sksewell@umich.edu // If this is the only load in the LSQ we don't care 4624661Sksewell@umich.edu if (load_idx == loadTail) 4634661Sksewell@umich.edu return; 4644661Sksewell@umich.edu 4654661Sksewell@umich.edu incrLdIdx(load_idx); 4664661Sksewell@umich.edu 4674661Sksewell@umich.edu bool force_squash = false; 4684661Sksewell@umich.edu 4694661Sksewell@umich.edu while (load_idx != loadTail) { 4704661Sksewell@umich.edu DynInstPtr ld_inst = loadQueue[load_idx]; 4714661Sksewell@umich.edu 4724661Sksewell@umich.edu if (!ld_inst->effAddrValid() || ld_inst->uncacheable()) { 4734661Sksewell@umich.edu incrLdIdx(load_idx); 4744661Sksewell@umich.edu continue; 4754661Sksewell@umich.edu } 4764661Sksewell@umich.edu 4774661Sksewell@umich.edu Addr load_addr = ld_inst->physEffAddr & cacheBlockMask; 4784661Sksewell@umich.edu DPRINTF(LSQUnit, "-- inst [sn:%lli] load_addr: %#x to pktAddr:%#x\n", 4794661Sksewell@umich.edu ld_inst->seqNum, load_addr, invalidate_addr); 4804661Sksewell@umich.edu 4814661Sksewell@umich.edu if (load_addr == invalidate_addr || force_squash) { 4824661Sksewell@umich.edu if (needsTSO) { 4834661Sksewell@umich.edu // If we have a TSO system, as all loads must be ordered with 4844661Sksewell@umich.edu // all other loads, this load as well as *all* subsequent loads 4854661Sksewell@umich.edu // need to be squashed to prevent possible load reordering. 4864661Sksewell@umich.edu force_squash = true; 4874661Sksewell@umich.edu } 4884661Sksewell@umich.edu if (ld_inst->possibleLoadViolation() || force_squash) { 4894661Sksewell@umich.edu DPRINTF(LSQUnit, "Conflicting load at addr %#x [sn:%lli]\n", 4904661Sksewell@umich.edu pkt->getAddr(), ld_inst->seqNum); 4914661Sksewell@umich.edu 4924661Sksewell@umich.edu // Mark the load for re-execution 4934661Sksewell@umich.edu ld_inst->fault = new ReExec; 4944661Sksewell@umich.edu } else { 4954661Sksewell@umich.edu DPRINTF(LSQUnit, "HitExternal Snoop for addr %#x [sn:%lli]\n", 496 pkt->getAddr(), ld_inst->seqNum); 497 498 // Make sure that we don't lose a snoop hitting a LOCKED 499 // address since the LOCK* flags don't get updated until 500 // commit. 501 if (ld_inst->memReqFlags & Request::LLSC) 502 TheISA::handleLockedSnoopHit(ld_inst.get()); 503 504 // If a older load checks this and it's true 505 // then we might have missed the snoop 506 // in which case we need to invalidate to be sure 507 ld_inst->hitExternalSnoop(true); 508 } 509 } 510 incrLdIdx(load_idx); 511 } 512 return; 513} 514 515template <class Impl> 516Fault 517LSQUnit<Impl>::checkViolations(int load_idx, DynInstPtr &inst) 518{ 519 Addr inst_eff_addr1 = inst->effAddr >> depCheckShift; 520 Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift; 521 522 /** @todo in theory you only need to check an instruction that has executed 523 * however, there isn't a good way in the pipeline at the moment to check 524 * all instructions that will execute before the store writes back. Thus, 525 * like the implementation that came before it, we're overly conservative. 526 */ 527 while (load_idx != loadTail) { 528 DynInstPtr ld_inst = loadQueue[load_idx]; 529 if (!ld_inst->effAddrValid() || ld_inst->uncacheable()) { 530 incrLdIdx(load_idx); 531 continue; 532 } 533 534 Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift; 535 Addr ld_eff_addr2 = 536 (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift; 537 538 if (inst_eff_addr2 >= ld_eff_addr1 && inst_eff_addr1 <= ld_eff_addr2) { 539 if (inst->isLoad()) { 540 // If this load is to the same block as an external snoop 541 // invalidate that we've observed then the load needs to be 542 // squashed as it could have newer data 543 if (ld_inst->hitExternalSnoop()) { 544 if (!memDepViolator || 545 ld_inst->seqNum < memDepViolator->seqNum) { 546 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] " 547 "and [sn:%lli] at address %#x\n", 548 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 549 memDepViolator = ld_inst; 550 551 ++lsqMemOrderViolation; 552 553 return new GenericISA::M5PanicFault( 554 "Detected fault with inst [sn:%lli] and " 555 "[sn:%lli] at address %#x\n", 556 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 557 } 558 } 559 560 // Otherwise, mark the load has a possible load violation 561 // and if we see a snoop before it's commited, we need to squash 562 ld_inst->possibleLoadViolation(true); 563 DPRINTF(LSQUnit, "Found possible load violaiton at addr: %#x" 564 " between instructions [sn:%lli] and [sn:%lli]\n", 565 inst_eff_addr1, inst->seqNum, ld_inst->seqNum); 566 } else { 567 // A load/store incorrectly passed this store. 568 // Check if we already have a violator, or if it's newer 569 // squash and refetch. 570 if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum) 571 break; 572 573 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and " 574 "[sn:%lli] at address %#x\n", 575 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 576 memDepViolator = ld_inst; 577 578 ++lsqMemOrderViolation; 579 580 return new GenericISA::M5PanicFault("Detected fault with " 581 "inst [sn:%lli] and [sn:%lli] at address %#x\n", 582 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 583 } 584 } 585 586 incrLdIdx(load_idx); 587 } 588 return NoFault; 589} 590 591 592 593 594template <class Impl> 595Fault 596LSQUnit<Impl>::executeLoad(DynInstPtr &inst) 597{ 598 using namespace TheISA; 599 // Execute a specific load. 600 Fault load_fault = NoFault; 601 602 DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n", 603 inst->pcState(), inst->seqNum); 604 605 assert(!inst->isSquashed()); 606 607 load_fault = inst->initiateAcc(); 608 609 if (inst->isTranslationDelayed() && 610 load_fault == NoFault) 611 return load_fault; 612 613 // If the instruction faulted or predicated false, then we need to send it 614 // along to commit without the instruction completing. 615 if (load_fault != NoFault || !inst->readPredicate()) { 616 // Send this instruction to commit, also make sure iew stage 617 // realizes there is activity. 618 // Mark it as executed unless it is an uncached load that 619 // needs to hit the head of commit. 620 if (!inst->readPredicate()) 621 inst->forwardOldRegs(); 622 DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", 623 inst->seqNum, 624 (load_fault != NoFault ? "fault" : "predication")); 625 if (!(inst->hasRequest() && inst->uncacheable()) || 626 inst->isAtCommit()) { 627 inst->setExecuted(); 628 } 629 iewStage->instToCommit(inst); 630 iewStage->activityThisCycle(); 631 } else if (!loadBlocked()) { 632 assert(inst->effAddrValid()); 633 int load_idx = inst->lqIdx; 634 incrLdIdx(load_idx); 635 636 if (checkLoads) 637 return checkViolations(load_idx, inst); 638 } 639 640 return load_fault; 641} 642 643template <class Impl> 644Fault 645LSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 646{ 647 using namespace TheISA; 648 // Make sure that a store exists. 649 assert(stores != 0); 650 651 int store_idx = store_inst->sqIdx; 652 653 DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n", 654 store_inst->pcState(), store_inst->seqNum); 655 656 assert(!store_inst->isSquashed()); 657 658 // Check the recently completed loads to see if any match this store's 659 // address. If so, then we have a memory ordering violation. 660 int load_idx = store_inst->lqIdx; 661 662 Fault store_fault = store_inst->initiateAcc(); 663 664 if (store_inst->isTranslationDelayed() && 665 store_fault == NoFault) 666 return store_fault; 667 668 if (!store_inst->readPredicate()) 669 store_inst->forwardOldRegs(); 670 671 if (storeQueue[store_idx].size == 0) { 672 DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", 673 store_inst->pcState(), store_inst->seqNum); 674 675 return store_fault; 676 } else if (!store_inst->readPredicate()) { 677 DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", 678 store_inst->seqNum); 679 return store_fault; 680 } 681 682 assert(store_fault == NoFault); 683 684 if (store_inst->isStoreConditional()) { 685 // Store conditionals need to set themselves as able to 686 // writeback if we haven't had a fault by here. 687 storeQueue[store_idx].canWB = true; 688 689 ++storesToWB; 690 } 691 692 return checkViolations(load_idx, store_inst); 693 694} 695 696template <class Impl> 697void 698LSQUnit<Impl>::commitLoad() 699{ 700 assert(loadQueue[loadHead]); 701 702 DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n", 703 loadQueue[loadHead]->pcState()); 704 705 loadQueue[loadHead] = NULL; 706 707 incrLdIdx(loadHead); 708 709 --loads; 710} 711 712template <class Impl> 713void 714LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 715{ 716 assert(loads == 0 || loadQueue[loadHead]); 717 718 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 719 commitLoad(); 720 } 721} 722 723template <class Impl> 724void 725LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 726{ 727 assert(stores == 0 || storeQueue[storeHead].inst); 728 729 int store_idx = storeHead; 730 731 while (store_idx != storeTail) { 732 assert(storeQueue[store_idx].inst); 733 // Mark any stores that are now committed and have not yet 734 // been marked as able to write back. 735 if (!storeQueue[store_idx].canWB) { 736 if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 737 break; 738 } 739 DPRINTF(LSQUnit, "Marking store as able to write back, PC " 740 "%s [sn:%lli]\n", 741 storeQueue[store_idx].inst->pcState(), 742 storeQueue[store_idx].inst->seqNum); 743 744 storeQueue[store_idx].canWB = true; 745 746 ++storesToWB; 747 } 748 749 incrStIdx(store_idx); 750 } 751} 752 753template <class Impl> 754void 755LSQUnit<Impl>::writebackPendingStore() 756{ 757 if (hasPendingPkt) { 758 assert(pendingPkt != NULL); 759 760 // If the cache is blocked, this will store the packet for retry. 761 if (sendStore(pendingPkt)) { 762 storePostSend(pendingPkt); 763 } 764 pendingPkt = NULL; 765 hasPendingPkt = false; 766 } 767} 768 769template <class Impl> 770void 771LSQUnit<Impl>::writebackStores() 772{ 773 // First writeback the second packet from any split store that didn't 774 // complete last cycle because there weren't enough cache ports available. 775 if (TheISA::HasUnalignedMemAcc) { 776 writebackPendingStore(); 777 } 778 779 while (storesToWB > 0 && 780 storeWBIdx != storeTail && 781 storeQueue[storeWBIdx].inst && 782 storeQueue[storeWBIdx].canWB && 783 ((!needsTSO) || (!storeInFlight)) && 784 usedPorts < cachePorts) { 785 786 if (isStoreBlocked || lsq->cacheBlocked()) { 787 DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 788 " is blocked!\n"); 789 break; 790 } 791 792 // Store didn't write any data so no need to write it back to 793 // memory. 794 if (storeQueue[storeWBIdx].size == 0) { 795 completeStore(storeWBIdx); 796 797 incrStIdx(storeWBIdx); 798 799 continue; 800 } 801 802 ++usedPorts; 803 804 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 805 incrStIdx(storeWBIdx); 806 807 continue; 808 } 809 810 assert(storeQueue[storeWBIdx].req); 811 assert(!storeQueue[storeWBIdx].committed); 812 813 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 814 assert(storeQueue[storeWBIdx].sreqLow); 815 assert(storeQueue[storeWBIdx].sreqHigh); 816 } 817 818 DynInstPtr inst = storeQueue[storeWBIdx].inst; 819 820 Request *req = storeQueue[storeWBIdx].req; 821 RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow; 822 RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh; 823 824 storeQueue[storeWBIdx].committed = true; 825 826 assert(!inst->memData); 827 inst->memData = new uint8_t[req->getSize()]; 828 829 if (storeQueue[storeWBIdx].isAllZeros) 830 memset(inst->memData, 0, req->getSize()); 831 else 832 memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); 833 834 MemCmd command = 835 req->isSwap() ? MemCmd::SwapReq : 836 (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq); 837 PacketPtr data_pkt; 838 PacketPtr snd_data_pkt = NULL; 839 840 LSQSenderState *state = new LSQSenderState; 841 state->isLoad = false; 842 state->idx = storeWBIdx; 843 state->inst = inst; 844 845 if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) { 846 847 // Build a single data packet if the store isn't split. 848 data_pkt = new Packet(req, command); 849 data_pkt->dataStatic(inst->memData); 850 data_pkt->senderState = state; 851 } else { 852 // Create two packets if the store is split in two. 853 data_pkt = new Packet(sreqLow, command); 854 snd_data_pkt = new Packet(sreqHigh, command); 855 856 data_pkt->dataStatic(inst->memData); 857 snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize()); 858 859 data_pkt->senderState = state; 860 snd_data_pkt->senderState = state; 861 862 state->isSplit = true; 863 state->outstanding = 2; 864 865 // Can delete the main request now. 866 delete req; 867 req = sreqLow; 868 } 869 870 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s " 871 "to Addr:%#x, data:%#x [sn:%lli]\n", 872 storeWBIdx, inst->pcState(), 873 req->getPaddr(), (int)*(inst->memData), 874 inst->seqNum); 875 876 // @todo: Remove this SC hack once the memory system handles it. 877 if (inst->isStoreConditional()) { 878 assert(!storeQueue[storeWBIdx].isSplit); 879 // Disable recording the result temporarily. Writing to 880 // misc regs normally updates the result, but this is not 881 // the desired behavior when handling store conditionals. 882 inst->recordResult(false); 883 bool success = TheISA::handleLockedWrite(inst.get(), req, cacheBlockMask); 884 inst->recordResult(true); 885 886 if (!success) { 887 // Instantly complete this store. 888 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 889 "Instantly completing it.\n", 890 inst->seqNum); 891 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 892 cpu->schedule(wb, curTick() + 1); 893 if (cpu->checker) { 894 // Make sure to set the LLSC data for verification 895 // if checker is loaded 896 inst->reqToVerify->setExtraData(0); 897 inst->completeAcc(data_pkt); 898 } 899 completeStore(storeWBIdx); 900 incrStIdx(storeWBIdx); 901 continue; 902 } 903 } else { 904 // Non-store conditionals do not need a writeback. 905 state->noWB = true; 906 } 907 908 bool split = 909 TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit; 910 911 ThreadContext *thread = cpu->tcBase(lsqID); 912 913 if (req->isMmappedIpr()) { 914 assert(!inst->isStoreConditional()); 915 TheISA::handleIprWrite(thread, data_pkt); 916 delete data_pkt; 917 if (split) { 918 assert(snd_data_pkt->req->isMmappedIpr()); 919 TheISA::handleIprWrite(thread, snd_data_pkt); 920 delete snd_data_pkt; 921 delete sreqLow; 922 delete sreqHigh; 923 } 924 delete state; 925 delete req; 926 completeStore(storeWBIdx); 927 incrStIdx(storeWBIdx); 928 } else if (!sendStore(data_pkt)) { 929 DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 930 "retry later\n", 931 inst->seqNum); 932 933 // Need to store the second packet, if split. 934 if (split) { 935 state->pktToSend = true; 936 state->pendingPacket = snd_data_pkt; 937 } 938 } else { 939 940 // If split, try to send the second packet too 941 if (split) { 942 assert(snd_data_pkt); 943 944 // Ensure there are enough ports to use. 945 if (usedPorts < cachePorts) { 946 ++usedPorts; 947 if (sendStore(snd_data_pkt)) { 948 storePostSend(snd_data_pkt); 949 } else { 950 DPRINTF(IEW, "D-Cache became blocked when writing" 951 " [sn:%lli] second packet, will retry later\n", 952 inst->seqNum); 953 } 954 } else { 955 956 // Store the packet for when there's free ports. 957 assert(pendingPkt == NULL); 958 pendingPkt = snd_data_pkt; 959 hasPendingPkt = true; 960 } 961 } else { 962 963 // Not a split store. 964 storePostSend(data_pkt); 965 } 966 } 967 } 968 969 // Not sure this should set it to 0. 970 usedPorts = 0; 971 972 assert(stores >= 0 && storesToWB >= 0); 973} 974 975/*template <class Impl> 976void 977LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 978{ 979 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 980 mshrSeqNums.end(), 981 seqNum); 982 983 if (mshr_it != mshrSeqNums.end()) { 984 mshrSeqNums.erase(mshr_it); 985 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 986 } 987}*/ 988 989template <class Impl> 990void 991LSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 992{ 993 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 994 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 995 996 int load_idx = loadTail; 997 decrLdIdx(load_idx); 998 999 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 1000 DPRINTF(LSQUnit,"Load Instruction PC %s squashed, " 1001 "[sn:%lli]\n", 1002 loadQueue[load_idx]->pcState(), 1003 loadQueue[load_idx]->seqNum); 1004 1005 if (isStalled() && load_idx == stallingLoadIdx) { 1006 stalled = false; 1007 stallingStoreIsn = 0; 1008 stallingLoadIdx = 0; 1009 } 1010 1011 // Clear the smart pointer to make sure it is decremented. 1012 loadQueue[load_idx]->setSquashed(); 1013 loadQueue[load_idx] = NULL; 1014 --loads; 1015 1016 // Inefficient! 1017 loadTail = load_idx; 1018 1019 decrLdIdx(load_idx); 1020 ++lsqSquashedLoads; 1021 } 1022 1023 if (isLoadBlocked) { 1024 if (squashed_num < blockedLoadSeqNum) { 1025 isLoadBlocked = false; 1026 loadBlockedHandled = false; 1027 blockedLoadSeqNum = 0; 1028 } 1029 } 1030 1031 if (memDepViolator && squashed_num < memDepViolator->seqNum) { 1032 memDepViolator = NULL; 1033 } 1034 1035 int store_idx = storeTail; 1036 decrStIdx(store_idx); 1037 1038 while (stores != 0 && 1039 storeQueue[store_idx].inst->seqNum > squashed_num) { 1040 // Instructions marked as can WB are already committed. 1041 if (storeQueue[store_idx].canWB) { 1042 break; 1043 } 1044 1045 DPRINTF(LSQUnit,"Store Instruction PC %s squashed, " 1046 "idx:%i [sn:%lli]\n", 1047 storeQueue[store_idx].inst->pcState(), 1048 store_idx, storeQueue[store_idx].inst->seqNum); 1049 1050 // I don't think this can happen. It should have been cleared 1051 // by the stalling load. 1052 if (isStalled() && 1053 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 1054 panic("Is stalled should have been cleared by stalling load!\n"); 1055 stalled = false; 1056 stallingStoreIsn = 0; 1057 } 1058 1059 // Clear the smart pointer to make sure it is decremented. 1060 storeQueue[store_idx].inst->setSquashed(); 1061 storeQueue[store_idx].inst = NULL; 1062 storeQueue[store_idx].canWB = 0; 1063 1064 // Must delete request now that it wasn't handed off to 1065 // memory. This is quite ugly. @todo: Figure out the proper 1066 // place to really handle request deletes. 1067 delete storeQueue[store_idx].req; 1068 if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) { 1069 delete storeQueue[store_idx].sreqLow; 1070 delete storeQueue[store_idx].sreqHigh; 1071 1072 storeQueue[store_idx].sreqLow = NULL; 1073 storeQueue[store_idx].sreqHigh = NULL; 1074 } 1075 1076 storeQueue[store_idx].req = NULL; 1077 --stores; 1078 1079 // Inefficient! 1080 storeTail = store_idx; 1081 1082 decrStIdx(store_idx); 1083 ++lsqSquashedStores; 1084 } 1085} 1086 1087template <class Impl> 1088void 1089LSQUnit<Impl>::storePostSend(PacketPtr pkt) 1090{ 1091 if (isStalled() && 1092 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 1093 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 1094 "load idx:%i\n", 1095 stallingStoreIsn, stallingLoadIdx); 1096 stalled = false; 1097 stallingStoreIsn = 0; 1098 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 1099 } 1100 1101 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 1102 // The store is basically completed at this time. This 1103 // only works so long as the checker doesn't try to 1104 // verify the value in memory for stores. 1105 storeQueue[storeWBIdx].inst->setCompleted(); 1106 1107 if (cpu->checker) { 1108 cpu->checker->verify(storeQueue[storeWBIdx].inst); 1109 } 1110 } 1111 1112 if (needsTSO) { 1113 storeInFlight = true; 1114 } 1115 1116 incrStIdx(storeWBIdx); 1117} 1118 1119template <class Impl> 1120void 1121LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 1122{ 1123 iewStage->wakeCPU(); 1124 1125 // Squashed instructions do not need to complete their access. 1126 if (inst->isSquashed()) { 1127 iewStage->decrWb(inst->seqNum); 1128 assert(!inst->isStore()); 1129 ++lsqIgnoredResponses; 1130 return; 1131 } 1132 1133 if (!inst->isExecuted()) { 1134 inst->setExecuted(); 1135 1136 // Complete access to copy data to proper place. 1137 inst->completeAcc(pkt); 1138 } 1139 1140 // Need to insert instruction into queue to commit 1141 iewStage->instToCommit(inst); 1142 1143 iewStage->activityThisCycle(); 1144 1145 // see if this load changed the PC 1146 iewStage->checkMisprediction(inst); 1147} 1148 1149template <class Impl> 1150void 1151LSQUnit<Impl>::completeStore(int store_idx) 1152{ 1153 assert(storeQueue[store_idx].inst); 1154 storeQueue[store_idx].completed = true; 1155 --storesToWB; 1156 // A bit conservative because a store completion may not free up entries, 1157 // but hopefully avoids two store completions in one cycle from making 1158 // the CPU tick twice. 1159 cpu->wakeCPU(); 1160 cpu->activityThisCycle(); 1161 1162 if (store_idx == storeHead) { 1163 do { 1164 incrStIdx(storeHead); 1165 1166 --stores; 1167 } while (storeQueue[storeHead].completed && 1168 storeHead != storeTail); 1169 1170 iewStage->updateLSQNextCycle = true; 1171 } 1172 1173 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 1174 "idx:%i\n", 1175 storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 1176 1177#if TRACING_ON 1178 if (DTRACE(O3PipeView)) { 1179 storeQueue[store_idx].inst->storeTick = 1180 curTick() - storeQueue[store_idx].inst->fetchTick; 1181 } 1182#endif 1183 1184 if (isStalled() && 1185 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 1186 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 1187 "load idx:%i\n", 1188 stallingStoreIsn, stallingLoadIdx); 1189 stalled = false; 1190 stallingStoreIsn = 0; 1191 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 1192 } 1193 1194 storeQueue[store_idx].inst->setCompleted(); 1195 1196 if (needsTSO) { 1197 storeInFlight = false; 1198 } 1199 1200 // Tell the checker we've completed this instruction. Some stores 1201 // may get reported twice to the checker, but the checker can 1202 // handle that case. 1203 if (cpu->checker) { 1204 cpu->checker->verify(storeQueue[store_idx].inst); 1205 } 1206} 1207 1208template <class Impl> 1209bool 1210LSQUnit<Impl>::sendStore(PacketPtr data_pkt) 1211{ 1212 if (!dcachePort->sendTimingReq(data_pkt)) { 1213 // Need to handle becoming blocked on a store. 1214 isStoreBlocked = true; 1215 ++lsqCacheBlocked; 1216 assert(retryPkt == NULL); 1217 retryPkt = data_pkt; 1218 lsq->setRetryTid(lsqID); 1219 return false; 1220 } 1221 return true; 1222} 1223 1224template <class Impl> 1225void 1226LSQUnit<Impl>::recvRetry() 1227{ 1228 if (isStoreBlocked) { 1229 DPRINTF(LSQUnit, "Receiving retry: store blocked\n"); 1230 assert(retryPkt != NULL); 1231 1232 LSQSenderState *state = 1233 dynamic_cast<LSQSenderState *>(retryPkt->senderState); 1234 1235 if (dcachePort->sendTimingReq(retryPkt)) { 1236 // Don't finish the store unless this is the last packet. 1237 if (!TheISA::HasUnalignedMemAcc || !state->pktToSend || 1238 state->pendingPacket == retryPkt) { 1239 state->pktToSend = false; 1240 storePostSend(retryPkt); 1241 } 1242 retryPkt = NULL; 1243 isStoreBlocked = false; 1244 lsq->setRetryTid(InvalidThreadID); 1245 1246 // Send any outstanding packet. 1247 if (TheISA::HasUnalignedMemAcc && state->pktToSend) { 1248 assert(state->pendingPacket); 1249 if (sendStore(state->pendingPacket)) { 1250 storePostSend(state->pendingPacket); 1251 } 1252 } 1253 } else { 1254 // Still blocked! 1255 ++lsqCacheBlocked; 1256 lsq->setRetryTid(lsqID); 1257 } 1258 } else if (isLoadBlocked) { 1259 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 1260 "no need to resend packet.\n"); 1261 } else { 1262 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 1263 } 1264} 1265 1266template <class Impl> 1267inline void 1268LSQUnit<Impl>::incrStIdx(int &store_idx) const 1269{ 1270 if (++store_idx >= SQEntries) 1271 store_idx = 0; 1272} 1273 1274template <class Impl> 1275inline void 1276LSQUnit<Impl>::decrStIdx(int &store_idx) const 1277{ 1278 if (--store_idx < 0) 1279 store_idx += SQEntries; 1280} 1281 1282template <class Impl> 1283inline void 1284LSQUnit<Impl>::incrLdIdx(int &load_idx) const 1285{ 1286 if (++load_idx >= LQEntries) 1287 load_idx = 0; 1288} 1289 1290template <class Impl> 1291inline void 1292LSQUnit<Impl>::decrLdIdx(int &load_idx) const 1293{ 1294 if (--load_idx < 0) 1295 load_idx += LQEntries; 1296} 1297 1298template <class Impl> 1299void 1300LSQUnit<Impl>::dumpInsts() const 1301{ 1302 cprintf("Load store queue: Dumping instructions.\n"); 1303 cprintf("Load queue size: %i\n", loads); 1304 cprintf("Load queue: "); 1305 1306 int load_idx = loadHead; 1307 1308 while (load_idx != loadTail && loadQueue[load_idx]) { 1309 const DynInstPtr &inst(loadQueue[load_idx]); 1310 cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum); 1311 1312 incrLdIdx(load_idx); 1313 } 1314 cprintf("\n"); 1315 1316 cprintf("Store queue size: %i\n", stores); 1317 cprintf("Store queue: "); 1318 1319 int store_idx = storeHead; 1320 1321 while (store_idx != storeTail && storeQueue[store_idx].inst) { 1322 const DynInstPtr &inst(storeQueue[store_idx].inst); 1323 cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum); 1324 1325 incrStIdx(store_idx); 1326 } 1327 1328 cprintf("\n"); 1329} 1330 1331#endif//__CPU_O3_LSQ_UNIT_IMPL_HH__ 1332