lsq_unit.hh revision 6658 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#ifndef __CPU_O3_LSQ_UNIT_HH__
33#define __CPU_O3_LSQ_UNIT_HH__
34
35#include <algorithm>
36#include <cstring>
37#include <map>
38#include <queue>
39
40#include "arch/faults.hh"
41#include "arch/locked_mem.hh"
42#include "config/full_system.hh"
43#include "config/the_isa.hh"
44#include "base/fast_alloc.hh"
45#include "base/hashmap.hh"
46#include "cpu/inst_seq.hh"
47#include "mem/packet.hh"
48#include "mem/port.hh"
49
50class DerivO3CPUParams;
51
52/**
53 * Class that implements the actual LQ and SQ for each specific
54 * thread.  Both are circular queues; load entries are freed upon
55 * committing, while store entries are freed once they writeback. The
56 * LSQUnit tracks if there are memory ordering violations, and also
57 * detects partial load to store forwarding cases (a store only has
58 * part of a load's data) that requires the load to wait until the
59 * store writes back. In the former case it holds onto the instruction
60 * until the dependence unit looks at it, and in the latter it stalls
61 * the LSQ until the store writes back. At that point the load is
62 * replayed.
63 */
64template <class Impl>
65class LSQUnit {
66  protected:
67    typedef TheISA::IntReg IntReg;
68  public:
69    typedef typename Impl::O3CPU O3CPU;
70    typedef typename Impl::DynInstPtr DynInstPtr;
71    typedef typename Impl::CPUPol::IEW IEW;
72    typedef typename Impl::CPUPol::LSQ LSQ;
73    typedef typename Impl::CPUPol::IssueStruct IssueStruct;
74
75  public:
76    /** Constructs an LSQ unit. init() must be called prior to use. */
77    LSQUnit();
78
79    /** Initializes the LSQ unit with the specified number of entries. */
80    void init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
81            LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries,
82            unsigned id);
83
84    /** Returns the name of the LSQ unit. */
85    std::string name() const;
86
87    /** Registers statistics. */
88    void regStats();
89
90    /** Sets the pointer to the dcache port. */
91    void setDcachePort(Port *dcache_port);
92
93    /** Switches out LSQ unit. */
94    void switchOut();
95
96    /** Takes over from another CPU's thread. */
97    void takeOverFrom();
98
99    /** Returns if the LSQ is switched out. */
100    bool isSwitchedOut() { return switchedOut; }
101
102    /** Ticks the LSQ unit, which in this case only resets the number of
103     * used cache ports.
104     * @todo: Move the number of used ports up to the LSQ level so it can
105     * be shared by all LSQ units.
106     */
107    void tick() { usedPorts = 0; }
108
109    /** Inserts an instruction. */
110    void insert(DynInstPtr &inst);
111    /** Inserts a load instruction. */
112    void insertLoad(DynInstPtr &load_inst);
113    /** Inserts a store instruction. */
114    void insertStore(DynInstPtr &store_inst);
115
116    /** Executes a load instruction. */
117    Fault executeLoad(DynInstPtr &inst);
118
119    Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; }
120    /** Executes a store instruction. */
121    Fault executeStore(DynInstPtr &inst);
122
123    /** Commits the head load. */
124    void commitLoad();
125    /** Commits loads older than a specific sequence number. */
126    void commitLoads(InstSeqNum &youngest_inst);
127
128    /** Commits stores older than a specific sequence number. */
129    void commitStores(InstSeqNum &youngest_inst);
130
131    /** Writes back stores. */
132    void writebackStores();
133
134    /** Completes the data access that has been returned from the
135     * memory system. */
136    void completeDataAccess(PacketPtr pkt);
137
138    /** Clears all the entries in the LQ. */
139    void clearLQ();
140
141    /** Clears all the entries in the SQ. */
142    void clearSQ();
143
144    /** Resizes the LQ to a given size. */
145    void resizeLQ(unsigned size);
146
147    /** Resizes the SQ to a given size. */
148    void resizeSQ(unsigned size);
149
150    /** Squashes all instructions younger than a specific sequence number. */
151    void squash(const InstSeqNum &squashed_num);
152
153    /** Returns if there is a memory ordering violation. Value is reset upon
154     * call to getMemDepViolator().
155     */
156    bool violation() { return memDepViolator; }
157
158    /** Returns the memory ordering violator. */
159    DynInstPtr getMemDepViolator();
160
161    /** Returns if a load became blocked due to the memory system. */
162    bool loadBlocked()
163    { return isLoadBlocked; }
164
165    /** Clears the signal that a load became blocked. */
166    void clearLoadBlocked()
167    { isLoadBlocked = false; }
168
169    /** Returns if the blocked load was handled. */
170    bool isLoadBlockedHandled()
171    { return loadBlockedHandled; }
172
173    /** Records the blocked load as being handled. */
174    void setLoadBlockedHandled()
175    { loadBlockedHandled = true; }
176
177    /** Returns the number of free entries (min of free LQ and SQ entries). */
178    unsigned numFreeEntries();
179
180    /** Returns the number of loads ready to execute. */
181    int numLoadsReady();
182
183    /** Returns the number of loads in the LQ. */
184    int numLoads() { return loads; }
185
186    /** Returns the number of stores in the SQ. */
187    int numStores() { return stores; }
188
189    /** Returns if either the LQ or SQ is full. */
190    bool isFull() { return lqFull() || sqFull(); }
191
192    /** Returns if the LQ is full. */
193    bool lqFull() { return loads >= (LQEntries - 1); }
194
195    /** Returns if the SQ is full. */
196    bool sqFull() { return stores >= (SQEntries - 1); }
197
198    /** Returns the number of instructions in the LSQ. */
199    unsigned getCount() { return loads + stores; }
200
201    /** Returns if there are any stores to writeback. */
202    bool hasStoresToWB() { return storesToWB; }
203
204    /** Returns the number of stores to writeback. */
205    int numStoresToWB() { return storesToWB; }
206
207    /** Returns if the LSQ unit will writeback on this cycle. */
208    bool willWB() { return storeQueue[storeWBIdx].canWB &&
209                        !storeQueue[storeWBIdx].completed &&
210                        !isStoreBlocked; }
211
212    /** Handles doing the retry. */
213    void recvRetry();
214
215  private:
216    /** Writes back the instruction, sending it to IEW. */
217    void writeback(DynInstPtr &inst, PacketPtr pkt);
218
219    /** Handles completing the send of a store to memory. */
220    void storePostSend(PacketPtr pkt);
221
222    /** Completes the store at the specified index. */
223    void completeStore(int store_idx);
224
225    /** Increments the given store index (circular queue). */
226    inline void incrStIdx(int &store_idx);
227    /** Decrements the given store index (circular queue). */
228    inline void decrStIdx(int &store_idx);
229    /** Increments the given load index (circular queue). */
230    inline void incrLdIdx(int &load_idx);
231    /** Decrements the given load index (circular queue). */
232    inline void decrLdIdx(int &load_idx);
233
234  public:
235    /** Debugging function to dump instructions in the LSQ. */
236    void dumpInsts();
237
238  private:
239    /** Pointer to the CPU. */
240    O3CPU *cpu;
241
242    /** Pointer to the IEW stage. */
243    IEW *iewStage;
244
245    /** Pointer to the LSQ. */
246    LSQ *lsq;
247
248    /** Pointer to the dcache port.  Used only for sending. */
249    Port *dcachePort;
250
251    /** Derived class to hold any sender state the LSQ needs. */
252    class LSQSenderState : public Packet::SenderState, public FastAlloc
253    {
254      public:
255        /** Default constructor. */
256        LSQSenderState()
257            : noWB(false)
258        { }
259
260        /** Instruction who initiated the access to memory. */
261        DynInstPtr inst;
262        /** Whether or not it is a load. */
263        bool isLoad;
264        /** The LQ/SQ index of the instruction. */
265        int idx;
266        /** Whether or not the instruction will need to writeback. */
267        bool noWB;
268    };
269
270    /** Writeback event, specifically for when stores forward data to loads. */
271    class WritebackEvent : public Event {
272      public:
273        /** Constructs a writeback event. */
274        WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr);
275
276        /** Processes the writeback event. */
277        void process();
278
279        /** Returns the description of this event. */
280        const char *description() const;
281
282      private:
283        /** Instruction whose results are being written back. */
284        DynInstPtr inst;
285
286        /** The packet that would have been sent to memory. */
287        PacketPtr pkt;
288
289        /** The pointer to the LSQ unit that issued the store. */
290        LSQUnit<Impl> *lsqPtr;
291    };
292
293  public:
294    struct SQEntry {
295        /** Constructs an empty store queue entry. */
296        SQEntry()
297            : inst(NULL), req(NULL), size(0),
298              canWB(0), committed(0), completed(0)
299        {
300            std::memset(data, 0, sizeof(data));
301        }
302
303        /** Constructs a store queue entry for a given instruction. */
304        SQEntry(DynInstPtr &_inst)
305            : inst(_inst), req(NULL), size(0),
306              canWB(0), committed(0), completed(0)
307        {
308            std::memset(data, 0, sizeof(data));
309        }
310
311        /** The store instruction. */
312        DynInstPtr inst;
313        /** The request for the store. */
314        RequestPtr req;
315        /** The size of the store. */
316        int size;
317        /** The store data. */
318        char data[sizeof(IntReg)];
319        /** Whether or not the store can writeback. */
320        bool canWB;
321        /** Whether or not the store is committed. */
322        bool committed;
323        /** Whether or not the store is completed. */
324        bool completed;
325    };
326
327  private:
328    /** The LSQUnit thread id. */
329    ThreadID lsqID;
330
331    /** The store queue. */
332    std::vector<SQEntry> storeQueue;
333
334    /** The load queue. */
335    std::vector<DynInstPtr> loadQueue;
336
337    /** The number of LQ entries, plus a sentinel entry (circular queue).
338     *  @todo: Consider having var that records the true number of LQ entries.
339     */
340    unsigned LQEntries;
341    /** The number of SQ entries, plus a sentinel entry (circular queue).
342     *  @todo: Consider having var that records the true number of SQ entries.
343     */
344    unsigned SQEntries;
345
346    /** The number of load instructions in the LQ. */
347    int loads;
348    /** The number of store instructions in the SQ. */
349    int stores;
350    /** The number of store instructions in the SQ waiting to writeback. */
351    int storesToWB;
352
353    /** The index of the head instruction in the LQ. */
354    int loadHead;
355    /** The index of the tail instruction in the LQ. */
356    int loadTail;
357
358    /** The index of the head instruction in the SQ. */
359    int storeHead;
360    /** The index of the first instruction that may be ready to be
361     * written back, and has not yet been written back.
362     */
363    int storeWBIdx;
364    /** The index of the tail instruction in the SQ. */
365    int storeTail;
366
367    /// @todo Consider moving to a more advanced model with write vs read ports
368    /** The number of cache ports available each cycle. */
369    int cachePorts;
370
371    /** The number of used cache ports in this cycle. */
372    int usedPorts;
373
374    /** Is the LSQ switched out. */
375    bool switchedOut;
376
377    //list<InstSeqNum> mshrSeqNums;
378
379    /** Wire to read information from the issue stage time queue. */
380    typename TimeBuffer<IssueStruct>::wire fromIssue;
381
382    /** Whether or not the LSQ is stalled. */
383    bool stalled;
384    /** The store that causes the stall due to partial store to load
385     * forwarding.
386     */
387    InstSeqNum stallingStoreIsn;
388    /** The index of the above store. */
389    int stallingLoadIdx;
390
391    /** The packet that needs to be retried. */
392    PacketPtr retryPkt;
393
394    /** Whehter or not a store is blocked due to the memory system. */
395    bool isStoreBlocked;
396
397    /** Whether or not a load is blocked due to the memory system. */
398    bool isLoadBlocked;
399
400    /** Has the blocked load been handled. */
401    bool loadBlockedHandled;
402
403    /** The sequence number of the blocked load. */
404    InstSeqNum blockedLoadSeqNum;
405
406    /** The oldest load that caused a memory ordering violation. */
407    DynInstPtr memDepViolator;
408
409    // Will also need how many read/write ports the Dcache has.  Or keep track
410    // of that in stage that is one level up, and only call executeLoad/Store
411    // the appropriate number of times.
412    /** Total number of loads forwaded from LSQ stores. */
413    Stats::Scalar lsqForwLoads;
414
415    /** Total number of loads ignored due to invalid addresses. */
416    Stats::Scalar invAddrLoads;
417
418    /** Total number of squashed loads. */
419    Stats::Scalar lsqSquashedLoads;
420
421    /** Total number of responses from the memory system that are
422     * ignored due to the instruction already being squashed. */
423    Stats::Scalar lsqIgnoredResponses;
424
425    /** Tota number of memory ordering violations. */
426    Stats::Scalar lsqMemOrderViolation;
427
428    /** Total number of squashed stores. */
429    Stats::Scalar lsqSquashedStores;
430
431    /** Total number of software prefetches ignored due to invalid addresses. */
432    Stats::Scalar invAddrSwpfs;
433
434    /** Ready loads blocked due to partial store-forwarding. */
435    Stats::Scalar lsqBlockedLoads;
436
437    /** Number of loads that were rescheduled. */
438    Stats::Scalar lsqRescheduledLoads;
439
440    /** Number of times the LSQ is blocked due to the cache. */
441    Stats::Scalar lsqCacheBlocked;
442
443  public:
444    /** Executes the load at the given index. */
445    template <class T>
446    Fault read(Request *req, T &data, int load_idx);
447
448    /** Executes the store at the given index. */
449    template <class T>
450    Fault write(Request *req, T &data, int store_idx);
451
452    /** Returns the index of the head load instruction. */
453    int getLoadHead() { return loadHead; }
454    /** Returns the sequence number of the head load instruction. */
455    InstSeqNum getLoadHeadSeqNum()
456    {
457        if (loadQueue[loadHead]) {
458            return loadQueue[loadHead]->seqNum;
459        } else {
460            return 0;
461        }
462
463    }
464
465    /** Returns the index of the head store instruction. */
466    int getStoreHead() { return storeHead; }
467    /** Returns the sequence number of the head store instruction. */
468    InstSeqNum getStoreHeadSeqNum()
469    {
470        if (storeQueue[storeHead].inst) {
471            return storeQueue[storeHead].inst->seqNum;
472        } else {
473            return 0;
474        }
475
476    }
477
478    /** Returns whether or not the LSQ unit is stalled. */
479    bool isStalled()  { return stalled; }
480};
481
482template <class Impl>
483template <class T>
484Fault
485LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
486{
487    DynInstPtr load_inst = loadQueue[load_idx];
488
489    assert(load_inst);
490
491    assert(!load_inst->isExecuted());
492
493    // Make sure this isn't an uncacheable access
494    // A bit of a hackish way to get uncached accesses to work only if they're
495    // at the head of the LSQ and are ready to commit (at the head of the ROB
496    // too).
497    if (req->isUncacheable() &&
498        (load_idx != loadHead || !load_inst->isAtCommit())) {
499        iewStage->rescheduleMemInst(load_inst);
500        ++lsqRescheduledLoads;
501
502        // Must delete request now that it wasn't handed off to
503        // memory.  This is quite ugly.  @todo: Figure out the proper
504        // place to really handle request deletes.
505        delete req;
506        return TheISA::genMachineCheckFault();
507    }
508
509    // Check the SQ for any previous stores that might lead to forwarding
510    int store_idx = load_inst->sqIdx;
511
512    int store_size = 0;
513
514    DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, "
515            "storeHead: %i addr: %#x\n",
516            load_idx, store_idx, storeHead, req->getPaddr());
517
518    if (req->isLLSC()) {
519        // Disable recording the result temporarily.  Writing to misc
520        // regs normally updates the result, but this is not the
521        // desired behavior when handling store conditionals.
522        load_inst->recordResult = false;
523        TheISA::handleLockedRead(load_inst.get(), req);
524        load_inst->recordResult = true;
525    }
526
527    while (store_idx != -1) {
528        // End once we've reached the top of the LSQ
529        if (store_idx == storeWBIdx) {
530            break;
531        }
532
533        // Move the index to one younger
534        if (--store_idx < 0)
535            store_idx += SQEntries;
536
537        assert(storeQueue[store_idx].inst);
538
539        store_size = storeQueue[store_idx].size;
540
541        if (store_size == 0)
542            continue;
543        else if (storeQueue[store_idx].inst->uncacheable())
544            continue;
545
546        assert(storeQueue[store_idx].inst->effAddrValid);
547
548        // Check if the store data is within the lower and upper bounds of
549        // addresses that the request needs.
550        bool store_has_lower_limit =
551            req->getVaddr() >= storeQueue[store_idx].inst->effAddr;
552        bool store_has_upper_limit =
553            (req->getVaddr() + req->getSize()) <=
554            (storeQueue[store_idx].inst->effAddr + store_size);
555        bool lower_load_has_store_part =
556            req->getVaddr() < (storeQueue[store_idx].inst->effAddr +
557                           store_size);
558        bool upper_load_has_store_part =
559            (req->getVaddr() + req->getSize()) >
560            storeQueue[store_idx].inst->effAddr;
561
562        // If the store's data has all of the data needed, we can forward.
563        if ((store_has_lower_limit && store_has_upper_limit)) {
564            // Get shift amount for offset into the store's data.
565            int shift_amt = req->getVaddr() & (store_size - 1);
566
567            memcpy(&data, storeQueue[store_idx].data + shift_amt, sizeof(T));
568
569            assert(!load_inst->memData);
570            load_inst->memData = new uint8_t[64];
571
572            memcpy(load_inst->memData,
573                    storeQueue[store_idx].data + shift_amt, req->getSize());
574
575            DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
576                    "addr %#x, data %#x\n",
577                    store_idx, req->getVaddr(), data);
578
579            PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq,
580                                            Packet::Broadcast);
581            data_pkt->dataStatic(load_inst->memData);
582
583            WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
584
585            // We'll say this has a 1 cycle load-store forwarding latency
586            // for now.
587            // @todo: Need to make this a parameter.
588            cpu->schedule(wb, curTick);
589
590            ++lsqForwLoads;
591            return NoFault;
592        } else if ((store_has_lower_limit && lower_load_has_store_part) ||
593                   (store_has_upper_limit && upper_load_has_store_part) ||
594                   (lower_load_has_store_part && upper_load_has_store_part)) {
595            // This is the partial store-load forwarding case where a store
596            // has only part of the load's data.
597
598            // If it's already been written back, then don't worry about
599            // stalling on it.
600            if (storeQueue[store_idx].completed) {
601                panic("Should not check one of these");
602                continue;
603            }
604
605            // Must stall load and force it to retry, so long as it's the oldest
606            // load that needs to do so.
607            if (!stalled ||
608                (stalled &&
609                 load_inst->seqNum <
610                 loadQueue[stallingLoadIdx]->seqNum)) {
611                stalled = true;
612                stallingStoreIsn = storeQueue[store_idx].inst->seqNum;
613                stallingLoadIdx = load_idx;
614            }
615
616            // Tell IQ/mem dep unit that this instruction will need to be
617            // rescheduled eventually
618            iewStage->rescheduleMemInst(load_inst);
619            iewStage->decrWb(load_inst->seqNum);
620            load_inst->clearIssued();
621            ++lsqRescheduledLoads;
622
623            // Do not generate a writeback event as this instruction is not
624            // complete.
625            DPRINTF(LSQUnit, "Load-store forwarding mis-match. "
626                    "Store idx %i to load addr %#x\n",
627                    store_idx, req->getVaddr());
628
629            // Must delete request now that it wasn't handed off to
630            // memory.  This is quite ugly.  @todo: Figure out the
631            // proper place to really handle request deletes.
632            delete req;
633
634            return NoFault;
635        }
636    }
637
638    // If there's no forwarding case, then go access memory
639    DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %#x\n",
640            load_inst->seqNum, load_inst->readPC());
641
642    assert(!load_inst->memData);
643    load_inst->memData = new uint8_t[64];
644
645    ++usedPorts;
646
647    // if we the cache is not blocked, do cache access
648    if (!lsq->cacheBlocked()) {
649        PacketPtr data_pkt =
650            new Packet(req,
651                       (req->isLLSC() ?
652                        MemCmd::LoadLockedReq : MemCmd::ReadReq),
653                       Packet::Broadcast);
654        data_pkt->dataStatic(load_inst->memData);
655
656        LSQSenderState *state = new LSQSenderState;
657        state->isLoad = true;
658        state->idx = load_idx;
659        state->inst = load_inst;
660        data_pkt->senderState = state;
661
662        if (!dcachePort->sendTiming(data_pkt)) {
663            // Delete state and data packet because a load retry
664            // initiates a pipeline restart; it does not retry.
665            delete state;
666            delete data_pkt->req;
667            delete data_pkt;
668
669            req = NULL;
670
671            // If the access didn't succeed, tell the LSQ by setting
672            // the retry thread id.
673            lsq->setRetryTid(lsqID);
674        }
675    }
676
677    // If the cache was blocked, or has become blocked due to the access,
678    // handle it.
679    if (lsq->cacheBlocked()) {
680        if (req)
681            delete req;
682
683        ++lsqCacheBlocked;
684
685        iewStage->decrWb(load_inst->seqNum);
686        // There's an older load that's already going to squash.
687        if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum)
688            return NoFault;
689
690        // Record that the load was blocked due to memory.  This
691        // load will squash all instructions after it, be
692        // refetched, and re-executed.
693        isLoadBlocked = true;
694        loadBlockedHandled = false;
695        blockedLoadSeqNum = load_inst->seqNum;
696        // No fault occurred, even though the interface is blocked.
697        return NoFault;
698    }
699
700    return NoFault;
701}
702
703template <class Impl>
704template <class T>
705Fault
706LSQUnit<Impl>::write(Request *req, T &data, int store_idx)
707{
708    assert(storeQueue[store_idx].inst);
709
710    DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x data %#x"
711            " | storeHead:%i [sn:%i]\n",
712            store_idx, req->getPaddr(), data, storeHead,
713            storeQueue[store_idx].inst->seqNum);
714
715    storeQueue[store_idx].req = req;
716    storeQueue[store_idx].size = sizeof(T);
717    assert(sizeof(T) <= sizeof(storeQueue[store_idx].data));
718
719    T gData = htog(data);
720    memcpy(storeQueue[store_idx].data, &gData, sizeof(T));
721
722    // This function only writes the data to the store queue, so no fault
723    // can happen here.
724    return NoFault;
725}
726
727#endif // __CPU_O3_LSQ_UNIT_HH__
728