lsq_unit.hh revision 3803:031d9d1b3924
12036SN/A/* 22036SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 32036SN/A * All rights reserved. 42036SN/A * 52036SN/A * Redistribution and use in source and binary forms, with or without 62036SN/A * modification, are permitted provided that the following conditions are 72036SN/A * met: redistributions of source code must retain the above copyright 82036SN/A * notice, this list of conditions and the following disclaimer; 92036SN/A * redistributions in binary form must reproduce the above copyright 102036SN/A * notice, this list of conditions and the following disclaimer in the 112036SN/A * documentation and/or other materials provided with the distribution; 122036SN/A * neither the name of the copyright holders nor the names of its 132036SN/A * contributors may be used to endorse or promote products derived from 142036SN/A * this software without specific prior written permission. 152036SN/A * 162036SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172036SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182036SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192036SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202036SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212036SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222036SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232036SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242036SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252036SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262036SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282956Sgblack@eecs.umich.edu * Authors: Kevin Lim 292956Sgblack@eecs.umich.edu * Korey Sewell 302772Ssaidi@eecs.umich.edu */ 312036SN/A 322036SN/A#ifndef __CPU_O3_LSQ_UNIT_HH__ 332036SN/A#define __CPU_O3_LSQ_UNIT_HH__ 342036SN/A 352036SN/A#include <algorithm> 362036SN/A#include <map> 372036SN/A#include <queue> 382036SN/A 392036SN/A#include "arch/faults.hh" 402779Sbinkertn@umich.edu#include "arch/locked_mem.hh" 412036SN/A#include "config/full_system.hh" 422036SN/A#include "base/hashmap.hh" 432036SN/A#include "cpu/inst_seq.hh" 442036SN/A#include "mem/packet.hh" 452036SN/A#include "mem/port.hh" 462565SN/A 472565SN/A/** 482565SN/A * Class that implements the actual LQ and SQ for each specific 492565SN/A * thread. Both are circular queues; load entries are freed upon 502036SN/A * committing, while store entries are freed once they writeback. The 512036SN/A * LSQUnit tracks if there are memory ordering violations, and also 522036SN/A * detects partial load to store forwarding cases (a store only has 532036SN/A * part of a load's data) that requires the load to wait until the 542778Ssaidi@eecs.umich.edu * store writes back. In the former case it holds onto the instruction 552778Ssaidi@eecs.umich.edu * until the dependence unit looks at it, and in the latter it stalls 562778Ssaidi@eecs.umich.edu * the LSQ until the store writes back. At that point the load is 572778Ssaidi@eecs.umich.edu * replayed. 582036SN/A */ 592036SN/Atemplate <class Impl> 602036SN/Aclass LSQUnit { 612036SN/A protected: 622036SN/A typedef TheISA::IntReg IntReg; 632565SN/A public: 642565SN/A typedef typename Impl::Params Params; 652778Ssaidi@eecs.umich.edu typedef typename Impl::O3CPU O3CPU; 662778Ssaidi@eecs.umich.edu typedef typename Impl::DynInstPtr DynInstPtr; 672565SN/A typedef typename Impl::CPUPol::IEW IEW; 682036SN/A typedef typename Impl::CPUPol::LSQ LSQ; 692036SN/A typedef typename Impl::CPUPol::IssueStruct IssueStruct; 702036SN/A 712036SN/A public: 722036SN/A /** Constructs an LSQ unit. init() must be called prior to use. */ 732036SN/A LSQUnit(); 742036SN/A 752036SN/A /** Initializes the LSQ unit with the specified number of entries. */ 762565SN/A void init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries, 772036SN/A unsigned maxSQEntries, unsigned id); 782036SN/A 792036SN/A /** Returns the name of the LSQ unit. */ 802036SN/A std::string name() const; 812036SN/A 822565SN/A /** Registers statistics. */ 832565SN/A void regStats(); 842778Ssaidi@eecs.umich.edu 852778Ssaidi@eecs.umich.edu /** Sets the CPU pointer. */ 862565SN/A void setCPU(O3CPU *cpu_ptr); 872036SN/A 882036SN/A /** Sets the IEW stage pointer. */ 892036SN/A void setIEW(IEW *iew_ptr) 902565SN/A { iewStage = iew_ptr; } 912036SN/A 922036SN/A /** Sets the pointer to the dcache port. */ 932036SN/A void setDcachePort(Port *dcache_port) 942036SN/A { dcachePort = dcache_port; } 952036SN/A 962565SN/A /** Switches out LSQ unit. */ 972565SN/A void switchOut(); 982778Ssaidi@eecs.umich.edu 992778Ssaidi@eecs.umich.edu /** Takes over from another CPU's thread. */ 1002565SN/A void takeOverFrom(); 1012036SN/A 1022036SN/A /** Returns if the LSQ is switched out. */ 1032565SN/A bool isSwitchedOut() { return switchedOut; } 1042036SN/A 1052036SN/A /** Ticks the LSQ unit, which in this case only resets the number of 1062764Sstever@eecs.umich.edu * used cache ports. 1072764Sstever@eecs.umich.edu * @todo: Move the number of used ports up to the LSQ level so it can 1082764Sstever@eecs.umich.edu * be shared by all LSQ units. 1092764Sstever@eecs.umich.edu */ 1102764Sstever@eecs.umich.edu void tick() { usedPorts = 0; } 1112764Sstever@eecs.umich.edu 1122764Sstever@eecs.umich.edu /** Inserts an instruction. */ 1132764Sstever@eecs.umich.edu void insert(DynInstPtr &inst); 1142764Sstever@eecs.umich.edu /** Inserts a load instruction. */ 1152764Sstever@eecs.umich.edu void insertLoad(DynInstPtr &load_inst); 1162764Sstever@eecs.umich.edu /** Inserts a store instruction. */ 1172764Sstever@eecs.umich.edu void insertStore(DynInstPtr &store_inst); 1182764Sstever@eecs.umich.edu 1192764Sstever@eecs.umich.edu /** Executes a load instruction. */ 1202764Sstever@eecs.umich.edu Fault executeLoad(DynInstPtr &inst); 1212764Sstever@eecs.umich.edu 1222764Sstever@eecs.umich.edu Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; } 1232036SN/A /** Executes a store instruction. */ 1242036SN/A Fault executeStore(DynInstPtr &inst); 1252036SN/A 1262036SN/A /** Commits the head load. */ 1272036SN/A void commitLoad(); 1282036SN/A /** Commits loads older than a specific sequence number. */ 1292036SN/A void commitLoads(InstSeqNum &youngest_inst); 1302036SN/A 1312036SN/A /** Commits stores older than a specific sequence number. */ 1322036SN/A void commitStores(InstSeqNum &youngest_inst); 1332036SN/A 1342036SN/A /** Writes back stores. */ 1352036SN/A void writebackStores(); 1362036SN/A 1372036SN/A /** Completes the data access that has been returned from the 1382036SN/A * memory system. */ 1392036SN/A void completeDataAccess(PacketPtr pkt); 1402036SN/A 1412036SN/A /** Clears all the entries in the LQ. */ 1422036SN/A void clearLQ(); 1432036SN/A 1442036SN/A /** Clears all the entries in the SQ. */ 1452036SN/A void clearSQ(); 1462036SN/A 1472036SN/A /** Resizes the LQ to a given size. */ 1482036SN/A void resizeLQ(unsigned size); 1492036SN/A 1502036SN/A /** Resizes the SQ to a given size. */ 1512036SN/A void resizeSQ(unsigned size); 1522036SN/A 1532036SN/A /** Squashes all instructions younger than a specific sequence number. */ 1542036SN/A void squash(const InstSeqNum &squashed_num); 1552036SN/A 1562036SN/A /** Returns if there is a memory ordering violation. Value is reset upon 1572036SN/A * call to getMemDepViolator(). 1582036SN/A */ 1592036SN/A bool violation() { return memDepViolator; } 1602036SN/A 1612036SN/A /** Returns the memory ordering violator. */ 1622036SN/A DynInstPtr getMemDepViolator(); 1632036SN/A 1642036SN/A /** Returns if a load became blocked due to the memory system. */ 1652036SN/A bool loadBlocked() 1662036SN/A { return isLoadBlocked; } 1672036SN/A 1682036SN/A /** Clears the signal that a load became blocked. */ 1692036SN/A void clearLoadBlocked() 1702036SN/A { isLoadBlocked = false; } 1712036SN/A 1722036SN/A /** Returns if the blocked load was handled. */ 1732036SN/A bool isLoadBlockedHandled() 1742036SN/A { return loadBlockedHandled; } 1752036SN/A 1762036SN/A /** Records the blocked load as being handled. */ 177 void setLoadBlockedHandled() 178 { loadBlockedHandled = true; } 179 180 /** Returns the number of free entries (min of free LQ and SQ entries). */ 181 unsigned numFreeEntries(); 182 183 /** Returns the number of loads ready to execute. */ 184 int numLoadsReady(); 185 186 /** Returns the number of loads in the LQ. */ 187 int numLoads() { return loads; } 188 189 /** Returns the number of stores in the SQ. */ 190 int numStores() { return stores; } 191 192 /** Returns if either the LQ or SQ is full. */ 193 bool isFull() { return lqFull() || sqFull(); } 194 195 /** Returns if the LQ is full. */ 196 bool lqFull() { return loads >= (LQEntries - 1); } 197 198 /** Returns if the SQ is full. */ 199 bool sqFull() { return stores >= (SQEntries - 1); } 200 201 /** Returns the number of instructions in the LSQ. */ 202 unsigned getCount() { return loads + stores; } 203 204 /** Returns if there are any stores to writeback. */ 205 bool hasStoresToWB() { return storesToWB; } 206 207 /** Returns the number of stores to writeback. */ 208 int numStoresToWB() { return storesToWB; } 209 210 /** Returns if the LSQ unit will writeback on this cycle. */ 211 bool willWB() { return storeQueue[storeWBIdx].canWB && 212 !storeQueue[storeWBIdx].completed && 213 !isStoreBlocked; } 214 215 /** Handles doing the retry. */ 216 void recvRetry(); 217 218 private: 219 /** Writes back the instruction, sending it to IEW. */ 220 void writeback(DynInstPtr &inst, PacketPtr pkt); 221 222 /** Handles completing the send of a store to memory. */ 223 void storePostSend(PacketPtr pkt); 224 225 /** Completes the store at the specified index. */ 226 void completeStore(int store_idx); 227 228 /** Increments the given store index (circular queue). */ 229 inline void incrStIdx(int &store_idx); 230 /** Decrements the given store index (circular queue). */ 231 inline void decrStIdx(int &store_idx); 232 /** Increments the given load index (circular queue). */ 233 inline void incrLdIdx(int &load_idx); 234 /** Decrements the given load index (circular queue). */ 235 inline void decrLdIdx(int &load_idx); 236 237 public: 238 /** Debugging function to dump instructions in the LSQ. */ 239 void dumpInsts(); 240 241 private: 242 /** Pointer to the CPU. */ 243 O3CPU *cpu; 244 245 /** Pointer to the IEW stage. */ 246 IEW *iewStage; 247 248 /** Pointer to the LSQ. */ 249 LSQ *lsq; 250 251 /** Pointer to the dcache port. Used only for sending. */ 252 Port *dcachePort; 253 254 /** Derived class to hold any sender state the LSQ needs. */ 255 class LSQSenderState : public Packet::SenderState 256 { 257 public: 258 /** Default constructor. */ 259 LSQSenderState() 260 : noWB(false) 261 { } 262 263 /** Instruction who initiated the access to memory. */ 264 DynInstPtr inst; 265 /** Whether or not it is a load. */ 266 bool isLoad; 267 /** The LQ/SQ index of the instruction. */ 268 int idx; 269 /** Whether or not the instruction will need to writeback. */ 270 bool noWB; 271 }; 272 273 /** Writeback event, specifically for when stores forward data to loads. */ 274 class WritebackEvent : public Event { 275 public: 276 /** Constructs a writeback event. */ 277 WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr); 278 279 /** Processes the writeback event. */ 280 void process(); 281 282 /** Returns the description of this event. */ 283 const char *description(); 284 285 private: 286 /** Instruction whose results are being written back. */ 287 DynInstPtr inst; 288 289 /** The packet that would have been sent to memory. */ 290 PacketPtr pkt; 291 292 /** The pointer to the LSQ unit that issued the store. */ 293 LSQUnit<Impl> *lsqPtr; 294 }; 295 296 public: 297 struct SQEntry { 298 /** Constructs an empty store queue entry. */ 299 SQEntry() 300 : inst(NULL), req(NULL), size(0), data(0), 301 canWB(0), committed(0), completed(0) 302 { } 303 304 /** Constructs a store queue entry for a given instruction. */ 305 SQEntry(DynInstPtr &_inst) 306 : inst(_inst), req(NULL), size(0), data(0), 307 canWB(0), committed(0), completed(0) 308 { } 309 310 /** The store instruction. */ 311 DynInstPtr inst; 312 /** The request for the store. */ 313 RequestPtr req; 314 /** The size of the store. */ 315 int size; 316 /** The store data. */ 317 IntReg data; 318 /** Whether or not the store can writeback. */ 319 bool canWB; 320 /** Whether or not the store is committed. */ 321 bool committed; 322 /** Whether or not the store is completed. */ 323 bool completed; 324 }; 325 326 private: 327 /** The LSQUnit thread id. */ 328 unsigned lsqID; 329 330 /** The store queue. */ 331 std::vector<SQEntry> storeQueue; 332 333 /** The load queue. */ 334 std::vector<DynInstPtr> loadQueue; 335 336 /** The number of LQ entries, plus a sentinel entry (circular queue). 337 * @todo: Consider having var that records the true number of LQ entries. 338 */ 339 unsigned LQEntries; 340 /** The number of SQ entries, plus a sentinel entry (circular queue). 341 * @todo: Consider having var that records the true number of SQ entries. 342 */ 343 unsigned SQEntries; 344 345 /** The number of load instructions in the LQ. */ 346 int loads; 347 /** The number of store instructions in the SQ. */ 348 int stores; 349 /** The number of store instructions in the SQ waiting to writeback. */ 350 int storesToWB; 351 352 /** The index of the head instruction in the LQ. */ 353 int loadHead; 354 /** The index of the tail instruction in the LQ. */ 355 int loadTail; 356 357 /** The index of the head instruction in the SQ. */ 358 int storeHead; 359 /** The index of the first instruction that may be ready to be 360 * written back, and has not yet been written back. 361 */ 362 int storeWBIdx; 363 /** The index of the tail instruction in the SQ. */ 364 int storeTail; 365 366 /// @todo Consider moving to a more advanced model with write vs read ports 367 /** The number of cache ports available each cycle. */ 368 int cachePorts; 369 370 /** The number of used cache ports in this cycle. */ 371 int usedPorts; 372 373 /** Is the LSQ switched out. */ 374 bool switchedOut; 375 376 //list<InstSeqNum> mshrSeqNums; 377 378 /** Wire to read information from the issue stage time queue. */ 379 typename TimeBuffer<IssueStruct>::wire fromIssue; 380 381 /** Whether or not the LSQ is stalled. */ 382 bool stalled; 383 /** The store that causes the stall due to partial store to load 384 * forwarding. 385 */ 386 InstSeqNum stallingStoreIsn; 387 /** The index of the above store. */ 388 int stallingLoadIdx; 389 390 /** The packet that needs to be retried. */ 391 PacketPtr retryPkt; 392 393 /** Whehter or not a store is blocked due to the memory system. */ 394 bool isStoreBlocked; 395 396 /** Whether or not a load is blocked due to the memory system. */ 397 bool isLoadBlocked; 398 399 /** Has the blocked load been handled. */ 400 bool loadBlockedHandled; 401 402 /** The sequence number of the blocked load. */ 403 InstSeqNum blockedLoadSeqNum; 404 405 /** The oldest load that caused a memory ordering violation. */ 406 DynInstPtr memDepViolator; 407 408 // Will also need how many read/write ports the Dcache has. Or keep track 409 // of that in stage that is one level up, and only call executeLoad/Store 410 // the appropriate number of times. 411 /** Total number of loads forwaded from LSQ stores. */ 412 Stats::Scalar<> lsqForwLoads; 413 414 /** Total number of loads ignored due to invalid addresses. */ 415 Stats::Scalar<> invAddrLoads; 416 417 /** Total number of squashed loads. */ 418 Stats::Scalar<> lsqSquashedLoads; 419 420 /** Total number of responses from the memory system that are 421 * ignored due to the instruction already being squashed. */ 422 Stats::Scalar<> lsqIgnoredResponses; 423 424 /** Tota number of memory ordering violations. */ 425 Stats::Scalar<> lsqMemOrderViolation; 426 427 /** Total number of squashed stores. */ 428 Stats::Scalar<> lsqSquashedStores; 429 430 /** Total number of software prefetches ignored due to invalid addresses. */ 431 Stats::Scalar<> invAddrSwpfs; 432 433 /** Ready loads blocked due to partial store-forwarding. */ 434 Stats::Scalar<> lsqBlockedLoads; 435 436 /** Number of loads that were rescheduled. */ 437 Stats::Scalar<> lsqRescheduledLoads; 438 439 /** Number of times the LSQ is blocked due to the cache. */ 440 Stats::Scalar<> lsqCacheBlocked; 441 442 public: 443 /** Executes the load at the given index. */ 444 template <class T> 445 Fault read(Request *req, T &data, int load_idx); 446 447 /** Executes the store at the given index. */ 448 template <class T> 449 Fault write(Request *req, T &data, int store_idx); 450 451 /** Returns the index of the head load instruction. */ 452 int getLoadHead() { return loadHead; } 453 /** Returns the sequence number of the head load instruction. */ 454 InstSeqNum getLoadHeadSeqNum() 455 { 456 if (loadQueue[loadHead]) { 457 return loadQueue[loadHead]->seqNum; 458 } else { 459 return 0; 460 } 461 462 } 463 464 /** Returns the index of the head store instruction. */ 465 int getStoreHead() { return storeHead; } 466 /** Returns the sequence number of the head store instruction. */ 467 InstSeqNum getStoreHeadSeqNum() 468 { 469 if (storeQueue[storeHead].inst) { 470 return storeQueue[storeHead].inst->seqNum; 471 } else { 472 return 0; 473 } 474 475 } 476 477 /** Returns whether or not the LSQ unit is stalled. */ 478 bool isStalled() { return stalled; } 479}; 480 481template <class Impl> 482template <class T> 483Fault 484LSQUnit<Impl>::read(Request *req, T &data, int load_idx) 485{ 486 DynInstPtr load_inst = loadQueue[load_idx]; 487 488 assert(load_inst); 489 490 assert(!load_inst->isExecuted()); 491 492 // Make sure this isn't an uncacheable access 493 // A bit of a hackish way to get uncached accesses to work only if they're 494 // at the head of the LSQ and are ready to commit (at the head of the ROB 495 // too). 496 if (req->isUncacheable() && 497 (load_idx != loadHead || !load_inst->isAtCommit())) { 498 iewStage->rescheduleMemInst(load_inst); 499 ++lsqRescheduledLoads; 500 return TheISA::genMachineCheckFault(); 501 } 502 503 // Check the SQ for any previous stores that might lead to forwarding 504 int store_idx = load_inst->sqIdx; 505 506 int store_size = 0; 507 508 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, " 509 "storeHead: %i addr: %#x\n", 510 load_idx, store_idx, storeHead, req->getPaddr()); 511 512#if FULL_SYSTEM 513 if (req->isLocked()) { 514 // Disable recording the result temporarily. Writing to misc 515 // regs normally updates the result, but this is not the 516 // desired behavior when handling store conditionals. 517 load_inst->recordResult = false; 518 TheISA::handleLockedRead(load_inst.get(), req); 519 load_inst->recordResult = true; 520 } 521#endif 522 523 while (store_idx != -1) { 524 // End once we've reached the top of the LSQ 525 if (store_idx == storeWBIdx) { 526 break; 527 } 528 529 // Move the index to one younger 530 if (--store_idx < 0) 531 store_idx += SQEntries; 532 533 assert(storeQueue[store_idx].inst); 534 535 store_size = storeQueue[store_idx].size; 536 537 if (store_size == 0) 538 continue; 539 540 // Check if the store data is within the lower and upper bounds of 541 // addresses that the request needs. 542 bool store_has_lower_limit = 543 req->getVaddr() >= storeQueue[store_idx].inst->effAddr; 544 bool store_has_upper_limit = 545 (req->getVaddr() + req->getSize()) <= 546 (storeQueue[store_idx].inst->effAddr + store_size); 547 bool lower_load_has_store_part = 548 req->getVaddr() < (storeQueue[store_idx].inst->effAddr + 549 store_size); 550 bool upper_load_has_store_part = 551 (req->getVaddr() + req->getSize()) > 552 storeQueue[store_idx].inst->effAddr; 553 554 // If the store's data has all of the data needed, we can forward. 555 if (store_has_lower_limit && store_has_upper_limit) { 556 // Get shift amount for offset into the store's data. 557 int shift_amt = req->getVaddr() & (store_size - 1); 558 // @todo: Magic number, assumes byte addressing 559 shift_amt = shift_amt << 3; 560 561 // Cast this to type T? 562 data = storeQueue[store_idx].data >> shift_amt; 563 564 // When the data comes from the store queue entry, it's in host 565 // order. When it gets sent to the load, it needs to be in guest 566 // order so when the load converts it again, it ends up back 567 // in host order like the inst expects. 568 data = TheISA::htog(data); 569 570 assert(!load_inst->memData); 571 load_inst->memData = new uint8_t[64]; 572 573 memcpy(load_inst->memData, &data, req->getSize()); 574 575 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to " 576 "addr %#x, data %#x\n", 577 store_idx, req->getVaddr(), data); 578 579 PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast); 580 data_pkt->dataStatic(load_inst->memData); 581 582 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this); 583 584 // We'll say this has a 1 cycle load-store forwarding latency 585 // for now. 586 // @todo: Need to make this a parameter. 587 wb->schedule(curTick); 588 589 ++lsqForwLoads; 590 return NoFault; 591 } else if ((store_has_lower_limit && lower_load_has_store_part) || 592 (store_has_upper_limit && upper_load_has_store_part) || 593 (lower_load_has_store_part && upper_load_has_store_part)) { 594 // This is the partial store-load forwarding case where a store 595 // has only part of the load's data. 596 597 // If it's already been written back, then don't worry about 598 // stalling on it. 599 if (storeQueue[store_idx].completed) { 600 continue; 601 } 602 603 // Must stall load and force it to retry, so long as it's the oldest 604 // load that needs to do so. 605 if (!stalled || 606 (stalled && 607 load_inst->seqNum < 608 loadQueue[stallingLoadIdx]->seqNum)) { 609 stalled = true; 610 stallingStoreIsn = storeQueue[store_idx].inst->seqNum; 611 stallingLoadIdx = load_idx; 612 } 613 614 // Tell IQ/mem dep unit that this instruction will need to be 615 // rescheduled eventually 616 iewStage->rescheduleMemInst(load_inst); 617 iewStage->decrWb(load_inst->seqNum); 618 ++lsqRescheduledLoads; 619 620 // Do not generate a writeback event as this instruction is not 621 // complete. 622 DPRINTF(LSQUnit, "Load-store forwarding mis-match. " 623 "Store idx %i to load addr %#x\n", 624 store_idx, req->getVaddr()); 625 626 ++lsqBlockedLoads; 627 return NoFault; 628 } 629 } 630 631 // If there's no forwarding case, then go access memory 632 DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %#x\n", 633 load_inst->seqNum, load_inst->readPC()); 634 635 assert(!load_inst->memData); 636 load_inst->memData = new uint8_t[64]; 637 638 ++usedPorts; 639 640 // if we the cache is not blocked, do cache access 641 if (!lsq->cacheBlocked()) { 642 PacketPtr data_pkt = 643 new Packet(req, Packet::ReadReq, Packet::Broadcast); 644 data_pkt->dataStatic(load_inst->memData); 645 646 LSQSenderState *state = new LSQSenderState; 647 state->isLoad = true; 648 state->idx = load_idx; 649 state->inst = load_inst; 650 data_pkt->senderState = state; 651 652 if (!dcachePort->sendTiming(data_pkt)) { 653 Packet::Result result = data_pkt->result; 654 655 // Delete state and data packet because a load retry 656 // initiates a pipeline restart; it does not retry. 657 delete state; 658 delete data_pkt; 659 660 if (result == Packet::BadAddress) { 661 return TheISA::genMachineCheckFault(); 662 } 663 664 // If the access didn't succeed, tell the LSQ by setting 665 // the retry thread id. 666 lsq->setRetryTid(lsqID); 667 } 668 } 669 670 // If the cache was blocked, or has become blocked due to the access, 671 // handle it. 672 if (lsq->cacheBlocked()) { 673 ++lsqCacheBlocked; 674 675 iewStage->decrWb(load_inst->seqNum); 676 // There's an older load that's already going to squash. 677 if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum) 678 return NoFault; 679 680 // Record that the load was blocked due to memory. This 681 // load will squash all instructions after it, be 682 // refetched, and re-executed. 683 isLoadBlocked = true; 684 loadBlockedHandled = false; 685 blockedLoadSeqNum = load_inst->seqNum; 686 // No fault occurred, even though the interface is blocked. 687 return NoFault; 688 } 689 690 return NoFault; 691} 692 693template <class Impl> 694template <class T> 695Fault 696LSQUnit<Impl>::write(Request *req, T &data, int store_idx) 697{ 698 assert(storeQueue[store_idx].inst); 699 700 DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x data %#x" 701 " | storeHead:%i [sn:%i]\n", 702 store_idx, req->getPaddr(), data, storeHead, 703 storeQueue[store_idx].inst->seqNum); 704 705 storeQueue[store_idx].req = req; 706 storeQueue[store_idx].size = sizeof(T); 707 storeQueue[store_idx].data = data; 708 709 // This function only writes the data to the store queue, so no fault 710 // can happen here. 711 return NoFault; 712} 713 714#endif // __CPU_O3_LSQ_UNIT_HH__ 715