lsq_unit.hh revision 2871:7ed5c9ef3eb6
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#ifndef __CPU_O3_LSQ_UNIT_HH__ 33#define __CPU_O3_LSQ_UNIT_HH__ 34 35#include <algorithm> 36#include <map> 37#include <queue> 38 39#include "arch/faults.hh" 40#include "config/full_system.hh" 41#include "base/hashmap.hh" 42#include "cpu/inst_seq.hh" 43#include "mem/packet_impl.hh" 44#include "mem/port.hh" 45 46/** 47 * Class that implements the actual LQ and SQ for each specific 48 * thread. Both are circular queues; load entries are freed upon 49 * committing, while store entries are freed once they writeback. The 50 * LSQUnit tracks if there are memory ordering violations, and also 51 * detects partial load to store forwarding cases (a store only has 52 * part of a load's data) that requires the load to wait until the 53 * store writes back. In the former case it holds onto the instruction 54 * until the dependence unit looks at it, and in the latter it stalls 55 * the LSQ until the store writes back. At that point the load is 56 * replayed. 57 */ 58template <class Impl> 59class LSQUnit { 60 protected: 61 typedef TheISA::IntReg IntReg; 62 public: 63 typedef typename Impl::Params Params; 64 typedef typename Impl::O3CPU O3CPU; 65 typedef typename Impl::DynInstPtr DynInstPtr; 66 typedef typename Impl::CPUPol::IEW IEW; 67 typedef typename Impl::CPUPol::IssueStruct IssueStruct; 68 69 public: 70 /** Constructs an LSQ unit. init() must be called prior to use. */ 71 LSQUnit(); 72 73 /** Initializes the LSQ unit with the specified number of entries. */ 74 void init(Params *params, unsigned maxLQEntries, 75 unsigned maxSQEntries, unsigned id); 76 77 /** Returns the name of the LSQ unit. */ 78 std::string name() const; 79 80 /** Returns the dcache port. 81 * @todo: Remove this once the port moves up to the LSQ level. 82 */ 83 Port *getDcachePort() { return dcachePort; } 84 85 /** Registers statistics. */ 86 void regStats(); 87 88 /** Sets the CPU pointer. */ 89 void setCPU(O3CPU *cpu_ptr); 90 91 /** Sets the IEW stage pointer. */ 92 void setIEW(IEW *iew_ptr) 93 { iewStage = iew_ptr; } 94 95 /** Switches out LSQ unit. */ 96 void switchOut(); 97 98 /** Takes over from another CPU's thread. */ 99 void takeOverFrom(); 100 101 /** Returns if the LSQ is switched out. */ 102 bool isSwitchedOut() { return switchedOut; } 103 104 /** Ticks the LSQ unit, which in this case only resets the number of 105 * used cache ports. 106 * @todo: Move the number of used ports up to the LSQ level so it can 107 * be shared by all LSQ units. 108 */ 109 void tick() { usedPorts = 0; } 110 111 /** Inserts an instruction. */ 112 void insert(DynInstPtr &inst); 113 /** Inserts a load instruction. */ 114 void insertLoad(DynInstPtr &load_inst); 115 /** Inserts a store instruction. */ 116 void insertStore(DynInstPtr &store_inst); 117 118 /** Executes a load instruction. */ 119 Fault executeLoad(DynInstPtr &inst); 120 121 Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; } 122 /** Executes a store instruction. */ 123 Fault executeStore(DynInstPtr &inst); 124 125 /** Commits the head load. */ 126 void commitLoad(); 127 /** Commits loads older than a specific sequence number. */ 128 void commitLoads(InstSeqNum &youngest_inst); 129 130 /** Commits stores older than a specific sequence number. */ 131 void commitStores(InstSeqNum &youngest_inst); 132 133 /** Writes back stores. */ 134 void writebackStores(); 135 136 /** Completes the data access that has been returned from the 137 * memory system. */ 138 void completeDataAccess(PacketPtr pkt); 139 140 /** Clears all the entries in the LQ. */ 141 void clearLQ(); 142 143 /** Clears all the entries in the SQ. */ 144 void clearSQ(); 145 146 /** Resizes the LQ to a given size. */ 147 void resizeLQ(unsigned size); 148 149 /** Resizes the SQ to a given size. */ 150 void resizeSQ(unsigned size); 151 152 /** Squashes all instructions younger than a specific sequence number. */ 153 void squash(const InstSeqNum &squashed_num); 154 155 /** Returns if there is a memory ordering violation. Value is reset upon 156 * call to getMemDepViolator(). 157 */ 158 bool violation() { return memDepViolator; } 159 160 /** Returns the memory ordering violator. */ 161 DynInstPtr getMemDepViolator(); 162 163 /** Returns if a load became blocked due to the memory system. */ 164 bool loadBlocked() 165 { return isLoadBlocked; } 166 167 /** Clears the signal that a load became blocked. */ 168 void clearLoadBlocked() 169 { isLoadBlocked = false; } 170 171 /** Returns if the blocked load was handled. */ 172 bool isLoadBlockedHandled() 173 { return loadBlockedHandled; } 174 175 /** Records the blocked load as being handled. */ 176 void setLoadBlockedHandled() 177 { loadBlockedHandled = true; } 178 179 /** Returns the number of free entries (min of free LQ and SQ entries). */ 180 unsigned numFreeEntries(); 181 182 /** Returns the number of loads ready to execute. */ 183 int numLoadsReady(); 184 185 /** Returns the number of loads in the LQ. */ 186 int numLoads() { return loads; } 187 188 /** Returns the number of stores in the SQ. */ 189 int numStores() { return stores; } 190 191 /** Returns if either the LQ or SQ is full. */ 192 bool isFull() { return lqFull() || sqFull(); } 193 194 /** Returns if the LQ is full. */ 195 bool lqFull() { return loads >= (LQEntries - 1); } 196 197 /** Returns if the SQ is full. */ 198 bool sqFull() { return stores >= (SQEntries - 1); } 199 200 /** Returns the number of instructions in the LSQ. */ 201 unsigned getCount() { return loads + stores; } 202 203 /** Returns if there are any stores to writeback. */ 204 bool hasStoresToWB() { return storesToWB; } 205 206 /** Returns the number of stores to writeback. */ 207 int numStoresToWB() { return storesToWB; } 208 209 /** Returns if the LSQ unit will writeback on this cycle. */ 210 bool willWB() { return storeQueue[storeWBIdx].canWB && 211 !storeQueue[storeWBIdx].completed && 212 !isStoreBlocked; } 213 214 private: 215 /** Writes back the instruction, sending it to IEW. */ 216 void writeback(DynInstPtr &inst, PacketPtr pkt); 217 218 /** Handles completing the send of a store to memory. */ 219 void storePostSend(Packet *pkt); 220 221 /** Completes the store at the specified index. */ 222 void completeStore(int store_idx); 223 224 /** Handles doing the retry. */ 225 void recvRetry(); 226 227 /** Increments the given store index (circular queue). */ 228 inline void incrStIdx(int &store_idx); 229 /** Decrements the given store index (circular queue). */ 230 inline void decrStIdx(int &store_idx); 231 /** Increments the given load index (circular queue). */ 232 inline void incrLdIdx(int &load_idx); 233 /** Decrements the given load index (circular queue). */ 234 inline void decrLdIdx(int &load_idx); 235 236 public: 237 /** Debugging function to dump instructions in the LSQ. */ 238 void dumpInsts(); 239 240 private: 241 /** Pointer to the CPU. */ 242 O3CPU *cpu; 243 244 /** Pointer to the IEW stage. */ 245 IEW *iewStage; 246 247 /** Pointer to memory object. */ 248 MemObject *mem; 249 250 /** DcachePort class for this LSQ Unit. Handles doing the 251 * communication with the cache/memory. 252 * @todo: Needs to be moved to the LSQ level and have some sort 253 * of arbitration. 254 */ 255 class DcachePort : public Port 256 { 257 protected: 258 /** Pointer to CPU. */ 259 O3CPU *cpu; 260 /** Pointer to LSQ. */ 261 LSQUnit *lsq; 262 263 public: 264 /** Default constructor. */ 265 DcachePort(O3CPU *_cpu, LSQUnit *_lsq) 266 : Port(_lsq->name() + "-dport"), cpu(_cpu), lsq(_lsq) 267 { } 268 269 protected: 270 /** Atomic version of receive. Panics. */ 271 virtual Tick recvAtomic(PacketPtr pkt); 272 273 /** Functional version of receive. Panics. */ 274 virtual void recvFunctional(PacketPtr pkt); 275 276 /** Receives status change. Other than range changing, panics. */ 277 virtual void recvStatusChange(Status status); 278 279 /** Returns the address ranges of this device. */ 280 virtual void getDeviceAddressRanges(AddrRangeList &resp, 281 AddrRangeList &snoop) 282 { resp.clear(); snoop.clear(); } 283 284 /** Timing version of receive. Handles writing back and 285 * completing the load or store that has returned from 286 * memory. */ 287 virtual bool recvTiming(PacketPtr pkt); 288 289 /** Handles doing a retry of the previous send. */ 290 virtual void recvRetry(); 291 }; 292 293 /** Pointer to the D-cache. */ 294 DcachePort *dcachePort; 295 296 /** Derived class to hold any sender state the LSQ needs. */ 297 class LSQSenderState : public Packet::SenderState 298 { 299 public: 300 /** Default constructor. */ 301 LSQSenderState() 302 : noWB(false) 303 { } 304 305 /** Instruction who initiated the access to memory. */ 306 DynInstPtr inst; 307 /** Whether or not it is a load. */ 308 bool isLoad; 309 /** The LQ/SQ index of the instruction. */ 310 int idx; 311 /** Whether or not the instruction will need to writeback. */ 312 bool noWB; 313 }; 314 315 /** Writeback event, specifically for when stores forward data to loads. */ 316 class WritebackEvent : public Event { 317 public: 318 /** Constructs a writeback event. */ 319 WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr); 320 321 /** Processes the writeback event. */ 322 void process(); 323 324 /** Returns the description of this event. */ 325 const char *description(); 326 327 private: 328 /** Instruction whose results are being written back. */ 329 DynInstPtr inst; 330 331 /** The packet that would have been sent to memory. */ 332 PacketPtr pkt; 333 334 /** The pointer to the LSQ unit that issued the store. */ 335 LSQUnit<Impl> *lsqPtr; 336 }; 337 338 public: 339 struct SQEntry { 340 /** Constructs an empty store queue entry. */ 341 SQEntry() 342 : inst(NULL), req(NULL), size(0), data(0), 343 canWB(0), committed(0), completed(0) 344 { } 345 346 /** Constructs a store queue entry for a given instruction. */ 347 SQEntry(DynInstPtr &_inst) 348 : inst(_inst), req(NULL), size(0), data(0), 349 canWB(0), committed(0), completed(0) 350 { } 351 352 /** The store instruction. */ 353 DynInstPtr inst; 354 /** The request for the store. */ 355 RequestPtr req; 356 /** The size of the store. */ 357 int size; 358 /** The store data. */ 359 IntReg data; 360 /** Whether or not the store can writeback. */ 361 bool canWB; 362 /** Whether or not the store is committed. */ 363 bool committed; 364 /** Whether or not the store is completed. */ 365 bool completed; 366 }; 367 368 private: 369 /** The LSQUnit thread id. */ 370 unsigned lsqID; 371 372 /** The store queue. */ 373 std::vector<SQEntry> storeQueue; 374 375 /** The load queue. */ 376 std::vector<DynInstPtr> loadQueue; 377 378 /** The number of LQ entries, plus a sentinel entry (circular queue). 379 * @todo: Consider having var that records the true number of LQ entries. 380 */ 381 unsigned LQEntries; 382 /** The number of SQ entries, plus a sentinel entry (circular queue). 383 * @todo: Consider having var that records the true number of SQ entries. 384 */ 385 unsigned SQEntries; 386 387 /** The number of load instructions in the LQ. */ 388 int loads; 389 /** The number of store instructions in the SQ. */ 390 int stores; 391 /** The number of store instructions in the SQ waiting to writeback. */ 392 int storesToWB; 393 394 /** The index of the head instruction in the LQ. */ 395 int loadHead; 396 /** The index of the tail instruction in the LQ. */ 397 int loadTail; 398 399 /** The index of the head instruction in the SQ. */ 400 int storeHead; 401 /** The index of the first instruction that may be ready to be 402 * written back, and has not yet been written back. 403 */ 404 int storeWBIdx; 405 /** The index of the tail instruction in the SQ. */ 406 int storeTail; 407 408 /// @todo Consider moving to a more advanced model with write vs read ports 409 /** The number of cache ports available each cycle. */ 410 int cachePorts; 411 412 /** The number of used cache ports in this cycle. */ 413 int usedPorts; 414 415 /** Is the LSQ switched out. */ 416 bool switchedOut; 417 418 //list<InstSeqNum> mshrSeqNums; 419 420 /** Wire to read information from the issue stage time queue. */ 421 typename TimeBuffer<IssueStruct>::wire fromIssue; 422 423 /** Whether or not the LSQ is stalled. */ 424 bool stalled; 425 /** The store that causes the stall due to partial store to load 426 * forwarding. 427 */ 428 InstSeqNum stallingStoreIsn; 429 /** The index of the above store. */ 430 int stallingLoadIdx; 431 432 /** The packet that needs to be retried. */ 433 PacketPtr retryPkt; 434 435 /** Whehter or not a store is blocked due to the memory system. */ 436 bool isStoreBlocked; 437 438 /** Whether or not a load is blocked due to the memory system. */ 439 bool isLoadBlocked; 440 441 /** Has the blocked load been handled. */ 442 bool loadBlockedHandled; 443 444 /** The sequence number of the blocked load. */ 445 InstSeqNum blockedLoadSeqNum; 446 447 /** The oldest load that caused a memory ordering violation. */ 448 DynInstPtr memDepViolator; 449 450 // Will also need how many read/write ports the Dcache has. Or keep track 451 // of that in stage that is one level up, and only call executeLoad/Store 452 // the appropriate number of times. 453 454 /** Total number of loads forwaded from LSQ stores. */ 455 Stats::Scalar<> lsqForwLoads; 456 457 /** Total number of loads ignored due to invalid addresses. */ 458 Stats::Scalar<> invAddrLoads; 459 460 /** Total number of squashed loads. */ 461 Stats::Scalar<> lsqSquashedLoads; 462 463 /** Total number of responses from the memory system that are 464 * ignored due to the instruction already being squashed. */ 465 Stats::Scalar<> lsqIgnoredResponses; 466 467 /** Total number of squashed stores. */ 468 Stats::Scalar<> lsqSquashedStores; 469 470 /** Total number of software prefetches ignored due to invalid addresses. */ 471 Stats::Scalar<> invAddrSwpfs; 472 473 /** Ready loads blocked due to partial store-forwarding. */ 474 Stats::Scalar<> lsqBlockedLoads; 475 476 /** Number of loads that were rescheduled. */ 477 Stats::Scalar<> lsqRescheduledLoads; 478 479 /** Number of times the LSQ is blocked due to the cache. */ 480 Stats::Scalar<> lsqCacheBlocked; 481 482 public: 483 /** Executes the load at the given index. */ 484 template <class T> 485 Fault read(Request *req, T &data, int load_idx); 486 487 /** Executes the store at the given index. */ 488 template <class T> 489 Fault write(Request *req, T &data, int store_idx); 490 491 /** Returns the index of the head load instruction. */ 492 int getLoadHead() { return loadHead; } 493 /** Returns the sequence number of the head load instruction. */ 494 InstSeqNum getLoadHeadSeqNum() 495 { 496 if (loadQueue[loadHead]) { 497 return loadQueue[loadHead]->seqNum; 498 } else { 499 return 0; 500 } 501 502 } 503 504 /** Returns the index of the head store instruction. */ 505 int getStoreHead() { return storeHead; } 506 /** Returns the sequence number of the head store instruction. */ 507 InstSeqNum getStoreHeadSeqNum() 508 { 509 if (storeQueue[storeHead].inst) { 510 return storeQueue[storeHead].inst->seqNum; 511 } else { 512 return 0; 513 } 514 515 } 516 517 /** Returns whether or not the LSQ unit is stalled. */ 518 bool isStalled() { return stalled; } 519}; 520 521template <class Impl> 522template <class T> 523Fault 524LSQUnit<Impl>::read(Request *req, T &data, int load_idx) 525{ 526 DynInstPtr load_inst = loadQueue[load_idx]; 527 528 assert(load_inst); 529 530 assert(!load_inst->isExecuted()); 531 532 // Make sure this isn't an uncacheable access 533 // A bit of a hackish way to get uncached accesses to work only if they're 534 // at the head of the LSQ and are ready to commit (at the head of the ROB 535 // too). 536 if (req->getFlags() & UNCACHEABLE && 537 (load_idx != loadHead || !load_inst->isAtCommit())) { 538 iewStage->rescheduleMemInst(load_inst); 539 ++lsqRescheduledLoads; 540 return TheISA::genMachineCheckFault(); 541 } 542 543 // Check the SQ for any previous stores that might lead to forwarding 544 int store_idx = load_inst->sqIdx; 545 546 int store_size = 0; 547 548 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, " 549 "storeHead: %i addr: %#x\n", 550 load_idx, store_idx, storeHead, req->getPaddr()); 551 552#if FULL_SYSTEM 553 if (req->getFlags() & LOCKED) { 554 cpu->lockAddr = req->getPaddr(); 555 cpu->lockFlag = true; 556 } 557#endif 558 559 while (store_idx != -1) { 560 // End once we've reached the top of the LSQ 561 if (store_idx == storeWBIdx) { 562 break; 563 } 564 565 // Move the index to one younger 566 if (--store_idx < 0) 567 store_idx += SQEntries; 568 569 assert(storeQueue[store_idx].inst); 570 571 store_size = storeQueue[store_idx].size; 572 573 if (store_size == 0) 574 continue; 575 576 // Check if the store data is within the lower and upper bounds of 577 // addresses that the request needs. 578 bool store_has_lower_limit = 579 req->getVaddr() >= storeQueue[store_idx].inst->effAddr; 580 bool store_has_upper_limit = 581 (req->getVaddr() + req->getSize()) <= 582 (storeQueue[store_idx].inst->effAddr + store_size); 583 bool lower_load_has_store_part = 584 req->getVaddr() < (storeQueue[store_idx].inst->effAddr + 585 store_size); 586 bool upper_load_has_store_part = 587 (req->getVaddr() + req->getSize()) > 588 storeQueue[store_idx].inst->effAddr; 589 590 // If the store's data has all of the data needed, we can forward. 591 if (store_has_lower_limit && store_has_upper_limit) { 592 // Get shift amount for offset into the store's data. 593 int shift_amt = req->getVaddr() & (store_size - 1); 594 // @todo: Magic number, assumes byte addressing 595 shift_amt = shift_amt << 3; 596 597 // Cast this to type T? 598 data = storeQueue[store_idx].data >> shift_amt; 599 600 assert(!load_inst->memData); 601 load_inst->memData = new uint8_t[64]; 602 603 memcpy(load_inst->memData, &data, req->getSize()); 604 605 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to " 606 "addr %#x, data %#x\n", 607 store_idx, req->getVaddr(), data); 608 609 PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast); 610 data_pkt->dataStatic(load_inst->memData); 611 612 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this); 613 614 // We'll say this has a 1 cycle load-store forwarding latency 615 // for now. 616 // @todo: Need to make this a parameter. 617 wb->schedule(curTick); 618 619 ++lsqForwLoads; 620 return NoFault; 621 } else if ((store_has_lower_limit && lower_load_has_store_part) || 622 (store_has_upper_limit && upper_load_has_store_part) || 623 (lower_load_has_store_part && upper_load_has_store_part)) { 624 // This is the partial store-load forwarding case where a store 625 // has only part of the load's data. 626 627 // If it's already been written back, then don't worry about 628 // stalling on it. 629 if (storeQueue[store_idx].completed) { 630 continue; 631 } 632 633 // Must stall load and force it to retry, so long as it's the oldest 634 // load that needs to do so. 635 if (!stalled || 636 (stalled && 637 load_inst->seqNum < 638 loadQueue[stallingLoadIdx]->seqNum)) { 639 stalled = true; 640 stallingStoreIsn = storeQueue[store_idx].inst->seqNum; 641 stallingLoadIdx = load_idx; 642 } 643 644 // Tell IQ/mem dep unit that this instruction will need to be 645 // rescheduled eventually 646 iewStage->rescheduleMemInst(load_inst); 647 ++lsqRescheduledLoads; 648 649 // Do not generate a writeback event as this instruction is not 650 // complete. 651 DPRINTF(LSQUnit, "Load-store forwarding mis-match. " 652 "Store idx %i to load addr %#x\n", 653 store_idx, req->getVaddr()); 654 655 ++lsqBlockedLoads; 656 return NoFault; 657 } 658 } 659 660 // If there's no forwarding case, then go access memory 661 DPRINTF(LSQUnit, "Doing functional access for inst [sn:%lli] PC %#x\n", 662 load_inst->seqNum, load_inst->readPC()); 663 664 assert(!load_inst->memData); 665 load_inst->memData = new uint8_t[64]; 666 667 ++usedPorts; 668 669 DPRINTF(LSQUnit, "Doing timing access for inst PC %#x\n", 670 load_inst->readPC()); 671 672 PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast); 673 data_pkt->dataStatic(load_inst->memData); 674 675 LSQSenderState *state = new LSQSenderState; 676 state->isLoad = true; 677 state->idx = load_idx; 678 state->inst = load_inst; 679 data_pkt->senderState = state; 680 681 // if we have a cache, do cache access too 682 if (!dcachePort->sendTiming(data_pkt)) { 683 ++lsqCacheBlocked; 684 // There's an older load that's already going to squash. 685 if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum) 686 return NoFault; 687 688 // Record that the load was blocked due to memory. This 689 // load will squash all instructions after it, be 690 // refetched, and re-executed. 691 isLoadBlocked = true; 692 loadBlockedHandled = false; 693 blockedLoadSeqNum = load_inst->seqNum; 694 // No fault occurred, even though the interface is blocked. 695 return NoFault; 696 } 697 698 if (data_pkt->result != Packet::Success) { 699 DPRINTF(LSQUnit, "LSQUnit: D-cache miss!\n"); 700 DPRINTF(Activity, "Activity: ld accessing mem miss [sn:%lli]\n", 701 load_inst->seqNum); 702 } else { 703 DPRINTF(LSQUnit, "LSQUnit: D-cache hit!\n"); 704 DPRINTF(Activity, "Activity: ld accessing mem hit [sn:%lli]\n", 705 load_inst->seqNum); 706 } 707 708 return NoFault; 709} 710 711template <class Impl> 712template <class T> 713Fault 714LSQUnit<Impl>::write(Request *req, T &data, int store_idx) 715{ 716 assert(storeQueue[store_idx].inst); 717 718 DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x data %#x" 719 " | storeHead:%i [sn:%i]\n", 720 store_idx, req->getPaddr(), data, storeHead, 721 storeQueue[store_idx].inst->seqNum); 722 723 storeQueue[store_idx].req = req; 724 storeQueue[store_idx].size = sizeof(T); 725 storeQueue[store_idx].data = data; 726 727 // This function only writes the data to the store queue, so no fault 728 // can happen here. 729 return NoFault; 730} 731 732#endif // __CPU_O3_LSQ_UNIT_HH__ 733