lsq_unit.hh revision 10342
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * Copyright (c) 2013 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Korey Sewell
43 */
44
45#ifndef __CPU_O3_LSQ_UNIT_HH__
46#define __CPU_O3_LSQ_UNIT_HH__
47
48#include <algorithm>
49#include <cstring>
50#include <map>
51#include <queue>
52
53#include "arch/generic/debugfaults.hh"
54#include "arch/isa_traits.hh"
55#include "arch/locked_mem.hh"
56#include "arch/mmapped_ipr.hh"
57#include "base/hashmap.hh"
58#include "config/the_isa.hh"
59#include "cpu/inst_seq.hh"
60#include "cpu/timebuf.hh"
61#include "debug/LSQUnit.hh"
62#include "mem/packet.hh"
63#include "mem/port.hh"
64#include "sim/fault_fwd.hh"
65
66struct DerivO3CPUParams;
67
68/**
69 * Class that implements the actual LQ and SQ for each specific
70 * thread.  Both are circular queues; load entries are freed upon
71 * committing, while store entries are freed once they writeback. The
72 * LSQUnit tracks if there are memory ordering violations, and also
73 * detects partial load to store forwarding cases (a store only has
74 * part of a load's data) that requires the load to wait until the
75 * store writes back. In the former case it holds onto the instruction
76 * until the dependence unit looks at it, and in the latter it stalls
77 * the LSQ until the store writes back. At that point the load is
78 * replayed.
79 */
80template <class Impl>
81class LSQUnit {
82  public:
83    typedef typename Impl::O3CPU O3CPU;
84    typedef typename Impl::DynInstPtr DynInstPtr;
85    typedef typename Impl::CPUPol::IEW IEW;
86    typedef typename Impl::CPUPol::LSQ LSQ;
87    typedef typename Impl::CPUPol::IssueStruct IssueStruct;
88
89  public:
90    /** Constructs an LSQ unit. init() must be called prior to use. */
91    LSQUnit();
92
93    /** Initializes the LSQ unit with the specified number of entries. */
94    void init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
95            LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries,
96            unsigned id);
97
98    /** Returns the name of the LSQ unit. */
99    std::string name() const;
100
101    /** Registers statistics. */
102    void regStats();
103
104    /** Sets the pointer to the dcache port. */
105    void setDcachePort(MasterPort *dcache_port);
106
107    /** Perform sanity checks after a drain. */
108    void drainSanityCheck() const;
109
110    /** Takes over from another CPU's thread. */
111    void takeOverFrom();
112
113    /** Ticks the LSQ unit, which in this case only resets the number of
114     * used cache ports.
115     * @todo: Move the number of used ports up to the LSQ level so it can
116     * be shared by all LSQ units.
117     */
118    void tick() { usedPorts = 0; }
119
120    /** Inserts an instruction. */
121    void insert(DynInstPtr &inst);
122    /** Inserts a load instruction. */
123    void insertLoad(DynInstPtr &load_inst);
124    /** Inserts a store instruction. */
125    void insertStore(DynInstPtr &store_inst);
126
127    /** Check for ordering violations in the LSQ. For a store squash if we
128     * ever find a conflicting load. For a load, only squash if we
129     * an external snoop invalidate has been seen for that load address
130     * @param load_idx index to start checking at
131     * @param inst the instruction to check
132     */
133    Fault checkViolations(int load_idx, DynInstPtr &inst);
134
135    /** Check if an incoming invalidate hits in the lsq on a load
136     * that might have issued out of order wrt another load beacuse
137     * of the intermediate invalidate.
138     */
139    void checkSnoop(PacketPtr pkt);
140
141    /** Executes a load instruction. */
142    Fault executeLoad(DynInstPtr &inst);
143
144    Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; }
145    /** Executes a store instruction. */
146    Fault executeStore(DynInstPtr &inst);
147
148    /** Commits the head load. */
149    void commitLoad();
150    /** Commits loads older than a specific sequence number. */
151    void commitLoads(InstSeqNum &youngest_inst);
152
153    /** Commits stores older than a specific sequence number. */
154    void commitStores(InstSeqNum &youngest_inst);
155
156    /** Writes back stores. */
157    void writebackStores();
158
159    /** Completes the data access that has been returned from the
160     * memory system. */
161    void completeDataAccess(PacketPtr pkt);
162
163    /** Clears all the entries in the LQ. */
164    void clearLQ();
165
166    /** Clears all the entries in the SQ. */
167    void clearSQ();
168
169    /** Resizes the LQ to a given size. */
170    void resizeLQ(unsigned size);
171
172    /** Resizes the SQ to a given size. */
173    void resizeSQ(unsigned size);
174
175    /** Squashes all instructions younger than a specific sequence number. */
176    void squash(const InstSeqNum &squashed_num);
177
178    /** Returns if there is a memory ordering violation. Value is reset upon
179     * call to getMemDepViolator().
180     */
181    bool violation() { return memDepViolator; }
182
183    /** Returns the memory ordering violator. */
184    DynInstPtr getMemDepViolator();
185
186    /** Returns the number of free LQ entries. */
187    unsigned numFreeLoadEntries();
188
189    /** Returns the number of free SQ entries. */
190    unsigned numFreeStoreEntries();
191
192    /** Returns the number of loads in the LQ. */
193    int numLoads() { return loads; }
194
195    /** Returns the number of stores in the SQ. */
196    int numStores() { return stores; }
197
198    /** Returns if either the LQ or SQ is full. */
199    bool isFull() { return lqFull() || sqFull(); }
200
201    /** Returns if both the LQ and SQ are empty. */
202    bool isEmpty() const { return lqEmpty() && sqEmpty(); }
203
204    /** Returns if the LQ is full. */
205    bool lqFull() { return loads >= (LQEntries - 1); }
206
207    /** Returns if the SQ is full. */
208    bool sqFull() { return stores >= (SQEntries - 1); }
209
210    /** Returns if the LQ is empty. */
211    bool lqEmpty() const { return loads == 0; }
212
213    /** Returns if the SQ is empty. */
214    bool sqEmpty() const { return stores == 0; }
215
216    /** Returns the number of instructions in the LSQ. */
217    unsigned getCount() { return loads + stores; }
218
219    /** Returns if there are any stores to writeback. */
220    bool hasStoresToWB() { return storesToWB; }
221
222    /** Returns the number of stores to writeback. */
223    int numStoresToWB() { return storesToWB; }
224
225    /** Returns if the LSQ unit will writeback on this cycle. */
226    bool willWB() { return storeQueue[storeWBIdx].canWB &&
227                        !storeQueue[storeWBIdx].completed &&
228                        !isStoreBlocked; }
229
230    /** Handles doing the retry. */
231    void recvRetry();
232
233  private:
234    /** Reset the LSQ state */
235    void resetState();
236
237    /** Writes back the instruction, sending it to IEW. */
238    void writeback(DynInstPtr &inst, PacketPtr pkt);
239
240    /** Writes back a store that couldn't be completed the previous cycle. */
241    void writebackPendingStore();
242
243    /** Handles completing the send of a store to memory. */
244    void storePostSend(PacketPtr pkt);
245
246    /** Completes the store at the specified index. */
247    void completeStore(int store_idx);
248
249    /** Attempts to send a store to the cache. */
250    bool sendStore(PacketPtr data_pkt);
251
252    /** Increments the given store index (circular queue). */
253    inline void incrStIdx(int &store_idx) const;
254    /** Decrements the given store index (circular queue). */
255    inline void decrStIdx(int &store_idx) const;
256    /** Increments the given load index (circular queue). */
257    inline void incrLdIdx(int &load_idx) const;
258    /** Decrements the given load index (circular queue). */
259    inline void decrLdIdx(int &load_idx) const;
260
261  public:
262    /** Debugging function to dump instructions in the LSQ. */
263    void dumpInsts() const;
264
265  private:
266    /** Pointer to the CPU. */
267    O3CPU *cpu;
268
269    /** Pointer to the IEW stage. */
270    IEW *iewStage;
271
272    /** Pointer to the LSQ. */
273    LSQ *lsq;
274
275    /** Pointer to the dcache port.  Used only for sending. */
276    MasterPort *dcachePort;
277
278    /** Derived class to hold any sender state the LSQ needs. */
279    class LSQSenderState : public Packet::SenderState
280    {
281      public:
282        /** Default constructor. */
283        LSQSenderState()
284            : mainPkt(NULL), pendingPacket(NULL), outstanding(1),
285              noWB(false), isSplit(false), pktToSend(false), cacheBlocked(false)
286          { }
287
288        /** Instruction who initiated the access to memory. */
289        DynInstPtr inst;
290        /** The main packet from a split load, used during writeback. */
291        PacketPtr mainPkt;
292        /** A second packet from a split store that needs sending. */
293        PacketPtr pendingPacket;
294        /** The LQ/SQ index of the instruction. */
295        uint8_t idx;
296        /** Number of outstanding packets to complete. */
297        uint8_t outstanding;
298        /** Whether or not it is a load. */
299        bool isLoad;
300        /** Whether or not the instruction will need to writeback. */
301        bool noWB;
302        /** Whether or not this access is split in two. */
303        bool isSplit;
304        /** Whether or not there is a packet that needs sending. */
305        bool pktToSend;
306        /** Whether or not the second packet of this split load was blocked */
307        bool cacheBlocked;
308
309        /** Completes a packet and returns whether the access is finished. */
310        inline bool complete() { return --outstanding == 0; }
311    };
312
313    /** Writeback event, specifically for when stores forward data to loads. */
314    class WritebackEvent : public Event {
315      public:
316        /** Constructs a writeback event. */
317        WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr);
318
319        /** Processes the writeback event. */
320        void process();
321
322        /** Returns the description of this event. */
323        const char *description() const;
324
325      private:
326        /** Instruction whose results are being written back. */
327        DynInstPtr inst;
328
329        /** The packet that would have been sent to memory. */
330        PacketPtr pkt;
331
332        /** The pointer to the LSQ unit that issued the store. */
333        LSQUnit<Impl> *lsqPtr;
334    };
335
336  public:
337    struct SQEntry {
338        /** Constructs an empty store queue entry. */
339        SQEntry()
340            : inst(NULL), req(NULL), size(0),
341              canWB(0), committed(0), completed(0)
342        {
343            std::memset(data, 0, sizeof(data));
344        }
345
346        ~SQEntry()
347        {
348            inst = NULL;
349        }
350
351        /** Constructs a store queue entry for a given instruction. */
352        SQEntry(DynInstPtr &_inst)
353            : inst(_inst), req(NULL), sreqLow(NULL), sreqHigh(NULL), size(0),
354              isSplit(0), canWB(0), committed(0), completed(0), isAllZeros(0)
355        {
356            std::memset(data, 0, sizeof(data));
357        }
358        /** The store data. */
359        char data[16];
360        /** The store instruction. */
361        DynInstPtr inst;
362        /** The request for the store. */
363        RequestPtr req;
364        /** The split requests for the store. */
365        RequestPtr sreqLow;
366        RequestPtr sreqHigh;
367        /** The size of the store. */
368        uint8_t size;
369        /** Whether or not the store is split into two requests. */
370        bool isSplit;
371        /** Whether or not the store can writeback. */
372        bool canWB;
373        /** Whether or not the store is committed. */
374        bool committed;
375        /** Whether or not the store is completed. */
376        bool completed;
377        /** Does this request write all zeros and thus doesn't
378         * have any data attached to it. Used for cache block zero
379         * style instructs (ARM DC ZVA; ALPHA WH64)
380         */
381        bool isAllZeros;
382    };
383
384  private:
385    /** The LSQUnit thread id. */
386    ThreadID lsqID;
387
388    /** The store queue. */
389    std::vector<SQEntry> storeQueue;
390
391    /** The load queue. */
392    std::vector<DynInstPtr> loadQueue;
393
394    /** The number of LQ entries, plus a sentinel entry (circular queue).
395     *  @todo: Consider having var that records the true number of LQ entries.
396     */
397    unsigned LQEntries;
398    /** The number of SQ entries, plus a sentinel entry (circular queue).
399     *  @todo: Consider having var that records the true number of SQ entries.
400     */
401    unsigned SQEntries;
402
403    /** The number of places to shift addresses in the LSQ before checking
404     * for dependency violations
405     */
406    unsigned depCheckShift;
407
408    /** Should loads be checked for dependency issues */
409    bool checkLoads;
410
411    /** The number of load instructions in the LQ. */
412    int loads;
413    /** The number of store instructions in the SQ. */
414    int stores;
415    /** The number of store instructions in the SQ waiting to writeback. */
416    int storesToWB;
417
418    /** The index of the head instruction in the LQ. */
419    int loadHead;
420    /** The index of the tail instruction in the LQ. */
421    int loadTail;
422
423    /** The index of the head instruction in the SQ. */
424    int storeHead;
425    /** The index of the first instruction that may be ready to be
426     * written back, and has not yet been written back.
427     */
428    int storeWBIdx;
429    /** The index of the tail instruction in the SQ. */
430    int storeTail;
431
432    /// @todo Consider moving to a more advanced model with write vs read ports
433    /** The number of cache ports available each cycle. */
434    int cachePorts;
435
436    /** The number of used cache ports in this cycle. */
437    int usedPorts;
438
439    //list<InstSeqNum> mshrSeqNums;
440
441    /** Address Mask for a cache block (e.g. ~(cache_block_size-1)) */
442    Addr cacheBlockMask;
443
444    /** Wire to read information from the issue stage time queue. */
445    typename TimeBuffer<IssueStruct>::wire fromIssue;
446
447    /** Whether or not the LSQ is stalled. */
448    bool stalled;
449    /** The store that causes the stall due to partial store to load
450     * forwarding.
451     */
452    InstSeqNum stallingStoreIsn;
453    /** The index of the above store. */
454    int stallingLoadIdx;
455
456    /** The packet that needs to be retried. */
457    PacketPtr retryPkt;
458
459    /** Whehter or not a store is blocked due to the memory system. */
460    bool isStoreBlocked;
461
462    /** Whether or not a store is in flight. */
463    bool storeInFlight;
464
465    /** The oldest load that caused a memory ordering violation. */
466    DynInstPtr memDepViolator;
467
468    /** Whether or not there is a packet that couldn't be sent because of
469     * a lack of cache ports. */
470    bool hasPendingPkt;
471
472    /** The packet that is pending free cache ports. */
473    PacketPtr pendingPkt;
474
475    /** Flag for memory model. */
476    bool needsTSO;
477
478    // Will also need how many read/write ports the Dcache has.  Or keep track
479    // of that in stage that is one level up, and only call executeLoad/Store
480    // the appropriate number of times.
481    /** Total number of loads forwaded from LSQ stores. */
482    Stats::Scalar lsqForwLoads;
483
484    /** Total number of loads ignored due to invalid addresses. */
485    Stats::Scalar invAddrLoads;
486
487    /** Total number of squashed loads. */
488    Stats::Scalar lsqSquashedLoads;
489
490    /** Total number of responses from the memory system that are
491     * ignored due to the instruction already being squashed. */
492    Stats::Scalar lsqIgnoredResponses;
493
494    /** Tota number of memory ordering violations. */
495    Stats::Scalar lsqMemOrderViolation;
496
497    /** Total number of squashed stores. */
498    Stats::Scalar lsqSquashedStores;
499
500    /** Total number of software prefetches ignored due to invalid addresses. */
501    Stats::Scalar invAddrSwpfs;
502
503    /** Ready loads blocked due to partial store-forwarding. */
504    Stats::Scalar lsqBlockedLoads;
505
506    /** Number of loads that were rescheduled. */
507    Stats::Scalar lsqRescheduledLoads;
508
509    /** Number of times the LSQ is blocked due to the cache. */
510    Stats::Scalar lsqCacheBlocked;
511
512  public:
513    /** Executes the load at the given index. */
514    Fault read(Request *req, Request *sreqLow, Request *sreqHigh,
515               uint8_t *data, int load_idx);
516
517    /** Executes the store at the given index. */
518    Fault write(Request *req, Request *sreqLow, Request *sreqHigh,
519                uint8_t *data, int store_idx);
520
521    /** Returns the index of the head load instruction. */
522    int getLoadHead() { return loadHead; }
523    /** Returns the sequence number of the head load instruction. */
524    InstSeqNum getLoadHeadSeqNum()
525    {
526        if (loadQueue[loadHead]) {
527            return loadQueue[loadHead]->seqNum;
528        } else {
529            return 0;
530        }
531
532    }
533
534    /** Returns the index of the head store instruction. */
535    int getStoreHead() { return storeHead; }
536    /** Returns the sequence number of the head store instruction. */
537    InstSeqNum getStoreHeadSeqNum()
538    {
539        if (storeQueue[storeHead].inst) {
540            return storeQueue[storeHead].inst->seqNum;
541        } else {
542            return 0;
543        }
544
545    }
546
547    /** Returns whether or not the LSQ unit is stalled. */
548    bool isStalled()  { return stalled; }
549};
550
551template <class Impl>
552Fault
553LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
554                    uint8_t *data, int load_idx)
555{
556    DynInstPtr load_inst = loadQueue[load_idx];
557
558    assert(load_inst);
559
560    assert(!load_inst->isExecuted());
561
562    // Make sure this isn't an uncacheable access
563    // A bit of a hackish way to get uncached accesses to work only if they're
564    // at the head of the LSQ and are ready to commit (at the head of the ROB
565    // too).
566    if (req->isUncacheable() &&
567        (load_idx != loadHead || !load_inst->isAtCommit())) {
568        iewStage->rescheduleMemInst(load_inst);
569        ++lsqRescheduledLoads;
570        DPRINTF(LSQUnit, "Uncachable load [sn:%lli] PC %s\n",
571                load_inst->seqNum, load_inst->pcState());
572
573        // Must delete request now that it wasn't handed off to
574        // memory.  This is quite ugly.  @todo: Figure out the proper
575        // place to really handle request deletes.
576        delete req;
577        if (TheISA::HasUnalignedMemAcc && sreqLow) {
578            delete sreqLow;
579            delete sreqHigh;
580        }
581        return new GenericISA::M5PanicFault(
582                "Uncachable load [sn:%llx] PC %s\n",
583                load_inst->seqNum, load_inst->pcState());
584    }
585
586    // Check the SQ for any previous stores that might lead to forwarding
587    int store_idx = load_inst->sqIdx;
588
589    int store_size = 0;
590
591    DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, "
592            "storeHead: %i addr: %#x%s\n",
593            load_idx, store_idx, storeHead, req->getPaddr(),
594            sreqLow ? " split" : "");
595
596    if (req->isLLSC()) {
597        assert(!sreqLow);
598        // Disable recording the result temporarily.  Writing to misc
599        // regs normally updates the result, but this is not the
600        // desired behavior when handling store conditionals.
601        load_inst->recordResult(false);
602        TheISA::handleLockedRead(load_inst.get(), req);
603        load_inst->recordResult(true);
604    }
605
606    if (req->isMmappedIpr()) {
607        assert(!load_inst->memData);
608        load_inst->memData = new uint8_t[64];
609
610        ThreadContext *thread = cpu->tcBase(lsqID);
611        Cycles delay(0);
612        PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq);
613
614        if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
615            data_pkt->dataStatic(load_inst->memData);
616            delay = TheISA::handleIprRead(thread, data_pkt);
617        } else {
618            assert(sreqLow->isMmappedIpr() && sreqHigh->isMmappedIpr());
619            PacketPtr fst_data_pkt = new Packet(sreqLow, MemCmd::ReadReq);
620            PacketPtr snd_data_pkt = new Packet(sreqHigh, MemCmd::ReadReq);
621
622            fst_data_pkt->dataStatic(load_inst->memData);
623            snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());
624
625            delay = TheISA::handleIprRead(thread, fst_data_pkt);
626            Cycles delay2 = TheISA::handleIprRead(thread, snd_data_pkt);
627            if (delay2 > delay)
628                delay = delay2;
629
630            delete sreqLow;
631            delete sreqHigh;
632            delete fst_data_pkt;
633            delete snd_data_pkt;
634        }
635        WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
636        cpu->schedule(wb, cpu->clockEdge(delay));
637        return NoFault;
638    }
639
640    while (store_idx != -1) {
641        // End once we've reached the top of the LSQ
642        if (store_idx == storeWBIdx) {
643            break;
644        }
645
646        // Move the index to one younger
647        if (--store_idx < 0)
648            store_idx += SQEntries;
649
650        assert(storeQueue[store_idx].inst);
651
652        store_size = storeQueue[store_idx].size;
653
654        if (store_size == 0)
655            continue;
656        else if (storeQueue[store_idx].inst->uncacheable())
657            continue;
658
659        assert(storeQueue[store_idx].inst->effAddrValid());
660
661        // Check if the store data is within the lower and upper bounds of
662        // addresses that the request needs.
663        bool store_has_lower_limit =
664            req->getVaddr() >= storeQueue[store_idx].inst->effAddr;
665        bool store_has_upper_limit =
666            (req->getVaddr() + req->getSize()) <=
667            (storeQueue[store_idx].inst->effAddr + store_size);
668        bool lower_load_has_store_part =
669            req->getVaddr() < (storeQueue[store_idx].inst->effAddr +
670                           store_size);
671        bool upper_load_has_store_part =
672            (req->getVaddr() + req->getSize()) >
673            storeQueue[store_idx].inst->effAddr;
674
675        // If the store's data has all of the data needed, we can forward.
676        if ((store_has_lower_limit && store_has_upper_limit)) {
677            // Get shift amount for offset into the store's data.
678            int shift_amt = req->getVaddr() - storeQueue[store_idx].inst->effAddr;
679
680            if (storeQueue[store_idx].isAllZeros)
681                memset(data, 0, req->getSize());
682            else
683                memcpy(data, storeQueue[store_idx].data + shift_amt,
684                   req->getSize());
685
686            // Allocate memory if this is the first time a load is issued.
687            if (!load_inst->memData) {
688                load_inst->memData = new uint8_t[req->getSize()];
689            }
690            if (storeQueue[store_idx].isAllZeros)
691                memset(load_inst->memData, 0, req->getSize());
692            else
693                memcpy(load_inst->memData,
694                    storeQueue[store_idx].data + shift_amt, req->getSize());
695
696            DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
697                    "addr %#x\n", store_idx, req->getVaddr());
698
699            PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq);
700            data_pkt->dataStatic(load_inst->memData);
701
702            WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
703
704            // We'll say this has a 1 cycle load-store forwarding latency
705            // for now.
706            // @todo: Need to make this a parameter.
707            cpu->schedule(wb, curTick());
708
709            // Don't need to do anything special for split loads.
710            if (TheISA::HasUnalignedMemAcc && sreqLow) {
711                delete sreqLow;
712                delete sreqHigh;
713            }
714
715            ++lsqForwLoads;
716            return NoFault;
717        } else if ((store_has_lower_limit && lower_load_has_store_part) ||
718                   (store_has_upper_limit && upper_load_has_store_part) ||
719                   (lower_load_has_store_part && upper_load_has_store_part)) {
720            // This is the partial store-load forwarding case where a store
721            // has only part of the load's data.
722
723            // If it's already been written back, then don't worry about
724            // stalling on it.
725            if (storeQueue[store_idx].completed) {
726                panic("Should not check one of these");
727                continue;
728            }
729
730            // Must stall load and force it to retry, so long as it's the oldest
731            // load that needs to do so.
732            if (!stalled ||
733                (stalled &&
734                 load_inst->seqNum <
735                 loadQueue[stallingLoadIdx]->seqNum)) {
736                stalled = true;
737                stallingStoreIsn = storeQueue[store_idx].inst->seqNum;
738                stallingLoadIdx = load_idx;
739            }
740
741            // Tell IQ/mem dep unit that this instruction will need to be
742            // rescheduled eventually
743            iewStage->rescheduleMemInst(load_inst);
744            load_inst->clearIssued();
745            ++lsqRescheduledLoads;
746
747            // Do not generate a writeback event as this instruction is not
748            // complete.
749            DPRINTF(LSQUnit, "Load-store forwarding mis-match. "
750                    "Store idx %i to load addr %#x\n",
751                    store_idx, req->getVaddr());
752
753            // Must delete request now that it wasn't handed off to
754            // memory.  This is quite ugly.  @todo: Figure out the
755            // proper place to really handle request deletes.
756            delete req;
757            if (TheISA::HasUnalignedMemAcc && sreqLow) {
758                delete sreqLow;
759                delete sreqHigh;
760            }
761
762            return NoFault;
763        }
764    }
765
766    // If there's no forwarding case, then go access memory
767    DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %s\n",
768            load_inst->seqNum, load_inst->pcState());
769
770    // Allocate memory if this is the first time a load is issued.
771    if (!load_inst->memData) {
772        load_inst->memData = new uint8_t[req->getSize()];
773    }
774
775    ++usedPorts;
776
777    // if we the cache is not blocked, do cache access
778    bool completedFirst = false;
779    PacketPtr data_pkt = Packet::createRead(req);
780    PacketPtr fst_data_pkt = NULL;
781    PacketPtr snd_data_pkt = NULL;
782
783    data_pkt->dataStatic(load_inst->memData);
784
785    LSQSenderState *state = new LSQSenderState;
786    state->isLoad = true;
787    state->idx = load_idx;
788    state->inst = load_inst;
789    data_pkt->senderState = state;
790
791    if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
792        // Point the first packet at the main data packet.
793        fst_data_pkt = data_pkt;
794    } else {
795        // Create the split packets.
796        fst_data_pkt = Packet::createRead(sreqLow);
797        snd_data_pkt = Packet::createRead(sreqHigh);
798
799        fst_data_pkt->dataStatic(load_inst->memData);
800        snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());
801
802        fst_data_pkt->senderState = state;
803        snd_data_pkt->senderState = state;
804
805        state->isSplit = true;
806        state->outstanding = 2;
807        state->mainPkt = data_pkt;
808    }
809
810    bool successful_load = true;
811    if (!dcachePort->sendTimingReq(fst_data_pkt)) {
812        successful_load = false;
813    } else if (TheISA::HasUnalignedMemAcc && sreqLow) {
814        completedFirst = true;
815
816        // The first packet was sent without problems, so send this one
817        // too. If there is a problem with this packet then the whole
818        // load will be squashed, so indicate this to the state object.
819        // The first packet will return in completeDataAccess and be
820        // handled there.
821        ++usedPorts;
822        if (!dcachePort->sendTimingReq(snd_data_pkt)) {
823            // The main packet will be deleted in completeDataAccess.
824            state->complete();
825            // Signify to 1st half that the 2nd half was blocked via state
826            state->cacheBlocked = true;
827            successful_load = false;
828        }
829    }
830
831    // If the cache was blocked, or has become blocked due to the access,
832    // handle it.
833    if (!successful_load) {
834        if (!sreqLow) {
835            // Packet wasn't split, just delete main packet info
836            delete state;
837            delete req;
838            delete data_pkt;
839        }
840
841        if (TheISA::HasUnalignedMemAcc && sreqLow) {
842            if (!completedFirst) {
843                // Split packet, but first failed.  Delete all state.
844                delete state;
845                delete req;
846                delete data_pkt;
847                delete fst_data_pkt;
848                delete snd_data_pkt;
849                delete sreqLow;
850                delete sreqHigh;
851                sreqLow = NULL;
852                sreqHigh = NULL;
853            } else {
854                // Can't delete main packet data or state because first packet
855                // was sent to the memory system
856                delete data_pkt;
857                delete req;
858                delete sreqHigh;
859                delete snd_data_pkt;
860                sreqHigh = NULL;
861            }
862        }
863
864        ++lsqCacheBlocked;
865
866        iewStage->blockMemInst(load_inst);
867
868        // No fault occurred, even though the interface is blocked.
869        return NoFault;
870    }
871
872    return NoFault;
873}
874
875template <class Impl>
876Fault
877LSQUnit<Impl>::write(Request *req, Request *sreqLow, Request *sreqHigh,
878                     uint8_t *data, int store_idx)
879{
880    assert(storeQueue[store_idx].inst);
881
882    DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x"
883            " | storeHead:%i [sn:%i]\n",
884            store_idx, req->getPaddr(), storeHead,
885            storeQueue[store_idx].inst->seqNum);
886
887    storeQueue[store_idx].req = req;
888    storeQueue[store_idx].sreqLow = sreqLow;
889    storeQueue[store_idx].sreqHigh = sreqHigh;
890    unsigned size = req->getSize();
891    storeQueue[store_idx].size = size;
892    storeQueue[store_idx].isAllZeros = req->getFlags() & Request::CACHE_BLOCK_ZERO;
893    assert(size <= sizeof(storeQueue[store_idx].data) ||
894            (req->getFlags() & Request::CACHE_BLOCK_ZERO));
895
896    // Split stores can only occur in ISAs with unaligned memory accesses.  If
897    // a store request has been split, sreqLow and sreqHigh will be non-null.
898    if (TheISA::HasUnalignedMemAcc && sreqLow) {
899        storeQueue[store_idx].isSplit = true;
900    }
901
902    if (!(req->getFlags() & Request::CACHE_BLOCK_ZERO))
903        memcpy(storeQueue[store_idx].data, data, size);
904
905    // This function only writes the data to the store queue, so no fault
906    // can happen here.
907    return NoFault;
908}
909
910#endif // __CPU_O3_LSQ_UNIT_HH__
911