lsq_unit.hh revision 8199
12292SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 32292SN/A * All rights reserved. 42292SN/A * 52292SN/A * Redistribution and use in source and binary forms, with or without 62292SN/A * modification, are permitted provided that the following conditions are 72292SN/A * met: redistributions of source code must retain the above copyright 82292SN/A * notice, this list of conditions and the following disclaimer; 92292SN/A * redistributions in binary form must reproduce the above copyright 102292SN/A * notice, this list of conditions and the following disclaimer in the 112292SN/A * documentation and/or other materials provided with the distribution; 122292SN/A * neither the name of the copyright holders nor the names of its 132292SN/A * contributors may be used to endorse or promote products derived from 142292SN/A * this software without specific prior written permission. 152292SN/A * 162292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292689Sktlim@umich.edu * Korey Sewell 302292SN/A */ 312292SN/A 322292SN/A#ifndef __CPU_O3_LSQ_UNIT_HH__ 332292SN/A#define __CPU_O3_LSQ_UNIT_HH__ 342292SN/A 352329SN/A#include <algorithm> 364395Ssaidi@eecs.umich.edu#include <cstring> 372292SN/A#include <map> 382292SN/A#include <queue> 392292SN/A 402329SN/A#include "arch/faults.hh" 413326Sktlim@umich.edu#include "arch/locked_mem.hh" 422292SN/A#include "config/full_system.hh" 436658Snate@binkert.org#include "config/the_isa.hh" 445386Sstever@gmail.com#include "base/fast_alloc.hh" 452292SN/A#include "base/hashmap.hh" 462292SN/A#include "cpu/inst_seq.hh" 473348Sbinkertn@umich.edu#include "mem/packet.hh" 482669Sktlim@umich.edu#include "mem/port.hh" 492292SN/A 505529Snate@binkert.orgclass DerivO3CPUParams; 515529Snate@binkert.org 522292SN/A/** 532329SN/A * Class that implements the actual LQ and SQ for each specific 542329SN/A * thread. Both are circular queues; load entries are freed upon 552329SN/A * committing, while store entries are freed once they writeback. The 562329SN/A * LSQUnit tracks if there are memory ordering violations, and also 572329SN/A * detects partial load to store forwarding cases (a store only has 582329SN/A * part of a load's data) that requires the load to wait until the 592329SN/A * store writes back. In the former case it holds onto the instruction 602329SN/A * until the dependence unit looks at it, and in the latter it stalls 612329SN/A * the LSQ until the store writes back. At that point the load is 622329SN/A * replayed. 632292SN/A */ 642292SN/Atemplate <class Impl> 652292SN/Aclass LSQUnit { 662292SN/A public: 672733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 682292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 692292SN/A typedef typename Impl::CPUPol::IEW IEW; 702907Sktlim@umich.edu typedef typename Impl::CPUPol::LSQ LSQ; 712292SN/A typedef typename Impl::CPUPol::IssueStruct IssueStruct; 722292SN/A 732292SN/A public: 742292SN/A /** Constructs an LSQ unit. init() must be called prior to use. */ 752292SN/A LSQUnit(); 762292SN/A 772292SN/A /** Initializes the LSQ unit with the specified number of entries. */ 785529Snate@binkert.org void init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 795529Snate@binkert.org LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 805529Snate@binkert.org unsigned id); 812292SN/A 822292SN/A /** Returns the name of the LSQ unit. */ 832292SN/A std::string name() const; 842292SN/A 852727Sktlim@umich.edu /** Registers statistics. */ 862727Sktlim@umich.edu void regStats(); 872727Sktlim@umich.edu 882907Sktlim@umich.edu /** Sets the pointer to the dcache port. */ 894329Sktlim@umich.edu void setDcachePort(Port *dcache_port); 902907Sktlim@umich.edu 912348SN/A /** Switches out LSQ unit. */ 922307SN/A void switchOut(); 932307SN/A 942348SN/A /** Takes over from another CPU's thread. */ 952307SN/A void takeOverFrom(); 962307SN/A 972348SN/A /** Returns if the LSQ is switched out. */ 982307SN/A bool isSwitchedOut() { return switchedOut; } 992307SN/A 1002292SN/A /** Ticks the LSQ unit, which in this case only resets the number of 1012292SN/A * used cache ports. 1022292SN/A * @todo: Move the number of used ports up to the LSQ level so it can 1032292SN/A * be shared by all LSQ units. 1042292SN/A */ 1052292SN/A void tick() { usedPorts = 0; } 1062292SN/A 1072292SN/A /** Inserts an instruction. */ 1082292SN/A void insert(DynInstPtr &inst); 1092292SN/A /** Inserts a load instruction. */ 1102292SN/A void insertLoad(DynInstPtr &load_inst); 1112292SN/A /** Inserts a store instruction. */ 1122292SN/A void insertStore(DynInstPtr &store_inst); 1132292SN/A 1148199SAli.Saidi@ARM.com /** Check for ordering violations in the LSQ 1158199SAli.Saidi@ARM.com * @param load_idx index to start checking at 1168199SAli.Saidi@ARM.com * @param inst the instruction to check 1178199SAli.Saidi@ARM.com */ 1188199SAli.Saidi@ARM.com Fault checkViolations(int load_idx, DynInstPtr &inst); 1198199SAli.Saidi@ARM.com 1202292SN/A /** Executes a load instruction. */ 1212292SN/A Fault executeLoad(DynInstPtr &inst); 1222292SN/A 1232329SN/A Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; } 1242292SN/A /** Executes a store instruction. */ 1252292SN/A Fault executeStore(DynInstPtr &inst); 1262292SN/A 1272292SN/A /** Commits the head load. */ 1282292SN/A void commitLoad(); 1292292SN/A /** Commits loads older than a specific sequence number. */ 1302292SN/A void commitLoads(InstSeqNum &youngest_inst); 1312292SN/A 1322292SN/A /** Commits stores older than a specific sequence number. */ 1332292SN/A void commitStores(InstSeqNum &youngest_inst); 1342292SN/A 1352292SN/A /** Writes back stores. */ 1362292SN/A void writebackStores(); 1372292SN/A 1382790Sktlim@umich.edu /** Completes the data access that has been returned from the 1392790Sktlim@umich.edu * memory system. */ 1402669Sktlim@umich.edu void completeDataAccess(PacketPtr pkt); 1412669Sktlim@umich.edu 1422292SN/A /** Clears all the entries in the LQ. */ 1432292SN/A void clearLQ(); 1442292SN/A 1452292SN/A /** Clears all the entries in the SQ. */ 1462292SN/A void clearSQ(); 1472292SN/A 1482292SN/A /** Resizes the LQ to a given size. */ 1492292SN/A void resizeLQ(unsigned size); 1502292SN/A 1512292SN/A /** Resizes the SQ to a given size. */ 1522292SN/A void resizeSQ(unsigned size); 1532292SN/A 1542292SN/A /** Squashes all instructions younger than a specific sequence number. */ 1552292SN/A void squash(const InstSeqNum &squashed_num); 1562292SN/A 1572292SN/A /** Returns if there is a memory ordering violation. Value is reset upon 1582292SN/A * call to getMemDepViolator(). 1592292SN/A */ 1602292SN/A bool violation() { return memDepViolator; } 1612292SN/A 1622292SN/A /** Returns the memory ordering violator. */ 1632292SN/A DynInstPtr getMemDepViolator(); 1642292SN/A 1652329SN/A /** Returns if a load became blocked due to the memory system. */ 1662292SN/A bool loadBlocked() 1672292SN/A { return isLoadBlocked; } 1682292SN/A 1692348SN/A /** Clears the signal that a load became blocked. */ 1702292SN/A void clearLoadBlocked() 1712292SN/A { isLoadBlocked = false; } 1722292SN/A 1732348SN/A /** Returns if the blocked load was handled. */ 1742292SN/A bool isLoadBlockedHandled() 1752292SN/A { return loadBlockedHandled; } 1762292SN/A 1772348SN/A /** Records the blocked load as being handled. */ 1782292SN/A void setLoadBlockedHandled() 1792292SN/A { loadBlockedHandled = true; } 1802292SN/A 1812292SN/A /** Returns the number of free entries (min of free LQ and SQ entries). */ 1822292SN/A unsigned numFreeEntries(); 1832292SN/A 1842292SN/A /** Returns the number of loads ready to execute. */ 1852292SN/A int numLoadsReady(); 1862292SN/A 1872292SN/A /** Returns the number of loads in the LQ. */ 1882292SN/A int numLoads() { return loads; } 1892292SN/A 1902292SN/A /** Returns the number of stores in the SQ. */ 1912292SN/A int numStores() { return stores; } 1922292SN/A 1932292SN/A /** Returns if either the LQ or SQ is full. */ 1942292SN/A bool isFull() { return lqFull() || sqFull(); } 1952292SN/A 1962292SN/A /** Returns if the LQ is full. */ 1972292SN/A bool lqFull() { return loads >= (LQEntries - 1); } 1982292SN/A 1992292SN/A /** Returns if the SQ is full. */ 2002292SN/A bool sqFull() { return stores >= (SQEntries - 1); } 2012292SN/A 2022292SN/A /** Returns the number of instructions in the LSQ. */ 2032292SN/A unsigned getCount() { return loads + stores; } 2042292SN/A 2052292SN/A /** Returns if there are any stores to writeback. */ 2062292SN/A bool hasStoresToWB() { return storesToWB; } 2072292SN/A 2082292SN/A /** Returns the number of stores to writeback. */ 2092292SN/A int numStoresToWB() { return storesToWB; } 2102292SN/A 2112292SN/A /** Returns if the LSQ unit will writeback on this cycle. */ 2122292SN/A bool willWB() { return storeQueue[storeWBIdx].canWB && 2132678Sktlim@umich.edu !storeQueue[storeWBIdx].completed && 2142678Sktlim@umich.edu !isStoreBlocked; } 2152292SN/A 2162907Sktlim@umich.edu /** Handles doing the retry. */ 2172907Sktlim@umich.edu void recvRetry(); 2182907Sktlim@umich.edu 2192292SN/A private: 2202698Sktlim@umich.edu /** Writes back the instruction, sending it to IEW. */ 2212678Sktlim@umich.edu void writeback(DynInstPtr &inst, PacketPtr pkt); 2222678Sktlim@umich.edu 2236974Stjones1@inf.ed.ac.uk /** Writes back a store that couldn't be completed the previous cycle. */ 2246974Stjones1@inf.ed.ac.uk void writebackPendingStore(); 2256974Stjones1@inf.ed.ac.uk 2262698Sktlim@umich.edu /** Handles completing the send of a store to memory. */ 2273349Sbinkertn@umich.edu void storePostSend(PacketPtr pkt); 2282693Sktlim@umich.edu 2292292SN/A /** Completes the store at the specified index. */ 2302292SN/A void completeStore(int store_idx); 2312292SN/A 2326974Stjones1@inf.ed.ac.uk /** Attempts to send a store to the cache. */ 2336974Stjones1@inf.ed.ac.uk bool sendStore(PacketPtr data_pkt); 2346974Stjones1@inf.ed.ac.uk 2352292SN/A /** Increments the given store index (circular queue). */ 2362292SN/A inline void incrStIdx(int &store_idx); 2372292SN/A /** Decrements the given store index (circular queue). */ 2382292SN/A inline void decrStIdx(int &store_idx); 2392292SN/A /** Increments the given load index (circular queue). */ 2402292SN/A inline void incrLdIdx(int &load_idx); 2412292SN/A /** Decrements the given load index (circular queue). */ 2422292SN/A inline void decrLdIdx(int &load_idx); 2432292SN/A 2442329SN/A public: 2452329SN/A /** Debugging function to dump instructions in the LSQ. */ 2462329SN/A void dumpInsts(); 2472329SN/A 2482292SN/A private: 2492292SN/A /** Pointer to the CPU. */ 2502733Sktlim@umich.edu O3CPU *cpu; 2512292SN/A 2522292SN/A /** Pointer to the IEW stage. */ 2532292SN/A IEW *iewStage; 2542292SN/A 2552907Sktlim@umich.edu /** Pointer to the LSQ. */ 2562907Sktlim@umich.edu LSQ *lsq; 2572669Sktlim@umich.edu 2582907Sktlim@umich.edu /** Pointer to the dcache port. Used only for sending. */ 2592907Sktlim@umich.edu Port *dcachePort; 2602292SN/A 2612698Sktlim@umich.edu /** Derived class to hold any sender state the LSQ needs. */ 2625386Sstever@gmail.com class LSQSenderState : public Packet::SenderState, public FastAlloc 2632678Sktlim@umich.edu { 2642678Sktlim@umich.edu public: 2652698Sktlim@umich.edu /** Default constructor. */ 2662678Sktlim@umich.edu LSQSenderState() 2676974Stjones1@inf.ed.ac.uk : noWB(false), isSplit(false), pktToSend(false), outstanding(1), 2686974Stjones1@inf.ed.ac.uk mainPkt(NULL), pendingPacket(NULL) 2692678Sktlim@umich.edu { } 2702678Sktlim@umich.edu 2712698Sktlim@umich.edu /** Instruction who initiated the access to memory. */ 2722678Sktlim@umich.edu DynInstPtr inst; 2732698Sktlim@umich.edu /** Whether or not it is a load. */ 2742678Sktlim@umich.edu bool isLoad; 2752698Sktlim@umich.edu /** The LQ/SQ index of the instruction. */ 2762678Sktlim@umich.edu int idx; 2772698Sktlim@umich.edu /** Whether or not the instruction will need to writeback. */ 2782678Sktlim@umich.edu bool noWB; 2796974Stjones1@inf.ed.ac.uk /** Whether or not this access is split in two. */ 2806974Stjones1@inf.ed.ac.uk bool isSplit; 2816974Stjones1@inf.ed.ac.uk /** Whether or not there is a packet that needs sending. */ 2826974Stjones1@inf.ed.ac.uk bool pktToSend; 2836974Stjones1@inf.ed.ac.uk /** Number of outstanding packets to complete. */ 2846974Stjones1@inf.ed.ac.uk int outstanding; 2856974Stjones1@inf.ed.ac.uk /** The main packet from a split load, used during writeback. */ 2866974Stjones1@inf.ed.ac.uk PacketPtr mainPkt; 2876974Stjones1@inf.ed.ac.uk /** A second packet from a split store that needs sending. */ 2886974Stjones1@inf.ed.ac.uk PacketPtr pendingPacket; 2896974Stjones1@inf.ed.ac.uk 2906974Stjones1@inf.ed.ac.uk /** Completes a packet and returns whether the access is finished. */ 2916974Stjones1@inf.ed.ac.uk inline bool complete() { return --outstanding == 0; } 2922678Sktlim@umich.edu }; 2932678Sktlim@umich.edu 2942698Sktlim@umich.edu /** Writeback event, specifically for when stores forward data to loads. */ 2952678Sktlim@umich.edu class WritebackEvent : public Event { 2962678Sktlim@umich.edu public: 2972678Sktlim@umich.edu /** Constructs a writeback event. */ 2982678Sktlim@umich.edu WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr); 2992678Sktlim@umich.edu 3002678Sktlim@umich.edu /** Processes the writeback event. */ 3012678Sktlim@umich.edu void process(); 3022678Sktlim@umich.edu 3032678Sktlim@umich.edu /** Returns the description of this event. */ 3045336Shines@cs.fsu.edu const char *description() const; 3052678Sktlim@umich.edu 3062678Sktlim@umich.edu private: 3072698Sktlim@umich.edu /** Instruction whose results are being written back. */ 3082678Sktlim@umich.edu DynInstPtr inst; 3092678Sktlim@umich.edu 3102698Sktlim@umich.edu /** The packet that would have been sent to memory. */ 3112678Sktlim@umich.edu PacketPtr pkt; 3122678Sktlim@umich.edu 3132678Sktlim@umich.edu /** The pointer to the LSQ unit that issued the store. */ 3142678Sktlim@umich.edu LSQUnit<Impl> *lsqPtr; 3152678Sktlim@umich.edu }; 3162678Sktlim@umich.edu 3172292SN/A public: 3182292SN/A struct SQEntry { 3192292SN/A /** Constructs an empty store queue entry. */ 3202292SN/A SQEntry() 3214326Sgblack@eecs.umich.edu : inst(NULL), req(NULL), size(0), 3222292SN/A canWB(0), committed(0), completed(0) 3234326Sgblack@eecs.umich.edu { 3244395Ssaidi@eecs.umich.edu std::memset(data, 0, sizeof(data)); 3254326Sgblack@eecs.umich.edu } 3262292SN/A 3272292SN/A /** Constructs a store queue entry for a given instruction. */ 3282292SN/A SQEntry(DynInstPtr &_inst) 3296974Stjones1@inf.ed.ac.uk : inst(_inst), req(NULL), sreqLow(NULL), sreqHigh(NULL), size(0), 3306974Stjones1@inf.ed.ac.uk isSplit(0), canWB(0), committed(0), completed(0) 3314326Sgblack@eecs.umich.edu { 3324395Ssaidi@eecs.umich.edu std::memset(data, 0, sizeof(data)); 3334326Sgblack@eecs.umich.edu } 3342292SN/A 3352292SN/A /** The store instruction. */ 3362292SN/A DynInstPtr inst; 3372669Sktlim@umich.edu /** The request for the store. */ 3382669Sktlim@umich.edu RequestPtr req; 3396974Stjones1@inf.ed.ac.uk /** The split requests for the store. */ 3406974Stjones1@inf.ed.ac.uk RequestPtr sreqLow; 3416974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh; 3422292SN/A /** The size of the store. */ 3432292SN/A int size; 3442292SN/A /** The store data. */ 3457786SAli.Saidi@ARM.com char data[16]; 3466974Stjones1@inf.ed.ac.uk /** Whether or not the store is split into two requests. */ 3476974Stjones1@inf.ed.ac.uk bool isSplit; 3482292SN/A /** Whether or not the store can writeback. */ 3492292SN/A bool canWB; 3502292SN/A /** Whether or not the store is committed. */ 3512292SN/A bool committed; 3522292SN/A /** Whether or not the store is completed. */ 3532292SN/A bool completed; 3542292SN/A }; 3552329SN/A 3562292SN/A private: 3572292SN/A /** The LSQUnit thread id. */ 3586221Snate@binkert.org ThreadID lsqID; 3592292SN/A 3602292SN/A /** The store queue. */ 3612292SN/A std::vector<SQEntry> storeQueue; 3622292SN/A 3632292SN/A /** The load queue. */ 3642292SN/A std::vector<DynInstPtr> loadQueue; 3652292SN/A 3662329SN/A /** The number of LQ entries, plus a sentinel entry (circular queue). 3672329SN/A * @todo: Consider having var that records the true number of LQ entries. 3682329SN/A */ 3692292SN/A unsigned LQEntries; 3702329SN/A /** The number of SQ entries, plus a sentinel entry (circular queue). 3712329SN/A * @todo: Consider having var that records the true number of SQ entries. 3722329SN/A */ 3732292SN/A unsigned SQEntries; 3742292SN/A 3758199SAli.Saidi@ARM.com /** The number of places to shift addresses in the LSQ before checking 3768199SAli.Saidi@ARM.com * for dependency violations 3778199SAli.Saidi@ARM.com */ 3788199SAli.Saidi@ARM.com unsigned depCheckShift; 3798199SAli.Saidi@ARM.com 3808199SAli.Saidi@ARM.com /** Should loads be checked for dependency issues */ 3818199SAli.Saidi@ARM.com bool checkLoads; 3828199SAli.Saidi@ARM.com 3832292SN/A /** The number of load instructions in the LQ. */ 3842292SN/A int loads; 3852329SN/A /** The number of store instructions in the SQ. */ 3862292SN/A int stores; 3872292SN/A /** The number of store instructions in the SQ waiting to writeback. */ 3882292SN/A int storesToWB; 3892292SN/A 3902292SN/A /** The index of the head instruction in the LQ. */ 3912292SN/A int loadHead; 3922292SN/A /** The index of the tail instruction in the LQ. */ 3932292SN/A int loadTail; 3942292SN/A 3952292SN/A /** The index of the head instruction in the SQ. */ 3962292SN/A int storeHead; 3972329SN/A /** The index of the first instruction that may be ready to be 3982329SN/A * written back, and has not yet been written back. 3992292SN/A */ 4002292SN/A int storeWBIdx; 4012292SN/A /** The index of the tail instruction in the SQ. */ 4022292SN/A int storeTail; 4032292SN/A 4042292SN/A /// @todo Consider moving to a more advanced model with write vs read ports 4052292SN/A /** The number of cache ports available each cycle. */ 4062292SN/A int cachePorts; 4072292SN/A 4082292SN/A /** The number of used cache ports in this cycle. */ 4092292SN/A int usedPorts; 4102292SN/A 4112348SN/A /** Is the LSQ switched out. */ 4122307SN/A bool switchedOut; 4132307SN/A 4142292SN/A //list<InstSeqNum> mshrSeqNums; 4152292SN/A 4162292SN/A /** Wire to read information from the issue stage time queue. */ 4172292SN/A typename TimeBuffer<IssueStruct>::wire fromIssue; 4182292SN/A 4192292SN/A /** Whether or not the LSQ is stalled. */ 4202292SN/A bool stalled; 4212292SN/A /** The store that causes the stall due to partial store to load 4222292SN/A * forwarding. 4232292SN/A */ 4242292SN/A InstSeqNum stallingStoreIsn; 4252292SN/A /** The index of the above store. */ 4262292SN/A int stallingLoadIdx; 4272292SN/A 4282698Sktlim@umich.edu /** The packet that needs to be retried. */ 4292698Sktlim@umich.edu PacketPtr retryPkt; 4302693Sktlim@umich.edu 4312698Sktlim@umich.edu /** Whehter or not a store is blocked due to the memory system. */ 4322678Sktlim@umich.edu bool isStoreBlocked; 4332678Sktlim@umich.edu 4342329SN/A /** Whether or not a load is blocked due to the memory system. */ 4352292SN/A bool isLoadBlocked; 4362292SN/A 4372348SN/A /** Has the blocked load been handled. */ 4382292SN/A bool loadBlockedHandled; 4392292SN/A 4402348SN/A /** The sequence number of the blocked load. */ 4412292SN/A InstSeqNum blockedLoadSeqNum; 4422292SN/A 4432292SN/A /** The oldest load that caused a memory ordering violation. */ 4442292SN/A DynInstPtr memDepViolator; 4452292SN/A 4466974Stjones1@inf.ed.ac.uk /** Whether or not there is a packet that couldn't be sent because of 4476974Stjones1@inf.ed.ac.uk * a lack of cache ports. */ 4486974Stjones1@inf.ed.ac.uk bool hasPendingPkt; 4496974Stjones1@inf.ed.ac.uk 4506974Stjones1@inf.ed.ac.uk /** The packet that is pending free cache ports. */ 4516974Stjones1@inf.ed.ac.uk PacketPtr pendingPkt; 4526974Stjones1@inf.ed.ac.uk 4532292SN/A // Will also need how many read/write ports the Dcache has. Or keep track 4542292SN/A // of that in stage that is one level up, and only call executeLoad/Store 4552292SN/A // the appropriate number of times. 4562727Sktlim@umich.edu /** Total number of loads forwaded from LSQ stores. */ 4575999Snate@binkert.org Stats::Scalar lsqForwLoads; 4582307SN/A 4593126Sktlim@umich.edu /** Total number of loads ignored due to invalid addresses. */ 4605999Snate@binkert.org Stats::Scalar invAddrLoads; 4613126Sktlim@umich.edu 4623126Sktlim@umich.edu /** Total number of squashed loads. */ 4635999Snate@binkert.org Stats::Scalar lsqSquashedLoads; 4643126Sktlim@umich.edu 4653126Sktlim@umich.edu /** Total number of responses from the memory system that are 4663126Sktlim@umich.edu * ignored due to the instruction already being squashed. */ 4675999Snate@binkert.org Stats::Scalar lsqIgnoredResponses; 4683126Sktlim@umich.edu 4693126Sktlim@umich.edu /** Tota number of memory ordering violations. */ 4705999Snate@binkert.org Stats::Scalar lsqMemOrderViolation; 4713126Sktlim@umich.edu 4722727Sktlim@umich.edu /** Total number of squashed stores. */ 4735999Snate@binkert.org Stats::Scalar lsqSquashedStores; 4742727Sktlim@umich.edu 4752727Sktlim@umich.edu /** Total number of software prefetches ignored due to invalid addresses. */ 4765999Snate@binkert.org Stats::Scalar invAddrSwpfs; 4772727Sktlim@umich.edu 4782727Sktlim@umich.edu /** Ready loads blocked due to partial store-forwarding. */ 4795999Snate@binkert.org Stats::Scalar lsqBlockedLoads; 4802727Sktlim@umich.edu 4812727Sktlim@umich.edu /** Number of loads that were rescheduled. */ 4825999Snate@binkert.org Stats::Scalar lsqRescheduledLoads; 4832727Sktlim@umich.edu 4842727Sktlim@umich.edu /** Number of times the LSQ is blocked due to the cache. */ 4855999Snate@binkert.org Stats::Scalar lsqCacheBlocked; 4862727Sktlim@umich.edu 4872292SN/A public: 4882292SN/A /** Executes the load at the given index. */ 4897520Sgblack@eecs.umich.edu Fault read(Request *req, Request *sreqLow, Request *sreqHigh, 4907520Sgblack@eecs.umich.edu uint8_t *data, int load_idx); 4912292SN/A 4922292SN/A /** Executes the store at the given index. */ 4937520Sgblack@eecs.umich.edu Fault write(Request *req, Request *sreqLow, Request *sreqHigh, 4947520Sgblack@eecs.umich.edu uint8_t *data, int store_idx); 4952292SN/A 4962292SN/A /** Returns the index of the head load instruction. */ 4972292SN/A int getLoadHead() { return loadHead; } 4982292SN/A /** Returns the sequence number of the head load instruction. */ 4992292SN/A InstSeqNum getLoadHeadSeqNum() 5002292SN/A { 5012292SN/A if (loadQueue[loadHead]) { 5022292SN/A return loadQueue[loadHead]->seqNum; 5032292SN/A } else { 5042292SN/A return 0; 5052292SN/A } 5062292SN/A 5072292SN/A } 5082292SN/A 5092292SN/A /** Returns the index of the head store instruction. */ 5102292SN/A int getStoreHead() { return storeHead; } 5112292SN/A /** Returns the sequence number of the head store instruction. */ 5122292SN/A InstSeqNum getStoreHeadSeqNum() 5132292SN/A { 5142292SN/A if (storeQueue[storeHead].inst) { 5152292SN/A return storeQueue[storeHead].inst->seqNum; 5162292SN/A } else { 5172292SN/A return 0; 5182292SN/A } 5192292SN/A 5202292SN/A } 5212292SN/A 5222292SN/A /** Returns whether or not the LSQ unit is stalled. */ 5232292SN/A bool isStalled() { return stalled; } 5242292SN/A}; 5252292SN/A 5262292SN/Atemplate <class Impl> 5272292SN/AFault 5286974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh, 5297520Sgblack@eecs.umich.edu uint8_t *data, int load_idx) 5302292SN/A{ 5312669Sktlim@umich.edu DynInstPtr load_inst = loadQueue[load_idx]; 5322292SN/A 5332669Sktlim@umich.edu assert(load_inst); 5342669Sktlim@umich.edu 5352669Sktlim@umich.edu assert(!load_inst->isExecuted()); 5362292SN/A 5372292SN/A // Make sure this isn't an uncacheable access 5382292SN/A // A bit of a hackish way to get uncached accesses to work only if they're 5392292SN/A // at the head of the LSQ and are ready to commit (at the head of the ROB 5402292SN/A // too). 5413172Sstever@eecs.umich.edu if (req->isUncacheable() && 5422731Sktlim@umich.edu (load_idx != loadHead || !load_inst->isAtCommit())) { 5432669Sktlim@umich.edu iewStage->rescheduleMemInst(load_inst); 5442727Sktlim@umich.edu ++lsqRescheduledLoads; 5457720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Uncachable load [sn:%lli] PC %s\n", 5467720Sgblack@eecs.umich.edu load_inst->seqNum, load_inst->pcState()); 5474032Sktlim@umich.edu 5484032Sktlim@umich.edu // Must delete request now that it wasn't handed off to 5494032Sktlim@umich.edu // memory. This is quite ugly. @todo: Figure out the proper 5504032Sktlim@umich.edu // place to really handle request deletes. 5514032Sktlim@umich.edu delete req; 5526974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && sreqLow) { 5536974Stjones1@inf.ed.ac.uk delete sreqLow; 5546974Stjones1@inf.ed.ac.uk delete sreqHigh; 5556974Stjones1@inf.ed.ac.uk } 5562292SN/A return TheISA::genMachineCheckFault(); 5572292SN/A } 5582292SN/A 5592292SN/A // Check the SQ for any previous stores that might lead to forwarding 5602669Sktlim@umich.edu int store_idx = load_inst->sqIdx; 5612292SN/A 5622292SN/A int store_size = 0; 5632292SN/A 5642292SN/A DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, " 5656974Stjones1@inf.ed.ac.uk "storeHead: %i addr: %#x%s\n", 5666974Stjones1@inf.ed.ac.uk load_idx, store_idx, storeHead, req->getPaddr(), 5676974Stjones1@inf.ed.ac.uk sreqLow ? " split" : ""); 5682292SN/A 5696102Sgblack@eecs.umich.edu if (req->isLLSC()) { 5706974Stjones1@inf.ed.ac.uk assert(!sreqLow); 5713326Sktlim@umich.edu // Disable recording the result temporarily. Writing to misc 5723326Sktlim@umich.edu // regs normally updates the result, but this is not the 5733326Sktlim@umich.edu // desired behavior when handling store conditionals. 5743326Sktlim@umich.edu load_inst->recordResult = false; 5753326Sktlim@umich.edu TheISA::handleLockedRead(load_inst.get(), req); 5763326Sktlim@umich.edu load_inst->recordResult = true; 5772292SN/A } 5782292SN/A 5792292SN/A while (store_idx != -1) { 5802292SN/A // End once we've reached the top of the LSQ 5812292SN/A if (store_idx == storeWBIdx) { 5822292SN/A break; 5832292SN/A } 5842292SN/A 5852292SN/A // Move the index to one younger 5862292SN/A if (--store_idx < 0) 5872292SN/A store_idx += SQEntries; 5882292SN/A 5892292SN/A assert(storeQueue[store_idx].inst); 5902292SN/A 5912292SN/A store_size = storeQueue[store_idx].size; 5922292SN/A 5932292SN/A if (store_size == 0) 5942292SN/A continue; 5954032Sktlim@umich.edu else if (storeQueue[store_idx].inst->uncacheable()) 5964032Sktlim@umich.edu continue; 5974032Sktlim@umich.edu 5984032Sktlim@umich.edu assert(storeQueue[store_idx].inst->effAddrValid); 5992292SN/A 6002292SN/A // Check if the store data is within the lower and upper bounds of 6012292SN/A // addresses that the request needs. 6022292SN/A bool store_has_lower_limit = 6032669Sktlim@umich.edu req->getVaddr() >= storeQueue[store_idx].inst->effAddr; 6042292SN/A bool store_has_upper_limit = 6052669Sktlim@umich.edu (req->getVaddr() + req->getSize()) <= 6062669Sktlim@umich.edu (storeQueue[store_idx].inst->effAddr + store_size); 6072292SN/A bool lower_load_has_store_part = 6082669Sktlim@umich.edu req->getVaddr() < (storeQueue[store_idx].inst->effAddr + 6092292SN/A store_size); 6102292SN/A bool upper_load_has_store_part = 6112669Sktlim@umich.edu (req->getVaddr() + req->getSize()) > 6122669Sktlim@umich.edu storeQueue[store_idx].inst->effAddr; 6132292SN/A 6142292SN/A // If the store's data has all of the data needed, we can forward. 6154032Sktlim@umich.edu if ((store_has_lower_limit && store_has_upper_limit)) { 6162329SN/A // Get shift amount for offset into the store's data. 6172669Sktlim@umich.edu int shift_amt = req->getVaddr() & (store_size - 1); 6182292SN/A 6197520Sgblack@eecs.umich.edu memcpy(data, storeQueue[store_idx].data + shift_amt, 6207520Sgblack@eecs.umich.edu req->getSize()); 6213803Sgblack@eecs.umich.edu 6222669Sktlim@umich.edu assert(!load_inst->memData); 6232669Sktlim@umich.edu load_inst->memData = new uint8_t[64]; 6242292SN/A 6254326Sgblack@eecs.umich.edu memcpy(load_inst->memData, 6264326Sgblack@eecs.umich.edu storeQueue[store_idx].data + shift_amt, req->getSize()); 6272292SN/A 6282292SN/A DPRINTF(LSQUnit, "Forwarding from store idx %i to load to " 6292292SN/A "addr %#x, data %#x\n", 6302693Sktlim@umich.edu store_idx, req->getVaddr(), data); 6312678Sktlim@umich.edu 6324022Sstever@eecs.umich.edu PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq, 6334022Sstever@eecs.umich.edu Packet::Broadcast); 6342678Sktlim@umich.edu data_pkt->dataStatic(load_inst->memData); 6352678Sktlim@umich.edu 6362678Sktlim@umich.edu WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this); 6372292SN/A 6382292SN/A // We'll say this has a 1 cycle load-store forwarding latency 6392292SN/A // for now. 6402292SN/A // @todo: Need to make this a parameter. 6417823Ssteve.reinhardt@amd.com cpu->schedule(wb, curTick()); 6422678Sktlim@umich.edu 6436974Stjones1@inf.ed.ac.uk // Don't need to do anything special for split loads. 6446974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && sreqLow) { 6456974Stjones1@inf.ed.ac.uk delete sreqLow; 6466974Stjones1@inf.ed.ac.uk delete sreqHigh; 6476974Stjones1@inf.ed.ac.uk } 6486974Stjones1@inf.ed.ac.uk 6492727Sktlim@umich.edu ++lsqForwLoads; 6502292SN/A return NoFault; 6512292SN/A } else if ((store_has_lower_limit && lower_load_has_store_part) || 6522292SN/A (store_has_upper_limit && upper_load_has_store_part) || 6532292SN/A (lower_load_has_store_part && upper_load_has_store_part)) { 6542292SN/A // This is the partial store-load forwarding case where a store 6552292SN/A // has only part of the load's data. 6562292SN/A 6572292SN/A // If it's already been written back, then don't worry about 6582292SN/A // stalling on it. 6592292SN/A if (storeQueue[store_idx].completed) { 6604032Sktlim@umich.edu panic("Should not check one of these"); 6612292SN/A continue; 6622292SN/A } 6632292SN/A 6642292SN/A // Must stall load and force it to retry, so long as it's the oldest 6652292SN/A // load that needs to do so. 6662292SN/A if (!stalled || 6672292SN/A (stalled && 6682669Sktlim@umich.edu load_inst->seqNum < 6692292SN/A loadQueue[stallingLoadIdx]->seqNum)) { 6702292SN/A stalled = true; 6712292SN/A stallingStoreIsn = storeQueue[store_idx].inst->seqNum; 6722292SN/A stallingLoadIdx = load_idx; 6732292SN/A } 6742292SN/A 6752292SN/A // Tell IQ/mem dep unit that this instruction will need to be 6762292SN/A // rescheduled eventually 6772669Sktlim@umich.edu iewStage->rescheduleMemInst(load_inst); 6782927Sktlim@umich.edu iewStage->decrWb(load_inst->seqNum); 6794032Sktlim@umich.edu load_inst->clearIssued(); 6802727Sktlim@umich.edu ++lsqRescheduledLoads; 6812292SN/A 6822292SN/A // Do not generate a writeback event as this instruction is not 6832292SN/A // complete. 6842292SN/A DPRINTF(LSQUnit, "Load-store forwarding mis-match. " 6852292SN/A "Store idx %i to load addr %#x\n", 6862669Sktlim@umich.edu store_idx, req->getVaddr()); 6872292SN/A 6884032Sktlim@umich.edu // Must delete request now that it wasn't handed off to 6894032Sktlim@umich.edu // memory. This is quite ugly. @todo: Figure out the 6904032Sktlim@umich.edu // proper place to really handle request deletes. 6914032Sktlim@umich.edu delete req; 6926974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && sreqLow) { 6936974Stjones1@inf.ed.ac.uk delete sreqLow; 6946974Stjones1@inf.ed.ac.uk delete sreqHigh; 6956974Stjones1@inf.ed.ac.uk } 6964032Sktlim@umich.edu 6972292SN/A return NoFault; 6982292SN/A } 6992292SN/A } 7002292SN/A 7012292SN/A // If there's no forwarding case, then go access memory 7027720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %s\n", 7037720Sgblack@eecs.umich.edu load_inst->seqNum, load_inst->pcState()); 7042292SN/A 7052669Sktlim@umich.edu assert(!load_inst->memData); 7062669Sktlim@umich.edu load_inst->memData = new uint8_t[64]; 7072292SN/A 7082292SN/A ++usedPorts; 7092292SN/A 7102907Sktlim@umich.edu // if we the cache is not blocked, do cache access 7116974Stjones1@inf.ed.ac.uk bool completedFirst = false; 7122907Sktlim@umich.edu if (!lsq->cacheBlocked()) { 7136974Stjones1@inf.ed.ac.uk MemCmd command = 7146974Stjones1@inf.ed.ac.uk req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq; 7156974Stjones1@inf.ed.ac.uk PacketPtr data_pkt = new Packet(req, command, Packet::Broadcast); 7166974Stjones1@inf.ed.ac.uk PacketPtr fst_data_pkt = NULL; 7176974Stjones1@inf.ed.ac.uk PacketPtr snd_data_pkt = NULL; 7186974Stjones1@inf.ed.ac.uk 7193228Sktlim@umich.edu data_pkt->dataStatic(load_inst->memData); 7203228Sktlim@umich.edu 7213228Sktlim@umich.edu LSQSenderState *state = new LSQSenderState; 7223228Sktlim@umich.edu state->isLoad = true; 7233228Sktlim@umich.edu state->idx = load_idx; 7243228Sktlim@umich.edu state->inst = load_inst; 7253228Sktlim@umich.edu data_pkt->senderState = state; 7263228Sktlim@umich.edu 7276974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || !sreqLow) { 7286974Stjones1@inf.ed.ac.uk 7296974Stjones1@inf.ed.ac.uk // Point the first packet at the main data packet. 7306974Stjones1@inf.ed.ac.uk fst_data_pkt = data_pkt; 7316974Stjones1@inf.ed.ac.uk } else { 7326974Stjones1@inf.ed.ac.uk 7336974Stjones1@inf.ed.ac.uk // Create the split packets. 7346974Stjones1@inf.ed.ac.uk fst_data_pkt = new Packet(sreqLow, command, Packet::Broadcast); 7356974Stjones1@inf.ed.ac.uk snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast); 7366974Stjones1@inf.ed.ac.uk 7376974Stjones1@inf.ed.ac.uk fst_data_pkt->dataStatic(load_inst->memData); 7386974Stjones1@inf.ed.ac.uk snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize()); 7396974Stjones1@inf.ed.ac.uk 7406974Stjones1@inf.ed.ac.uk fst_data_pkt->senderState = state; 7416974Stjones1@inf.ed.ac.uk snd_data_pkt->senderState = state; 7426974Stjones1@inf.ed.ac.uk 7436974Stjones1@inf.ed.ac.uk state->isSplit = true; 7446974Stjones1@inf.ed.ac.uk state->outstanding = 2; 7456974Stjones1@inf.ed.ac.uk state->mainPkt = data_pkt; 7466974Stjones1@inf.ed.ac.uk } 7476974Stjones1@inf.ed.ac.uk 7486974Stjones1@inf.ed.ac.uk if (!dcachePort->sendTiming(fst_data_pkt)) { 7493228Sktlim@umich.edu // Delete state and data packet because a load retry 7503228Sktlim@umich.edu // initiates a pipeline restart; it does not retry. 7513228Sktlim@umich.edu delete state; 7524032Sktlim@umich.edu delete data_pkt->req; 7533228Sktlim@umich.edu delete data_pkt; 7546974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && sreqLow) { 7556974Stjones1@inf.ed.ac.uk delete fst_data_pkt->req; 7566974Stjones1@inf.ed.ac.uk delete fst_data_pkt; 7576974Stjones1@inf.ed.ac.uk delete snd_data_pkt->req; 7586974Stjones1@inf.ed.ac.uk delete snd_data_pkt; 7597511Stjones1@inf.ed.ac.uk sreqLow = NULL; 7607511Stjones1@inf.ed.ac.uk sreqHigh = NULL; 7616974Stjones1@inf.ed.ac.uk } 7623228Sktlim@umich.edu 7634032Sktlim@umich.edu req = NULL; 7644032Sktlim@umich.edu 7652907Sktlim@umich.edu // If the access didn't succeed, tell the LSQ by setting 7662907Sktlim@umich.edu // the retry thread id. 7672907Sktlim@umich.edu lsq->setRetryTid(lsqID); 7686974Stjones1@inf.ed.ac.uk } else if (TheISA::HasUnalignedMemAcc && sreqLow) { 7696974Stjones1@inf.ed.ac.uk completedFirst = true; 7706974Stjones1@inf.ed.ac.uk 7716974Stjones1@inf.ed.ac.uk // The first packet was sent without problems, so send this one 7726974Stjones1@inf.ed.ac.uk // too. If there is a problem with this packet then the whole 7736974Stjones1@inf.ed.ac.uk // load will be squashed, so indicate this to the state object. 7746974Stjones1@inf.ed.ac.uk // The first packet will return in completeDataAccess and be 7756974Stjones1@inf.ed.ac.uk // handled there. 7766974Stjones1@inf.ed.ac.uk ++usedPorts; 7776974Stjones1@inf.ed.ac.uk if (!dcachePort->sendTiming(snd_data_pkt)) { 7786974Stjones1@inf.ed.ac.uk 7796974Stjones1@inf.ed.ac.uk // The main packet will be deleted in completeDataAccess. 7806974Stjones1@inf.ed.ac.uk delete snd_data_pkt->req; 7816974Stjones1@inf.ed.ac.uk delete snd_data_pkt; 7826974Stjones1@inf.ed.ac.uk 7836974Stjones1@inf.ed.ac.uk state->complete(); 7846974Stjones1@inf.ed.ac.uk 7856974Stjones1@inf.ed.ac.uk req = NULL; 7867511Stjones1@inf.ed.ac.uk sreqHigh = NULL; 7876974Stjones1@inf.ed.ac.uk 7886974Stjones1@inf.ed.ac.uk lsq->setRetryTid(lsqID); 7896974Stjones1@inf.ed.ac.uk } 7902907Sktlim@umich.edu } 7912907Sktlim@umich.edu } 7922907Sktlim@umich.edu 7932907Sktlim@umich.edu // If the cache was blocked, or has become blocked due to the access, 7942907Sktlim@umich.edu // handle it. 7952907Sktlim@umich.edu if (lsq->cacheBlocked()) { 7964032Sktlim@umich.edu if (req) 7974032Sktlim@umich.edu delete req; 7986974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && sreqLow && !completedFirst) { 7996974Stjones1@inf.ed.ac.uk delete sreqLow; 8006974Stjones1@inf.ed.ac.uk delete sreqHigh; 8016974Stjones1@inf.ed.ac.uk } 8024032Sktlim@umich.edu 8032727Sktlim@umich.edu ++lsqCacheBlocked; 8043014Srdreslin@umich.edu 8053014Srdreslin@umich.edu iewStage->decrWb(load_inst->seqNum); 8062669Sktlim@umich.edu // There's an older load that's already going to squash. 8072669Sktlim@umich.edu if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum) 8082669Sktlim@umich.edu return NoFault; 8092292SN/A 8102669Sktlim@umich.edu // Record that the load was blocked due to memory. This 8112669Sktlim@umich.edu // load will squash all instructions after it, be 8122669Sktlim@umich.edu // refetched, and re-executed. 8132669Sktlim@umich.edu isLoadBlocked = true; 8142669Sktlim@umich.edu loadBlockedHandled = false; 8152669Sktlim@umich.edu blockedLoadSeqNum = load_inst->seqNum; 8162669Sktlim@umich.edu // No fault occurred, even though the interface is blocked. 8172669Sktlim@umich.edu return NoFault; 8182292SN/A } 8192292SN/A 8202669Sktlim@umich.edu return NoFault; 8212292SN/A} 8222292SN/A 8232292SN/Atemplate <class Impl> 8242292SN/AFault 8256974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::write(Request *req, Request *sreqLow, Request *sreqHigh, 8267520Sgblack@eecs.umich.edu uint8_t *data, int store_idx) 8272292SN/A{ 8282292SN/A assert(storeQueue[store_idx].inst); 8292292SN/A 8302292SN/A DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x data %#x" 8312292SN/A " | storeHead:%i [sn:%i]\n", 8322669Sktlim@umich.edu store_idx, req->getPaddr(), data, storeHead, 8332292SN/A storeQueue[store_idx].inst->seqNum); 8342329SN/A 8352292SN/A storeQueue[store_idx].req = req; 8366974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqLow = sreqLow; 8376974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqHigh = sreqHigh; 8387520Sgblack@eecs.umich.edu unsigned size = req->getSize(); 8397520Sgblack@eecs.umich.edu storeQueue[store_idx].size = size; 8407520Sgblack@eecs.umich.edu assert(size <= sizeof(storeQueue[store_idx].data)); 8417509Stjones1@inf.ed.ac.uk 8427509Stjones1@inf.ed.ac.uk // Split stores can only occur in ISAs with unaligned memory accesses. If 8437509Stjones1@inf.ed.ac.uk // a store request has been split, sreqLow and sreqHigh will be non-null. 8447509Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && sreqLow) { 8457509Stjones1@inf.ed.ac.uk storeQueue[store_idx].isSplit = true; 8467509Stjones1@inf.ed.ac.uk } 8474326Sgblack@eecs.umich.edu 8487520Sgblack@eecs.umich.edu memcpy(storeQueue[store_idx].data, data, size); 8492329SN/A 8502292SN/A // This function only writes the data to the store queue, so no fault 8512292SN/A // can happen here. 8522292SN/A return NoFault; 8532292SN/A} 8542292SN/A 8552292SN/A#endif // __CPU_O3_LSQ_UNIT_HH__ 856