lsq_unit.hh revision 5386 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#ifndef __CPU_O3_LSQ_UNIT_HH__
33#define __CPU_O3_LSQ_UNIT_HH__
34
35#include <algorithm>
36#include <cstring>
37#include <map>
38#include <queue>
39
40#include "arch/faults.hh"
41#include "arch/locked_mem.hh"
42#include "config/full_system.hh"
43#include "base/fast_alloc.hh"
44#include "base/hashmap.hh"
45#include "cpu/inst_seq.hh"
46#include "mem/packet.hh"
47#include "mem/port.hh"
48
49/**
50 * Class that implements the actual LQ and SQ for each specific
51 * thread.  Both are circular queues; load entries are freed upon
52 * committing, while store entries are freed once they writeback. The
53 * LSQUnit tracks if there are memory ordering violations, and also
54 * detects partial load to store forwarding cases (a store only has
55 * part of a load's data) that requires the load to wait until the
56 * store writes back. In the former case it holds onto the instruction
57 * until the dependence unit looks at it, and in the latter it stalls
58 * the LSQ until the store writes back. At that point the load is
59 * replayed.
60 */
61template <class Impl>
62class LSQUnit {
63  protected:
64    typedef TheISA::IntReg IntReg;
65  public:
66    typedef typename Impl::Params Params;
67    typedef typename Impl::O3CPU O3CPU;
68    typedef typename Impl::DynInstPtr DynInstPtr;
69    typedef typename Impl::CPUPol::IEW IEW;
70    typedef typename Impl::CPUPol::LSQ LSQ;
71    typedef typename Impl::CPUPol::IssueStruct IssueStruct;
72
73  public:
74    /** Constructs an LSQ unit. init() must be called prior to use. */
75    LSQUnit();
76
77    /** Initializes the LSQ unit with the specified number of entries. */
78    void init(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params, LSQ *lsq_ptr,
79              unsigned maxLQEntries, unsigned maxSQEntries, unsigned id);
80
81    /** Returns the name of the LSQ unit. */
82    std::string name() const;
83
84    /** Registers statistics. */
85    void regStats();
86
87    /** Sets the pointer to the dcache port. */
88    void setDcachePort(Port *dcache_port);
89
90    /** Switches out LSQ unit. */
91    void switchOut();
92
93    /** Takes over from another CPU's thread. */
94    void takeOverFrom();
95
96    /** Returns if the LSQ is switched out. */
97    bool isSwitchedOut() { return switchedOut; }
98
99    /** Ticks the LSQ unit, which in this case only resets the number of
100     * used cache ports.
101     * @todo: Move the number of used ports up to the LSQ level so it can
102     * be shared by all LSQ units.
103     */
104    void tick() { usedPorts = 0; }
105
106    /** Inserts an instruction. */
107    void insert(DynInstPtr &inst);
108    /** Inserts a load instruction. */
109    void insertLoad(DynInstPtr &load_inst);
110    /** Inserts a store instruction. */
111    void insertStore(DynInstPtr &store_inst);
112
113    /** Executes a load instruction. */
114    Fault executeLoad(DynInstPtr &inst);
115
116    Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; }
117    /** Executes a store instruction. */
118    Fault executeStore(DynInstPtr &inst);
119
120    /** Commits the head load. */
121    void commitLoad();
122    /** Commits loads older than a specific sequence number. */
123    void commitLoads(InstSeqNum &youngest_inst);
124
125    /** Commits stores older than a specific sequence number. */
126    void commitStores(InstSeqNum &youngest_inst);
127
128    /** Writes back stores. */
129    void writebackStores();
130
131    /** Completes the data access that has been returned from the
132     * memory system. */
133    void completeDataAccess(PacketPtr pkt);
134
135    /** Clears all the entries in the LQ. */
136    void clearLQ();
137
138    /** Clears all the entries in the SQ. */
139    void clearSQ();
140
141    /** Resizes the LQ to a given size. */
142    void resizeLQ(unsigned size);
143
144    /** Resizes the SQ to a given size. */
145    void resizeSQ(unsigned size);
146
147    /** Squashes all instructions younger than a specific sequence number. */
148    void squash(const InstSeqNum &squashed_num);
149
150    /** Returns if there is a memory ordering violation. Value is reset upon
151     * call to getMemDepViolator().
152     */
153    bool violation() { return memDepViolator; }
154
155    /** Returns the memory ordering violator. */
156    DynInstPtr getMemDepViolator();
157
158    /** Returns if a load became blocked due to the memory system. */
159    bool loadBlocked()
160    { return isLoadBlocked; }
161
162    /** Clears the signal that a load became blocked. */
163    void clearLoadBlocked()
164    { isLoadBlocked = false; }
165
166    /** Returns if the blocked load was handled. */
167    bool isLoadBlockedHandled()
168    { return loadBlockedHandled; }
169
170    /** Records the blocked load as being handled. */
171    void setLoadBlockedHandled()
172    { loadBlockedHandled = true; }
173
174    /** Returns the number of free entries (min of free LQ and SQ entries). */
175    unsigned numFreeEntries();
176
177    /** Returns the number of loads ready to execute. */
178    int numLoadsReady();
179
180    /** Returns the number of loads in the LQ. */
181    int numLoads() { return loads; }
182
183    /** Returns the number of stores in the SQ. */
184    int numStores() { return stores; }
185
186    /** Returns if either the LQ or SQ is full. */
187    bool isFull() { return lqFull() || sqFull(); }
188
189    /** Returns if the LQ is full. */
190    bool lqFull() { return loads >= (LQEntries - 1); }
191
192    /** Returns if the SQ is full. */
193    bool sqFull() { return stores >= (SQEntries - 1); }
194
195    /** Returns the number of instructions in the LSQ. */
196    unsigned getCount() { return loads + stores; }
197
198    /** Returns if there are any stores to writeback. */
199    bool hasStoresToWB() { return storesToWB; }
200
201    /** Returns the number of stores to writeback. */
202    int numStoresToWB() { return storesToWB; }
203
204    /** Returns if the LSQ unit will writeback on this cycle. */
205    bool willWB() { return storeQueue[storeWBIdx].canWB &&
206                        !storeQueue[storeWBIdx].completed &&
207                        !isStoreBlocked; }
208
209    /** Handles doing the retry. */
210    void recvRetry();
211
212  private:
213    /** Writes back the instruction, sending it to IEW. */
214    void writeback(DynInstPtr &inst, PacketPtr pkt);
215
216    /** Handles completing the send of a store to memory. */
217    void storePostSend(PacketPtr pkt);
218
219    /** Completes the store at the specified index. */
220    void completeStore(int store_idx);
221
222    /** Increments the given store index (circular queue). */
223    inline void incrStIdx(int &store_idx);
224    /** Decrements the given store index (circular queue). */
225    inline void decrStIdx(int &store_idx);
226    /** Increments the given load index (circular queue). */
227    inline void incrLdIdx(int &load_idx);
228    /** Decrements the given load index (circular queue). */
229    inline void decrLdIdx(int &load_idx);
230
231  public:
232    /** Debugging function to dump instructions in the LSQ. */
233    void dumpInsts();
234
235  private:
236    /** Pointer to the CPU. */
237    O3CPU *cpu;
238
239    /** Pointer to the IEW stage. */
240    IEW *iewStage;
241
242    /** Pointer to the LSQ. */
243    LSQ *lsq;
244
245    /** Pointer to the dcache port.  Used only for sending. */
246    Port *dcachePort;
247
248    /** Derived class to hold any sender state the LSQ needs. */
249    class LSQSenderState : public Packet::SenderState, public FastAlloc
250    {
251      public:
252        /** Default constructor. */
253        LSQSenderState()
254            : noWB(false)
255        { }
256
257        /** Instruction who initiated the access to memory. */
258        DynInstPtr inst;
259        /** Whether or not it is a load. */
260        bool isLoad;
261        /** The LQ/SQ index of the instruction. */
262        int idx;
263        /** Whether or not the instruction will need to writeback. */
264        bool noWB;
265    };
266
267    /** Writeback event, specifically for when stores forward data to loads. */
268    class WritebackEvent : public Event {
269      public:
270        /** Constructs a writeback event. */
271        WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr);
272
273        /** Processes the writeback event. */
274        void process();
275
276        /** Returns the description of this event. */
277        const char *description() const;
278
279      private:
280        /** Instruction whose results are being written back. */
281        DynInstPtr inst;
282
283        /** The packet that would have been sent to memory. */
284        PacketPtr pkt;
285
286        /** The pointer to the LSQ unit that issued the store. */
287        LSQUnit<Impl> *lsqPtr;
288    };
289
290  public:
291    struct SQEntry {
292        /** Constructs an empty store queue entry. */
293        SQEntry()
294            : inst(NULL), req(NULL), size(0),
295              canWB(0), committed(0), completed(0)
296        {
297            std::memset(data, 0, sizeof(data));
298        }
299
300        /** Constructs a store queue entry for a given instruction. */
301        SQEntry(DynInstPtr &_inst)
302            : inst(_inst), req(NULL), size(0),
303              canWB(0), committed(0), completed(0)
304        {
305            std::memset(data, 0, sizeof(data));
306        }
307
308        /** The store instruction. */
309        DynInstPtr inst;
310        /** The request for the store. */
311        RequestPtr req;
312        /** The size of the store. */
313        int size;
314        /** The store data. */
315        char data[sizeof(IntReg)];
316        /** Whether or not the store can writeback. */
317        bool canWB;
318        /** Whether or not the store is committed. */
319        bool committed;
320        /** Whether or not the store is completed. */
321        bool completed;
322    };
323
324  private:
325    /** The LSQUnit thread id. */
326    unsigned lsqID;
327
328    /** The store queue. */
329    std::vector<SQEntry> storeQueue;
330
331    /** The load queue. */
332    std::vector<DynInstPtr> loadQueue;
333
334    /** The number of LQ entries, plus a sentinel entry (circular queue).
335     *  @todo: Consider having var that records the true number of LQ entries.
336     */
337    unsigned LQEntries;
338    /** The number of SQ entries, plus a sentinel entry (circular queue).
339     *  @todo: Consider having var that records the true number of SQ entries.
340     */
341    unsigned SQEntries;
342
343    /** The number of load instructions in the LQ. */
344    int loads;
345    /** The number of store instructions in the SQ. */
346    int stores;
347    /** The number of store instructions in the SQ waiting to writeback. */
348    int storesToWB;
349
350    /** The index of the head instruction in the LQ. */
351    int loadHead;
352    /** The index of the tail instruction in the LQ. */
353    int loadTail;
354
355    /** The index of the head instruction in the SQ. */
356    int storeHead;
357    /** The index of the first instruction that may be ready to be
358     * written back, and has not yet been written back.
359     */
360    int storeWBIdx;
361    /** The index of the tail instruction in the SQ. */
362    int storeTail;
363
364    /// @todo Consider moving to a more advanced model with write vs read ports
365    /** The number of cache ports available each cycle. */
366    int cachePorts;
367
368    /** The number of used cache ports in this cycle. */
369    int usedPorts;
370
371    /** Is the LSQ switched out. */
372    bool switchedOut;
373
374    //list<InstSeqNum> mshrSeqNums;
375
376    /** Wire to read information from the issue stage time queue. */
377    typename TimeBuffer<IssueStruct>::wire fromIssue;
378
379    /** Whether or not the LSQ is stalled. */
380    bool stalled;
381    /** The store that causes the stall due to partial store to load
382     * forwarding.
383     */
384    InstSeqNum stallingStoreIsn;
385    /** The index of the above store. */
386    int stallingLoadIdx;
387
388    /** The packet that needs to be retried. */
389    PacketPtr retryPkt;
390
391    /** Whehter or not a store is blocked due to the memory system. */
392    bool isStoreBlocked;
393
394    /** Whether or not a load is blocked due to the memory system. */
395    bool isLoadBlocked;
396
397    /** Has the blocked load been handled. */
398    bool loadBlockedHandled;
399
400    /** The sequence number of the blocked load. */
401    InstSeqNum blockedLoadSeqNum;
402
403    /** The oldest load that caused a memory ordering violation. */
404    DynInstPtr memDepViolator;
405
406    // Will also need how many read/write ports the Dcache has.  Or keep track
407    // of that in stage that is one level up, and only call executeLoad/Store
408    // the appropriate number of times.
409    /** Total number of loads forwaded from LSQ stores. */
410    Stats::Scalar<> lsqForwLoads;
411
412    /** Total number of loads ignored due to invalid addresses. */
413    Stats::Scalar<> invAddrLoads;
414
415    /** Total number of squashed loads. */
416    Stats::Scalar<> lsqSquashedLoads;
417
418    /** Total number of responses from the memory system that are
419     * ignored due to the instruction already being squashed. */
420    Stats::Scalar<> lsqIgnoredResponses;
421
422    /** Tota number of memory ordering violations. */
423    Stats::Scalar<> lsqMemOrderViolation;
424
425    /** Total number of squashed stores. */
426    Stats::Scalar<> lsqSquashedStores;
427
428    /** Total number of software prefetches ignored due to invalid addresses. */
429    Stats::Scalar<> invAddrSwpfs;
430
431    /** Ready loads blocked due to partial store-forwarding. */
432    Stats::Scalar<> lsqBlockedLoads;
433
434    /** Number of loads that were rescheduled. */
435    Stats::Scalar<> lsqRescheduledLoads;
436
437    /** Number of times the LSQ is blocked due to the cache. */
438    Stats::Scalar<> lsqCacheBlocked;
439
440  public:
441    /** Executes the load at the given index. */
442    template <class T>
443    Fault read(Request *req, T &data, int load_idx);
444
445    /** Executes the store at the given index. */
446    template <class T>
447    Fault write(Request *req, T &data, int store_idx);
448
449    /** Returns the index of the head load instruction. */
450    int getLoadHead() { return loadHead; }
451    /** Returns the sequence number of the head load instruction. */
452    InstSeqNum getLoadHeadSeqNum()
453    {
454        if (loadQueue[loadHead]) {
455            return loadQueue[loadHead]->seqNum;
456        } else {
457            return 0;
458        }
459
460    }
461
462    /** Returns the index of the head store instruction. */
463    int getStoreHead() { return storeHead; }
464    /** Returns the sequence number of the head store instruction. */
465    InstSeqNum getStoreHeadSeqNum()
466    {
467        if (storeQueue[storeHead].inst) {
468            return storeQueue[storeHead].inst->seqNum;
469        } else {
470            return 0;
471        }
472
473    }
474
475    /** Returns whether or not the LSQ unit is stalled. */
476    bool isStalled()  { return stalled; }
477};
478
479template <class Impl>
480template <class T>
481Fault
482LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
483{
484    DynInstPtr load_inst = loadQueue[load_idx];
485
486    assert(load_inst);
487
488    assert(!load_inst->isExecuted());
489
490    // Make sure this isn't an uncacheable access
491    // A bit of a hackish way to get uncached accesses to work only if they're
492    // at the head of the LSQ and are ready to commit (at the head of the ROB
493    // too).
494    if (req->isUncacheable() &&
495        (load_idx != loadHead || !load_inst->isAtCommit())) {
496        iewStage->rescheduleMemInst(load_inst);
497        ++lsqRescheduledLoads;
498
499        // Must delete request now that it wasn't handed off to
500        // memory.  This is quite ugly.  @todo: Figure out the proper
501        // place to really handle request deletes.
502        delete req;
503        return TheISA::genMachineCheckFault();
504    }
505
506    // Check the SQ for any previous stores that might lead to forwarding
507    int store_idx = load_inst->sqIdx;
508
509    int store_size = 0;
510
511    DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, "
512            "storeHead: %i addr: %#x\n",
513            load_idx, store_idx, storeHead, req->getPaddr());
514
515    if (req->isLocked()) {
516        // Disable recording the result temporarily.  Writing to misc
517        // regs normally updates the result, but this is not the
518        // desired behavior when handling store conditionals.
519        load_inst->recordResult = false;
520        TheISA::handleLockedRead(load_inst.get(), req);
521        load_inst->recordResult = true;
522    }
523
524    while (store_idx != -1) {
525        // End once we've reached the top of the LSQ
526        if (store_idx == storeWBIdx) {
527            break;
528        }
529
530        // Move the index to one younger
531        if (--store_idx < 0)
532            store_idx += SQEntries;
533
534        assert(storeQueue[store_idx].inst);
535
536        store_size = storeQueue[store_idx].size;
537
538        if (store_size == 0)
539            continue;
540        else if (storeQueue[store_idx].inst->uncacheable())
541            continue;
542
543        assert(storeQueue[store_idx].inst->effAddrValid);
544
545        // Check if the store data is within the lower and upper bounds of
546        // addresses that the request needs.
547        bool store_has_lower_limit =
548            req->getVaddr() >= storeQueue[store_idx].inst->effAddr;
549        bool store_has_upper_limit =
550            (req->getVaddr() + req->getSize()) <=
551            (storeQueue[store_idx].inst->effAddr + store_size);
552        bool lower_load_has_store_part =
553            req->getVaddr() < (storeQueue[store_idx].inst->effAddr +
554                           store_size);
555        bool upper_load_has_store_part =
556            (req->getVaddr() + req->getSize()) >
557            storeQueue[store_idx].inst->effAddr;
558
559        // If the store's data has all of the data needed, we can forward.
560        if ((store_has_lower_limit && store_has_upper_limit)) {
561            // Get shift amount for offset into the store's data.
562            int shift_amt = req->getVaddr() & (store_size - 1);
563
564            memcpy(&data, storeQueue[store_idx].data + shift_amt, sizeof(T));
565
566            assert(!load_inst->memData);
567            load_inst->memData = new uint8_t[64];
568
569            memcpy(load_inst->memData,
570                    storeQueue[store_idx].data + shift_amt, req->getSize());
571
572            DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
573                    "addr %#x, data %#x\n",
574                    store_idx, req->getVaddr(), data);
575
576            PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq,
577                                            Packet::Broadcast);
578            data_pkt->dataStatic(load_inst->memData);
579
580            WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
581
582            // We'll say this has a 1 cycle load-store forwarding latency
583            // for now.
584            // @todo: Need to make this a parameter.
585            wb->schedule(curTick);
586
587            ++lsqForwLoads;
588            return NoFault;
589        } else if ((store_has_lower_limit && lower_load_has_store_part) ||
590                   (store_has_upper_limit && upper_load_has_store_part) ||
591                   (lower_load_has_store_part && upper_load_has_store_part)) {
592            // This is the partial store-load forwarding case where a store
593            // has only part of the load's data.
594
595            // If it's already been written back, then don't worry about
596            // stalling on it.
597            if (storeQueue[store_idx].completed) {
598                panic("Should not check one of these");
599                continue;
600            }
601
602            // Must stall load and force it to retry, so long as it's the oldest
603            // load that needs to do so.
604            if (!stalled ||
605                (stalled &&
606                 load_inst->seqNum <
607                 loadQueue[stallingLoadIdx]->seqNum)) {
608                stalled = true;
609                stallingStoreIsn = storeQueue[store_idx].inst->seqNum;
610                stallingLoadIdx = load_idx;
611            }
612
613            // Tell IQ/mem dep unit that this instruction will need to be
614            // rescheduled eventually
615            iewStage->rescheduleMemInst(load_inst);
616            iewStage->decrWb(load_inst->seqNum);
617            load_inst->clearIssued();
618            ++lsqRescheduledLoads;
619
620            // Do not generate a writeback event as this instruction is not
621            // complete.
622            DPRINTF(LSQUnit, "Load-store forwarding mis-match. "
623                    "Store idx %i to load addr %#x\n",
624                    store_idx, req->getVaddr());
625
626            // Must delete request now that it wasn't handed off to
627            // memory.  This is quite ugly.  @todo: Figure out the
628            // proper place to really handle request deletes.
629            delete req;
630
631            return NoFault;
632        }
633    }
634
635    // If there's no forwarding case, then go access memory
636    DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %#x\n",
637            load_inst->seqNum, load_inst->readPC());
638
639    assert(!load_inst->memData);
640    load_inst->memData = new uint8_t[64];
641
642    ++usedPorts;
643
644    // if we the cache is not blocked, do cache access
645    if (!lsq->cacheBlocked()) {
646        PacketPtr data_pkt =
647            new Packet(req,
648                       (req->isLocked() ?
649                        MemCmd::LoadLockedReq : MemCmd::ReadReq),
650                       Packet::Broadcast);
651        data_pkt->dataStatic(load_inst->memData);
652
653        LSQSenderState *state = new LSQSenderState;
654        state->isLoad = true;
655        state->idx = load_idx;
656        state->inst = load_inst;
657        data_pkt->senderState = state;
658
659        if (!dcachePort->sendTiming(data_pkt)) {
660            // Delete state and data packet because a load retry
661            // initiates a pipeline restart; it does not retry.
662            delete state;
663            delete data_pkt->req;
664            delete data_pkt;
665
666            req = NULL;
667
668            // If the access didn't succeed, tell the LSQ by setting
669            // the retry thread id.
670            lsq->setRetryTid(lsqID);
671        }
672    }
673
674    // If the cache was blocked, or has become blocked due to the access,
675    // handle it.
676    if (lsq->cacheBlocked()) {
677        if (req)
678            delete req;
679
680        ++lsqCacheBlocked;
681
682        iewStage->decrWb(load_inst->seqNum);
683        // There's an older load that's already going to squash.
684        if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum)
685            return NoFault;
686
687        // Record that the load was blocked due to memory.  This
688        // load will squash all instructions after it, be
689        // refetched, and re-executed.
690        isLoadBlocked = true;
691        loadBlockedHandled = false;
692        blockedLoadSeqNum = load_inst->seqNum;
693        // No fault occurred, even though the interface is blocked.
694        return NoFault;
695    }
696
697    return NoFault;
698}
699
700template <class Impl>
701template <class T>
702Fault
703LSQUnit<Impl>::write(Request *req, T &data, int store_idx)
704{
705    assert(storeQueue[store_idx].inst);
706
707    DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x data %#x"
708            " | storeHead:%i [sn:%i]\n",
709            store_idx, req->getPaddr(), data, storeHead,
710            storeQueue[store_idx].inst->seqNum);
711
712    storeQueue[store_idx].req = req;
713    storeQueue[store_idx].size = sizeof(T);
714    assert(sizeof(T) <= sizeof(storeQueue[store_idx].data));
715
716    T gData = htog(data);
717    memcpy(storeQueue[store_idx].data, &gData, sizeof(T));
718
719    // This function only writes the data to the store queue, so no fault
720    // can happen here.
721    return NoFault;
722}
723
724#endif // __CPU_O3_LSQ_UNIT_HH__
725