lsq_unit.hh revision 13831
11689SN/A/* 210330Smitch.hayenga@arm.com * Copyright (c) 2012-2014,2017-2018 ARM Limited 38842Smrinmoy.ghosh@arm.com * All rights reserved 48842Smrinmoy.ghosh@arm.com * 58842Smrinmoy.ghosh@arm.com * The license below extends only to copyright in the software and shall 68842Smrinmoy.ghosh@arm.com * not be construed as granting a license to any other intellectual 78842Smrinmoy.ghosh@arm.com * property including but not limited to intellectual property relating 88842Smrinmoy.ghosh@arm.com * to a hardware implementation of the functionality of the software 98842Smrinmoy.ghosh@arm.com * licensed hereunder. You may use the software subject to the license 108842Smrinmoy.ghosh@arm.com * terms below provided that you ensure that this notice is replicated 118842Smrinmoy.ghosh@arm.com * unmodified and in its entirety in all distributions of the software, 128842Smrinmoy.ghosh@arm.com * modified or unmodified, in source code or in binary form. 138842Smrinmoy.ghosh@arm.com * 142345SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * Copyright (c) 2013 Advanced Micro Devices, Inc. 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392665SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665SN/A * 419480Snilay@cs.wisc.edu * Authors: Kevin Lim 429480Snilay@cs.wisc.edu * Korey Sewell 431689SN/A */ 441689SN/A 459480Snilay@cs.wisc.edu#ifndef __CPU_O3_LSQ_UNIT_HH__ 469480Snilay@cs.wisc.edu#define __CPU_O3_LSQ_UNIT_HH__ 471062SN/A 486216SN/A#include <algorithm> 496216SN/A#include <cstring> 506216SN/A#include <map> 519480Snilay@cs.wisc.edu#include <queue> 529480Snilay@cs.wisc.edu 5310785Sgope@wisc.edu#include "arch/generic/debugfaults.hh" 541062SN/A#include "arch/isa_traits.hh" 552345SN/A#include "arch/locked_mem.hh" 562345SN/A#include "arch/mmapped_ipr.hh" 572345SN/A#include "config/the_isa.hh" 582345SN/A#include "cpu/inst_seq.hh" 592345SN/A#include "cpu/timebuf.hh" 602345SN/A#include "debug/LSQUnit.hh" 612345SN/A#include "mem/packet.hh" 622345SN/A#include "mem/port.hh" 632345SN/A 649480Snilay@cs.wisc.edustruct DerivO3CPUParams; 651062SN/A#include "base/circular_queue.hh" 661062SN/A 671062SN/A/** 681062SN/A * Class that implements the actual LQ and SQ for each specific 691062SN/A * thread. Both are circular queues; load entries are freed upon 7010785Sgope@wisc.edu * committing, while store entries are freed once they writeback. The 711062SN/A * LSQUnit tracks if there are memory ordering violations, and also 721062SN/A * detects partial load to store forwarding cases (a store only has 731062SN/A * part of a load's data) that requires the load to wait until the 742345SN/A * store writes back. In the former case it holds onto the instruction 752345SN/A * until the dependence unit looks at it, and in the latter it stalls 761062SN/A * the LSQ until the store writes back. At that point the load is 772345SN/A * replayed. 781062SN/A */ 791062SN/Atemplate <class Impl> 809480Snilay@cs.wisc.educlass LSQUnit 812345SN/A{ 822345SN/A public: 832345SN/A typedef typename Impl::O3CPU O3CPU; 842345SN/A typedef typename Impl::DynInstPtr DynInstPtr; 852345SN/A typedef typename Impl::CPUPol::IEW IEW; 862345SN/A typedef typename Impl::CPUPol::LSQ LSQ; 872345SN/A typedef typename Impl::CPUPol::IssueStruct IssueStruct; 8810785Sgope@wisc.edu 898842Smrinmoy.ghosh@arm.com using LSQSenderState = typename LSQ::LSQSenderState; 908842Smrinmoy.ghosh@arm.com using LSQRequest = typename Impl::CPUPol::LSQ::LSQRequest; 918842Smrinmoy.ghosh@arm.com private: 928842Smrinmoy.ghosh@arm.com class LSQEntry 938842Smrinmoy.ghosh@arm.com { 948842Smrinmoy.ghosh@arm.com private: 958842Smrinmoy.ghosh@arm.com /** The instruction. */ 969480Snilay@cs.wisc.edu DynInstPtr inst; 971062SN/A /** The request. */ 981062SN/A LSQRequest* req; 991062SN/A /** The size of the operation. */ 1001062SN/A uint8_t _size; 1012345SN/A /** Valid entry. */ 1022345SN/A bool _valid; 1038842Smrinmoy.ghosh@arm.com public: 1048842Smrinmoy.ghosh@arm.com /** Constructs an empty store queue entry. */ 1051062SN/A LSQEntry() 1069480Snilay@cs.wisc.edu : inst(nullptr), req(nullptr), _size(0), _valid(false) 1071062SN/A { 10810330Smitch.hayenga@arm.com } 10910330Smitch.hayenga@arm.com 1102345SN/A ~LSQEntry() 1112345SN/A { 1122345SN/A inst = nullptr; 1132345SN/A if (req != nullptr) { 1142345SN/A req->freeLSQEntry(); 1152345SN/A req = nullptr; 1162345SN/A } 1172345SN/A } 1181684SN/A 1191062SN/A void 1201062SN/A clear() 1212345SN/A { 1222345SN/A inst = nullptr; 1232345SN/A if (req != nullptr) { 1242345SN/A req->freeLSQEntry(); 1252345SN/A } 1261062SN/A req = nullptr; 1271062SN/A _valid = false; 1282345SN/A _size = 0; 1292345SN/A } 1302345SN/A 1312345SN/A void 1321062SN/A set(const DynInstPtr& inst) 1331062SN/A { 1342345SN/A assert(!_valid); 1352345SN/A this->inst = inst; 1361062SN/A _valid = true; 1372345SN/A _size = 0; 1382345SN/A } 1392345SN/A LSQRequest* request() { return req; } 1402345SN/A void setRequest(LSQRequest* r) { req = r; } 1412345SN/A bool hasRequest() { return req != nullptr; } 1422345SN/A /** Member accessors. */ 1432345SN/A /** @{ */ 1442345SN/A bool valid() const { return _valid; } 1452345SN/A uint8_t& size() { return _size; } 1462345SN/A const uint8_t& size() const { return _size; } 1472345SN/A const DynInstPtr& instruction() const { return inst; } 1482345SN/A /** @} */ 1492345SN/A }; 1502345SN/A 1512345SN/A class SQEntry : public LSQEntry 1522345SN/A { 1532345SN/A private: 1542345SN/A /** The store data. */ 1552345SN/A char _data[64]; // TODO: 64 should become a parameter 1562345SN/A /** Whether or not the store can writeback. */ 1572345SN/A bool _canWB; 1582345SN/A /** Whether or not the store is committed. */ 1592345SN/A bool _committed; 1602345SN/A /** Whether or not the store is completed. */ 1612345SN/A bool _completed; 1622345SN/A /** Does this request write all zeros and thus doesn't 1632345SN/A * have any data attached to it. Used for cache block zero 1642345SN/A * style instructs (ARM DC ZVA; ALPHA WH64) 1652345SN/A */ 1662345SN/A bool _isAllZeros; 1672345SN/A public: 1682345SN/A static constexpr size_t DataSize = sizeof(_data); 1692345SN/A /** Constructs an empty store queue entry. */ 1708842Smrinmoy.ghosh@arm.com SQEntry() 1712345SN/A : _canWB(false), _committed(false), _completed(false), 1722345SN/A _isAllZeros(false) 1732345SN/A { 1742345SN/A std::memset(_data, 0, DataSize); 1751062SN/A } 1768842Smrinmoy.ghosh@arm.com 1778842Smrinmoy.ghosh@arm.com ~SQEntry() 1781062SN/A { 1792292SN/A } 1801062SN/A 1819360SE.Tomusk@sms.ed.ac.uk void 1821684SN/A set(const DynInstPtr& inst) 1831062SN/A { 1849360SE.Tomusk@sms.ed.ac.uk LSQEntry::set(inst); 1852356SN/A } 1862356SN/A 1871062SN/A void 1881684SN/A clear() 1891062SN/A { 1901062SN/A LSQEntry::clear(); 1912292SN/A _canWB = _completed = _committed = _isAllZeros = false; 1921062SN/A } 1939360SE.Tomusk@sms.ed.ac.uk /** Member accessors. */ 1941684SN/A /** @{ */ 1951062SN/A bool& canWB() { return _canWB; } 1969360SE.Tomusk@sms.ed.ac.uk const bool& canWB() const { return _canWB; } 1971684SN/A bool& completed() { return _completed; } 1981062SN/A const bool& completed() const { return _completed; } 1991062SN/A bool& committed() { return _committed; } 2002292SN/A const bool& committed() const { return _committed; } 2011062SN/A bool& isAllZeros() { return _isAllZeros; } 2029360SE.Tomusk@sms.ed.ac.uk const bool& isAllZeros() const { return _isAllZeros; } 2031684SN/A char* data() { return _data; } 2041062SN/A const char* data() const { return _data; } 2051062SN/A /** @} */ 2061684SN/A }; 2071062SN/A using LQEntry = LSQEntry; 2089360SE.Tomusk@sms.ed.ac.uk 2099360SE.Tomusk@sms.ed.ac.uk public: 2109360SE.Tomusk@sms.ed.ac.uk using LoadQueue = CircularQueue<LQEntry>; 2111684SN/A using StoreQueue = CircularQueue<SQEntry>; 2121062SN/A 2139360SE.Tomusk@sms.ed.ac.uk public: 2149360SE.Tomusk@sms.ed.ac.uk /** Constructs an LSQ unit. init() must be called prior to use. */ 2151684SN/A LSQUnit(uint32_t lqEntries, uint32_t sqEntries); 2161062SN/A 2179360SE.Tomusk@sms.ed.ac.uk /** We cannot copy LSQUnit because it has stats for which copy 2189360SE.Tomusk@sms.ed.ac.uk * contructor is deleted explicitly. However, STL vector requires 2191062SN/A * a valid copy constructor for the base type at compile time. 2201062SN/A */ 2219360SE.Tomusk@sms.ed.ac.uk LSQUnit(const LSQUnit &l) { panic("LSQUnit is not copy-able"); } 2229360SE.Tomusk@sms.ed.ac.uk 2239360SE.Tomusk@sms.ed.ac.uk /** Initializes the LSQ unit with the specified number of entries. */ 2249360SE.Tomusk@sms.ed.ac.uk void init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 2259360SE.Tomusk@sms.ed.ac.uk LSQ *lsq_ptr, unsigned id); 2269360SE.Tomusk@sms.ed.ac.uk 2279360SE.Tomusk@sms.ed.ac.uk /** Returns the name of the LSQ unit. */ 2289360SE.Tomusk@sms.ed.ac.uk std::string name() const; 2291062SN/A 2302292SN/A /** Registers statistics. */ 2311062SN/A void regStats(); 2329360SE.Tomusk@sms.ed.ac.uk 2331684SN/A /** Sets the pointer to the dcache port. */ 2341062SN/A void setDcachePort(MasterPort *dcache_port); 2359360SE.Tomusk@sms.ed.ac.uk 2361684SN/A /** Perform sanity checks after a drain. */ 2371062SN/A void drainSanityCheck() const; 2389360SE.Tomusk@sms.ed.ac.uk 2391062SN/A /** Takes over from another CPU's thread. */ 2401062SN/A void takeOverFrom(); 2419360SE.Tomusk@sms.ed.ac.uk 2429360SE.Tomusk@sms.ed.ac.uk /** Inserts an instruction. */ 2439360SE.Tomusk@sms.ed.ac.uk void insert(const DynInstPtr &inst); 2441062SN/A /** Inserts a load instruction. */ 2451062SN/A void insertLoad(const DynInstPtr &load_inst); 2469480Snilay@cs.wisc.edu /** Inserts a store instruction. */ 247 void insertStore(const DynInstPtr &store_inst); 248 249 /** Check for ordering violations in the LSQ. For a store squash if we 250 * ever find a conflicting load. For a load, only squash if we 251 * an external snoop invalidate has been seen for that load address 252 * @param load_idx index to start checking at 253 * @param inst the instruction to check 254 */ 255 Fault checkViolations(typename LoadQueue::iterator& loadIt, 256 const DynInstPtr& inst); 257 258 /** Check if an incoming invalidate hits in the lsq on a load 259 * that might have issued out of order wrt another load beacuse 260 * of the intermediate invalidate. 261 */ 262 void checkSnoop(PacketPtr pkt); 263 264 /** Executes a load instruction. */ 265 Fault executeLoad(const DynInstPtr &inst); 266 267 Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; } 268 /** Executes a store instruction. */ 269 Fault executeStore(const DynInstPtr &inst); 270 271 /** Commits the head load. */ 272 void commitLoad(); 273 /** Commits loads older than a specific sequence number. */ 274 void commitLoads(InstSeqNum &youngest_inst); 275 276 /** Commits stores older than a specific sequence number. */ 277 void commitStores(InstSeqNum &youngest_inst); 278 279 /** Writes back stores. */ 280 void writebackStores(); 281 282 /** Completes the data access that has been returned from the 283 * memory system. */ 284 void completeDataAccess(PacketPtr pkt); 285 286 /** Squashes all instructions younger than a specific sequence number. */ 287 void squash(const InstSeqNum &squashed_num); 288 289 /** Returns if there is a memory ordering violation. Value is reset upon 290 * call to getMemDepViolator(). 291 */ 292 bool violation() { return memDepViolator; } 293 294 /** Returns the memory ordering violator. */ 295 DynInstPtr getMemDepViolator(); 296 297 /** Returns the number of free LQ entries. */ 298 unsigned numFreeLoadEntries(); 299 300 /** Returns the number of free SQ entries. */ 301 unsigned numFreeStoreEntries(); 302 303 /** Returns the number of loads in the LQ. */ 304 int numLoads() { return loads; } 305 306 /** Returns the number of stores in the SQ. */ 307 int numStores() { return stores; } 308 309 /** Returns if either the LQ or SQ is full. */ 310 bool isFull() { return lqFull() || sqFull(); } 311 312 /** Returns if both the LQ and SQ are empty. */ 313 bool isEmpty() const { return lqEmpty() && sqEmpty(); } 314 315 /** Returns if the LQ is full. */ 316 bool lqFull() { return loadQueue.full(); } 317 318 /** Returns if the SQ is full. */ 319 bool sqFull() { return storeQueue.full(); } 320 321 /** Returns if the LQ is empty. */ 322 bool lqEmpty() const { return loads == 0; } 323 324 /** Returns if the SQ is empty. */ 325 bool sqEmpty() const { return stores == 0; } 326 327 /** Returns the number of instructions in the LSQ. */ 328 unsigned getCount() { return loads + stores; } 329 330 /** Returns if there are any stores to writeback. */ 331 bool hasStoresToWB() { return storesToWB; } 332 333 /** Returns the number of stores to writeback. */ 334 int numStoresToWB() { return storesToWB; } 335 336 /** Returns if the LSQ unit will writeback on this cycle. */ 337 bool 338 willWB() 339 { 340 return storeWBIt.dereferenceable() && 341 storeWBIt->valid() && 342 storeWBIt->canWB() && 343 !storeWBIt->completed() && 344 !isStoreBlocked; 345 } 346 347 /** Handles doing the retry. */ 348 void recvRetry(); 349 350 unsigned int cacheLineSize(); 351 private: 352 /** Reset the LSQ state */ 353 void resetState(); 354 355 /** Writes back the instruction, sending it to IEW. */ 356 void writeback(const DynInstPtr &inst, PacketPtr pkt); 357 358 /** Try to finish a previously blocked write back attempt */ 359 void writebackBlockedStore(); 360 361 /** Completes the store at the specified index. */ 362 void completeStore(typename StoreQueue::iterator store_idx); 363 364 /** Handles completing the send of a store to memory. */ 365 void storePostSend(); 366 367 public: 368 /** Attempts to send a packet to the cache. 369 * Check if there are ports available. Return true if 370 * there are, false if there are not. 371 */ 372 bool trySendPacket(bool isLoad, PacketPtr data_pkt); 373 374 375 /** Debugging function to dump instructions in the LSQ. */ 376 void dumpInsts() const; 377 378 /** Schedule event for the cpu. */ 379 void schedule(Event& ev, Tick when) { cpu->schedule(ev, when); } 380 381 BaseTLB* dTLB() { return cpu->dtb; } 382 383 private: 384 /** Pointer to the CPU. */ 385 O3CPU *cpu; 386 387 /** Pointer to the IEW stage. */ 388 IEW *iewStage; 389 390 /** Pointer to the LSQ. */ 391 LSQ *lsq; 392 393 /** Pointer to the dcache port. Used only for sending. */ 394 MasterPort *dcachePort; 395 396 /** Particularisation of the LSQSenderState to the LQ. */ 397 class LQSenderState : public LSQSenderState 398 { 399 using LSQSenderState::alive; 400 public: 401 LQSenderState(typename LoadQueue::iterator idx_) 402 : LSQSenderState(idx_->request(), true), idx(idx_) { } 403 404 /** The LQ index of the instruction. */ 405 typename LoadQueue::iterator idx; 406 //virtual LSQRequest* request() { return idx->request(); } 407 virtual void 408 complete() 409 { 410 //if (alive()) 411 // idx->request()->senderState(nullptr); 412 } 413 }; 414 415 /** Particularisation of the LSQSenderState to the SQ. */ 416 class SQSenderState : public LSQSenderState 417 { 418 using LSQSenderState::alive; 419 public: 420 SQSenderState(typename StoreQueue::iterator idx_) 421 : LSQSenderState(idx_->request(), false), idx(idx_) { } 422 /** The SQ index of the instruction. */ 423 typename StoreQueue::iterator idx; 424 //virtual LSQRequest* request() { return idx->request(); } 425 virtual void 426 complete() 427 { 428 //if (alive()) 429 // idx->request()->senderState(nullptr); 430 } 431 }; 432 433 /** Writeback event, specifically for when stores forward data to loads. */ 434 class WritebackEvent : public Event 435 { 436 public: 437 /** Constructs a writeback event. */ 438 WritebackEvent(const DynInstPtr &_inst, PacketPtr pkt, 439 LSQUnit *lsq_ptr); 440 441 /** Processes the writeback event. */ 442 void process(); 443 444 /** Returns the description of this event. */ 445 const char *description() const; 446 447 private: 448 /** Instruction whose results are being written back. */ 449 DynInstPtr inst; 450 451 /** The packet that would have been sent to memory. */ 452 PacketPtr pkt; 453 454 /** The pointer to the LSQ unit that issued the store. */ 455 LSQUnit<Impl> *lsqPtr; 456 }; 457 458 public: 459 /** 460 * Handles writing back and completing the load or store that has 461 * returned from memory. 462 * 463 * @param pkt Response packet from the memory sub-system 464 */ 465 bool recvTimingResp(PacketPtr pkt); 466 467 private: 468 /** The LSQUnit thread id. */ 469 ThreadID lsqID; 470 public: 471 /** The store queue. */ 472 CircularQueue<SQEntry> storeQueue; 473 474 /** The load queue. */ 475 LoadQueue loadQueue; 476 477 private: 478 /** The number of places to shift addresses in the LSQ before checking 479 * for dependency violations 480 */ 481 unsigned depCheckShift; 482 483 /** Should loads be checked for dependency issues */ 484 bool checkLoads; 485 486 /** The number of load instructions in the LQ. */ 487 int loads; 488 /** The number of store instructions in the SQ. */ 489 int stores; 490 /** The number of store instructions in the SQ waiting to writeback. */ 491 int storesToWB; 492 493 /** The index of the first instruction that may be ready to be 494 * written back, and has not yet been written back. 495 */ 496 typename StoreQueue::iterator storeWBIt; 497 498 /** Address Mask for a cache block (e.g. ~(cache_block_size-1)) */ 499 Addr cacheBlockMask; 500 501 /** Wire to read information from the issue stage time queue. */ 502 typename TimeBuffer<IssueStruct>::wire fromIssue; 503 504 /** Whether or not the LSQ is stalled. */ 505 bool stalled; 506 /** The store that causes the stall due to partial store to load 507 * forwarding. 508 */ 509 InstSeqNum stallingStoreIsn; 510 /** The index of the above store. */ 511 int stallingLoadIdx; 512 513 /** The packet that needs to be retried. */ 514 PacketPtr retryPkt; 515 516 /** Whehter or not a store is blocked due to the memory system. */ 517 bool isStoreBlocked; 518 519 /** Whether or not a store is in flight. */ 520 bool storeInFlight; 521 522 /** The oldest load that caused a memory ordering violation. */ 523 DynInstPtr memDepViolator; 524 525 /** Whether or not there is a packet that couldn't be sent because of 526 * a lack of cache ports. */ 527 bool hasPendingRequest; 528 529 /** The packet that is pending free cache ports. */ 530 LSQRequest* pendingRequest; 531 532 /** Flag for memory model. */ 533 bool needsTSO; 534 535 // Will also need how many read/write ports the Dcache has. Or keep track 536 // of that in stage that is one level up, and only call executeLoad/Store 537 // the appropriate number of times. 538 /** Total number of loads forwaded from LSQ stores. */ 539 Stats::Scalar lsqForwLoads; 540 541 /** Total number of loads ignored due to invalid addresses. */ 542 Stats::Scalar invAddrLoads; 543 544 /** Total number of squashed loads. */ 545 Stats::Scalar lsqSquashedLoads; 546 547 /** Total number of responses from the memory system that are 548 * ignored due to the instruction already being squashed. */ 549 Stats::Scalar lsqIgnoredResponses; 550 551 /** Tota number of memory ordering violations. */ 552 Stats::Scalar lsqMemOrderViolation; 553 554 /** Total number of squashed stores. */ 555 Stats::Scalar lsqSquashedStores; 556 557 /** Total number of software prefetches ignored due to invalid addresses. */ 558 Stats::Scalar invAddrSwpfs; 559 560 /** Ready loads blocked due to partial store-forwarding. */ 561 Stats::Scalar lsqBlockedLoads; 562 563 /** Number of loads that were rescheduled. */ 564 Stats::Scalar lsqRescheduledLoads; 565 566 /** Number of times the LSQ is blocked due to the cache. */ 567 Stats::Scalar lsqCacheBlocked; 568 569 public: 570 /** Executes the load at the given index. */ 571 Fault read(LSQRequest *req, int load_idx); 572 573 /** Executes the store at the given index. */ 574 Fault write(LSQRequest *req, uint8_t *data, int store_idx); 575 576 /** Returns the index of the head load instruction. */ 577 int getLoadHead() { return loadQueue.head(); } 578 579 /** Returns the sequence number of the head load instruction. */ 580 InstSeqNum 581 getLoadHeadSeqNum() 582 { 583 return loadQueue.front().valid() 584 ? loadQueue.front().instruction()->seqNum 585 : 0; 586 } 587 588 /** Returns the index of the head store instruction. */ 589 int getStoreHead() { return storeQueue.head(); } 590 /** Returns the sequence number of the head store instruction. */ 591 InstSeqNum 592 getStoreHeadSeqNum() 593 { 594 return storeQueue.front().valid() 595 ? storeQueue.front().instruction()->seqNum 596 : 0; 597 } 598 599 /** Returns whether or not the LSQ unit is stalled. */ 600 bool isStalled() { return stalled; } 601 public: 602 typedef typename CircularQueue<LQEntry>::iterator LQIterator; 603 typedef typename CircularQueue<SQEntry>::iterator SQIterator; 604 typedef CircularQueue<LQEntry> LQueue; 605 typedef CircularQueue<SQEntry> SQueue; 606}; 607 608template <class Impl> 609Fault 610LSQUnit<Impl>::read(LSQRequest *req, int load_idx) 611{ 612 LQEntry& load_req = loadQueue[load_idx]; 613 const DynInstPtr& load_inst = load_req.instruction(); 614 615 load_req.setRequest(req); 616 assert(load_inst); 617 618 assert(!load_inst->isExecuted()); 619 620 // Make sure this isn't a strictly ordered load 621 // A bit of a hackish way to get strictly ordered accesses to work 622 // only if they're at the head of the LSQ and are ready to commit 623 // (at the head of the ROB too). 624 625 if (req->mainRequest()->isStrictlyOrdered() && 626 (load_idx != loadQueue.head() || !load_inst->isAtCommit())) { 627 // Tell IQ/mem dep unit that this instruction will need to be 628 // rescheduled eventually 629 iewStage->rescheduleMemInst(load_inst); 630 load_inst->clearIssued(); 631 load_inst->effAddrValid(false); 632 ++lsqRescheduledLoads; 633 DPRINTF(LSQUnit, "Strictly ordered load [sn:%lli] PC %s\n", 634 load_inst->seqNum, load_inst->pcState()); 635 636 // Must delete request now that it wasn't handed off to 637 // memory. This is quite ugly. @todo: Figure out the proper 638 // place to really handle request deletes. 639 load_req.setRequest(nullptr); 640 req->discard(); 641 return std::make_shared<GenericISA::M5PanicFault>( 642 "Strictly ordered load [sn:%llx] PC %s\n", 643 load_inst->seqNum, load_inst->pcState()); 644 } 645 646 DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, " 647 "storeHead: %i addr: %#x%s\n", 648 load_idx - 1, load_inst->sqIt._idx, storeQueue.head() - 1, 649 req->mainRequest()->getPaddr(), req->isSplit() ? " split" : ""); 650 651 if (req->mainRequest()->isLLSC()) { 652 // Disable recording the result temporarily. Writing to misc 653 // regs normally updates the result, but this is not the 654 // desired behavior when handling store conditionals. 655 load_inst->recordResult(false); 656 TheISA::handleLockedRead(load_inst.get(), req->mainRequest()); 657 load_inst->recordResult(true); 658 } 659 660 if (req->mainRequest()->isMmappedIpr()) { 661 assert(!load_inst->memData); 662 load_inst->memData = new uint8_t[64]; 663 664 ThreadContext *thread = cpu->tcBase(lsqID); 665 PacketPtr main_pkt = new Packet(req->mainRequest(), MemCmd::ReadReq); 666 667 Cycles delay = req->handleIprRead(thread, main_pkt); 668 669 WritebackEvent *wb = new WritebackEvent(load_inst, main_pkt, this); 670 cpu->schedule(wb, cpu->clockEdge(delay)); 671 return NoFault; 672 } 673 674 // Check the SQ for any previous stores that might lead to forwarding 675 auto store_it = load_inst->sqIt; 676 assert (store_it >= storeWBIt); 677 // End once we've reached the top of the LSQ 678 while (store_it != storeWBIt) { 679 // Move the index to one younger 680 store_it--; 681 assert(store_it->valid()); 682 assert(store_it->instruction()->seqNum < load_inst->seqNum); 683 int store_size = store_it->size(); 684 685 // Cache maintenance instructions go down via the store 686 // path but they carry no data and they shouldn't be 687 // considered for forwarding 688 if (store_size != 0 && !store_it->instruction()->strictlyOrdered() && 689 !(store_it->request()->mainRequest() && 690 store_it->request()->mainRequest()->isCacheMaintenance())) { 691 assert(store_it->instruction()->effAddrValid()); 692 693 // Check if the store data is within the lower and upper bounds of 694 // addresses that the request needs. 695 auto req_s = req->mainRequest()->getVaddr(); 696 auto req_e = req_s + req->mainRequest()->getSize(); 697 auto st_s = store_it->instruction()->effAddr; 698 auto st_e = st_s + store_size; 699 700 bool store_has_lower_limit = req_s >= st_s; 701 bool store_has_upper_limit = req_e <= st_e; 702 bool lower_load_has_store_part = req_s < st_e; 703 bool upper_load_has_store_part = req_e > st_s; 704 705 // If the store entry is not atomic (atomic does not have valid 706 // data), the store has all of the data needed, and 707 // the load is not LLSC, then 708 // we can forward data from the store to the load 709 if (!store_it->instruction()->isAtomic() && 710 store_has_lower_limit && store_has_upper_limit && 711 !req->mainRequest()->isLLSC()) { 712 713 // Get shift amount for offset into the store's data. 714 int shift_amt = req->mainRequest()->getVaddr() - 715 store_it->instruction()->effAddr; 716 717 // Allocate memory if this is the first time a load is issued. 718 if (!load_inst->memData) { 719 load_inst->memData = 720 new uint8_t[req->mainRequest()->getSize()]; 721 } 722 if (store_it->isAllZeros()) 723 memset(load_inst->memData, 0, 724 req->mainRequest()->getSize()); 725 else 726 memcpy(load_inst->memData, 727 store_it->data() + shift_amt, 728 req->mainRequest()->getSize()); 729 730 DPRINTF(LSQUnit, "Forwarding from store idx %i to load to " 731 "addr %#x\n", store_it._idx, 732 req->mainRequest()->getVaddr()); 733 734 PacketPtr data_pkt = new Packet(req->mainRequest(), 735 MemCmd::ReadReq); 736 data_pkt->dataStatic(load_inst->memData); 737 738 if (req->isAnyOutstandingRequest()) { 739 assert(req->_numOutstandingPackets > 0); 740 // There are memory requests packets in flight already. 741 // This may happen if the store was not complete the 742 // first time this load got executed. Signal the senderSate 743 // that response packets should be discarded. 744 req->discardSenderState(); 745 } 746 747 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, 748 this); 749 750 // We'll say this has a 1 cycle load-store forwarding latency 751 // for now. 752 // @todo: Need to make this a parameter. 753 cpu->schedule(wb, curTick()); 754 755 // Don't need to do anything special for split loads. 756 ++lsqForwLoads; 757 758 return NoFault; 759 } else if ( 760 // This is the partial store-load forwarding case where a store 761 // has only part of the load's data and the load isn't LLSC 762 (!req->mainRequest()->isLLSC() && 763 ((store_has_lower_limit && lower_load_has_store_part) || 764 (store_has_upper_limit && upper_load_has_store_part) || 765 (lower_load_has_store_part && upper_load_has_store_part))) || 766 // The load is LLSC, and the store has all or part of the 767 // load's data 768 (req->mainRequest()->isLLSC() && 769 ((store_has_lower_limit || upper_load_has_store_part) && 770 (store_has_upper_limit || lower_load_has_store_part))) || 771 // The store entry is atomic and has all or part of the load's 772 // data 773 (store_it->instruction()->isAtomic() && 774 ((store_has_lower_limit || upper_load_has_store_part) && 775 (store_has_upper_limit || lower_load_has_store_part)))) { 776 777 // If it's already been written back, then don't worry about 778 // stalling on it. 779 if (store_it->completed()) { 780 panic("Should not check one of these"); 781 continue; 782 } 783 784 // Must stall load and force it to retry, so long as it's the 785 // oldest load that needs to do so. 786 if (!stalled || 787 (stalled && 788 load_inst->seqNum < 789 loadQueue[stallingLoadIdx].instruction()->seqNum)) { 790 stalled = true; 791 stallingStoreIsn = store_it->instruction()->seqNum; 792 stallingLoadIdx = load_idx; 793 } 794 795 // Tell IQ/mem dep unit that this instruction will need to be 796 // rescheduled eventually 797 iewStage->rescheduleMemInst(load_inst); 798 load_inst->clearIssued(); 799 load_inst->effAddrValid(false); 800 ++lsqRescheduledLoads; 801 802 // Do not generate a writeback event as this instruction is not 803 // complete. 804 DPRINTF(LSQUnit, "Load-store forwarding mis-match. " 805 "Store idx %i to load addr %#x\n", 806 store_it._idx, req->mainRequest()->getVaddr()); 807 808 // Must discard the request. 809 req->discard(); 810 load_req.setRequest(nullptr); 811 return NoFault; 812 } 813 } 814 } 815 816 // If there's no forwarding case, then go access memory 817 DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %s\n", 818 load_inst->seqNum, load_inst->pcState()); 819 820 // Allocate memory if this is the first time a load is issued. 821 if (!load_inst->memData) { 822 load_inst->memData = new uint8_t[req->mainRequest()->getSize()]; 823 } 824 825 // For now, load throughput is constrained by the number of 826 // load FUs only, and loads do not consume a cache port (only 827 // stores do). 828 // @todo We should account for cache port contention 829 // and arbitrate between loads and stores. 830 831 // if we the cache is not blocked, do cache access 832 if (req->senderState() == nullptr) { 833 LQSenderState *state = new LQSenderState( 834 loadQueue.getIterator(load_idx)); 835 state->isLoad = true; 836 state->inst = load_inst; 837 state->isSplit = req->isSplit(); 838 req->senderState(state); 839 } 840 req->buildPackets(); 841 req->sendPacketToCache(); 842 if (!req->isSent()) 843 iewStage->blockMemInst(load_inst); 844 845 return NoFault; 846} 847 848template <class Impl> 849Fault 850LSQUnit<Impl>::write(LSQRequest *req, uint8_t *data, int store_idx) 851{ 852 assert(storeQueue[store_idx].valid()); 853 854 DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x | storeHead:%i " 855 "[sn:%llu]\n", 856 store_idx - 1, req->request()->getPaddr(), storeQueue.head() - 1, 857 storeQueue[store_idx].instruction()->seqNum); 858 859 storeQueue[store_idx].setRequest(req); 860 unsigned size = req->_size; 861 storeQueue[store_idx].size() = size; 862 bool store_no_data = 863 req->mainRequest()->getFlags() & Request::STORE_NO_DATA; 864 storeQueue[store_idx].isAllZeros() = store_no_data; 865 assert(size <= SQEntry::DataSize || store_no_data); 866 867 // copy data into the storeQueue only if the store request has valid data 868 if (!(req->request()->getFlags() & Request::CACHE_BLOCK_ZERO) && 869 !req->request()->isCacheMaintenance() && 870 !req->request()->isAtomic()) 871 memcpy(storeQueue[store_idx].data(), data, size); 872 873 // This function only writes the data to the store queue, so no fault 874 // can happen here. 875 return NoFault; 876} 877 878#endif // __CPU_O3_LSQ_UNIT_HH__ 879