lsq.hh revision 9358:aa761458ddcb
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Korey Sewell 41 */ 42 43#ifndef __CPU_O3_LSQ_HH__ 44#define __CPU_O3_LSQ_HH__ 45 46#include <map> 47#include <queue> 48 49#include "cpu/o3/lsq_unit.hh" 50#include "cpu/inst_seq.hh" 51#include "mem/port.hh" 52#include "sim/sim_object.hh" 53 54struct DerivO3CPUParams; 55 56template <class Impl> 57class LSQ { 58 public: 59 typedef typename Impl::O3CPU O3CPU; 60 typedef typename Impl::DynInstPtr DynInstPtr; 61 typedef typename Impl::CPUPol::IEW IEW; 62 typedef typename Impl::CPUPol::LSQUnit LSQUnit; 63 64 /** SMT policy. */ 65 enum LSQPolicy { 66 Dynamic, 67 Partitioned, 68 Threshold 69 }; 70 71 /** Constructs an LSQ with the given parameters. */ 72 LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params); 73 74 /** Returns the name of the LSQ. */ 75 std::string name() const; 76 77 /** Registers statistics of each LSQ unit. */ 78 void regStats(); 79 80 /** Sets the pointer to the list of active threads. */ 81 void setActiveThreads(std::list<ThreadID> *at_ptr); 82 /** Switches out the LSQ. */ 83 void switchOut(); 84 /** Takes over execution from another CPU's thread. */ 85 void takeOverFrom(); 86 87 /** Number of entries needed for the given amount of threads.*/ 88 int entryAmount(ThreadID num_threads); 89 void removeEntries(ThreadID tid); 90 /** Reset the max entries for each thread. */ 91 void resetEntries(); 92 /** Resize the max entries for a thread. */ 93 void resizeEntries(unsigned size, ThreadID tid); 94 95 /** Ticks the LSQ. */ 96 void tick(); 97 /** Ticks a specific LSQ Unit. */ 98 void tick(ThreadID tid) 99 { thread[tid].tick(); } 100 101 /** Inserts a load into the LSQ. */ 102 void insertLoad(DynInstPtr &load_inst); 103 /** Inserts a store into the LSQ. */ 104 void insertStore(DynInstPtr &store_inst); 105 106 /** Executes a load. */ 107 Fault executeLoad(DynInstPtr &inst); 108 109 /** Executes a store. */ 110 Fault executeStore(DynInstPtr &inst); 111 112 /** 113 * Commits loads up until the given sequence number for a specific thread. 114 */ 115 void commitLoads(InstSeqNum &youngest_inst, ThreadID tid) 116 { thread[tid].commitLoads(youngest_inst); } 117 118 /** 119 * Commits stores up until the given sequence number for a specific thread. 120 */ 121 void commitStores(InstSeqNum &youngest_inst, ThreadID tid) 122 { thread[tid].commitStores(youngest_inst); } 123 124 /** 125 * Attempts to write back stores until all cache ports are used or the 126 * interface becomes blocked. 127 */ 128 void writebackStores(); 129 /** Same as above, but only for one thread. */ 130 void writebackStores(ThreadID tid); 131 132 /** 133 * Squash instructions from a thread until the specified sequence number. 134 */ 135 void squash(const InstSeqNum &squashed_num, ThreadID tid) 136 { thread[tid].squash(squashed_num); } 137 138 /** Returns whether or not there was a memory ordering violation. */ 139 bool violation(); 140 /** 141 * Returns whether or not there was a memory ordering violation for a 142 * specific thread. 143 */ 144 bool violation(ThreadID tid) 145 { return thread[tid].violation(); } 146 147 /** Returns if a load is blocked due to the memory system for a specific 148 * thread. 149 */ 150 bool loadBlocked(ThreadID tid) 151 { return thread[tid].loadBlocked(); } 152 153 bool isLoadBlockedHandled(ThreadID tid) 154 { return thread[tid].isLoadBlockedHandled(); } 155 156 void setLoadBlockedHandled(ThreadID tid) 157 { thread[tid].setLoadBlockedHandled(); } 158 159 /** Gets the instruction that caused the memory ordering violation. */ 160 DynInstPtr getMemDepViolator(ThreadID tid) 161 { return thread[tid].getMemDepViolator(); } 162 163 /** Returns the head index of the load queue for a specific thread. */ 164 int getLoadHead(ThreadID tid) 165 { return thread[tid].getLoadHead(); } 166 167 /** Returns the sequence number of the head of the load queue. */ 168 InstSeqNum getLoadHeadSeqNum(ThreadID tid) 169 { 170 return thread[tid].getLoadHeadSeqNum(); 171 } 172 173 /** Returns the head index of the store queue. */ 174 int getStoreHead(ThreadID tid) 175 { return thread[tid].getStoreHead(); } 176 177 /** Returns the sequence number of the head of the store queue. */ 178 InstSeqNum getStoreHeadSeqNum(ThreadID tid) 179 { 180 return thread[tid].getStoreHeadSeqNum(); 181 } 182 183 /** Returns the number of instructions in all of the queues. */ 184 int getCount(); 185 /** Returns the number of instructions in the queues of one thread. */ 186 int getCount(ThreadID tid) 187 { return thread[tid].getCount(); } 188 189 /** Returns the total number of loads in the load queue. */ 190 int numLoads(); 191 /** Returns the total number of loads for a single thread. */ 192 int numLoads(ThreadID tid) 193 { return thread[tid].numLoads(); } 194 195 /** Returns the total number of stores in the store queue. */ 196 int numStores(); 197 /** Returns the total number of stores for a single thread. */ 198 int numStores(ThreadID tid) 199 { return thread[tid].numStores(); } 200 201 /** Returns the number of free entries. */ 202 unsigned numFreeEntries(); 203 /** Returns the number of free entries for a specific thread. */ 204 unsigned numFreeEntries(ThreadID tid); 205 206 /** Returns if the LSQ is full (either LQ or SQ is full). */ 207 bool isFull(); 208 /** 209 * Returns if the LSQ is full for a specific thread (either LQ or SQ is 210 * full). 211 */ 212 bool isFull(ThreadID tid); 213 214 /** Returns if any of the LQs are full. */ 215 bool lqFull(); 216 /** Returns if the LQ of a given thread is full. */ 217 bool lqFull(ThreadID tid); 218 219 /** Returns if any of the SQs are full. */ 220 bool sqFull(); 221 /** Returns if the SQ of a given thread is full. */ 222 bool sqFull(ThreadID tid); 223 224 /** 225 * Returns if the LSQ is stalled due to a memory operation that must be 226 * replayed. 227 */ 228 bool isStalled(); 229 /** 230 * Returns if the LSQ of a specific thread is stalled due to a memory 231 * operation that must be replayed. 232 */ 233 bool isStalled(ThreadID tid); 234 235 /** Returns whether or not there are any stores to write back to memory. */ 236 bool hasStoresToWB(); 237 238 /** Returns whether or not a specific thread has any stores to write back 239 * to memory. 240 */ 241 bool hasStoresToWB(ThreadID tid) 242 { return thread[tid].hasStoresToWB(); } 243 244 /** Returns the number of stores a specific thread has to write back. */ 245 int numStoresToWB(ThreadID tid) 246 { return thread[tid].numStoresToWB(); } 247 248 /** Returns if the LSQ will write back to memory this cycle. */ 249 bool willWB(); 250 /** Returns if the LSQ of a specific thread will write back to memory this 251 * cycle. 252 */ 253 bool willWB(ThreadID tid) 254 { return thread[tid].willWB(); } 255 256 /** Returns if the cache is currently blocked. */ 257 bool cacheBlocked() 258 { return retryTid != InvalidThreadID; } 259 260 /** Sets the retry thread id, indicating that one of the LSQUnits 261 * tried to access the cache but the cache was blocked. */ 262 void setRetryTid(ThreadID tid) 263 { retryTid = tid; } 264 265 /** Debugging function to print out all instructions. */ 266 void dumpInsts(); 267 /** Debugging function to print out instructions from a specific thread. */ 268 void dumpInsts(ThreadID tid) 269 { thread[tid].dumpInsts(); } 270 271 /** Executes a read operation, using the load specified at the load 272 * index. 273 */ 274 Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 275 uint8_t *data, int load_idx); 276 277 /** Executes a store operation, using the store specified at the store 278 * index. 279 */ 280 Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 281 uint8_t *data, int store_idx); 282 283 /** 284 * Retry the previous send that failed. 285 */ 286 void recvRetry(); 287 288 /** 289 * Handles writing back and completing the load or store that has 290 * returned from memory. 291 * 292 * @param pkt Response packet from the memory sub-system 293 */ 294 bool recvTimingResp(PacketPtr pkt); 295 296 void recvTimingSnoopReq(PacketPtr pkt); 297 298 /** The CPU pointer. */ 299 O3CPU *cpu; 300 301 /** The IEW stage pointer. */ 302 IEW *iewStage; 303 304 protected: 305 /** The LSQ policy for SMT mode. */ 306 LSQPolicy lsqPolicy; 307 308 /** The LSQ units for individual threads. */ 309 LSQUnit thread[Impl::MaxThreads]; 310 311 /** List of Active Threads in System. */ 312 std::list<ThreadID> *activeThreads; 313 314 /** Total Size of LQ Entries. */ 315 unsigned LQEntries; 316 /** Total Size of SQ Entries. */ 317 unsigned SQEntries; 318 319 /** Max LQ Size - Used to Enforce Sharing Policies. */ 320 unsigned maxLQEntries; 321 322 /** Max SQ Size - Used to Enforce Sharing Policies. */ 323 unsigned maxSQEntries; 324 325 /** Number of Threads. */ 326 ThreadID numThreads; 327 328 /** The thread id of the LSQ Unit that is currently waiting for a 329 * retry. */ 330 ThreadID retryTid; 331}; 332 333template <class Impl> 334Fault 335LSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 336 uint8_t *data, int load_idx) 337{ 338 ThreadID tid = req->threadId(); 339 340 return thread[tid].read(req, sreqLow, sreqHigh, data, load_idx); 341} 342 343template <class Impl> 344Fault 345LSQ<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 346 uint8_t *data, int store_idx) 347{ 348 ThreadID tid = req->threadId(); 349 350 return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx); 351} 352 353#endif // __CPU_O3_LSQ_HH__ 354