lsq.hh revision 8975
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Korey Sewell 41 */ 42 43#ifndef __CPU_O3_LSQ_HH__ 44#define __CPU_O3_LSQ_HH__ 45 46#include <map> 47#include <queue> 48 49#include "cpu/o3/lsq_unit.hh" 50#include "cpu/inst_seq.hh" 51#include "mem/port.hh" 52#include "sim/sim_object.hh" 53 54struct DerivO3CPUParams; 55 56template <class Impl> 57class LSQ { 58 public: 59 typedef typename Impl::O3CPU O3CPU; 60 typedef typename Impl::DynInstPtr DynInstPtr; 61 typedef typename Impl::CPUPol::IEW IEW; 62 typedef typename Impl::CPUPol::LSQUnit LSQUnit; 63 64 /** SMT policy. */ 65 enum LSQPolicy { 66 Dynamic, 67 Partitioned, 68 Threshold 69 }; 70 71 /** Constructs an LSQ with the given parameters. */ 72 LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params); 73 74 /** Returns the name of the LSQ. */ 75 std::string name() const; 76 77 /** Registers statistics of each LSQ unit. */ 78 void regStats(); 79 80 /** Sets the pointer to the list of active threads. */ 81 void setActiveThreads(std::list<ThreadID> *at_ptr); 82 /** Switches out the LSQ. */ 83 void switchOut(); 84 /** Takes over execution from another CPU's thread. */ 85 void takeOverFrom(); 86 87 /** Number of entries needed for the given amount of threads.*/ 88 int entryAmount(ThreadID num_threads); 89 void removeEntries(ThreadID tid); 90 /** Reset the max entries for each thread. */ 91 void resetEntries(); 92 /** Resize the max entries for a thread. */ 93 void resizeEntries(unsigned size, ThreadID tid); 94 95 /** Ticks the LSQ. */ 96 void tick(); 97 /** Ticks a specific LSQ Unit. */ 98 void tick(ThreadID tid) 99 { thread[tid].tick(); } 100 101 /** Inserts a load into the LSQ. */ 102 void insertLoad(DynInstPtr &load_inst); 103 /** Inserts a store into the LSQ. */ 104 void insertStore(DynInstPtr &store_inst); 105 106 /** Executes a load. */ 107 Fault executeLoad(DynInstPtr &inst); 108 109 /** Executes a store. */ 110 Fault executeStore(DynInstPtr &inst); 111 112 /** 113 * Commits loads up until the given sequence number for a specific thread. 114 */ 115 void commitLoads(InstSeqNum &youngest_inst, ThreadID tid) 116 { thread[tid].commitLoads(youngest_inst); } 117 118 /** 119 * Commits stores up until the given sequence number for a specific thread. 120 */ 121 void commitStores(InstSeqNum &youngest_inst, ThreadID tid) 122 { thread[tid].commitStores(youngest_inst); } 123 124 /** 125 * Attempts to write back stores until all cache ports are used or the 126 * interface becomes blocked. 127 */ 128 void writebackStores(); 129 /** Same as above, but only for one thread. */ 130 void writebackStores(ThreadID tid); 131 132 /** 133 * Squash instructions from a thread until the specified sequence number. 134 */ 135 void squash(const InstSeqNum &squashed_num, ThreadID tid) 136 { thread[tid].squash(squashed_num); } 137 138 /** Returns whether or not there was a memory ordering violation. */ 139 bool violation(); 140 /** 141 * Returns whether or not there was a memory ordering violation for a 142 * specific thread. 143 */ 144 bool violation(ThreadID tid) 145 { return thread[tid].violation(); } 146 147 /** Returns if a load is blocked due to the memory system for a specific 148 * thread. 149 */ 150 bool loadBlocked(ThreadID tid) 151 { return thread[tid].loadBlocked(); } 152 153 bool isLoadBlockedHandled(ThreadID tid) 154 { return thread[tid].isLoadBlockedHandled(); } 155 156 void setLoadBlockedHandled(ThreadID tid) 157 { thread[tid].setLoadBlockedHandled(); } 158 159 /** Gets the instruction that caused the memory ordering violation. */ 160 DynInstPtr getMemDepViolator(ThreadID tid) 161 { return thread[tid].getMemDepViolator(); } 162 163 /** Returns the head index of the load queue for a specific thread. */ 164 int getLoadHead(ThreadID tid) 165 { return thread[tid].getLoadHead(); } 166 167 /** Returns the sequence number of the head of the load queue. */ 168 InstSeqNum getLoadHeadSeqNum(ThreadID tid) 169 { 170 return thread[tid].getLoadHeadSeqNum(); 171 } 172 173 /** Returns the head index of the store queue. */ 174 int getStoreHead(ThreadID tid) 175 { return thread[tid].getStoreHead(); } 176 177 /** Returns the sequence number of the head of the store queue. */ 178 InstSeqNum getStoreHeadSeqNum(ThreadID tid) 179 { 180 return thread[tid].getStoreHeadSeqNum(); 181 } 182 183 /** Returns the number of instructions in all of the queues. */ 184 int getCount(); 185 /** Returns the number of instructions in the queues of one thread. */ 186 int getCount(ThreadID tid) 187 { return thread[tid].getCount(); } 188 189 /** Returns the total number of loads in the load queue. */ 190 int numLoads(); 191 /** Returns the total number of loads for a single thread. */ 192 int numLoads(ThreadID tid) 193 { return thread[tid].numLoads(); } 194 195 /** Returns the total number of stores in the store queue. */ 196 int numStores(); 197 /** Returns the total number of stores for a single thread. */ 198 int numStores(ThreadID tid) 199 { return thread[tid].numStores(); } 200 201 /** Returns the total number of loads that are ready. */ 202 int numLoadsReady(); 203 /** Returns the number of loads that are ready for a single thread. */ 204 int numLoadsReady(ThreadID tid) 205 { return thread[tid].numLoadsReady(); } 206 207 /** Returns the number of free entries. */ 208 unsigned numFreeEntries(); 209 /** Returns the number of free entries for a specific thread. */ 210 unsigned numFreeEntries(ThreadID tid); 211 212 /** Returns if the LSQ is full (either LQ or SQ is full). */ 213 bool isFull(); 214 /** 215 * Returns if the LSQ is full for a specific thread (either LQ or SQ is 216 * full). 217 */ 218 bool isFull(ThreadID tid); 219 220 /** Returns if any of the LQs are full. */ 221 bool lqFull(); 222 /** Returns if the LQ of a given thread is full. */ 223 bool lqFull(ThreadID tid); 224 225 /** Returns if any of the SQs are full. */ 226 bool sqFull(); 227 /** Returns if the SQ of a given thread is full. */ 228 bool sqFull(ThreadID tid); 229 230 /** 231 * Returns if the LSQ is stalled due to a memory operation that must be 232 * replayed. 233 */ 234 bool isStalled(); 235 /** 236 * Returns if the LSQ of a specific thread is stalled due to a memory 237 * operation that must be replayed. 238 */ 239 bool isStalled(ThreadID tid); 240 241 /** Returns whether or not there are any stores to write back to memory. */ 242 bool hasStoresToWB(); 243 244 /** Returns whether or not a specific thread has any stores to write back 245 * to memory. 246 */ 247 bool hasStoresToWB(ThreadID tid) 248 { return thread[tid].hasStoresToWB(); } 249 250 /** Returns the number of stores a specific thread has to write back. */ 251 int numStoresToWB(ThreadID tid) 252 { return thread[tid].numStoresToWB(); } 253 254 /** Returns if the LSQ will write back to memory this cycle. */ 255 bool willWB(); 256 /** Returns if the LSQ of a specific thread will write back to memory this 257 * cycle. 258 */ 259 bool willWB(ThreadID tid) 260 { return thread[tid].willWB(); } 261 262 /** Returns if the cache is currently blocked. */ 263 bool cacheBlocked() 264 { return retryTid != InvalidThreadID; } 265 266 /** Sets the retry thread id, indicating that one of the LSQUnits 267 * tried to access the cache but the cache was blocked. */ 268 void setRetryTid(ThreadID tid) 269 { retryTid = tid; } 270 271 /** Debugging function to print out all instructions. */ 272 void dumpInsts(); 273 /** Debugging function to print out instructions from a specific thread. */ 274 void dumpInsts(ThreadID tid) 275 { thread[tid].dumpInsts(); } 276 277 /** Executes a read operation, using the load specified at the load 278 * index. 279 */ 280 Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 281 uint8_t *data, int load_idx); 282 283 /** Executes a store operation, using the store specified at the store 284 * index. 285 */ 286 Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 287 uint8_t *data, int store_idx); 288 289 /** 290 * Retry the previous send that failed. 291 */ 292 void recvRetry(); 293 294 /** 295 * Handles writing back and completing the load or store that has 296 * returned from memory. 297 * 298 * @param pkt Response packet from the memory sub-system 299 */ 300 bool recvTimingResp(PacketPtr pkt); 301 302 void recvTimingSnoopReq(PacketPtr pkt); 303 304 /** The CPU pointer. */ 305 O3CPU *cpu; 306 307 /** The IEW stage pointer. */ 308 IEW *iewStage; 309 310 protected: 311 /** The LSQ policy for SMT mode. */ 312 LSQPolicy lsqPolicy; 313 314 /** The LSQ units for individual threads. */ 315 LSQUnit thread[Impl::MaxThreads]; 316 317 /** List of Active Threads in System. */ 318 std::list<ThreadID> *activeThreads; 319 320 /** Total Size of LQ Entries. */ 321 unsigned LQEntries; 322 /** Total Size of SQ Entries. */ 323 unsigned SQEntries; 324 325 /** Max LQ Size - Used to Enforce Sharing Policies. */ 326 unsigned maxLQEntries; 327 328 /** Max SQ Size - Used to Enforce Sharing Policies. */ 329 unsigned maxSQEntries; 330 331 /** Number of Threads. */ 332 ThreadID numThreads; 333 334 /** The thread id of the LSQ Unit that is currently waiting for a 335 * retry. */ 336 ThreadID retryTid; 337}; 338 339template <class Impl> 340Fault 341LSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 342 uint8_t *data, int load_idx) 343{ 344 ThreadID tid = req->threadId(); 345 346 return thread[tid].read(req, sreqLow, sreqHigh, data, load_idx); 347} 348 349template <class Impl> 350Fault 351LSQ<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 352 uint8_t *data, int store_idx) 353{ 354 ThreadID tid = req->threadId(); 355 356 return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx); 357} 358 359#endif // __CPU_O3_LSQ_HH__ 360