lsq.hh revision 8737
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Korey Sewell 41 */ 42 43#ifndef __CPU_O3_LSQ_HH__ 44#define __CPU_O3_LSQ_HH__ 45 46#include <map> 47#include <queue> 48 49#include "config/full_system.hh" 50#include "cpu/o3/lsq_unit.hh" 51#include "cpu/inst_seq.hh" 52#include "mem/port.hh" 53#include "sim/sim_object.hh" 54 55struct DerivO3CPUParams; 56 57template <class Impl> 58class LSQ { 59 public: 60 typedef typename Impl::O3CPU O3CPU; 61 typedef typename Impl::DynInstPtr DynInstPtr; 62 typedef typename Impl::CPUPol::IEW IEW; 63 typedef typename Impl::CPUPol::LSQUnit LSQUnit; 64 65 /** SMT policy. */ 66 enum LSQPolicy { 67 Dynamic, 68 Partitioned, 69 Threshold 70 }; 71 72 /** Constructs an LSQ with the given parameters. */ 73 LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params); 74 75 /** Returns the name of the LSQ. */ 76 std::string name() const; 77 78 /** Registers statistics of each LSQ unit. */ 79 void regStats(); 80 81 /** Sets the pointer to the list of active threads. */ 82 void setActiveThreads(std::list<ThreadID> *at_ptr); 83 /** Switches out the LSQ. */ 84 void switchOut(); 85 /** Takes over execution from another CPU's thread. */ 86 void takeOverFrom(); 87 88 /** Number of entries needed for the given amount of threads.*/ 89 int entryAmount(ThreadID num_threads); 90 void removeEntries(ThreadID tid); 91 /** Reset the max entries for each thread. */ 92 void resetEntries(); 93 /** Resize the max entries for a thread. */ 94 void resizeEntries(unsigned size, ThreadID tid); 95 96 /** Ticks the LSQ. */ 97 void tick(); 98 /** Ticks a specific LSQ Unit. */ 99 void tick(ThreadID tid) 100 { thread[tid].tick(); } 101 102 /** Inserts a load into the LSQ. */ 103 void insertLoad(DynInstPtr &load_inst); 104 /** Inserts a store into the LSQ. */ 105 void insertStore(DynInstPtr &store_inst); 106 107 /** Executes a load. */ 108 Fault executeLoad(DynInstPtr &inst); 109 110 /** Executes a store. */ 111 Fault executeStore(DynInstPtr &inst); 112 113 /** 114 * Commits loads up until the given sequence number for a specific thread. 115 */ 116 void commitLoads(InstSeqNum &youngest_inst, ThreadID tid) 117 { thread[tid].commitLoads(youngest_inst); } 118 119 /** 120 * Commits stores up until the given sequence number for a specific thread. 121 */ 122 void commitStores(InstSeqNum &youngest_inst, ThreadID tid) 123 { thread[tid].commitStores(youngest_inst); } 124 125 /** 126 * Attempts to write back stores until all cache ports are used or the 127 * interface becomes blocked. 128 */ 129 void writebackStores(); 130 /** Same as above, but only for one thread. */ 131 void writebackStores(ThreadID tid); 132 133 /** 134 * Squash instructions from a thread until the specified sequence number. 135 */ 136 void squash(const InstSeqNum &squashed_num, ThreadID tid) 137 { thread[tid].squash(squashed_num); } 138 139 /** Returns whether or not there was a memory ordering violation. */ 140 bool violation(); 141 /** 142 * Returns whether or not there was a memory ordering violation for a 143 * specific thread. 144 */ 145 bool violation(ThreadID tid) 146 { return thread[tid].violation(); } 147 148 /** Returns if a load is blocked due to the memory system for a specific 149 * thread. 150 */ 151 bool loadBlocked(ThreadID tid) 152 { return thread[tid].loadBlocked(); } 153 154 bool isLoadBlockedHandled(ThreadID tid) 155 { return thread[tid].isLoadBlockedHandled(); } 156 157 void setLoadBlockedHandled(ThreadID tid) 158 { thread[tid].setLoadBlockedHandled(); } 159 160 /** Gets the instruction that caused the memory ordering violation. */ 161 DynInstPtr getMemDepViolator(ThreadID tid) 162 { return thread[tid].getMemDepViolator(); } 163 164 /** Returns the head index of the load queue for a specific thread. */ 165 int getLoadHead(ThreadID tid) 166 { return thread[tid].getLoadHead(); } 167 168 /** Returns the sequence number of the head of the load queue. */ 169 InstSeqNum getLoadHeadSeqNum(ThreadID tid) 170 { 171 return thread[tid].getLoadHeadSeqNum(); 172 } 173 174 /** Returns the head index of the store queue. */ 175 int getStoreHead(ThreadID tid) 176 { return thread[tid].getStoreHead(); } 177 178 /** Returns the sequence number of the head of the store queue. */ 179 InstSeqNum getStoreHeadSeqNum(ThreadID tid) 180 { 181 return thread[tid].getStoreHeadSeqNum(); 182 } 183 184 /** Returns the number of instructions in all of the queues. */ 185 int getCount(); 186 /** Returns the number of instructions in the queues of one thread. */ 187 int getCount(ThreadID tid) 188 { return thread[tid].getCount(); } 189 190 /** Returns the total number of loads in the load queue. */ 191 int numLoads(); 192 /** Returns the total number of loads for a single thread. */ 193 int numLoads(ThreadID tid) 194 { return thread[tid].numLoads(); } 195 196 /** Returns the total number of stores in the store queue. */ 197 int numStores(); 198 /** Returns the total number of stores for a single thread. */ 199 int numStores(ThreadID tid) 200 { return thread[tid].numStores(); } 201 202 /** Returns the total number of loads that are ready. */ 203 int numLoadsReady(); 204 /** Returns the number of loads that are ready for a single thread. */ 205 int numLoadsReady(ThreadID tid) 206 { return thread[tid].numLoadsReady(); } 207 208 /** Returns the number of free entries. */ 209 unsigned numFreeEntries(); 210 /** Returns the number of free entries for a specific thread. */ 211 unsigned numFreeEntries(ThreadID tid); 212 213 /** Returns if the LSQ is full (either LQ or SQ is full). */ 214 bool isFull(); 215 /** 216 * Returns if the LSQ is full for a specific thread (either LQ or SQ is 217 * full). 218 */ 219 bool isFull(ThreadID tid); 220 221 /** Returns if any of the LQs are full. */ 222 bool lqFull(); 223 /** Returns if the LQ of a given thread is full. */ 224 bool lqFull(ThreadID tid); 225 226 /** Returns if any of the SQs are full. */ 227 bool sqFull(); 228 /** Returns if the SQ of a given thread is full. */ 229 bool sqFull(ThreadID tid); 230 231 /** 232 * Returns if the LSQ is stalled due to a memory operation that must be 233 * replayed. 234 */ 235 bool isStalled(); 236 /** 237 * Returns if the LSQ of a specific thread is stalled due to a memory 238 * operation that must be replayed. 239 */ 240 bool isStalled(ThreadID tid); 241 242 /** Returns whether or not there are any stores to write back to memory. */ 243 bool hasStoresToWB(); 244 245 /** Returns whether or not a specific thread has any stores to write back 246 * to memory. 247 */ 248 bool hasStoresToWB(ThreadID tid) 249 { return thread[tid].hasStoresToWB(); } 250 251 /** Returns the number of stores a specific thread has to write back. */ 252 int numStoresToWB(ThreadID tid) 253 { return thread[tid].numStoresToWB(); } 254 255 /** Returns if the LSQ will write back to memory this cycle. */ 256 bool willWB(); 257 /** Returns if the LSQ of a specific thread will write back to memory this 258 * cycle. 259 */ 260 bool willWB(ThreadID tid) 261 { return thread[tid].willWB(); } 262 263 /** Returns if the cache is currently blocked. */ 264 bool cacheBlocked() 265 { return retryTid != InvalidThreadID; } 266 267 /** Sets the retry thread id, indicating that one of the LSQUnits 268 * tried to access the cache but the cache was blocked. */ 269 void setRetryTid(ThreadID tid) 270 { retryTid = tid; } 271 272 /** Debugging function to print out all instructions. */ 273 void dumpInsts(); 274 /** Debugging function to print out instructions from a specific thread. */ 275 void dumpInsts(ThreadID tid) 276 { thread[tid].dumpInsts(); } 277 278 /** Executes a read operation, using the load specified at the load 279 * index. 280 */ 281 Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 282 uint8_t *data, int load_idx); 283 284 /** Executes a store operation, using the store specified at the store 285 * index. 286 */ 287 Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 288 uint8_t *data, int store_idx); 289 290 /** 291 * Retry the previous send that failed. 292 */ 293 void recvRetry(); 294 295 /** 296 * Handles writing back and completing the load or store that has 297 * returned from memory. 298 * 299 * @param pkt Response packet from the memory sub-system 300 */ 301 bool recvTiming(PacketPtr pkt); 302 303 /** The CPU pointer. */ 304 O3CPU *cpu; 305 306 /** The IEW stage pointer. */ 307 IEW *iewStage; 308 309 protected: 310 /** The LSQ policy for SMT mode. */ 311 LSQPolicy lsqPolicy; 312 313 /** The LSQ units for individual threads. */ 314 LSQUnit thread[Impl::MaxThreads]; 315 316 /** List of Active Threads in System. */ 317 std::list<ThreadID> *activeThreads; 318 319 /** Total Size of LQ Entries. */ 320 unsigned LQEntries; 321 /** Total Size of SQ Entries. */ 322 unsigned SQEntries; 323 324 /** Max LQ Size - Used to Enforce Sharing Policies. */ 325 unsigned maxLQEntries; 326 327 /** Max SQ Size - Used to Enforce Sharing Policies. */ 328 unsigned maxSQEntries; 329 330 /** Number of Threads. */ 331 ThreadID numThreads; 332 333 /** The thread id of the LSQ Unit that is currently waiting for a 334 * retry. */ 335 ThreadID retryTid; 336}; 337 338template <class Impl> 339Fault 340LSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 341 uint8_t *data, int load_idx) 342{ 343 ThreadID tid = req->threadId(); 344 345 return thread[tid].read(req, sreqLow, sreqHigh, data, load_idx); 346} 347 348template <class Impl> 349Fault 350LSQ<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 351 uint8_t *data, int store_idx) 352{ 353 ThreadID tid = req->threadId(); 354 355 return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx); 356} 357 358#endif // __CPU_O3_LSQ_HH__ 359