lsq.hh revision 8707:489489c67fd9
16184SN/A/* 26184SN/A * Copyright (c) 2011 ARM Limited 36184SN/A * All rights reserved 46184SN/A * 56184SN/A * The license below extends only to copyright in the software and shall 66184SN/A * not be construed as granting a license to any other intellectual 76184SN/A * property including but not limited to intellectual property relating 86184SN/A * to a hardware implementation of the functionality of the software 96184SN/A * licensed hereunder. You may use the software subject to the license 106184SN/A * terms below provided that you ensure that this notice is replicated 116184SN/A * unmodified and in its entirety in all distributions of the software, 126184SN/A * modified or unmodified, in source code or in binary form. 136184SN/A * 146184SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 156184SN/A * All rights reserved. 166184SN/A * 176184SN/A * Redistribution and use in source and binary forms, with or without 186184SN/A * modification, are permitted provided that the following conditions are 196184SN/A * met: redistributions of source code must retain the above copyright 206184SN/A * notice, this list of conditions and the following disclaimer; 216184SN/A * redistributions in binary form must reproduce the above copyright 226184SN/A * notice, this list of conditions and the following disclaimer in the 236184SN/A * documentation and/or other materials provided with the distribution; 246184SN/A * neither the name of the copyright holders nor the names of its 256184SN/A * contributors may be used to endorse or promote products derived from 266184SN/A * this software without specific prior written permission. 276184SN/A * 286184SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296184SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306184SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3111793Sbrandon.potter@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3211793Sbrandon.potter@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336184SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3412334Sgabeblack@google.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356184SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 368232Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376184SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3810785Sgope@wisc.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399480Snilay@cs.wisc.edu * 409480Snilay@cs.wisc.edu * Authors: Korey Sewell 4113959Sodanrc@yahoo.com.br */ 4213959Sodanrc@yahoo.com.br 4313959Sodanrc@yahoo.com.br#ifndef __CPU_O3_LSQ_HH__ 4413959Sodanrc@yahoo.com.br#define __CPU_O3_LSQ_HH__ 456184SN/A 466184SN/A#include <map> 476184SN/A#include <queue> 486184SN/A 496184SN/A#include "config/full_system.hh" 506184SN/A#include "cpu/o3/lsq_unit.hh" 516184SN/A#include "cpu/inst_seq.hh" 526184SN/A#include "mem/port.hh" 536184SN/A#include "sim/sim_object.hh" 549480Snilay@cs.wisc.edu 556184SN/Aclass DerivO3CPUParams; 569480Snilay@cs.wisc.edu 576184SN/Atemplate <class Impl> 586184SN/Aclass LSQ { 599480Snilay@cs.wisc.edu public: 606184SN/A typedef typename Impl::O3CPU O3CPU; 619480Snilay@cs.wisc.edu typedef typename Impl::DynInstPtr DynInstPtr; 626184SN/A typedef typename Impl::CPUPol::IEW IEW; 636184SN/A typedef typename Impl::CPUPol::LSQUnit LSQUnit; 646184SN/A 656184SN/A /** SMT policy. */ 6611434Smitch.hayenga@arm.com enum LSQPolicy { 678842Smrinmoy.ghosh@arm.com Dynamic, 688842Smrinmoy.ghosh@arm.com Partitioned, 698842Smrinmoy.ghosh@arm.com Threshold 708842Smrinmoy.ghosh@arm.com }; 718842Smrinmoy.ghosh@arm.com 728842Smrinmoy.ghosh@arm.com /** Constructs an LSQ with the given parameters. */ 736184SN/A LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params); 7411434Smitch.hayenga@arm.com 756184SN/A /** Returns the name of the LSQ. */ 766184SN/A std::string name() const; 776184SN/A 786184SN/A /** Registers statistics of each LSQ unit. */ 799480Snilay@cs.wisc.edu void regStats(); 806184SN/A 816184SN/A /** Sets the pointer to the list of active threads. */ 8213959Sodanrc@yahoo.com.br void setActiveThreads(std::list<ThreadID> *at_ptr); 836184SN/A /** Switches out the LSQ. */ 849480Snilay@cs.wisc.edu void switchOut(); 856184SN/A /** Takes over execution from another CPU's thread. */ 866184SN/A void takeOverFrom(); 876184SN/A 886184SN/A /** Number of entries needed for the given amount of threads.*/ 896184SN/A int entryAmount(ThreadID num_threads); 906184SN/A void removeEntries(ThreadID tid); 916184SN/A /** Reset the max entries for each thread. */ 929480Snilay@cs.wisc.edu void resetEntries(); 9313959Sodanrc@yahoo.com.br /** Resize the max entries for a thread. */ 946184SN/A void resizeEntries(unsigned size, ThreadID tid); 959480Snilay@cs.wisc.edu 9613959Sodanrc@yahoo.com.br /** Ticks the LSQ. */ 976184SN/A void tick(); 986184SN/A /** Ticks a specific LSQ Unit. */ 996184SN/A void tick(ThreadID tid) 1006184SN/A { thread[tid].tick(); } 1016184SN/A 1026184SN/A /** Inserts a load into the LSQ. */ 1036184SN/A void insertLoad(DynInstPtr &load_inst); 10411434Smitch.hayenga@arm.com /** Inserts a store into the LSQ. */ 10513626Sjairo.balart@metempsy.com void insertStore(DynInstPtr &store_inst); 1066184SN/A 1076184SN/A /** Executes a load. */ 1086184SN/A Fault executeLoad(DynInstPtr &inst); 1096184SN/A 11011783Sarthur.perais@inria.fr /** Executes a store. */ 11111783Sarthur.perais@inria.fr Fault executeStore(DynInstPtr &inst); 11211783Sarthur.perais@inria.fr 11311783Sarthur.perais@inria.fr /** 11411783Sarthur.perais@inria.fr * Commits loads up until the given sequence number for a specific thread. 11511783Sarthur.perais@inria.fr */ 1166184SN/A void commitLoads(InstSeqNum &youngest_inst, ThreadID tid) 1176184SN/A { thread[tid].commitLoads(youngest_inst); } 1186184SN/A 1199480Snilay@cs.wisc.edu /** 1206184SN/A * Commits stores up until the given sequence number for a specific thread. 1216184SN/A */ 1229480Snilay@cs.wisc.edu void commitStores(InstSeqNum &youngest_inst, ThreadID tid) 12313959Sodanrc@yahoo.com.br { thread[tid].commitStores(youngest_inst); } 1246184SN/A 1259480Snilay@cs.wisc.edu /** 12613959Sodanrc@yahoo.com.br * Attempts to write back stores until all cache ports are used or the 1276184SN/A * interface becomes blocked. 1286184SN/A */ 1296184SN/A void writebackStores(); 1306184SN/A /** Same as above, but only for one thread. */ 1316184SN/A void writebackStores(ThreadID tid); 1326184SN/A 1336184SN/A /** 1346184SN/A * Squash instructions from a thread until the specified sequence number. 1356184SN/A */ 1366184SN/A void squash(const InstSeqNum &squashed_num, ThreadID tid) 1376184SN/A { thread[tid].squash(squashed_num); } 1386184SN/A 1396184SN/A /** Returns whether or not there was a memory ordering violation. */ 1406184SN/A bool violation(); 1416184SN/A /** 1426184SN/A * Returns whether or not there was a memory ordering violation for a 1436184SN/A * specific thread. 1449480Snilay@cs.wisc.edu */ 1459480Snilay@cs.wisc.edu bool violation(ThreadID tid) 14611434Smitch.hayenga@arm.com { return thread[tid].violation(); } 1479480Snilay@cs.wisc.edu 1489480Snilay@cs.wisc.edu /** Returns if a load is blocked due to the memory system for a specific 14910785Sgope@wisc.edu * thread. 15010785Sgope@wisc.edu */ 15110785Sgope@wisc.edu bool loadBlocked(ThreadID tid) 15210785Sgope@wisc.edu { return thread[tid].loadBlocked(); } 15310785Sgope@wisc.edu 15410785Sgope@wisc.edu bool isLoadBlockedHandled(ThreadID tid) 155 { return thread[tid].isLoadBlockedHandled(); } 156 157 void setLoadBlockedHandled(ThreadID tid) 158 { thread[tid].setLoadBlockedHandled(); } 159 160 /** Gets the instruction that caused the memory ordering violation. */ 161 DynInstPtr getMemDepViolator(ThreadID tid) 162 { return thread[tid].getMemDepViolator(); } 163 164 /** Returns the head index of the load queue for a specific thread. */ 165 int getLoadHead(ThreadID tid) 166 { return thread[tid].getLoadHead(); } 167 168 /** Returns the sequence number of the head of the load queue. */ 169 InstSeqNum getLoadHeadSeqNum(ThreadID tid) 170 { 171 return thread[tid].getLoadHeadSeqNum(); 172 } 173 174 /** Returns the head index of the store queue. */ 175 int getStoreHead(ThreadID tid) 176 { return thread[tid].getStoreHead(); } 177 178 /** Returns the sequence number of the head of the store queue. */ 179 InstSeqNum getStoreHeadSeqNum(ThreadID tid) 180 { 181 return thread[tid].getStoreHeadSeqNum(); 182 } 183 184 /** Returns the number of instructions in all of the queues. */ 185 int getCount(); 186 /** Returns the number of instructions in the queues of one thread. */ 187 int getCount(ThreadID tid) 188 { return thread[tid].getCount(); } 189 190 /** Returns the total number of loads in the load queue. */ 191 int numLoads(); 192 /** Returns the total number of loads for a single thread. */ 193 int numLoads(ThreadID tid) 194 { return thread[tid].numLoads(); } 195 196 /** Returns the total number of stores in the store queue. */ 197 int numStores(); 198 /** Returns the total number of stores for a single thread. */ 199 int numStores(ThreadID tid) 200 { return thread[tid].numStores(); } 201 202 /** Returns the total number of loads that are ready. */ 203 int numLoadsReady(); 204 /** Returns the number of loads that are ready for a single thread. */ 205 int numLoadsReady(ThreadID tid) 206 { return thread[tid].numLoadsReady(); } 207 208 /** Returns the number of free entries. */ 209 unsigned numFreeEntries(); 210 /** Returns the number of free entries for a specific thread. */ 211 unsigned numFreeEntries(ThreadID tid); 212 213 /** Returns if the LSQ is full (either LQ or SQ is full). */ 214 bool isFull(); 215 /** 216 * Returns if the LSQ is full for a specific thread (either LQ or SQ is 217 * full). 218 */ 219 bool isFull(ThreadID tid); 220 221 /** Returns if any of the LQs are full. */ 222 bool lqFull(); 223 /** Returns if the LQ of a given thread is full. */ 224 bool lqFull(ThreadID tid); 225 226 /** Returns if any of the SQs are full. */ 227 bool sqFull(); 228 /** Returns if the SQ of a given thread is full. */ 229 bool sqFull(ThreadID tid); 230 231 /** 232 * Returns if the LSQ is stalled due to a memory operation that must be 233 * replayed. 234 */ 235 bool isStalled(); 236 /** 237 * Returns if the LSQ of a specific thread is stalled due to a memory 238 * operation that must be replayed. 239 */ 240 bool isStalled(ThreadID tid); 241 242 /** Returns whether or not there are any stores to write back to memory. */ 243 bool hasStoresToWB(); 244 245 /** Returns whether or not a specific thread has any stores to write back 246 * to memory. 247 */ 248 bool hasStoresToWB(ThreadID tid) 249 { return thread[tid].hasStoresToWB(); } 250 251 /** Returns the number of stores a specific thread has to write back. */ 252 int numStoresToWB(ThreadID tid) 253 { return thread[tid].numStoresToWB(); } 254 255 /** Returns if the LSQ will write back to memory this cycle. */ 256 bool willWB(); 257 /** Returns if the LSQ of a specific thread will write back to memory this 258 * cycle. 259 */ 260 bool willWB(ThreadID tid) 261 { return thread[tid].willWB(); } 262 263 /** Returns if the cache is currently blocked. */ 264 bool cacheBlocked() 265 { return retryTid != InvalidThreadID; } 266 267 /** Sets the retry thread id, indicating that one of the LSQUnits 268 * tried to access the cache but the cache was blocked. */ 269 void setRetryTid(ThreadID tid) 270 { retryTid = tid; } 271 272 /** Debugging function to print out all instructions. */ 273 void dumpInsts(); 274 /** Debugging function to print out instructions from a specific thread. */ 275 void dumpInsts(ThreadID tid) 276 { thread[tid].dumpInsts(); } 277 278 /** Executes a read operation, using the load specified at the load 279 * index. 280 */ 281 Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 282 uint8_t *data, int load_idx); 283 284 /** Executes a store operation, using the store specified at the store 285 * index. 286 */ 287 Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 288 uint8_t *data, int store_idx); 289 290 /** 291 * Retry the previous send that failed. 292 */ 293 void recvRetry(); 294 295 /** 296 * Handles writing back and completing the load or store that has 297 * returned from memory. 298 * 299 * @param pkt Response packet from the memory sub-system 300 */ 301 bool recvTiming(PacketPtr pkt); 302 303 /** The CPU pointer. */ 304 O3CPU *cpu; 305 306 /** The IEW stage pointer. */ 307 IEW *iewStage; 308 309 protected: 310 /** The LSQ policy for SMT mode. */ 311 LSQPolicy lsqPolicy; 312 313 /** The LSQ units for individual threads. */ 314 LSQUnit thread[Impl::MaxThreads]; 315 316 /** List of Active Threads in System. */ 317 std::list<ThreadID> *activeThreads; 318 319 /** Total Size of LQ Entries. */ 320 unsigned LQEntries; 321 /** Total Size of SQ Entries. */ 322 unsigned SQEntries; 323 324 /** Max LQ Size - Used to Enforce Sharing Policies. */ 325 unsigned maxLQEntries; 326 327 /** Max SQ Size - Used to Enforce Sharing Policies. */ 328 unsigned maxSQEntries; 329 330 /** Number of Threads. */ 331 ThreadID numThreads; 332 333 /** The thread id of the LSQ Unit that is currently waiting for a 334 * retry. */ 335 ThreadID retryTid; 336}; 337 338template <class Impl> 339Fault 340LSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 341 uint8_t *data, int load_idx) 342{ 343 ThreadID tid = req->threadId(); 344 345 return thread[tid].read(req, sreqLow, sreqHigh, data, load_idx); 346} 347 348template <class Impl> 349Fault 350LSQ<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 351 uint8_t *data, int store_idx) 352{ 353 ThreadID tid = req->threadId(); 354 355 return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx); 356} 357 358#endif // __CPU_O3_LSQ_HH__ 359