lsq.hh revision 4329:52057dbec096 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 */
30
31#ifndef __CPU_O3_LSQ_HH__
32#define __CPU_O3_LSQ_HH__
33
34#include <map>
35#include <queue>
36
37#include "config/full_system.hh"
38#include "cpu/inst_seq.hh"
39#include "cpu/o3/lsq_unit.hh"
40#include "mem/port.hh"
41#include "sim/sim_object.hh"
42
43template <class Impl>
44class LSQ {
45  public:
46    typedef typename Impl::Params Params;
47    typedef typename Impl::O3CPU O3CPU;
48    typedef typename Impl::DynInstPtr DynInstPtr;
49    typedef typename Impl::CPUPol::IEW IEW;
50    typedef typename Impl::CPUPol::LSQUnit LSQUnit;
51
52    /** SMT policy. */
53    enum LSQPolicy {
54        Dynamic,
55        Partitioned,
56        Threshold
57    };
58
59    /** Constructs an LSQ with the given parameters. */
60    LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params);
61
62    /** Returns the name of the LSQ. */
63    std::string name() const;
64
65    /** Registers statistics of each LSQ unit. */
66    void regStats();
67
68    /** Returns dcache port.
69     *  @todo: Dcache port needs to be moved up to this level for SMT
70     *  to work.  For now it just returns the port from one of the
71     *  threads.
72     */
73    Port *getDcachePort() { return &dcachePort; }
74
75    /** Sets the pointer to the list of active threads. */
76    void setActiveThreads(std::list<unsigned> *at_ptr);
77    /** Switches out the LSQ. */
78    void switchOut();
79    /** Takes over execution from another CPU's thread. */
80    void takeOverFrom();
81
82    /** Number of entries needed for the given amount of threads.*/
83    int entryAmount(int num_threads);
84    void removeEntries(unsigned tid);
85    /** Reset the max entries for each thread. */
86    void resetEntries();
87    /** Resize the max entries for a thread. */
88    void resizeEntries(unsigned size, unsigned tid);
89
90    /** Ticks the LSQ. */
91    void tick();
92    /** Ticks a specific LSQ Unit. */
93    void tick(unsigned tid)
94    { thread[tid].tick(); }
95
96    /** Inserts a load into the LSQ. */
97    void insertLoad(DynInstPtr &load_inst);
98    /** Inserts a store into the LSQ. */
99    void insertStore(DynInstPtr &store_inst);
100
101    /** Executes a load. */
102    Fault executeLoad(DynInstPtr &inst);
103
104    /** Executes a store. */
105    Fault executeStore(DynInstPtr &inst);
106
107    /**
108     * Commits loads up until the given sequence number for a specific thread.
109     */
110    void commitLoads(InstSeqNum &youngest_inst, unsigned tid)
111    { thread[tid].commitLoads(youngest_inst); }
112
113    /**
114     * Commits stores up until the given sequence number for a specific thread.
115     */
116    void commitStores(InstSeqNum &youngest_inst, unsigned tid)
117    { thread[tid].commitStores(youngest_inst); }
118
119    /**
120     * Attempts to write back stores until all cache ports are used or the
121     * interface becomes blocked.
122     */
123    void writebackStores();
124    /** Same as above, but only for one thread. */
125    void writebackStores(unsigned tid);
126
127    /**
128     * Squash instructions from a thread until the specified sequence number.
129     */
130    void squash(const InstSeqNum &squashed_num, unsigned tid)
131    { thread[tid].squash(squashed_num); }
132
133    /** Returns whether or not there was a memory ordering violation. */
134    bool violation();
135    /**
136     * Returns whether or not there was a memory ordering violation for a
137     * specific thread.
138     */
139    bool violation(unsigned tid)
140    { return thread[tid].violation(); }
141
142    /** Returns if a load is blocked due to the memory system for a specific
143     *  thread.
144     */
145    bool loadBlocked(unsigned tid)
146    { return thread[tid].loadBlocked(); }
147
148    bool isLoadBlockedHandled(unsigned tid)
149    { return thread[tid].isLoadBlockedHandled(); }
150
151    void setLoadBlockedHandled(unsigned tid)
152    { thread[tid].setLoadBlockedHandled(); }
153
154    /** Gets the instruction that caused the memory ordering violation. */
155    DynInstPtr getMemDepViolator(unsigned tid)
156    { return thread[tid].getMemDepViolator(); }
157
158    /** Returns the head index of the load queue for a specific thread. */
159    int getLoadHead(unsigned tid)
160    { return thread[tid].getLoadHead(); }
161
162    /** Returns the sequence number of the head of the load queue. */
163    InstSeqNum getLoadHeadSeqNum(unsigned tid)
164    {
165        return thread[tid].getLoadHeadSeqNum();
166    }
167
168    /** Returns the head index of the store queue. */
169    int getStoreHead(unsigned tid)
170    { return thread[tid].getStoreHead(); }
171
172    /** Returns the sequence number of the head of the store queue. */
173    InstSeqNum getStoreHeadSeqNum(unsigned tid)
174    {
175        return thread[tid].getStoreHeadSeqNum();
176    }
177
178    /** Returns the number of instructions in all of the queues. */
179    int getCount();
180    /** Returns the number of instructions in the queues of one thread. */
181    int getCount(unsigned tid)
182    { return thread[tid].getCount(); }
183
184    /** Returns the total number of loads in the load queue. */
185    int numLoads();
186    /** Returns the total number of loads for a single thread. */
187    int numLoads(unsigned tid)
188    { return thread[tid].numLoads(); }
189
190    /** Returns the total number of stores in the store queue. */
191    int numStores();
192    /** Returns the total number of stores for a single thread. */
193    int numStores(unsigned tid)
194    { return thread[tid].numStores(); }
195
196    /** Returns the total number of loads that are ready. */
197    int numLoadsReady();
198    /** Returns the number of loads that are ready for a single thread. */
199    int numLoadsReady(unsigned tid)
200    { return thread[tid].numLoadsReady(); }
201
202    /** Returns the number of free entries. */
203    unsigned numFreeEntries();
204    /** Returns the number of free entries for a specific thread. */
205    unsigned numFreeEntries(unsigned tid);
206
207    /** Returns if the LSQ is full (either LQ or SQ is full). */
208    bool isFull();
209    /**
210     * Returns if the LSQ is full for a specific thread (either LQ or SQ is
211     * full).
212     */
213    bool isFull(unsigned tid);
214
215    /** Returns if any of the LQs are full. */
216    bool lqFull();
217    /** Returns if the LQ of a given thread is full. */
218    bool lqFull(unsigned tid);
219
220    /** Returns if any of the SQs are full. */
221    bool sqFull();
222    /** Returns if the SQ of a given thread is full. */
223    bool sqFull(unsigned tid);
224
225    /**
226     * Returns if the LSQ is stalled due to a memory operation that must be
227     * replayed.
228     */
229    bool isStalled();
230    /**
231     * Returns if the LSQ of a specific thread is stalled due to a memory
232     * operation that must be replayed.
233     */
234    bool isStalled(unsigned tid);
235
236    /** Returns whether or not there are any stores to write back to memory. */
237    bool hasStoresToWB();
238
239    /** Returns whether or not a specific thread has any stores to write back
240     * to memory.
241     */
242    bool hasStoresToWB(unsigned tid)
243    { return thread[tid].hasStoresToWB(); }
244
245    /** Returns the number of stores a specific thread has to write back. */
246    int  numStoresToWB(unsigned tid)
247    { return thread[tid].numStoresToWB(); }
248
249    /** Returns if the LSQ will write back to memory this cycle. */
250    bool willWB();
251    /** Returns if the LSQ of a specific thread will write back to memory this
252     * cycle.
253     */
254    bool willWB(unsigned tid)
255    { return thread[tid].willWB(); }
256
257    /** Returns if the cache is currently blocked. */
258    bool cacheBlocked()
259    { return retryTid != -1; }
260
261    /** Sets the retry thread id, indicating that one of the LSQUnits
262     * tried to access the cache but the cache was blocked. */
263    void setRetryTid(int tid)
264    { retryTid = tid; }
265
266    /** Debugging function to print out all instructions. */
267    void dumpInsts();
268    /** Debugging function to print out instructions from a specific thread. */
269    void dumpInsts(unsigned tid)
270    { thread[tid].dumpInsts(); }
271
272    /** Executes a read operation, using the load specified at the load index. */
273    template <class T>
274    Fault read(RequestPtr req, T &data, int load_idx);
275
276    /** Executes a store operation, using the store specified at the store
277     *   index.
278     */
279    template <class T>
280    Fault write(RequestPtr req, T &data, int store_idx);
281
282    /** The CPU pointer. */
283    O3CPU *cpu;
284
285    /** The IEW stage pointer. */
286    IEW *iewStage;
287
288    /** DcachePort class for this LSQ.  Handles doing the
289     * communication with the cache/memory.
290     */
291    class DcachePort : public Port
292    {
293      protected:
294        /** Pointer to LSQ. */
295        LSQ *lsq;
296
297      public:
298        /** Default constructor. */
299        DcachePort(LSQ *_lsq)
300            : Port(_lsq->name() + "-dport"), lsq(_lsq)
301        { }
302
303        bool snoopRangeSent;
304
305        virtual void setPeer(Port *port);
306
307      protected:
308        /** Atomic version of receive.  Panics. */
309        virtual Tick recvAtomic(PacketPtr pkt);
310
311        /** Functional version of receive.  Panics. */
312        virtual void recvFunctional(PacketPtr pkt);
313
314        /** Receives status change.  Other than range changing, panics. */
315        virtual void recvStatusChange(Status status);
316
317        /** Returns the address ranges of this device. */
318        virtual void getDeviceAddressRanges(AddrRangeList &resp,
319                                            AddrRangeList &snoop)
320        { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); }
321
322        /** Timing version of receive.  Handles writing back and
323         * completing the load or store that has returned from
324         * memory. */
325        virtual bool recvTiming(PacketPtr pkt);
326
327        /** Handles doing a retry of the previous send. */
328        virtual void recvRetry();
329    };
330
331    /** D-cache port. */
332    DcachePort dcachePort;
333
334#if FULL_SYSTEM
335    /** Tell the CPU to update the Phys and Virt ports. */
336    void updateMemPorts() { cpu->updateMemPorts(); }
337#endif
338
339  protected:
340    /** The LSQ policy for SMT mode. */
341    LSQPolicy lsqPolicy;
342
343    /** The LSQ units for individual threads. */
344    LSQUnit thread[Impl::MaxThreads];
345
346    /** List of Active Threads in System. */
347    std::list<unsigned> *activeThreads;
348
349    /** Total Size of LQ Entries. */
350    unsigned LQEntries;
351    /** Total Size of SQ Entries. */
352    unsigned SQEntries;
353
354    /** Max LQ Size - Used to Enforce Sharing Policies. */
355    unsigned maxLQEntries;
356
357    /** Max SQ Size - Used to Enforce Sharing Policies. */
358    unsigned maxSQEntries;
359
360    /** Number of Threads. */
361    unsigned numThreads;
362
363    /** The thread id of the LSQ Unit that is currently waiting for a
364     * retry. */
365    int retryTid;
366};
367
368template <class Impl>
369template <class T>
370Fault
371LSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
372{
373    unsigned tid = req->getThreadNum();
374
375    return thread[tid].read(req, data, load_idx);
376}
377
378template <class Impl>
379template <class T>
380Fault
381LSQ<Impl>::write(RequestPtr req, T &data, int store_idx)
382{
383    unsigned tid = req->getThreadNum();
384
385    return thread[tid].write(req, data, store_idx);
386}
387
388#endif // __CPU_O3_LSQ_HH__
389