lsq.hh revision 2698:d5f35d41e017 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 */
30
31#ifndef __CPU_O3_LSQ_HH__
32#define __CPU_O3_LSQ_HH__
33
34#include <map>
35#include <queue>
36
37#include "config/full_system.hh"
38#include "cpu/inst_seq.hh"
39#include "cpu/o3/lsq_unit.hh"
40#include "mem/port.hh"
41#include "sim/sim_object.hh"
42
43template <class Impl>
44class LSQ {
45  public:
46    typedef typename Impl::Params Params;
47    typedef typename Impl::FullCPU FullCPU;
48    typedef typename Impl::DynInstPtr DynInstPtr;
49    typedef typename Impl::CPUPol::IEW IEW;
50    typedef typename Impl::CPUPol::LSQUnit LSQUnit;
51
52    /** SMT policy. */
53    enum LSQPolicy {
54        Dynamic,
55        Partitioned,
56        Threshold
57    };
58
59    /** Constructs an LSQ with the given parameters. */
60    LSQ(Params *params);
61
62    /** Returns the name of the LSQ. */
63    std::string name() const;
64
65    /** Sets the pointer to the list of active threads. */
66    void setActiveThreads(std::list<unsigned> *at_ptr);
67    /** Sets the CPU pointer. */
68    void setCPU(FullCPU *cpu_ptr);
69    /** Sets the IEW stage pointer. */
70    void setIEW(IEW *iew_ptr);
71    /** Switches out the LSQ. */
72    void switchOut();
73    /** Takes over execution from another CPU's thread. */
74    void takeOverFrom();
75
76    /** Number of entries needed for the given amount of threads.*/
77    int entryAmount(int num_threads);
78    void removeEntries(unsigned tid);
79    /** Reset the max entries for each thread. */
80    void resetEntries();
81    /** Resize the max entries for a thread. */
82    void resizeEntries(unsigned size, unsigned tid);
83
84    /** Ticks the LSQ. */
85    void tick();
86    /** Ticks a specific LSQ Unit. */
87    void tick(unsigned tid)
88    { thread[tid].tick(); }
89
90    /** Inserts a load into the LSQ. */
91    void insertLoad(DynInstPtr &load_inst);
92    /** Inserts a store into the LSQ. */
93    void insertStore(DynInstPtr &store_inst);
94
95    /** Executes a load. */
96    Fault executeLoad(DynInstPtr &inst);
97
98    /** Executes a store. */
99    Fault executeStore(DynInstPtr &inst);
100
101    /**
102     * Commits loads up until the given sequence number for a specific thread.
103     */
104    void commitLoads(InstSeqNum &youngest_inst, unsigned tid)
105    { thread[tid].commitLoads(youngest_inst); }
106
107    /**
108     * Commits stores up until the given sequence number for a specific thread.
109     */
110    void commitStores(InstSeqNum &youngest_inst, unsigned tid)
111    { thread[tid].commitStores(youngest_inst); }
112
113    /**
114     * Attempts to write back stores until all cache ports are used or the
115     * interface becomes blocked.
116     */
117    void writebackStores();
118    /** Same as above, but only for one thread. */
119    void writebackStores(unsigned tid);
120
121    /**
122     * Squash instructions from a thread until the specified sequence number.
123     */
124    void squash(const InstSeqNum &squashed_num, unsigned tid)
125    { thread[tid].squash(squashed_num); }
126
127    /** Returns whether or not there was a memory ordering violation. */
128    bool violation();
129    /**
130     * Returns whether or not there was a memory ordering violation for a
131     * specific thread.
132     */
133    bool violation(unsigned tid)
134    { return thread[tid].violation(); }
135
136    /** Returns if a load is blocked due to the memory system for a specific
137     *  thread.
138     */
139    bool loadBlocked(unsigned tid)
140    { return thread[tid].loadBlocked(); }
141
142    bool isLoadBlockedHandled(unsigned tid)
143    { return thread[tid].isLoadBlockedHandled(); }
144
145    void setLoadBlockedHandled(unsigned tid)
146    { thread[tid].setLoadBlockedHandled(); }
147
148    /** Gets the instruction that caused the memory ordering violation. */
149    DynInstPtr getMemDepViolator(unsigned tid)
150    { return thread[tid].getMemDepViolator(); }
151
152    /** Returns the head index of the load queue for a specific thread. */
153    int getLoadHead(unsigned tid)
154    { return thread[tid].getLoadHead(); }
155
156    /** Returns the sequence number of the head of the load queue. */
157    InstSeqNum getLoadHeadSeqNum(unsigned tid)
158    {
159        return thread[tid].getLoadHeadSeqNum();
160    }
161
162    /** Returns the head index of the store queue. */
163    int getStoreHead(unsigned tid)
164    { return thread[tid].getStoreHead(); }
165
166    /** Returns the sequence number of the head of the store queue. */
167    InstSeqNum getStoreHeadSeqNum(unsigned tid)
168    {
169        return thread[tid].getStoreHeadSeqNum();
170    }
171
172    /** Returns the number of instructions in all of the queues. */
173    int getCount();
174    /** Returns the number of instructions in the queues of one thread. */
175    int getCount(unsigned tid)
176    { return thread[tid].getCount(); }
177
178    /** Returns the total number of loads in the load queue. */
179    int numLoads();
180    /** Returns the total number of loads for a single thread. */
181    int numLoads(unsigned tid)
182    { return thread[tid].numLoads(); }
183
184    /** Returns the total number of stores in the store queue. */
185    int numStores();
186    /** Returns the total number of stores for a single thread. */
187    int numStores(unsigned tid)
188    { return thread[tid].numStores(); }
189
190    /** Returns the total number of loads that are ready. */
191    int numLoadsReady();
192    /** Returns the number of loads that are ready for a single thread. */
193    int numLoadsReady(unsigned tid)
194    { return thread[tid].numLoadsReady(); }
195
196    /** Returns the number of free entries. */
197    unsigned numFreeEntries();
198    /** Returns the number of free entries for a specific thread. */
199    unsigned numFreeEntries(unsigned tid);
200
201    /** Returns if the LSQ is full (either LQ or SQ is full). */
202    bool isFull();
203    /**
204     * Returns if the LSQ is full for a specific thread (either LQ or SQ is
205     * full).
206     */
207    bool isFull(unsigned tid);
208
209    /** Returns if any of the LQs are full. */
210    bool lqFull();
211    /** Returns if the LQ of a given thread is full. */
212    bool lqFull(unsigned tid);
213
214    /** Returns if any of the SQs are full. */
215    bool sqFull();
216    /** Returns if the SQ of a given thread is full. */
217    bool sqFull(unsigned tid);
218
219    /**
220     * Returns if the LSQ is stalled due to a memory operation that must be
221     * replayed.
222     */
223    bool isStalled();
224    /**
225     * Returns if the LSQ of a specific thread is stalled due to a memory
226     * operation that must be replayed.
227     */
228    bool isStalled(unsigned tid);
229
230    /** Returns whether or not there are any stores to write back to memory. */
231    bool hasStoresToWB();
232
233    /** Returns whether or not a specific thread has any stores to write back
234     * to memory.
235     */
236    bool hasStoresToWB(unsigned tid)
237    { return thread[tid].hasStoresToWB(); }
238
239    /** Returns the number of stores a specific thread has to write back. */
240    int  numStoresToWB(unsigned tid)
241    { return thread[tid].numStoresToWB(); }
242
243    /** Returns if the LSQ will write back to memory this cycle. */
244    bool willWB();
245    /** Returns if the LSQ of a specific thread will write back to memory this
246     * cycle.
247     */
248    bool willWB(unsigned tid)
249    { return thread[tid].willWB(); }
250
251    /** Debugging function to print out all instructions. */
252    void dumpInsts();
253    /** Debugging function to print out instructions from a specific thread. */
254    void dumpInsts(unsigned tid)
255    { thread[tid].dumpInsts(); }
256
257    /** Executes a read operation, using the load specified at the load index. */
258    template <class T>
259    Fault read(RequestPtr req, T &data, int load_idx);
260
261    /** Executes a store operation, using the store specified at the store
262     *   index.
263     */
264    template <class T>
265    Fault write(RequestPtr req, T &data, int store_idx);
266
267  private:
268    /** The LSQ policy for SMT mode. */
269    LSQPolicy lsqPolicy;
270
271    /** The LSQ units for individual threads. */
272    LSQUnit thread[Impl::MaxThreads];
273
274    /** The CPU pointer. */
275    FullCPU *cpu;
276
277    /** The IEW stage pointer. */
278    IEW *iewStage;
279
280    /** List of Active Threads in System. */
281    std::list<unsigned> *activeThreads;
282
283    /** Total Size of LQ Entries. */
284    unsigned LQEntries;
285    /** Total Size of SQ Entries. */
286    unsigned SQEntries;
287
288    /** Max LQ Size - Used to Enforce Sharing Policies. */
289    unsigned maxLQEntries;
290
291    /** Max SQ Size - Used to Enforce Sharing Policies. */
292    unsigned maxSQEntries;
293
294    /** Number of Threads. */
295    unsigned numThreads;
296};
297
298template <class Impl>
299template <class T>
300Fault
301LSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
302{
303    unsigned tid = req->getThreadNum();
304
305    return thread[tid].read(req, data, load_idx);
306}
307
308template <class Impl>
309template <class T>
310Fault
311LSQ<Impl>::write(RequestPtr req, T &data, int store_idx)
312{
313    unsigned tid = req->getThreadNum();
314
315    return thread[tid].write(req, data, store_idx);
316}
317
318#endif // __CPU_O3_LSQ_HH__
319