lsq.hh revision 2674:6d4afef73a20
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __CPU_O3_LSQ_HH__ 30#define __CPU_O3_LSQ_HH__ 31 32#include <map> 33#include <queue> 34 35#include "config/full_system.hh" 36#include "cpu/inst_seq.hh" 37//#include "cpu/o3/cpu_policy.hh" 38#include "cpu/o3/lsq_unit.hh" 39#include "mem/port.hh" 40//#include "mem/page_table.hh" 41#include "sim/sim_object.hh" 42 43template <class Impl> 44class LSQ { 45 public: 46 typedef typename Impl::Params Params; 47 typedef typename Impl::FullCPU FullCPU; 48 typedef typename Impl::DynInstPtr DynInstPtr; 49 typedef typename Impl::CPUPol::IEW IEW; 50 typedef typename Impl::CPUPol::LSQUnit LSQUnit; 51 52 /** SMT policy. */ 53 enum LSQPolicy { 54 Dynamic, 55 Partitioned, 56 Threshold 57 }; 58 59 /** Constructs an LSQ with the given parameters. */ 60 LSQ(Params *params); 61 62 /** Returns the name of the LSQ. */ 63 std::string name() const; 64 65 /** Sets the pointer to the list of active threads. */ 66 void setActiveThreads(std::list<unsigned> *at_ptr); 67 /** Sets the CPU pointer. */ 68 void setCPU(FullCPU *cpu_ptr); 69 /** Sets the IEW stage pointer. */ 70 void setIEW(IEW *iew_ptr); 71 /** Sets the page table pointer. */ 72// void setPageTable(PageTable *pt_ptr); 73 /** Switches out the LSQ. */ 74 void switchOut(); 75 /** Takes over execution from another CPU's thread. */ 76 void takeOverFrom(); 77 78 /** Number of entries needed for the given amount of threads.*/ 79 int entryAmount(int num_threads); 80 void removeEntries(unsigned tid); 81 /** Reset the max entries for each thread. */ 82 void resetEntries(); 83 /** Resize the max entries for a thread. */ 84 void resizeEntries(unsigned size, unsigned tid); 85 86 /** Ticks the LSQ. */ 87 void tick(); 88 /** Ticks a specific LSQ Unit. */ 89 void tick(unsigned tid) 90 { thread[tid].tick(); } 91 92 /** Inserts a load into the LSQ. */ 93 void insertLoad(DynInstPtr &load_inst); 94 /** Inserts a store into the LSQ. */ 95 void insertStore(DynInstPtr &store_inst); 96 97 /** Executes a load. */ 98 Fault executeLoad(DynInstPtr &inst); 99 100 /** Executes a store. */ 101 Fault executeStore(DynInstPtr &inst); 102 103 /** 104 * Commits loads up until the given sequence number for a specific thread. 105 */ 106 void commitLoads(InstSeqNum &youngest_inst, unsigned tid) 107 { thread[tid].commitLoads(youngest_inst); } 108 109 /** 110 * Commits stores up until the given sequence number for a specific thread. 111 */ 112 void commitStores(InstSeqNum &youngest_inst, unsigned tid) 113 { thread[tid].commitStores(youngest_inst); } 114 115 /** 116 * Attempts to write back stores until all cache ports are used or the 117 * interface becomes blocked. 118 */ 119 void writebackStores(); 120 /** Same as above, but only for one thread. */ 121 void writebackStores(unsigned tid); 122 123 /** 124 * Squash instructions from a thread until the specified sequence number. 125 */ 126 void squash(const InstSeqNum &squashed_num, unsigned tid) 127 { thread[tid].squash(squashed_num); } 128 129 /** Returns whether or not there was a memory ordering violation. */ 130 bool violation(); 131 /** 132 * Returns whether or not there was a memory ordering violation for a 133 * specific thread. 134 */ 135 bool violation(unsigned tid) 136 { return thread[tid].violation(); } 137 138 /** Returns if a load is blocked due to the memory system for a specific 139 * thread. 140 */ 141 bool loadBlocked(unsigned tid) 142 { return thread[tid].loadBlocked(); } 143 144 bool isLoadBlockedHandled(unsigned tid) 145 { return thread[tid].isLoadBlockedHandled(); } 146 147 void setLoadBlockedHandled(unsigned tid) 148 { thread[tid].setLoadBlockedHandled(); } 149 150 /** Gets the instruction that caused the memory ordering violation. */ 151 DynInstPtr getMemDepViolator(unsigned tid) 152 { return thread[tid].getMemDepViolator(); } 153 154 /** Returns the head index of the load queue for a specific thread. */ 155 int getLoadHead(unsigned tid) 156 { return thread[tid].getLoadHead(); } 157 158 /** Returns the sequence number of the head of the load queue. */ 159 InstSeqNum getLoadHeadSeqNum(unsigned tid) 160 { 161 return thread[tid].getLoadHeadSeqNum(); 162 } 163 164 /** Returns the head index of the store queue. */ 165 int getStoreHead(unsigned tid) 166 { return thread[tid].getStoreHead(); } 167 168 /** Returns the sequence number of the head of the store queue. */ 169 InstSeqNum getStoreHeadSeqNum(unsigned tid) 170 { 171 return thread[tid].getStoreHeadSeqNum(); 172 } 173 174 /** Returns the number of instructions in all of the queues. */ 175 int getCount(); 176 /** Returns the number of instructions in the queues of one thread. */ 177 int getCount(unsigned tid) 178 { return thread[tid].getCount(); } 179 180 /** Returns the total number of loads in the load queue. */ 181 int numLoads(); 182 /** Returns the total number of loads for a single thread. */ 183 int numLoads(unsigned tid) 184 { return thread[tid].numLoads(); } 185 186 /** Returns the total number of stores in the store queue. */ 187 int numStores(); 188 /** Returns the total number of stores for a single thread. */ 189 int numStores(unsigned tid) 190 { return thread[tid].numStores(); } 191 192 /** Returns the total number of loads that are ready. */ 193 int numLoadsReady(); 194 /** Returns the number of loads that are ready for a single thread. */ 195 int numLoadsReady(unsigned tid) 196 { return thread[tid].numLoadsReady(); } 197 198 /** Returns the number of free entries. */ 199 unsigned numFreeEntries(); 200 /** Returns the number of free entries for a specific thread. */ 201 unsigned numFreeEntries(unsigned tid); 202 203 /** Returns if the LSQ is full (either LQ or SQ is full). */ 204 bool isFull(); 205 /** 206 * Returns if the LSQ is full for a specific thread (either LQ or SQ is 207 * full). 208 */ 209 bool isFull(unsigned tid); 210 211 /** Returns if any of the LQs are full. */ 212 bool lqFull(); 213 /** Returns if the LQ of a given thread is full. */ 214 bool lqFull(unsigned tid); 215 216 /** Returns if any of the SQs are full. */ 217 bool sqFull(); 218 /** Returns if the SQ of a given thread is full. */ 219 bool sqFull(unsigned tid); 220 221 /** 222 * Returns if the LSQ is stalled due to a memory operation that must be 223 * replayed. 224 */ 225 bool isStalled(); 226 /** 227 * Returns if the LSQ of a specific thread is stalled due to a memory 228 * operation that must be replayed. 229 */ 230 bool isStalled(unsigned tid); 231 232 /** Returns whether or not there are any stores to write back to memory. */ 233 bool hasStoresToWB(); 234 235 /** Returns whether or not a specific thread has any stores to write back 236 * to memory. 237 */ 238 bool hasStoresToWB(unsigned tid) 239 { return thread[tid].hasStoresToWB(); } 240 241 /** Returns the number of stores a specific thread has to write back. */ 242 int numStoresToWB(unsigned tid) 243 { return thread[tid].numStoresToWB(); } 244 245 /** Returns if the LSQ will write back to memory this cycle. */ 246 bool willWB(); 247 /** Returns if the LSQ of a specific thread will write back to memory this 248 * cycle. 249 */ 250 bool willWB(unsigned tid) 251 { return thread[tid].willWB(); } 252 253 /** Debugging function to print out all instructions. */ 254 void dumpInsts(); 255 /** Debugging function to print out instructions from a specific thread. */ 256 void dumpInsts(unsigned tid) 257 { thread[tid].dumpInsts(); } 258 259 /** Executes a read operation, using the load specified at the load index. */ 260 template <class T> 261 Fault read(RequestPtr req, T &data, int load_idx); 262 263 /** Executes a store operation, using the store specified at the store 264 * index. 265 */ 266 template <class T> 267 Fault write(RequestPtr req, T &data, int store_idx); 268 269 private: 270 /** The LSQ policy for SMT mode. */ 271 LSQPolicy lsqPolicy; 272 273 /** The LSQ units for individual threads. */ 274 LSQUnit thread[Impl::MaxThreads]; 275 276 /** The CPU pointer. */ 277 FullCPU *cpu; 278 279 /** The IEW stage pointer. */ 280 IEW *iewStage; 281 282 /** The pointer to the page table. */ 283// PageTable *pTable; 284 285 /** List of Active Threads in System. */ 286 std::list<unsigned> *activeThreads; 287 288 /** Total Size of LQ Entries. */ 289 unsigned LQEntries; 290 /** Total Size of SQ Entries. */ 291 unsigned SQEntries; 292 293 /** Max LQ Size - Used to Enforce Sharing Policies. */ 294 unsigned maxLQEntries; 295 296 /** Max SQ Size - Used to Enforce Sharing Policies. */ 297 unsigned maxSQEntries; 298 299 /** Number of Threads. */ 300 unsigned numThreads; 301}; 302 303template <class Impl> 304template <class T> 305Fault 306LSQ<Impl>::read(RequestPtr req, T &data, int load_idx) 307{ 308 unsigned tid = req->getThreadNum(); 309 310 return thread[tid].read(req, data, load_idx); 311} 312 313template <class Impl> 314template <class T> 315Fault 316LSQ<Impl>::write(RequestPtr req, T &data, int store_idx) 317{ 318 unsigned tid = req->getThreadNum(); 319 320 return thread[tid].write(req, data, store_idx); 321} 322 323#endif // __CPU_O3_LSQ_HH__ 324