lsq.hh revision 2292
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __CPU_O3_LSQ_HH__ 30#define __CPU_O3_LSQ_HH__ 31 32#include <map> 33#include <queue> 34 35#include "base/hashmap.hh" 36#include "config/full_system.hh" 37#include "cpu/inst_seq.hh" 38#include "cpu/o3/cpu_policy.hh" 39#include "cpu/o3/lsq_unit.hh" 40#include "mem/mem_interface.hh" 41//#include "mem/page_table.hh" 42#include "sim/sim_object.hh" 43 44template <class Impl> 45class LSQ { 46 public: 47 typedef typename Impl::Params Params; 48 typedef typename Impl::FullCPU FullCPU; 49 typedef typename Impl::DynInstPtr DynInstPtr; 50 typedef typename Impl::CPUPol::IEW IEW; 51 typedef typename Impl::CPUPol::LSQUnit LSQUnit; 52 53 enum LSQPolicy { 54 Dynamic, 55 Partitioned, 56 Threshold 57 }; 58 59 /** Constructs an LSQ with the given parameters. */ 60 LSQ(Params *params); 61 62 /** Returns the name of the LSQ. */ 63 std::string name() const; 64 65 /** Sets the pointer to the list of active threads. */ 66 void setActiveThreads(std::list<unsigned> *at_ptr); 67 /** Sets the CPU pointer. */ 68 void setCPU(FullCPU *cpu_ptr); 69 /** Sets the IEW stage pointer. */ 70 void setIEW(IEW *iew_ptr); 71 /** Sets the page table pointer. */ 72// void setPageTable(PageTable *pt_ptr); 73 74 /** Number of entries needed for the given amount of threads.*/ 75 int entryAmount(int num_threads); 76 void removeEntries(unsigned tid); 77 /** Reset the max entries for each thread. */ 78 void resetEntries(); 79 /** Resize the max entries for a thread. */ 80 void resizeEntries(unsigned size, unsigned tid); 81 82 /** Ticks the LSQ. */ 83 void tick(); 84 /** Ticks a specific LSQ Unit. */ 85 void tick(unsigned tid); 86 87 /** Inserts a load into the LSQ. */ 88 void insertLoad(DynInstPtr &load_inst); 89 /** Inserts a store into the LSQ. */ 90 void insertStore(DynInstPtr &store_inst); 91 92 /** Executes a load. */ 93 Fault executeLoad(DynInstPtr &inst); 94 95 Fault executeLoad(int lq_idx, unsigned tid); 96 /** Executes a store. */ 97 Fault executeStore(DynInstPtr &inst); 98 99 /** 100 * Commits loads up until the given sequence number for a specific thread. 101 */ 102 void commitLoads(InstSeqNum &youngest_inst, unsigned tid); 103 /** 104 * Commits stores up until the given sequence number for a specific thread. 105 */ 106 void commitStores(InstSeqNum &youngest_inst, unsigned tid); 107 108 /** 109 * Attempts to write back stores until all cache ports are used or the 110 * interface becomes blocked. 111 */ 112 void writebackStores(); 113 /** Same as above, but only for one thread. */ 114 void writebackStores(unsigned tid); 115 116 /** 117 * Squash instructions from a thread until the specified sequence number. 118 */ 119 void squash(const InstSeqNum &squashed_num, unsigned tid); 120 121 /** Returns whether or not there was a memory ordering violation. */ 122 bool violation(); 123 /** 124 * Returns whether or not there was a memory ordering violation for a 125 * specific thread. 126 */ 127 bool violation(unsigned tid); 128 129 /** Returns if a load is blocked due to the memory system for a specific 130 * thread. 131 */ 132 bool loadBlocked(unsigned tid); 133 134 bool isLoadBlockedHandled(unsigned tid) 135 { return thread[tid].isLoadBlockedHandled(); } 136 137 void setLoadBlockedHandled(unsigned tid) 138 { thread[tid].setLoadBlockedHandled(); } 139 140 /** Gets the instruction that caused the memory ordering violation. */ 141 DynInstPtr getMemDepViolator(unsigned tid); 142 143 /** Returns the head index of the load queue for a specific thread. */ 144 int getLoadHead(unsigned tid); 145 /** Returns the sequence number of the head of the load queue. */ 146 InstSeqNum getLoadHeadSeqNum(unsigned tid) 147 { 148 return thread[tid].getLoadHeadSeqNum(); 149 } 150 151 /** Returns the head index of the store queue. */ 152 int getStoreHead(unsigned tid); 153 /** Returns the sequence number of the head of the store queue. */ 154 InstSeqNum getStoreHeadSeqNum(unsigned tid) 155 { 156 return thread[tid].getStoreHeadSeqNum(); 157 } 158 159 /** Returns the number of instructions in all of the queues. */ 160 int getCount(); 161 /** Returns the number of instructions in the queues of one thread. */ 162 int getCount(unsigned tid); 163 164 /** Returns the total number of loads in the load queue. */ 165 int numLoads(); 166 /** Returns the total number of loads for a single thread. */ 167 int numLoads(unsigned tid); 168 169 /** Returns the total number of stores in the store queue. */ 170 int numStores(); 171 /** Returns the total number of stores for a single thread. */ 172 int numStores(unsigned tid); 173 174 /** Returns the total number of loads that are ready. */ 175 int numLoadsReady(); 176 /** Returns the number of loads that are ready for a single thread. */ 177 int numLoadsReady(unsigned tid); 178 179 /** Returns the number of free entries. */ 180 unsigned numFreeEntries(); 181 /** Returns the number of free entries for a specific thread. */ 182 unsigned numFreeEntries(unsigned tid); 183 184 /** Returns if the LSQ is full (either LQ or SQ is full). */ 185 bool isFull(); 186 /** 187 * Returns if the LSQ is full for a specific thread (either LQ or SQ is 188 * full). 189 */ 190 bool isFull(unsigned tid); 191 192 /** Returns if any of the LQs are full. */ 193 bool lqFull(); 194 /** Returns if the LQ of a given thread is full. */ 195 bool lqFull(unsigned tid); 196 197 /** Returns if any of the SQs are full. */ 198 bool sqFull(); 199 /** Returns if the SQ of a given thread is full. */ 200 bool sqFull(unsigned tid); 201 202 /** 203 * Returns if the LSQ is stalled due to a memory operation that must be 204 * replayed. 205 */ 206 bool isStalled(); 207 /** 208 * Returns if the LSQ of a specific thread is stalled due to a memory 209 * operation that must be replayed. 210 */ 211 bool isStalled(unsigned tid); 212 213 /** Returns whether or not there are any stores to write back to memory. */ 214 bool hasStoresToWB(); 215 /** Returns whether or not a specific thread has any stores to write back 216 * to memory. 217 */ 218 bool hasStoresToWB(unsigned tid); 219 /** Returns the number of stores a specific thread has to write back. */ 220 int numStoresToWB(unsigned tid); 221 222 /** Returns if the LSQ will write back to memory this cycle. */ 223 bool willWB(); 224 /** Returns if the LSQ of a specific thread will write back to memory this 225 * cycle. 226 */ 227 bool willWB(unsigned tid); 228 229 /** Debugging function to print out all instructions. */ 230 void dumpInsts(); 231 /** Debugging function to print out instructions from a specific thread. */ 232 void dumpInsts(unsigned tid); 233 234 /** Executes a read operation, using the load specified at the load index. */ 235 template <class T> 236 Fault read(MemReqPtr &req, T &data, int load_idx); 237 238 /** Executes a store operation, using the store specified at the store 239 * index. 240 */ 241 template <class T> 242 Fault write(MemReqPtr &req, T &data, int store_idx); 243 244 private: 245 /** The LSQ policy for SMT mode. */ 246 LSQPolicy lsqPolicy; 247 248 /** The LSQ units for individual threads. */ 249 LSQUnit thread[Impl::MaxThreads]; 250 251 /** The CPU pointer. */ 252 FullCPU *cpu; 253 254 /** The IEW stage pointer. */ 255 IEW *iewStage; 256 257 /** The pointer to the page table. */ 258// PageTable *pTable; 259 260 /** List of Active Threads in System. */ 261 std::list<unsigned> *activeThreads; 262 263 /** Total Size of LQ Entries. */ 264 unsigned LQEntries; 265 /** Total Size of SQ Entries. */ 266 unsigned SQEntries; 267 268 /** Max LQ Size - Used to Enforce Sharing Policies. */ 269 unsigned maxLQEntries; 270 271 /** Max SQ Size - Used to Enforce Sharing Policies. */ 272 unsigned maxSQEntries; 273 274 /** Global Load Count. */ 275 int loads; 276 277 /** Global Store Count */ 278 int stores; 279 280 /** Global Store To WB Count */ 281 int storesToWB; 282 283 /** Number of Threads. */ 284 unsigned numThreads; 285}; 286 287template <class Impl> 288template <class T> 289Fault 290LSQ<Impl>::read(MemReqPtr &req, T &data, int load_idx) 291{ 292 unsigned tid = req->thread_num; 293 294 return thread[tid].read(req, data, load_idx); 295} 296 297template <class Impl> 298template <class T> 299Fault 300LSQ<Impl>::write(MemReqPtr &req, T &data, int store_idx) 301{ 302 unsigned tid = req->thread_num; 303 304 return thread[tid].write(req, data, store_idx); 305} 306 307#endif // __CPU_O3_LSQ_HH__ 308