lsq.hh revision 11429:cf5af0cc3be4
12600SN/A/* 22600SN/A * Copyright (c) 2011-2012, 2014 ARM Limited 32600SN/A * Copyright (c) 2013 Advanced Micro Devices, Inc. 42600SN/A * All rights reserved 52600SN/A * 62600SN/A * The license below extends only to copyright in the software and shall 72600SN/A * not be construed as granting a license to any other intellectual 82600SN/A * property including but not limited to intellectual property relating 92600SN/A * to a hardware implementation of the functionality of the software 102600SN/A * licensed hereunder. You may use the software subject to the license 112600SN/A * terms below provided that you ensure that this notice is replicated 122600SN/A * unmodified and in its entirety in all distributions of the software, 132600SN/A * modified or unmodified, in source code or in binary form. 142600SN/A * 152600SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 162600SN/A * All rights reserved. 172600SN/A * 182600SN/A * Redistribution and use in source and binary forms, with or without 192600SN/A * modification, are permitted provided that the following conditions are 202600SN/A * met: redistributions of source code must retain the above copyright 212600SN/A * notice, this list of conditions and the following disclaimer; 222600SN/A * redistributions in binary form must reproduce the above copyright 232600SN/A * notice, this list of conditions and the following disclaimer in the 242600SN/A * documentation and/or other materials provided with the distribution; 252600SN/A * neither the name of the copyright holders nor the names of its 262600SN/A * contributors may be used to endorse or promote products derived from 272665Ssaidi@eecs.umich.edu * this software without specific prior written permission. 282665Ssaidi@eecs.umich.edu * 292600SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302600SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312600SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322600SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332600SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342600SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352600SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362600SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372600SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382600SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392600SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402600SN/A * 412600SN/A * Authors: Korey Sewell 422600SN/A */ 432600SN/A 442600SN/A#ifndef __CPU_O3_LSQ_HH__ 452600SN/A#define __CPU_O3_LSQ_HH__ 462600SN/A 472600SN/A#include <map> 482600SN/A#include <queue> 492600SN/A 502600SN/A#include "cpu/o3/lsq_unit.hh" 512600SN/A#include "cpu/inst_seq.hh" 522600SN/A#include "mem/port.hh" 532600SN/A#include "sim/sim_object.hh" 542600SN/A 552600SN/Astruct DerivO3CPUParams; 562600SN/A 572600SN/Atemplate <class Impl> 582600SN/Aclass LSQ { 592600SN/A public: 602600SN/A typedef typename Impl::O3CPU O3CPU; 612600SN/A typedef typename Impl::DynInstPtr DynInstPtr; 622600SN/A typedef typename Impl::CPUPol::IEW IEW; 632600SN/A typedef typename Impl::CPUPol::LSQUnit LSQUnit; 642600SN/A 652600SN/A /** SMT policy. */ 662600SN/A enum LSQPolicy { 672600SN/A Dynamic, 682600SN/A Partitioned, 692600SN/A Threshold 702600SN/A }; 712600SN/A 722600SN/A /** Constructs an LSQ with the given parameters. */ 732600SN/A LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params); 742600SN/A ~LSQ() { 752600SN/A if (thread) delete [] thread; 762600SN/A } 772600SN/A 782600SN/A /** Returns the name of the LSQ. */ 792600SN/A std::string name() const; 802600SN/A 812600SN/A /** Registers statistics of each LSQ unit. */ 822600SN/A void regStats(); 832600SN/A 842600SN/A /** Sets the pointer to the list of active threads. */ 852600SN/A void setActiveThreads(std::list<ThreadID> *at_ptr); 862600SN/A 872600SN/A /** Perform sanity checks after a drain. */ 882600SN/A void drainSanityCheck() const; 892600SN/A /** Has the LSQ drained? */ 902600SN/A bool isDrained() const; 912600SN/A /** Takes over execution from another CPU's thread. */ 922600SN/A void takeOverFrom(); 932600SN/A 942600SN/A /** Number of entries needed for the given amount of threads.*/ 952600SN/A int entryAmount(ThreadID num_threads); 962600SN/A void removeEntries(ThreadID tid); 972600SN/A /** Reset the max entries for each thread. */ 982600SN/A void resetEntries(); 992600SN/A /** Resize the max entries for a thread. */ 1002600SN/A void resizeEntries(unsigned size, ThreadID tid); 1012600SN/A 1022600SN/A /** Ticks the LSQ. */ 1032600SN/A void tick(); 1042600SN/A /** Ticks a specific LSQ Unit. */ 1052600SN/A void tick(ThreadID tid) 1062600SN/A { thread[tid].tick(); } 1072600SN/A 1082600SN/A /** Inserts a load into the LSQ. */ 1092600SN/A void insertLoad(DynInstPtr &load_inst); 1102600SN/A /** Inserts a store into the LSQ. */ 1112600SN/A void insertStore(DynInstPtr &store_inst); 1122600SN/A 1132600SN/A /** Executes a load. */ 1142600SN/A Fault executeLoad(DynInstPtr &inst); 1152600SN/A 1162600SN/A /** Executes a store. */ 1172600SN/A Fault executeStore(DynInstPtr &inst); 1182600SN/A 1192600SN/A /** 1202600SN/A * Commits loads up until the given sequence number for a specific thread. 1212600SN/A */ 1222600SN/A void commitLoads(InstSeqNum &youngest_inst, ThreadID tid) 1232600SN/A { thread[tid].commitLoads(youngest_inst); } 1242600SN/A 1252600SN/A /** 1262600SN/A * Commits stores up until the given sequence number for a specific thread. 1272600SN/A */ 1282600SN/A void commitStores(InstSeqNum &youngest_inst, ThreadID tid) 1292600SN/A { thread[tid].commitStores(youngest_inst); } 1302600SN/A 1312600SN/A /** 1322600SN/A * Attempts to write back stores until all cache ports are used or the 1332600SN/A * interface becomes blocked. 1342600SN/A */ 1352600SN/A void writebackStores(); 1362600SN/A /** Same as above, but only for one thread. */ 1372600SN/A void writebackStores(ThreadID tid); 1382600SN/A 1392600SN/A /** 1402600SN/A * Squash instructions from a thread until the specified sequence number. 1412600SN/A */ 1422600SN/A void squash(const InstSeqNum &squashed_num, ThreadID tid) 1432600SN/A { thread[tid].squash(squashed_num); } 1442600SN/A 1452600SN/A /** Returns whether or not there was a memory ordering violation. */ 1462600SN/A bool violation(); 1472600SN/A /** 1482600SN/A * Returns whether or not there was a memory ordering violation for a 1492600SN/A * specific thread. 1502600SN/A */ 1512600SN/A bool violation(ThreadID tid) 1522600SN/A { return thread[tid].violation(); } 1532600SN/A 1542600SN/A /** Gets the instruction that caused the memory ordering violation. */ 1552600SN/A DynInstPtr getMemDepViolator(ThreadID tid) 1562600SN/A { return thread[tid].getMemDepViolator(); } 1572600SN/A 1582600SN/A /** Returns the head index of the load queue for a specific thread. */ 1592600SN/A int getLoadHead(ThreadID tid) 1602600SN/A { return thread[tid].getLoadHead(); } 1612600SN/A 1622600SN/A /** Returns the sequence number of the head of the load queue. */ 1632600SN/A InstSeqNum getLoadHeadSeqNum(ThreadID tid) 1642600SN/A { 1652600SN/A return thread[tid].getLoadHeadSeqNum(); 1662600SN/A } 1672600SN/A 1682600SN/A /** Returns the head index of the store queue. */ 1692600SN/A int getStoreHead(ThreadID tid) 1702600SN/A { return thread[tid].getStoreHead(); } 1712600SN/A 1722600SN/A /** Returns the sequence number of the head of the store queue. */ 1732600SN/A InstSeqNum getStoreHeadSeqNum(ThreadID tid) 1742600SN/A { 1752600SN/A return thread[tid].getStoreHeadSeqNum(); 1762600SN/A } 1772600SN/A 1782600SN/A /** Returns the number of instructions in all of the queues. */ 1792600SN/A int getCount(); 1802600SN/A /** Returns the number of instructions in the queues of one thread. */ 1812600SN/A int getCount(ThreadID tid) 1822600SN/A { return thread[tid].getCount(); } 1832600SN/A 1842600SN/A /** Returns the total number of loads in the load queue. */ 1852600SN/A int numLoads(); 1862600SN/A /** Returns the total number of loads for a single thread. */ 1872600SN/A int numLoads(ThreadID tid) 1882600SN/A { return thread[tid].numLoads(); } 1892600SN/A 1902600SN/A /** Returns the total number of stores in the store queue. */ 1912600SN/A int numStores(); 1922600SN/A /** Returns the total number of stores for a single thread. */ 1932600SN/A int numStores(ThreadID tid) 1942600SN/A { return thread[tid].numStores(); } 1952600SN/A 1962600SN/A /** Returns the number of free load entries. */ 1972600SN/A unsigned numFreeLoadEntries(); 1982600SN/A 1992600SN/A /** Returns the number of free store entries. */ 2002600SN/A unsigned numFreeStoreEntries(); 2012600SN/A 2022600SN/A /** Returns the number of free entries for a specific thread. */ 2032600SN/A unsigned numFreeEntries(ThreadID tid); 2042600SN/A 2052600SN/A /** Returns the number of free entries in the LQ for a specific thread. */ 2062600SN/A unsigned numFreeLoadEntries(ThreadID tid); 2072600SN/A 2082600SN/A /** Returns the number of free entries in the SQ for a specific thread. */ 2092600SN/A unsigned numFreeStoreEntries(ThreadID tid); 2102600SN/A 2112600SN/A /** Returns if the LSQ is full (either LQ or SQ is full). */ 2122600SN/A bool isFull(); 2132600SN/A /** 2142600SN/A * Returns if the LSQ is full for a specific thread (either LQ or SQ is 2152600SN/A * full). 2162600SN/A */ 2172600SN/A bool isFull(ThreadID tid); 2182600SN/A 2192600SN/A /** Returns if the LSQ is empty (both LQ and SQ are empty). */ 2202600SN/A bool isEmpty() const; 2212600SN/A /** Returns if all of the LQs are empty. */ 2222600SN/A bool lqEmpty() const; 2232600SN/A /** Returns if all of the SQs are empty. */ 2242600SN/A bool sqEmpty() const; 2252600SN/A 2262600SN/A /** Returns if any of the LQs are full. */ 2272600SN/A bool lqFull(); 2282600SN/A /** Returns if the LQ of a given thread is full. */ 2292600SN/A bool lqFull(ThreadID tid); 2302600SN/A 2312600SN/A /** Returns if any of the SQs are full. */ 2322600SN/A bool sqFull(); 2332600SN/A /** Returns if the SQ of a given thread is full. */ 2342600SN/A bool sqFull(ThreadID tid); 2352600SN/A 2362600SN/A /** 2372600SN/A * Returns if the LSQ is stalled due to a memory operation that must be 2382600SN/A * replayed. 2392600SN/A */ 2402600SN/A bool isStalled(); 2412600SN/A /** 2422600SN/A * Returns if the LSQ of a specific thread is stalled due to a memory 2432600SN/A * operation that must be replayed. 2442600SN/A */ 2452600SN/A bool isStalled(ThreadID tid); 2462600SN/A 2472600SN/A /** Returns whether or not there are any stores to write back to memory. */ 2482600SN/A bool hasStoresToWB(); 2492600SN/A 2502600SN/A /** Returns whether or not a specific thread has any stores to write back 2512600SN/A * to memory. 2522600SN/A */ 2532600SN/A bool hasStoresToWB(ThreadID tid) 2542600SN/A { return thread[tid].hasStoresToWB(); } 2552600SN/A 2562600SN/A /** Returns the number of stores a specific thread has to write back. */ 2572600SN/A int numStoresToWB(ThreadID tid) 2582600SN/A { return thread[tid].numStoresToWB(); } 2592600SN/A 2602600SN/A /** Returns if the LSQ will write back to memory this cycle. */ 2612600SN/A bool willWB(); 2622600SN/A /** Returns if the LSQ of a specific thread will write back to memory this 2632600SN/A * cycle. 2642600SN/A */ 2652600SN/A bool willWB(ThreadID tid) 2662600SN/A { return thread[tid].willWB(); } 2672600SN/A 2682600SN/A /** Debugging function to print out all instructions. */ 2692600SN/A void dumpInsts() const; 2702600SN/A /** Debugging function to print out instructions from a specific thread. */ 2712600SN/A void dumpInsts(ThreadID tid) const 2722600SN/A { thread[tid].dumpInsts(); } 2732600SN/A 2742600SN/A /** Executes a read operation, using the load specified at the load 2752600SN/A * index. 2762600SN/A */ 2772600SN/A Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 2782600SN/A int load_idx); 2792600SN/A 2802600SN/A /** Executes a store operation, using the store specified at the store 2812600SN/A * index. 2822600SN/A */ 2832600SN/A Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 2842600SN/A uint8_t *data, int store_idx); 2852600SN/A 2862600SN/A /** 2872600SN/A * Retry the previous send that failed. 2882600SN/A */ 2892600SN/A void recvReqRetry(); 2902600SN/A 2912600SN/A /** 2922600SN/A * Handles writing back and completing the load or store that has 2932600SN/A * returned from memory. 2942600SN/A * 2952600SN/A * @param pkt Response packet from the memory sub-system 2962600SN/A */ 2972600SN/A bool recvTimingResp(PacketPtr pkt); 2982600SN/A 2992600SN/A void recvTimingSnoopReq(PacketPtr pkt); 3002600SN/A 3012600SN/A /** The CPU pointer. */ 3022600SN/A O3CPU *cpu; 3032600SN/A 3042600SN/A /** The IEW stage pointer. */ 3052600SN/A IEW *iewStage; 3062600SN/A 3072600SN/A protected: 3082600SN/A /** The LSQ policy for SMT mode. */ 3092600SN/A LSQPolicy lsqPolicy; 3102600SN/A 3112600SN/A /** The LSQ units for individual threads. */ 3122600SN/A LSQUnit *thread; 3132600SN/A 3142600SN/A /** List of Active Threads in System. */ 3152600SN/A std::list<ThreadID> *activeThreads; 3162600SN/A 3172600SN/A /** Total Size of LQ Entries. */ 3182600SN/A unsigned LQEntries; 3192600SN/A /** Total Size of SQ Entries. */ 3202600SN/A unsigned SQEntries; 3212600SN/A 3222600SN/A /** Max LQ Size - Used to Enforce Sharing Policies. */ 3232600SN/A unsigned maxLQEntries; 3242600SN/A 3252600SN/A /** Max SQ Size - Used to Enforce Sharing Policies. */ 3262600SN/A unsigned maxSQEntries; 3272600SN/A 3282600SN/A /** Number of Threads. */ 3292600SN/A ThreadID numThreads; 3302600SN/A}; 3312600SN/A 3322600SN/Atemplate <class Impl> 3332600SN/AFault 3342600SN/ALSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 3352600SN/A int load_idx) 3362600SN/A{ 3372600SN/A ThreadID tid = req->threadId(); 3382600SN/A 3392600SN/A return thread[tid].read(req, sreqLow, sreqHigh, load_idx); 3402600SN/A} 3412600SN/A 3422600SN/Atemplate <class Impl> 3432600SN/AFault 3442600SN/ALSQ<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 3452600SN/A uint8_t *data, int store_idx) 3462600SN/A{ 3472600SN/A ThreadID tid = req->threadId(); 3482600SN/A 3492600SN/A return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx); 350} 351 352#endif // __CPU_O3_LSQ_HH__ 353