lsq.hh revision 8707
12292SN/A/* 28707Sandreas.hansson@arm.com * Copyright (c) 2011 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 152292SN/A * All rights reserved. 162292SN/A * 172292SN/A * Redistribution and use in source and binary forms, with or without 182292SN/A * modification, are permitted provided that the following conditions are 192292SN/A * met: redistributions of source code must retain the above copyright 202292SN/A * notice, this list of conditions and the following disclaimer; 212292SN/A * redistributions in binary form must reproduce the above copyright 222292SN/A * notice, this list of conditions and the following disclaimer in the 232292SN/A * documentation and/or other materials provided with the distribution; 242292SN/A * neither the name of the copyright holders nor the names of its 252292SN/A * contributors may be used to endorse or promote products derived from 262292SN/A * this software without specific prior written permission. 272292SN/A * 282292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392689Sktlim@umich.edu * 402689Sktlim@umich.edu * Authors: Korey Sewell 412292SN/A */ 422292SN/A 432292SN/A#ifndef __CPU_O3_LSQ_HH__ 442292SN/A#define __CPU_O3_LSQ_HH__ 452292SN/A 462292SN/A#include <map> 472292SN/A#include <queue> 482292SN/A 492292SN/A#include "config/full_system.hh" 508229Snate@binkert.org#include "cpu/o3/lsq_unit.hh" 512292SN/A#include "cpu/inst_seq.hh" 522669Sktlim@umich.edu#include "mem/port.hh" 532292SN/A#include "sim/sim_object.hh" 542292SN/A 555529Snate@binkert.orgclass DerivO3CPUParams; 565529Snate@binkert.org 572292SN/Atemplate <class Impl> 582292SN/Aclass LSQ { 592292SN/A public: 602733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 612292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 622292SN/A typedef typename Impl::CPUPol::IEW IEW; 632292SN/A typedef typename Impl::CPUPol::LSQUnit LSQUnit; 642292SN/A 652348SN/A /** SMT policy. */ 662292SN/A enum LSQPolicy { 672292SN/A Dynamic, 682292SN/A Partitioned, 692292SN/A Threshold 702292SN/A }; 712292SN/A 722292SN/A /** Constructs an LSQ with the given parameters. */ 735529Snate@binkert.org LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params); 742292SN/A 752292SN/A /** Returns the name of the LSQ. */ 762292SN/A std::string name() const; 772292SN/A 782727Sktlim@umich.edu /** Registers statistics of each LSQ unit. */ 792727Sktlim@umich.edu void regStats(); 802727Sktlim@umich.edu 812292SN/A /** Sets the pointer to the list of active threads. */ 826221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 832348SN/A /** Switches out the LSQ. */ 842307SN/A void switchOut(); 852348SN/A /** Takes over execution from another CPU's thread. */ 862307SN/A void takeOverFrom(); 872307SN/A 882292SN/A /** Number of entries needed for the given amount of threads.*/ 896221Snate@binkert.org int entryAmount(ThreadID num_threads); 906221Snate@binkert.org void removeEntries(ThreadID tid); 912292SN/A /** Reset the max entries for each thread. */ 922292SN/A void resetEntries(); 932292SN/A /** Resize the max entries for a thread. */ 946221Snate@binkert.org void resizeEntries(unsigned size, ThreadID tid); 952292SN/A 962292SN/A /** Ticks the LSQ. */ 972292SN/A void tick(); 982292SN/A /** Ticks a specific LSQ Unit. */ 996221Snate@binkert.org void tick(ThreadID tid) 1002329SN/A { thread[tid].tick(); } 1012292SN/A 1022292SN/A /** Inserts a load into the LSQ. */ 1032292SN/A void insertLoad(DynInstPtr &load_inst); 1042292SN/A /** Inserts a store into the LSQ. */ 1052292SN/A void insertStore(DynInstPtr &store_inst); 1062292SN/A 1072292SN/A /** Executes a load. */ 1082292SN/A Fault executeLoad(DynInstPtr &inst); 1092292SN/A 1102292SN/A /** Executes a store. */ 1112292SN/A Fault executeStore(DynInstPtr &inst); 1122292SN/A 1132292SN/A /** 1142292SN/A * Commits loads up until the given sequence number for a specific thread. 1152292SN/A */ 1166221Snate@binkert.org void commitLoads(InstSeqNum &youngest_inst, ThreadID tid) 1172329SN/A { thread[tid].commitLoads(youngest_inst); } 1182329SN/A 1192292SN/A /** 1202292SN/A * Commits stores up until the given sequence number for a specific thread. 1212292SN/A */ 1226221Snate@binkert.org void commitStores(InstSeqNum &youngest_inst, ThreadID tid) 1232329SN/A { thread[tid].commitStores(youngest_inst); } 1242292SN/A 1252292SN/A /** 1262292SN/A * Attempts to write back stores until all cache ports are used or the 1272292SN/A * interface becomes blocked. 1282292SN/A */ 1292292SN/A void writebackStores(); 1302292SN/A /** Same as above, but only for one thread. */ 1316221Snate@binkert.org void writebackStores(ThreadID tid); 1322292SN/A 1332292SN/A /** 1342292SN/A * Squash instructions from a thread until the specified sequence number. 1352292SN/A */ 1366221Snate@binkert.org void squash(const InstSeqNum &squashed_num, ThreadID tid) 1372329SN/A { thread[tid].squash(squashed_num); } 1382292SN/A 1392292SN/A /** Returns whether or not there was a memory ordering violation. */ 1402292SN/A bool violation(); 1412292SN/A /** 1422292SN/A * Returns whether or not there was a memory ordering violation for a 1432292SN/A * specific thread. 1442292SN/A */ 1456221Snate@binkert.org bool violation(ThreadID tid) 1462329SN/A { return thread[tid].violation(); } 1472292SN/A 1482292SN/A /** Returns if a load is blocked due to the memory system for a specific 1492292SN/A * thread. 1502292SN/A */ 1516221Snate@binkert.org bool loadBlocked(ThreadID tid) 1522329SN/A { return thread[tid].loadBlocked(); } 1532292SN/A 1546221Snate@binkert.org bool isLoadBlockedHandled(ThreadID tid) 1552292SN/A { return thread[tid].isLoadBlockedHandled(); } 1562292SN/A 1576221Snate@binkert.org void setLoadBlockedHandled(ThreadID tid) 1582292SN/A { thread[tid].setLoadBlockedHandled(); } 1592292SN/A 1602292SN/A /** Gets the instruction that caused the memory ordering violation. */ 1616221Snate@binkert.org DynInstPtr getMemDepViolator(ThreadID tid) 1622329SN/A { return thread[tid].getMemDepViolator(); } 1632292SN/A 1642292SN/A /** Returns the head index of the load queue for a specific thread. */ 1656221Snate@binkert.org int getLoadHead(ThreadID tid) 1662329SN/A { return thread[tid].getLoadHead(); } 1672329SN/A 1682292SN/A /** Returns the sequence number of the head of the load queue. */ 1696221Snate@binkert.org InstSeqNum getLoadHeadSeqNum(ThreadID tid) 1702292SN/A { 1712292SN/A return thread[tid].getLoadHeadSeqNum(); 1722292SN/A } 1732292SN/A 1742292SN/A /** Returns the head index of the store queue. */ 1756221Snate@binkert.org int getStoreHead(ThreadID tid) 1762329SN/A { return thread[tid].getStoreHead(); } 1772329SN/A 1782292SN/A /** Returns the sequence number of the head of the store queue. */ 1796221Snate@binkert.org InstSeqNum getStoreHeadSeqNum(ThreadID tid) 1802292SN/A { 1812292SN/A return thread[tid].getStoreHeadSeqNum(); 1822292SN/A } 1832292SN/A 1842292SN/A /** Returns the number of instructions in all of the queues. */ 1852292SN/A int getCount(); 1862292SN/A /** Returns the number of instructions in the queues of one thread. */ 1876221Snate@binkert.org int getCount(ThreadID tid) 1882329SN/A { return thread[tid].getCount(); } 1892292SN/A 1902292SN/A /** Returns the total number of loads in the load queue. */ 1912292SN/A int numLoads(); 1922292SN/A /** Returns the total number of loads for a single thread. */ 1936221Snate@binkert.org int numLoads(ThreadID tid) 1942329SN/A { return thread[tid].numLoads(); } 1952292SN/A 1962292SN/A /** Returns the total number of stores in the store queue. */ 1972292SN/A int numStores(); 1982292SN/A /** Returns the total number of stores for a single thread. */ 1996221Snate@binkert.org int numStores(ThreadID tid) 2002329SN/A { return thread[tid].numStores(); } 2012292SN/A 2022292SN/A /** Returns the total number of loads that are ready. */ 2032292SN/A int numLoadsReady(); 2042292SN/A /** Returns the number of loads that are ready for a single thread. */ 2056221Snate@binkert.org int numLoadsReady(ThreadID tid) 2062329SN/A { return thread[tid].numLoadsReady(); } 2072292SN/A 2082292SN/A /** Returns the number of free entries. */ 2092292SN/A unsigned numFreeEntries(); 2102292SN/A /** Returns the number of free entries for a specific thread. */ 2116221Snate@binkert.org unsigned numFreeEntries(ThreadID tid); 2122292SN/A 2132292SN/A /** Returns if the LSQ is full (either LQ or SQ is full). */ 2142292SN/A bool isFull(); 2152292SN/A /** 2162292SN/A * Returns if the LSQ is full for a specific thread (either LQ or SQ is 2172292SN/A * full). 2182292SN/A */ 2196221Snate@binkert.org bool isFull(ThreadID tid); 2202292SN/A 2212292SN/A /** Returns if any of the LQs are full. */ 2222292SN/A bool lqFull(); 2232292SN/A /** Returns if the LQ of a given thread is full. */ 2246221Snate@binkert.org bool lqFull(ThreadID tid); 2252292SN/A 2262292SN/A /** Returns if any of the SQs are full. */ 2272292SN/A bool sqFull(); 2282292SN/A /** Returns if the SQ of a given thread is full. */ 2296221Snate@binkert.org bool sqFull(ThreadID tid); 2302292SN/A 2312292SN/A /** 2322292SN/A * Returns if the LSQ is stalled due to a memory operation that must be 2332292SN/A * replayed. 2342292SN/A */ 2352292SN/A bool isStalled(); 2362292SN/A /** 2372292SN/A * Returns if the LSQ of a specific thread is stalled due to a memory 2382292SN/A * operation that must be replayed. 2392292SN/A */ 2406221Snate@binkert.org bool isStalled(ThreadID tid); 2412292SN/A 2422292SN/A /** Returns whether or not there are any stores to write back to memory. */ 2432292SN/A bool hasStoresToWB(); 2442329SN/A 2452292SN/A /** Returns whether or not a specific thread has any stores to write back 2462292SN/A * to memory. 2472292SN/A */ 2486221Snate@binkert.org bool hasStoresToWB(ThreadID tid) 2492329SN/A { return thread[tid].hasStoresToWB(); } 2502329SN/A 2512292SN/A /** Returns the number of stores a specific thread has to write back. */ 2526221Snate@binkert.org int numStoresToWB(ThreadID tid) 2532329SN/A { return thread[tid].numStoresToWB(); } 2542292SN/A 2552292SN/A /** Returns if the LSQ will write back to memory this cycle. */ 2562292SN/A bool willWB(); 2572292SN/A /** Returns if the LSQ of a specific thread will write back to memory this 2582292SN/A * cycle. 2592292SN/A */ 2606221Snate@binkert.org bool willWB(ThreadID tid) 2612329SN/A { return thread[tid].willWB(); } 2622292SN/A 2632907Sktlim@umich.edu /** Returns if the cache is currently blocked. */ 2642907Sktlim@umich.edu bool cacheBlocked() 2656221Snate@binkert.org { return retryTid != InvalidThreadID; } 2662907Sktlim@umich.edu 2672907Sktlim@umich.edu /** Sets the retry thread id, indicating that one of the LSQUnits 2682907Sktlim@umich.edu * tried to access the cache but the cache was blocked. */ 2696221Snate@binkert.org void setRetryTid(ThreadID tid) 2702907Sktlim@umich.edu { retryTid = tid; } 2712907Sktlim@umich.edu 2722292SN/A /** Debugging function to print out all instructions. */ 2732292SN/A void dumpInsts(); 2742292SN/A /** Debugging function to print out instructions from a specific thread. */ 2756221Snate@binkert.org void dumpInsts(ThreadID tid) 2762329SN/A { thread[tid].dumpInsts(); } 2772292SN/A 2786974Stjones1@inf.ed.ac.uk /** Executes a read operation, using the load specified at the load 2796974Stjones1@inf.ed.ac.uk * index. 2806974Stjones1@inf.ed.ac.uk */ 2816974Stjones1@inf.ed.ac.uk Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 2827520Sgblack@eecs.umich.edu uint8_t *data, int load_idx); 2832292SN/A 2842292SN/A /** Executes a store operation, using the store specified at the store 2856974Stjones1@inf.ed.ac.uk * index. 2862292SN/A */ 2876974Stjones1@inf.ed.ac.uk Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 2887520Sgblack@eecs.umich.edu uint8_t *data, int store_idx); 2892292SN/A 2908707Sandreas.hansson@arm.com /** 2918707Sandreas.hansson@arm.com * Retry the previous send that failed. 2928707Sandreas.hansson@arm.com */ 2938707Sandreas.hansson@arm.com void recvRetry(); 2948707Sandreas.hansson@arm.com 2958707Sandreas.hansson@arm.com /** 2968707Sandreas.hansson@arm.com * Handles writing back and completing the load or store that has 2978707Sandreas.hansson@arm.com * returned from memory. 2988707Sandreas.hansson@arm.com * 2998707Sandreas.hansson@arm.com * @param pkt Response packet from the memory sub-system 3008707Sandreas.hansson@arm.com */ 3018707Sandreas.hansson@arm.com bool recvTiming(PacketPtr pkt); 3028707Sandreas.hansson@arm.com 3034329Sktlim@umich.edu /** The CPU pointer. */ 3044329Sktlim@umich.edu O3CPU *cpu; 3054329Sktlim@umich.edu 3064329Sktlim@umich.edu /** The IEW stage pointer. */ 3074329Sktlim@umich.edu IEW *iewStage; 3084329Sktlim@umich.edu 3092907Sktlim@umich.edu protected: 3102292SN/A /** The LSQ policy for SMT mode. */ 3112292SN/A LSQPolicy lsqPolicy; 3122292SN/A 3132292SN/A /** The LSQ units for individual threads. */ 3142292SN/A LSQUnit thread[Impl::MaxThreads]; 3152292SN/A 3162292SN/A /** List of Active Threads in System. */ 3176221Snate@binkert.org std::list<ThreadID> *activeThreads; 3182292SN/A 3192292SN/A /** Total Size of LQ Entries. */ 3202292SN/A unsigned LQEntries; 3212292SN/A /** Total Size of SQ Entries. */ 3222292SN/A unsigned SQEntries; 3232292SN/A 3242292SN/A /** Max LQ Size - Used to Enforce Sharing Policies. */ 3252292SN/A unsigned maxLQEntries; 3262292SN/A 3272292SN/A /** Max SQ Size - Used to Enforce Sharing Policies. */ 3282292SN/A unsigned maxSQEntries; 3292292SN/A 3302292SN/A /** Number of Threads. */ 3316221Snate@binkert.org ThreadID numThreads; 3322907Sktlim@umich.edu 3332907Sktlim@umich.edu /** The thread id of the LSQ Unit that is currently waiting for a 3342907Sktlim@umich.edu * retry. */ 3356221Snate@binkert.org ThreadID retryTid; 3362292SN/A}; 3372292SN/A 3382292SN/Atemplate <class Impl> 3392292SN/AFault 3406974Stjones1@inf.ed.ac.ukLSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 3417520Sgblack@eecs.umich.edu uint8_t *data, int load_idx) 3422292SN/A{ 3436221Snate@binkert.org ThreadID tid = req->threadId(); 3442292SN/A 3456974Stjones1@inf.ed.ac.uk return thread[tid].read(req, sreqLow, sreqHigh, data, load_idx); 3462292SN/A} 3472292SN/A 3482292SN/Atemplate <class Impl> 3492292SN/AFault 3506974Stjones1@inf.ed.ac.ukLSQ<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 3517520Sgblack@eecs.umich.edu uint8_t *data, int store_idx) 3522292SN/A{ 3536221Snate@binkert.org ThreadID tid = req->threadId(); 3542292SN/A 3556974Stjones1@inf.ed.ac.uk return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx); 3562292SN/A} 3572292SN/A 3582292SN/A#endif // __CPU_O3_LSQ_HH__ 359