lsq.hh revision 4475
12292SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 32292SN/A * All rights reserved. 42292SN/A * 52292SN/A * Redistribution and use in source and binary forms, with or without 62292SN/A * modification, are permitted provided that the following conditions are 72292SN/A * met: redistributions of source code must retain the above copyright 82292SN/A * notice, this list of conditions and the following disclaimer; 92292SN/A * redistributions in binary form must reproduce the above copyright 102292SN/A * notice, this list of conditions and the following disclaimer in the 112292SN/A * documentation and/or other materials provided with the distribution; 122292SN/A * neither the name of the copyright holders nor the names of its 132292SN/A * contributors may be used to endorse or promote products derived from 142292SN/A * this software without specific prior written permission. 152292SN/A * 162292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Korey Sewell 292292SN/A */ 302292SN/A 312292SN/A#ifndef __CPU_O3_LSQ_HH__ 322292SN/A#define __CPU_O3_LSQ_HH__ 332292SN/A 342292SN/A#include <map> 352292SN/A#include <queue> 362292SN/A 372292SN/A#include "config/full_system.hh" 382292SN/A#include "cpu/inst_seq.hh" 392292SN/A#include "cpu/o3/lsq_unit.hh" 402669Sktlim@umich.edu#include "mem/port.hh" 412292SN/A#include "sim/sim_object.hh" 422292SN/A 432292SN/Atemplate <class Impl> 442292SN/Aclass LSQ { 452292SN/A public: 462292SN/A typedef typename Impl::Params Params; 472733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 482292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 492292SN/A typedef typename Impl::CPUPol::IEW IEW; 502292SN/A typedef typename Impl::CPUPol::LSQUnit LSQUnit; 512292SN/A 522348SN/A /** SMT policy. */ 532292SN/A enum LSQPolicy { 542292SN/A Dynamic, 552292SN/A Partitioned, 562292SN/A Threshold 572292SN/A }; 582292SN/A 592292SN/A /** Constructs an LSQ with the given parameters. */ 604329Sktlim@umich.edu LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params); 612292SN/A 622292SN/A /** Returns the name of the LSQ. */ 632292SN/A std::string name() const; 642292SN/A 652727Sktlim@umich.edu /** Registers statistics of each LSQ unit. */ 662727Sktlim@umich.edu void regStats(); 672727Sktlim@umich.edu 682871Sktlim@umich.edu /** Returns dcache port. 692871Sktlim@umich.edu * @todo: Dcache port needs to be moved up to this level for SMT 702871Sktlim@umich.edu * to work. For now it just returns the port from one of the 712871Sktlim@umich.edu * threads. 722871Sktlim@umich.edu */ 732907Sktlim@umich.edu Port *getDcachePort() { return &dcachePort; } 742871Sktlim@umich.edu 752292SN/A /** Sets the pointer to the list of active threads. */ 762292SN/A void setActiveThreads(std::list<unsigned> *at_ptr); 772348SN/A /** Switches out the LSQ. */ 782307SN/A void switchOut(); 792348SN/A /** Takes over execution from another CPU's thread. */ 802307SN/A void takeOverFrom(); 812307SN/A 822292SN/A /** Number of entries needed for the given amount of threads.*/ 832292SN/A int entryAmount(int num_threads); 842292SN/A void removeEntries(unsigned tid); 852292SN/A /** Reset the max entries for each thread. */ 862292SN/A void resetEntries(); 872292SN/A /** Resize the max entries for a thread. */ 882292SN/A void resizeEntries(unsigned size, unsigned tid); 892292SN/A 902292SN/A /** Ticks the LSQ. */ 912292SN/A void tick(); 922292SN/A /** Ticks a specific LSQ Unit. */ 932329SN/A void tick(unsigned tid) 942329SN/A { thread[tid].tick(); } 952292SN/A 962292SN/A /** Inserts a load into the LSQ. */ 972292SN/A void insertLoad(DynInstPtr &load_inst); 982292SN/A /** Inserts a store into the LSQ. */ 992292SN/A void insertStore(DynInstPtr &store_inst); 1002292SN/A 1012292SN/A /** Executes a load. */ 1022292SN/A Fault executeLoad(DynInstPtr &inst); 1032292SN/A 1042292SN/A /** Executes a store. */ 1052292SN/A Fault executeStore(DynInstPtr &inst); 1062292SN/A 1072292SN/A /** 1082292SN/A * Commits loads up until the given sequence number for a specific thread. 1092292SN/A */ 1102329SN/A void commitLoads(InstSeqNum &youngest_inst, unsigned tid) 1112329SN/A { thread[tid].commitLoads(youngest_inst); } 1122329SN/A 1132292SN/A /** 1142292SN/A * Commits stores up until the given sequence number for a specific thread. 1152292SN/A */ 1162329SN/A void commitStores(InstSeqNum &youngest_inst, unsigned tid) 1172329SN/A { thread[tid].commitStores(youngest_inst); } 1182292SN/A 1192292SN/A /** 1202292SN/A * Attempts to write back stores until all cache ports are used or the 1212292SN/A * interface becomes blocked. 1222292SN/A */ 1232292SN/A void writebackStores(); 1242292SN/A /** Same as above, but only for one thread. */ 1252292SN/A void writebackStores(unsigned tid); 1262292SN/A 1272292SN/A /** 1282292SN/A * Squash instructions from a thread until the specified sequence number. 1292292SN/A */ 1302329SN/A void squash(const InstSeqNum &squashed_num, unsigned tid) 1312329SN/A { thread[tid].squash(squashed_num); } 1322292SN/A 1332292SN/A /** Returns whether or not there was a memory ordering violation. */ 1342292SN/A bool violation(); 1352292SN/A /** 1362292SN/A * Returns whether or not there was a memory ordering violation for a 1372292SN/A * specific thread. 1382292SN/A */ 1392329SN/A bool violation(unsigned tid) 1402329SN/A { return thread[tid].violation(); } 1412292SN/A 1422292SN/A /** Returns if a load is blocked due to the memory system for a specific 1432292SN/A * thread. 1442292SN/A */ 1452329SN/A bool loadBlocked(unsigned tid) 1462329SN/A { return thread[tid].loadBlocked(); } 1472292SN/A 1482292SN/A bool isLoadBlockedHandled(unsigned tid) 1492292SN/A { return thread[tid].isLoadBlockedHandled(); } 1502292SN/A 1512292SN/A void setLoadBlockedHandled(unsigned tid) 1522292SN/A { thread[tid].setLoadBlockedHandled(); } 1532292SN/A 1542292SN/A /** Gets the instruction that caused the memory ordering violation. */ 1552329SN/A DynInstPtr getMemDepViolator(unsigned tid) 1562329SN/A { return thread[tid].getMemDepViolator(); } 1572292SN/A 1582292SN/A /** Returns the head index of the load queue for a specific thread. */ 1592329SN/A int getLoadHead(unsigned tid) 1602329SN/A { return thread[tid].getLoadHead(); } 1612329SN/A 1622292SN/A /** Returns the sequence number of the head of the load queue. */ 1632292SN/A InstSeqNum getLoadHeadSeqNum(unsigned tid) 1642292SN/A { 1652292SN/A return thread[tid].getLoadHeadSeqNum(); 1662292SN/A } 1672292SN/A 1682292SN/A /** Returns the head index of the store queue. */ 1692329SN/A int getStoreHead(unsigned tid) 1702329SN/A { return thread[tid].getStoreHead(); } 1712329SN/A 1722292SN/A /** Returns the sequence number of the head of the store queue. */ 1732292SN/A InstSeqNum getStoreHeadSeqNum(unsigned tid) 1742292SN/A { 1752292SN/A return thread[tid].getStoreHeadSeqNum(); 1762292SN/A } 1772292SN/A 1782292SN/A /** Returns the number of instructions in all of the queues. */ 1792292SN/A int getCount(); 1802292SN/A /** Returns the number of instructions in the queues of one thread. */ 1812329SN/A int getCount(unsigned tid) 1822329SN/A { return thread[tid].getCount(); } 1832292SN/A 1842292SN/A /** Returns the total number of loads in the load queue. */ 1852292SN/A int numLoads(); 1862292SN/A /** Returns the total number of loads for a single thread. */ 1872329SN/A int numLoads(unsigned tid) 1882329SN/A { return thread[tid].numLoads(); } 1892292SN/A 1902292SN/A /** Returns the total number of stores in the store queue. */ 1912292SN/A int numStores(); 1922292SN/A /** Returns the total number of stores for a single thread. */ 1932329SN/A int numStores(unsigned tid) 1942329SN/A { return thread[tid].numStores(); } 1952292SN/A 1962292SN/A /** Returns the total number of loads that are ready. */ 1972292SN/A int numLoadsReady(); 1982292SN/A /** Returns the number of loads that are ready for a single thread. */ 1992329SN/A int numLoadsReady(unsigned tid) 2002329SN/A { return thread[tid].numLoadsReady(); } 2012292SN/A 2022292SN/A /** Returns the number of free entries. */ 2032292SN/A unsigned numFreeEntries(); 2042292SN/A /** Returns the number of free entries for a specific thread. */ 2052292SN/A unsigned numFreeEntries(unsigned tid); 2062292SN/A 2072292SN/A /** Returns if the LSQ is full (either LQ or SQ is full). */ 2082292SN/A bool isFull(); 2092292SN/A /** 2102292SN/A * Returns if the LSQ is full for a specific thread (either LQ or SQ is 2112292SN/A * full). 2122292SN/A */ 2132292SN/A bool isFull(unsigned tid); 2142292SN/A 2152292SN/A /** Returns if any of the LQs are full. */ 2162292SN/A bool lqFull(); 2172292SN/A /** Returns if the LQ of a given thread is full. */ 2182292SN/A bool lqFull(unsigned tid); 2192292SN/A 2202292SN/A /** Returns if any of the SQs are full. */ 2212292SN/A bool sqFull(); 2222292SN/A /** Returns if the SQ of a given thread is full. */ 2232292SN/A bool sqFull(unsigned tid); 2242292SN/A 2252292SN/A /** 2262292SN/A * Returns if the LSQ is stalled due to a memory operation that must be 2272292SN/A * replayed. 2282292SN/A */ 2292292SN/A bool isStalled(); 2302292SN/A /** 2312292SN/A * Returns if the LSQ of a specific thread is stalled due to a memory 2322292SN/A * operation that must be replayed. 2332292SN/A */ 2342292SN/A bool isStalled(unsigned tid); 2352292SN/A 2362292SN/A /** Returns whether or not there are any stores to write back to memory. */ 2372292SN/A bool hasStoresToWB(); 2382329SN/A 2392292SN/A /** Returns whether or not a specific thread has any stores to write back 2402292SN/A * to memory. 2412292SN/A */ 2422329SN/A bool hasStoresToWB(unsigned tid) 2432329SN/A { return thread[tid].hasStoresToWB(); } 2442329SN/A 2452292SN/A /** Returns the number of stores a specific thread has to write back. */ 2462329SN/A int numStoresToWB(unsigned tid) 2472329SN/A { return thread[tid].numStoresToWB(); } 2482292SN/A 2492292SN/A /** Returns if the LSQ will write back to memory this cycle. */ 2502292SN/A bool willWB(); 2512292SN/A /** Returns if the LSQ of a specific thread will write back to memory this 2522292SN/A * cycle. 2532292SN/A */ 2542329SN/A bool willWB(unsigned tid) 2552329SN/A { return thread[tid].willWB(); } 2562292SN/A 2572907Sktlim@umich.edu /** Returns if the cache is currently blocked. */ 2582907Sktlim@umich.edu bool cacheBlocked() 2592907Sktlim@umich.edu { return retryTid != -1; } 2602907Sktlim@umich.edu 2612907Sktlim@umich.edu /** Sets the retry thread id, indicating that one of the LSQUnits 2622907Sktlim@umich.edu * tried to access the cache but the cache was blocked. */ 2632907Sktlim@umich.edu void setRetryTid(int tid) 2642907Sktlim@umich.edu { retryTid = tid; } 2652907Sktlim@umich.edu 2662292SN/A /** Debugging function to print out all instructions. */ 2672292SN/A void dumpInsts(); 2682292SN/A /** Debugging function to print out instructions from a specific thread. */ 2692329SN/A void dumpInsts(unsigned tid) 2702329SN/A { thread[tid].dumpInsts(); } 2712292SN/A 2722292SN/A /** Executes a read operation, using the load specified at the load index. */ 2732292SN/A template <class T> 2742669Sktlim@umich.edu Fault read(RequestPtr req, T &data, int load_idx); 2752292SN/A 2762292SN/A /** Executes a store operation, using the store specified at the store 2772292SN/A * index. 2782292SN/A */ 2792292SN/A template <class T> 2802669Sktlim@umich.edu Fault write(RequestPtr req, T &data, int store_idx); 2812292SN/A 2824329Sktlim@umich.edu /** The CPU pointer. */ 2834329Sktlim@umich.edu O3CPU *cpu; 2844329Sktlim@umich.edu 2854329Sktlim@umich.edu /** The IEW stage pointer. */ 2864329Sktlim@umich.edu IEW *iewStage; 2874329Sktlim@umich.edu 2882907Sktlim@umich.edu /** DcachePort class for this LSQ. Handles doing the 2892907Sktlim@umich.edu * communication with the cache/memory. 2902907Sktlim@umich.edu */ 2912907Sktlim@umich.edu class DcachePort : public Port 2922907Sktlim@umich.edu { 2932907Sktlim@umich.edu protected: 2942907Sktlim@umich.edu /** Pointer to LSQ. */ 2952907Sktlim@umich.edu LSQ *lsq; 2962907Sktlim@umich.edu 2972907Sktlim@umich.edu public: 2982907Sktlim@umich.edu /** Default constructor. */ 2992907Sktlim@umich.edu DcachePort(LSQ *_lsq) 3004329Sktlim@umich.edu : Port(_lsq->name() + "-dport"), lsq(_lsq) 3012907Sktlim@umich.edu { } 3022907Sktlim@umich.edu 3033647Srdreslin@umich.edu bool snoopRangeSent; 3043647Srdreslin@umich.edu 3054192Sktlim@umich.edu virtual void setPeer(Port *port); 3064192Sktlim@umich.edu 3072907Sktlim@umich.edu protected: 3082907Sktlim@umich.edu /** Atomic version of receive. Panics. */ 3092907Sktlim@umich.edu virtual Tick recvAtomic(PacketPtr pkt); 3102907Sktlim@umich.edu 3112907Sktlim@umich.edu /** Functional version of receive. Panics. */ 3122907Sktlim@umich.edu virtual void recvFunctional(PacketPtr pkt); 3132907Sktlim@umich.edu 3142907Sktlim@umich.edu /** Receives status change. Other than range changing, panics. */ 3152907Sktlim@umich.edu virtual void recvStatusChange(Status status); 3162907Sktlim@umich.edu 3172907Sktlim@umich.edu /** Returns the address ranges of this device. */ 3182907Sktlim@umich.edu virtual void getDeviceAddressRanges(AddrRangeList &resp, 3194475Sstever@eecs.umich.edu bool &snoop) 3204475Sstever@eecs.umich.edu { resp.clear(); snoop = true; } 3212907Sktlim@umich.edu 3222907Sktlim@umich.edu /** Timing version of receive. Handles writing back and 3232907Sktlim@umich.edu * completing the load or store that has returned from 3242907Sktlim@umich.edu * memory. */ 3252907Sktlim@umich.edu virtual bool recvTiming(PacketPtr pkt); 3262907Sktlim@umich.edu 3272907Sktlim@umich.edu /** Handles doing a retry of the previous send. */ 3282907Sktlim@umich.edu virtual void recvRetry(); 3292907Sktlim@umich.edu }; 3302907Sktlim@umich.edu 3312907Sktlim@umich.edu /** D-cache port. */ 3322907Sktlim@umich.edu DcachePort dcachePort; 3332907Sktlim@umich.edu 3344192Sktlim@umich.edu#if FULL_SYSTEM 3354192Sktlim@umich.edu /** Tell the CPU to update the Phys and Virt ports. */ 3364192Sktlim@umich.edu void updateMemPorts() { cpu->updateMemPorts(); } 3374192Sktlim@umich.edu#endif 3384192Sktlim@umich.edu 3392907Sktlim@umich.edu protected: 3402292SN/A /** The LSQ policy for SMT mode. */ 3412292SN/A LSQPolicy lsqPolicy; 3422292SN/A 3432292SN/A /** The LSQ units for individual threads. */ 3442292SN/A LSQUnit thread[Impl::MaxThreads]; 3452292SN/A 3462292SN/A /** List of Active Threads in System. */ 3472292SN/A std::list<unsigned> *activeThreads; 3482292SN/A 3492292SN/A /** Total Size of LQ Entries. */ 3502292SN/A unsigned LQEntries; 3512292SN/A /** Total Size of SQ Entries. */ 3522292SN/A unsigned SQEntries; 3532292SN/A 3542292SN/A /** Max LQ Size - Used to Enforce Sharing Policies. */ 3552292SN/A unsigned maxLQEntries; 3562292SN/A 3572292SN/A /** Max SQ Size - Used to Enforce Sharing Policies. */ 3582292SN/A unsigned maxSQEntries; 3592292SN/A 3602292SN/A /** Number of Threads. */ 3612292SN/A unsigned numThreads; 3622907Sktlim@umich.edu 3632907Sktlim@umich.edu /** The thread id of the LSQ Unit that is currently waiting for a 3642907Sktlim@umich.edu * retry. */ 3652907Sktlim@umich.edu int retryTid; 3662292SN/A}; 3672292SN/A 3682292SN/Atemplate <class Impl> 3692292SN/Atemplate <class T> 3702292SN/AFault 3712669Sktlim@umich.eduLSQ<Impl>::read(RequestPtr req, T &data, int load_idx) 3722292SN/A{ 3732669Sktlim@umich.edu unsigned tid = req->getThreadNum(); 3742292SN/A 3752292SN/A return thread[tid].read(req, data, load_idx); 3762292SN/A} 3772292SN/A 3782292SN/Atemplate <class Impl> 3792292SN/Atemplate <class T> 3802292SN/AFault 3812669Sktlim@umich.eduLSQ<Impl>::write(RequestPtr req, T &data, int store_idx) 3822292SN/A{ 3832669Sktlim@umich.edu unsigned tid = req->getThreadNum(); 3842292SN/A 3852292SN/A return thread[tid].write(req, data, store_idx); 3862292SN/A} 3872292SN/A 3882292SN/A#endif // __CPU_O3_LSQ_HH__ 389