lsq.hh revision 2307 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_O3_LSQ_HH__
30#define __CPU_O3_LSQ_HH__
31
32#include <map>
33#include <queue>
34
35#include "base/hashmap.hh"
36#include "config/full_system.hh"
37#include "cpu/inst_seq.hh"
38#include "cpu/o3/cpu_policy.hh"
39#include "cpu/o3/lsq_unit.hh"
40#include "mem/mem_interface.hh"
41//#include "mem/page_table.hh"
42#include "sim/sim_object.hh"
43
44template <class Impl>
45class LSQ {
46  public:
47    typedef typename Impl::Params Params;
48    typedef typename Impl::FullCPU FullCPU;
49    typedef typename Impl::DynInstPtr DynInstPtr;
50    typedef typename Impl::CPUPol::IEW IEW;
51    typedef typename Impl::CPUPol::LSQUnit LSQUnit;
52
53    enum LSQPolicy {
54        Dynamic,
55        Partitioned,
56        Threshold
57    };
58
59    /** Constructs an LSQ with the given parameters. */
60    LSQ(Params *params);
61
62    /** Returns the name of the LSQ. */
63    std::string name() const;
64
65    /** Sets the pointer to the list of active threads. */
66    void setActiveThreads(std::list<unsigned> *at_ptr);
67    /** Sets the CPU pointer. */
68    void setCPU(FullCPU *cpu_ptr);
69    /** Sets the IEW stage pointer. */
70    void setIEW(IEW *iew_ptr);
71    /** Sets the page table pointer. */
72//    void setPageTable(PageTable *pt_ptr);
73
74    void switchOut();
75    void takeOverFrom();
76
77    /** Number of entries needed for the given amount of threads.*/
78    int entryAmount(int num_threads);
79    void removeEntries(unsigned tid);
80    /** Reset the max entries for each thread. */
81    void resetEntries();
82    /** Resize the max entries for a thread. */
83    void resizeEntries(unsigned size, unsigned tid);
84
85    /** Ticks the LSQ. */
86    void tick();
87    /** Ticks a specific LSQ Unit. */
88    void tick(unsigned tid);
89
90    /** Inserts a load into the LSQ. */
91    void insertLoad(DynInstPtr &load_inst);
92    /** Inserts a store into the LSQ. */
93    void insertStore(DynInstPtr &store_inst);
94
95    /** Executes a load. */
96    Fault executeLoad(DynInstPtr &inst);
97
98    Fault executeLoad(int lq_idx, unsigned tid);
99    /** Executes a store. */
100    Fault executeStore(DynInstPtr &inst);
101
102    /**
103     * Commits loads up until the given sequence number for a specific thread.
104     */
105    void commitLoads(InstSeqNum &youngest_inst, unsigned tid);
106    /**
107     * Commits stores up until the given sequence number for a specific thread.
108     */
109    void commitStores(InstSeqNum &youngest_inst, unsigned tid);
110
111    /**
112     * Attempts to write back stores until all cache ports are used or the
113     * interface becomes blocked.
114     */
115    void writebackStores();
116    /** Same as above, but only for one thread. */
117    void writebackStores(unsigned tid);
118
119    /**
120     * Squash instructions from a thread until the specified sequence number.
121     */
122    void squash(const InstSeqNum &squashed_num, unsigned tid);
123
124    /** Returns whether or not there was a memory ordering violation. */
125    bool violation();
126    /**
127     * Returns whether or not there was a memory ordering violation for a
128     * specific thread.
129     */
130    bool violation(unsigned tid);
131
132    /** Returns if a load is blocked due to the memory system for a specific
133     *  thread.
134     */
135    bool loadBlocked(unsigned tid);
136
137    bool isLoadBlockedHandled(unsigned tid)
138    { return thread[tid].isLoadBlockedHandled(); }
139
140    void setLoadBlockedHandled(unsigned tid)
141    { thread[tid].setLoadBlockedHandled(); }
142
143    /** Gets the instruction that caused the memory ordering violation. */
144    DynInstPtr getMemDepViolator(unsigned tid);
145
146    /** Returns the head index of the load queue for a specific thread. */
147    int getLoadHead(unsigned tid);
148    /** Returns the sequence number of the head of the load queue. */
149    InstSeqNum getLoadHeadSeqNum(unsigned tid)
150    {
151        return thread[tid].getLoadHeadSeqNum();
152    }
153
154    /** Returns the head index of the store queue. */
155    int getStoreHead(unsigned tid);
156    /** Returns the sequence number of the head of the store queue. */
157    InstSeqNum getStoreHeadSeqNum(unsigned tid)
158    {
159        return thread[tid].getStoreHeadSeqNum();
160    }
161
162    /** Returns the number of instructions in all of the queues. */
163    int getCount();
164    /** Returns the number of instructions in the queues of one thread. */
165    int getCount(unsigned tid);
166
167    /** Returns the total number of loads in the load queue. */
168    int numLoads();
169    /** Returns the total number of loads for a single thread. */
170    int numLoads(unsigned tid);
171
172    /** Returns the total number of stores in the store queue. */
173    int numStores();
174    /** Returns the total number of stores for a single thread. */
175    int numStores(unsigned tid);
176
177    /** Returns the total number of loads that are ready. */
178    int numLoadsReady();
179    /** Returns the number of loads that are ready for a single thread. */
180    int numLoadsReady(unsigned tid);
181
182    /** Returns the number of free entries. */
183    unsigned numFreeEntries();
184    /** Returns the number of free entries for a specific thread. */
185    unsigned numFreeEntries(unsigned tid);
186
187    /** Returns if the LSQ is full (either LQ or SQ is full). */
188    bool isFull();
189    /**
190     * Returns if the LSQ is full for a specific thread (either LQ or SQ is
191     * full).
192     */
193    bool isFull(unsigned tid);
194
195    /** Returns if any of the LQs are full. */
196    bool lqFull();
197    /** Returns if the LQ of a given thread is full. */
198    bool lqFull(unsigned tid);
199
200    /** Returns if any of the SQs are full. */
201    bool sqFull();
202    /** Returns if the SQ of a given thread is full. */
203    bool sqFull(unsigned tid);
204
205    /**
206     * Returns if the LSQ is stalled due to a memory operation that must be
207     * replayed.
208     */
209    bool isStalled();
210    /**
211     * Returns if the LSQ of a specific thread is stalled due to a memory
212     * operation that must be replayed.
213     */
214    bool isStalled(unsigned tid);
215
216    /** Returns whether or not there are any stores to write back to memory. */
217    bool hasStoresToWB();
218    /** Returns whether or not a specific thread has any stores to write back
219     * to memory.
220     */
221    bool hasStoresToWB(unsigned tid);
222    /** Returns the number of stores a specific thread has to write back. */
223    int  numStoresToWB(unsigned tid);
224
225    /** Returns if the LSQ will write back to memory this cycle. */
226    bool willWB();
227    /** Returns if the LSQ of a specific thread will write back to memory this
228     * cycle.
229     */
230    bool willWB(unsigned tid);
231
232    /** Debugging function to print out all instructions. */
233    void dumpInsts();
234    /** Debugging function to print out instructions from a specific thread. */
235    void dumpInsts(unsigned tid);
236
237    /** Executes a read operation, using the load specified at the load index. */
238    template <class T>
239    Fault read(MemReqPtr &req, T &data, int load_idx);
240
241    /** Executes a store operation, using the store specified at the store
242     *   index.
243     */
244    template <class T>
245    Fault write(MemReqPtr &req, T &data, int store_idx);
246
247  private:
248    /** The LSQ policy for SMT mode. */
249    LSQPolicy lsqPolicy;
250
251    /** The LSQ units for individual threads. */
252    LSQUnit thread[Impl::MaxThreads];
253
254    /** The CPU pointer. */
255    FullCPU *cpu;
256
257    /** The IEW stage pointer. */
258    IEW *iewStage;
259
260    /** The pointer to the page table. */
261//    PageTable *pTable;
262
263    /** List of Active Threads in System. */
264    std::list<unsigned> *activeThreads;
265
266    /** Total Size of LQ Entries. */
267    unsigned LQEntries;
268    /** Total Size of SQ Entries. */
269    unsigned SQEntries;
270
271    /** Max LQ Size - Used to Enforce Sharing Policies. */
272    unsigned maxLQEntries;
273
274    /** Max SQ Size - Used to Enforce Sharing Policies. */
275    unsigned maxSQEntries;
276
277    /** Number of Threads. */
278    unsigned numThreads;
279};
280
281template <class Impl>
282template <class T>
283Fault
284LSQ<Impl>::read(MemReqPtr &req, T &data, int load_idx)
285{
286    unsigned tid = req->thread_num;
287
288    return thread[tid].read(req, data, load_idx);
289}
290
291template <class Impl>
292template <class T>
293Fault
294LSQ<Impl>::write(MemReqPtr &req, T &data, int store_idx)
295{
296    unsigned tid = req->thread_num;
297
298    return thread[tid].write(req, data, store_idx);
299}
300
301#endif // __CPU_O3_LSQ_HH__
302