lsq.hh revision 10379
12292SN/A/* 210333Smitch.hayenga@arm.com * Copyright (c) 2011-2012, 2014 ARM Limited 310239Sbinhpham@cs.rutgers.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 48707Sandreas.hansson@arm.com * All rights reserved 58707Sandreas.hansson@arm.com * 68707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148707Sandreas.hansson@arm.com * 152329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 162292SN/A * All rights reserved. 172292SN/A * 182292SN/A * Redistribution and use in source and binary forms, with or without 192292SN/A * modification, are permitted provided that the following conditions are 202292SN/A * met: redistributions of source code must retain the above copyright 212292SN/A * notice, this list of conditions and the following disclaimer; 222292SN/A * redistributions in binary form must reproduce the above copyright 232292SN/A * notice, this list of conditions and the following disclaimer in the 242292SN/A * documentation and/or other materials provided with the distribution; 252292SN/A * neither the name of the copyright holders nor the names of its 262292SN/A * contributors may be used to endorse or promote products derived from 272292SN/A * this software without specific prior written permission. 282292SN/A * 292292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402689Sktlim@umich.edu * 412689Sktlim@umich.edu * Authors: Korey Sewell 422292SN/A */ 432292SN/A 442292SN/A#ifndef __CPU_O3_LSQ_HH__ 452292SN/A#define __CPU_O3_LSQ_HH__ 462292SN/A 472292SN/A#include <map> 482292SN/A#include <queue> 492292SN/A 508229Snate@binkert.org#include "cpu/o3/lsq_unit.hh" 512292SN/A#include "cpu/inst_seq.hh" 522669Sktlim@umich.edu#include "mem/port.hh" 532292SN/A#include "sim/sim_object.hh" 542292SN/A 558737Skoansin.tan@gmail.comstruct DerivO3CPUParams; 565529Snate@binkert.org 572292SN/Atemplate <class Impl> 582292SN/Aclass LSQ { 592292SN/A public: 602733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 612292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 622292SN/A typedef typename Impl::CPUPol::IEW IEW; 632292SN/A typedef typename Impl::CPUPol::LSQUnit LSQUnit; 642292SN/A 652348SN/A /** SMT policy. */ 662292SN/A enum LSQPolicy { 672292SN/A Dynamic, 682292SN/A Partitioned, 692292SN/A Threshold 702292SN/A }; 712292SN/A 722292SN/A /** Constructs an LSQ with the given parameters. */ 735529Snate@binkert.org LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params); 749868Sjthestness@gmail.com ~LSQ() { 759868Sjthestness@gmail.com if (thread) delete [] thread; 769868Sjthestness@gmail.com } 772292SN/A 782292SN/A /** Returns the name of the LSQ. */ 792292SN/A std::string name() const; 802292SN/A 812727Sktlim@umich.edu /** Registers statistics of each LSQ unit. */ 822727Sktlim@umich.edu void regStats(); 832727Sktlim@umich.edu 842292SN/A /** Sets the pointer to the list of active threads. */ 856221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 869444SAndreas.Sandberg@ARM.com 879444SAndreas.Sandberg@ARM.com /** Perform sanity checks after a drain. */ 889444SAndreas.Sandberg@ARM.com void drainSanityCheck() const; 899444SAndreas.Sandberg@ARM.com /** Has the LSQ drained? */ 909444SAndreas.Sandberg@ARM.com bool isDrained() const; 912348SN/A /** Takes over execution from another CPU's thread. */ 922307SN/A void takeOverFrom(); 932307SN/A 942292SN/A /** Number of entries needed for the given amount of threads.*/ 956221Snate@binkert.org int entryAmount(ThreadID num_threads); 966221Snate@binkert.org void removeEntries(ThreadID tid); 972292SN/A /** Reset the max entries for each thread. */ 982292SN/A void resetEntries(); 992292SN/A /** Resize the max entries for a thread. */ 1006221Snate@binkert.org void resizeEntries(unsigned size, ThreadID tid); 1012292SN/A 1022292SN/A /** Ticks the LSQ. */ 1032292SN/A void tick(); 1042292SN/A /** Ticks a specific LSQ Unit. */ 1056221Snate@binkert.org void tick(ThreadID tid) 1062329SN/A { thread[tid].tick(); } 1072292SN/A 1082292SN/A /** Inserts a load into the LSQ. */ 1092292SN/A void insertLoad(DynInstPtr &load_inst); 1102292SN/A /** Inserts a store into the LSQ. */ 1112292SN/A void insertStore(DynInstPtr &store_inst); 1122292SN/A 1132292SN/A /** Executes a load. */ 1142292SN/A Fault executeLoad(DynInstPtr &inst); 1152292SN/A 1162292SN/A /** Executes a store. */ 1172292SN/A Fault executeStore(DynInstPtr &inst); 1182292SN/A 1192292SN/A /** 1202292SN/A * Commits loads up until the given sequence number for a specific thread. 1212292SN/A */ 1226221Snate@binkert.org void commitLoads(InstSeqNum &youngest_inst, ThreadID tid) 1232329SN/A { thread[tid].commitLoads(youngest_inst); } 1242329SN/A 1252292SN/A /** 1262292SN/A * Commits stores up until the given sequence number for a specific thread. 1272292SN/A */ 1286221Snate@binkert.org void commitStores(InstSeqNum &youngest_inst, ThreadID tid) 1292329SN/A { thread[tid].commitStores(youngest_inst); } 1302292SN/A 1312292SN/A /** 1322292SN/A * Attempts to write back stores until all cache ports are used or the 1332292SN/A * interface becomes blocked. 1342292SN/A */ 1352292SN/A void writebackStores(); 1362292SN/A /** Same as above, but only for one thread. */ 1376221Snate@binkert.org void writebackStores(ThreadID tid); 1382292SN/A 1392292SN/A /** 1402292SN/A * Squash instructions from a thread until the specified sequence number. 1412292SN/A */ 1426221Snate@binkert.org void squash(const InstSeqNum &squashed_num, ThreadID tid) 1432329SN/A { thread[tid].squash(squashed_num); } 1442292SN/A 1452292SN/A /** Returns whether or not there was a memory ordering violation. */ 1462292SN/A bool violation(); 1472292SN/A /** 1482292SN/A * Returns whether or not there was a memory ordering violation for a 1492292SN/A * specific thread. 1502292SN/A */ 1516221Snate@binkert.org bool violation(ThreadID tid) 1522329SN/A { return thread[tid].violation(); } 1532292SN/A 1542292SN/A /** Gets the instruction that caused the memory ordering violation. */ 1556221Snate@binkert.org DynInstPtr getMemDepViolator(ThreadID tid) 1562329SN/A { return thread[tid].getMemDepViolator(); } 1572292SN/A 1582292SN/A /** Returns the head index of the load queue for a specific thread. */ 1596221Snate@binkert.org int getLoadHead(ThreadID tid) 1602329SN/A { return thread[tid].getLoadHead(); } 1612329SN/A 1622292SN/A /** Returns the sequence number of the head of the load queue. */ 1636221Snate@binkert.org InstSeqNum getLoadHeadSeqNum(ThreadID tid) 1642292SN/A { 1652292SN/A return thread[tid].getLoadHeadSeqNum(); 1662292SN/A } 1672292SN/A 1682292SN/A /** Returns the head index of the store queue. */ 1696221Snate@binkert.org int getStoreHead(ThreadID tid) 1702329SN/A { return thread[tid].getStoreHead(); } 1712329SN/A 1722292SN/A /** Returns the sequence number of the head of the store queue. */ 1736221Snate@binkert.org InstSeqNum getStoreHeadSeqNum(ThreadID tid) 1742292SN/A { 1752292SN/A return thread[tid].getStoreHeadSeqNum(); 1762292SN/A } 1772292SN/A 1782292SN/A /** Returns the number of instructions in all of the queues. */ 1792292SN/A int getCount(); 1802292SN/A /** Returns the number of instructions in the queues of one thread. */ 1816221Snate@binkert.org int getCount(ThreadID tid) 1822329SN/A { return thread[tid].getCount(); } 1832292SN/A 1842292SN/A /** Returns the total number of loads in the load queue. */ 1852292SN/A int numLoads(); 1862292SN/A /** Returns the total number of loads for a single thread. */ 1876221Snate@binkert.org int numLoads(ThreadID tid) 1882329SN/A { return thread[tid].numLoads(); } 1892292SN/A 1902292SN/A /** Returns the total number of stores in the store queue. */ 1912292SN/A int numStores(); 1922292SN/A /** Returns the total number of stores for a single thread. */ 1936221Snate@binkert.org int numStores(ThreadID tid) 1942329SN/A { return thread[tid].numStores(); } 1952292SN/A 19610239Sbinhpham@cs.rutgers.edu /** Returns the number of free load entries. */ 19710239Sbinhpham@cs.rutgers.edu unsigned numFreeLoadEntries(); 19810239Sbinhpham@cs.rutgers.edu 19910239Sbinhpham@cs.rutgers.edu /** Returns the number of free store entries. */ 20010239Sbinhpham@cs.rutgers.edu unsigned numFreeStoreEntries(); 20110239Sbinhpham@cs.rutgers.edu 2022292SN/A /** Returns the number of free entries for a specific thread. */ 2036221Snate@binkert.org unsigned numFreeEntries(ThreadID tid); 2042292SN/A 20510239Sbinhpham@cs.rutgers.edu /** Returns the number of free entries in the LQ for a specific thread. */ 20610239Sbinhpham@cs.rutgers.edu unsigned numFreeLoadEntries(ThreadID tid); 20710239Sbinhpham@cs.rutgers.edu 20810239Sbinhpham@cs.rutgers.edu /** Returns the number of free entries in the SQ for a specific thread. */ 20910239Sbinhpham@cs.rutgers.edu unsigned numFreeStoreEntries(ThreadID tid); 21010239Sbinhpham@cs.rutgers.edu 2112292SN/A /** Returns if the LSQ is full (either LQ or SQ is full). */ 2122292SN/A bool isFull(); 2132292SN/A /** 2142292SN/A * Returns if the LSQ is full for a specific thread (either LQ or SQ is 2152292SN/A * full). 2162292SN/A */ 2176221Snate@binkert.org bool isFull(ThreadID tid); 2182292SN/A 2199444SAndreas.Sandberg@ARM.com /** Returns if the LSQ is empty (both LQ and SQ are empty). */ 2209444SAndreas.Sandberg@ARM.com bool isEmpty() const; 2219444SAndreas.Sandberg@ARM.com /** Returns if all of the LQs are empty. */ 2229444SAndreas.Sandberg@ARM.com bool lqEmpty() const; 2239444SAndreas.Sandberg@ARM.com /** Returns if all of the SQs are empty. */ 2249444SAndreas.Sandberg@ARM.com bool sqEmpty() const; 2259444SAndreas.Sandberg@ARM.com 2262292SN/A /** Returns if any of the LQs are full. */ 2272292SN/A bool lqFull(); 2282292SN/A /** Returns if the LQ of a given thread is full. */ 2296221Snate@binkert.org bool lqFull(ThreadID tid); 2302292SN/A 2312292SN/A /** Returns if any of the SQs are full. */ 2322292SN/A bool sqFull(); 2332292SN/A /** Returns if the SQ of a given thread is full. */ 2346221Snate@binkert.org bool sqFull(ThreadID tid); 2352292SN/A 2362292SN/A /** 2372292SN/A * Returns if the LSQ is stalled due to a memory operation that must be 2382292SN/A * replayed. 2392292SN/A */ 2402292SN/A bool isStalled(); 2412292SN/A /** 2422292SN/A * Returns if the LSQ of a specific thread is stalled due to a memory 2432292SN/A * operation that must be replayed. 2442292SN/A */ 2456221Snate@binkert.org bool isStalled(ThreadID tid); 2462292SN/A 2472292SN/A /** Returns whether or not there are any stores to write back to memory. */ 2482292SN/A bool hasStoresToWB(); 2492329SN/A 2502292SN/A /** Returns whether or not a specific thread has any stores to write back 2512292SN/A * to memory. 2522292SN/A */ 2536221Snate@binkert.org bool hasStoresToWB(ThreadID tid) 2542329SN/A { return thread[tid].hasStoresToWB(); } 2552329SN/A 2562292SN/A /** Returns the number of stores a specific thread has to write back. */ 2576221Snate@binkert.org int numStoresToWB(ThreadID tid) 2582329SN/A { return thread[tid].numStoresToWB(); } 2592292SN/A 2602292SN/A /** Returns if the LSQ will write back to memory this cycle. */ 2612292SN/A bool willWB(); 2622292SN/A /** Returns if the LSQ of a specific thread will write back to memory this 2632292SN/A * cycle. 2642292SN/A */ 2656221Snate@binkert.org bool willWB(ThreadID tid) 2662329SN/A { return thread[tid].willWB(); } 2672292SN/A 2682292SN/A /** Debugging function to print out all instructions. */ 2699440SAndreas.Sandberg@ARM.com void dumpInsts() const; 2702292SN/A /** Debugging function to print out instructions from a specific thread. */ 2719440SAndreas.Sandberg@ARM.com void dumpInsts(ThreadID tid) const 2722329SN/A { thread[tid].dumpInsts(); } 2732292SN/A 2746974Stjones1@inf.ed.ac.uk /** Executes a read operation, using the load specified at the load 2756974Stjones1@inf.ed.ac.uk * index. 2766974Stjones1@inf.ed.ac.uk */ 2776974Stjones1@inf.ed.ac.uk Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 2787520Sgblack@eecs.umich.edu uint8_t *data, int load_idx); 2792292SN/A 2802292SN/A /** Executes a store operation, using the store specified at the store 2816974Stjones1@inf.ed.ac.uk * index. 2822292SN/A */ 2836974Stjones1@inf.ed.ac.uk Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 2847520Sgblack@eecs.umich.edu uint8_t *data, int store_idx); 2852292SN/A 2868707Sandreas.hansson@arm.com /** 2878707Sandreas.hansson@arm.com * Retry the previous send that failed. 2888707Sandreas.hansson@arm.com */ 2898707Sandreas.hansson@arm.com void recvRetry(); 2908707Sandreas.hansson@arm.com 2918707Sandreas.hansson@arm.com /** 2928707Sandreas.hansson@arm.com * Handles writing back and completing the load or store that has 2938707Sandreas.hansson@arm.com * returned from memory. 2948707Sandreas.hansson@arm.com * 2958707Sandreas.hansson@arm.com * @param pkt Response packet from the memory sub-system 2968707Sandreas.hansson@arm.com */ 2978975Sandreas.hansson@arm.com bool recvTimingResp(PacketPtr pkt); 2988707Sandreas.hansson@arm.com 2998975Sandreas.hansson@arm.com void recvTimingSnoopReq(PacketPtr pkt); 3008948Sandreas.hansson@arm.com 3014329Sktlim@umich.edu /** The CPU pointer. */ 3024329Sktlim@umich.edu O3CPU *cpu; 3034329Sktlim@umich.edu 3044329Sktlim@umich.edu /** The IEW stage pointer. */ 3054329Sktlim@umich.edu IEW *iewStage; 3064329Sktlim@umich.edu 3072907Sktlim@umich.edu protected: 3082292SN/A /** The LSQ policy for SMT mode. */ 3092292SN/A LSQPolicy lsqPolicy; 3102292SN/A 3112292SN/A /** The LSQ units for individual threads. */ 3129868Sjthestness@gmail.com LSQUnit *thread; 3132292SN/A 3142292SN/A /** List of Active Threads in System. */ 3156221Snate@binkert.org std::list<ThreadID> *activeThreads; 3162292SN/A 3172292SN/A /** Total Size of LQ Entries. */ 3182292SN/A unsigned LQEntries; 3192292SN/A /** Total Size of SQ Entries. */ 3202292SN/A unsigned SQEntries; 3212292SN/A 3222292SN/A /** Max LQ Size - Used to Enforce Sharing Policies. */ 3232292SN/A unsigned maxLQEntries; 3242292SN/A 3252292SN/A /** Max SQ Size - Used to Enforce Sharing Policies. */ 3262292SN/A unsigned maxSQEntries; 3272292SN/A 3282292SN/A /** Number of Threads. */ 3296221Snate@binkert.org ThreadID numThreads; 3302292SN/A}; 3312292SN/A 3322292SN/Atemplate <class Impl> 3332292SN/AFault 3346974Stjones1@inf.ed.ac.ukLSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 3357520Sgblack@eecs.umich.edu uint8_t *data, int load_idx) 3362292SN/A{ 3376221Snate@binkert.org ThreadID tid = req->threadId(); 3382292SN/A 3396974Stjones1@inf.ed.ac.uk return thread[tid].read(req, sreqLow, sreqHigh, data, load_idx); 3402292SN/A} 3412292SN/A 3422292SN/Atemplate <class Impl> 3432292SN/AFault 3446974Stjones1@inf.ed.ac.ukLSQ<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 3457520Sgblack@eecs.umich.edu uint8_t *data, int store_idx) 3462292SN/A{ 3476221Snate@binkert.org ThreadID tid = req->threadId(); 3482292SN/A 3496974Stjones1@inf.ed.ac.uk return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx); 3502292SN/A} 3512292SN/A 3522292SN/A#endif // __CPU_O3_LSQ_HH__ 353