inst_queue_impl.hh revision 8489:2e12a633d269
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Korey Sewell 42 */ 43 44#include <limits> 45#include <vector> 46 47#include "cpu/o3/fu_pool.hh" 48#include "cpu/o3/inst_queue.hh" 49#include "debug/IQ.hh" 50#include "enums/OpClass.hh" 51#include "params/DerivO3CPU.hh" 52#include "sim/core.hh" 53 54using namespace std; 55 56template <class Impl> 57InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 58 int fu_idx, InstructionQueue<Impl> *iq_ptr) 59 : Event(Stat_Event_Pri), inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), 60 freeFU(false) 61{ 62 this->setFlags(Event::AutoDelete); 63} 64 65template <class Impl> 66void 67InstructionQueue<Impl>::FUCompletion::process() 68{ 69 iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 70 inst = NULL; 71} 72 73 74template <class Impl> 75const char * 76InstructionQueue<Impl>::FUCompletion::description() const 77{ 78 return "Functional unit completion"; 79} 80 81template <class Impl> 82InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 83 DerivO3CPUParams *params) 84 : cpu(cpu_ptr), 85 iewStage(iew_ptr), 86 fuPool(params->fuPool), 87 numEntries(params->numIQEntries), 88 totalWidth(params->issueWidth), 89 numPhysIntRegs(params->numPhysIntRegs), 90 numPhysFloatRegs(params->numPhysFloatRegs), 91 commitToIEWDelay(params->commitToIEWDelay) 92{ 93 assert(fuPool); 94 95 switchedOut = false; 96 97 numThreads = params->numThreads; 98 99 // Set the number of physical registers as the number of int + float 100 numPhysRegs = numPhysIntRegs + numPhysFloatRegs; 101 102 //Create an entry for each physical register within the 103 //dependency graph. 104 dependGraph.resize(numPhysRegs); 105 106 // Resize the register scoreboard. 107 regScoreboard.resize(numPhysRegs); 108 109 //Initialize Mem Dependence Units 110 for (ThreadID tid = 0; tid < numThreads; tid++) { 111 memDepUnit[tid].init(params, tid); 112 memDepUnit[tid].setIQ(this); 113 } 114 115 resetState(); 116 117 std::string policy = params->smtIQPolicy; 118 119 //Convert string to lowercase 120 std::transform(policy.begin(), policy.end(), policy.begin(), 121 (int(*)(int)) tolower); 122 123 //Figure out resource sharing policy 124 if (policy == "dynamic") { 125 iqPolicy = Dynamic; 126 127 //Set Max Entries to Total ROB Capacity 128 for (ThreadID tid = 0; tid < numThreads; tid++) { 129 maxEntries[tid] = numEntries; 130 } 131 132 } else if (policy == "partitioned") { 133 iqPolicy = Partitioned; 134 135 //@todo:make work if part_amt doesnt divide evenly. 136 int part_amt = numEntries / numThreads; 137 138 //Divide ROB up evenly 139 for (ThreadID tid = 0; tid < numThreads; tid++) { 140 maxEntries[tid] = part_amt; 141 } 142 143 DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 144 "%i entries per thread.\n",part_amt); 145 } else if (policy == "threshold") { 146 iqPolicy = Threshold; 147 148 double threshold = (double)params->smtIQThreshold / 100; 149 150 int thresholdIQ = (int)((double)threshold * numEntries); 151 152 //Divide up by threshold amount 153 for (ThreadID tid = 0; tid < numThreads; tid++) { 154 maxEntries[tid] = thresholdIQ; 155 } 156 157 DPRINTF(IQ, "IQ sharing policy set to Threshold:" 158 "%i entries per thread.\n",thresholdIQ); 159 } else { 160 assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 161 "Partitioned, Threshold}"); 162 } 163} 164 165template <class Impl> 166InstructionQueue<Impl>::~InstructionQueue() 167{ 168 dependGraph.reset(); 169#ifdef DEBUG 170 cprintf("Nodes traversed: %i, removed: %i\n", 171 dependGraph.nodesTraversed, dependGraph.nodesRemoved); 172#endif 173} 174 175template <class Impl> 176std::string 177InstructionQueue<Impl>::name() const 178{ 179 return cpu->name() + ".iq"; 180} 181 182template <class Impl> 183void 184InstructionQueue<Impl>::regStats() 185{ 186 using namespace Stats; 187 iqInstsAdded 188 .name(name() + ".iqInstsAdded") 189 .desc("Number of instructions added to the IQ (excludes non-spec)") 190 .prereq(iqInstsAdded); 191 192 iqNonSpecInstsAdded 193 .name(name() + ".iqNonSpecInstsAdded") 194 .desc("Number of non-speculative instructions added to the IQ") 195 .prereq(iqNonSpecInstsAdded); 196 197 iqInstsIssued 198 .name(name() + ".iqInstsIssued") 199 .desc("Number of instructions issued") 200 .prereq(iqInstsIssued); 201 202 iqIntInstsIssued 203 .name(name() + ".iqIntInstsIssued") 204 .desc("Number of integer instructions issued") 205 .prereq(iqIntInstsIssued); 206 207 iqFloatInstsIssued 208 .name(name() + ".iqFloatInstsIssued") 209 .desc("Number of float instructions issued") 210 .prereq(iqFloatInstsIssued); 211 212 iqBranchInstsIssued 213 .name(name() + ".iqBranchInstsIssued") 214 .desc("Number of branch instructions issued") 215 .prereq(iqBranchInstsIssued); 216 217 iqMemInstsIssued 218 .name(name() + ".iqMemInstsIssued") 219 .desc("Number of memory instructions issued") 220 .prereq(iqMemInstsIssued); 221 222 iqMiscInstsIssued 223 .name(name() + ".iqMiscInstsIssued") 224 .desc("Number of miscellaneous instructions issued") 225 .prereq(iqMiscInstsIssued); 226 227 iqSquashedInstsIssued 228 .name(name() + ".iqSquashedInstsIssued") 229 .desc("Number of squashed instructions issued") 230 .prereq(iqSquashedInstsIssued); 231 232 iqSquashedInstsExamined 233 .name(name() + ".iqSquashedInstsExamined") 234 .desc("Number of squashed instructions iterated over during squash;" 235 " mainly for profiling") 236 .prereq(iqSquashedInstsExamined); 237 238 iqSquashedOperandsExamined 239 .name(name() + ".iqSquashedOperandsExamined") 240 .desc("Number of squashed operands that are examined and possibly " 241 "removed from graph") 242 .prereq(iqSquashedOperandsExamined); 243 244 iqSquashedNonSpecRemoved 245 .name(name() + ".iqSquashedNonSpecRemoved") 246 .desc("Number of squashed non-spec instructions that were removed") 247 .prereq(iqSquashedNonSpecRemoved); 248/* 249 queueResDist 250 .init(Num_OpClasses, 0, 99, 2) 251 .name(name() + ".IQ:residence:") 252 .desc("cycles from dispatch to issue") 253 .flags(total | pdf | cdf ) 254 ; 255 for (int i = 0; i < Num_OpClasses; ++i) { 256 queueResDist.subname(i, opClassStrings[i]); 257 } 258*/ 259 numIssuedDist 260 .init(0,totalWidth,1) 261 .name(name() + ".issued_per_cycle") 262 .desc("Number of insts issued each cycle") 263 .flags(pdf) 264 ; 265/* 266 dist_unissued 267 .init(Num_OpClasses+2) 268 .name(name() + ".unissued_cause") 269 .desc("Reason ready instruction not issued") 270 .flags(pdf | dist) 271 ; 272 for (int i=0; i < (Num_OpClasses + 2); ++i) { 273 dist_unissued.subname(i, unissued_names[i]); 274 } 275*/ 276 statIssuedInstType 277 .init(numThreads,Enums::Num_OpClass) 278 .name(name() + ".FU_type") 279 .desc("Type of FU issued") 280 .flags(total | pdf | dist) 281 ; 282 statIssuedInstType.ysubnames(Enums::OpClassStrings); 283 284 // 285 // How long did instructions for a particular FU type wait prior to issue 286 // 287/* 288 issueDelayDist 289 .init(Num_OpClasses,0,99,2) 290 .name(name() + ".") 291 .desc("cycles from operands ready to issue") 292 .flags(pdf | cdf) 293 ; 294 295 for (int i=0; i<Num_OpClasses; ++i) { 296 std::stringstream subname; 297 subname << opClassStrings[i] << "_delay"; 298 issueDelayDist.subname(i, subname.str()); 299 } 300*/ 301 issueRate 302 .name(name() + ".rate") 303 .desc("Inst issue rate") 304 .flags(total) 305 ; 306 issueRate = iqInstsIssued / cpu->numCycles; 307 308 statFuBusy 309 .init(Num_OpClasses) 310 .name(name() + ".fu_full") 311 .desc("attempts to use FU when none available") 312 .flags(pdf | dist) 313 ; 314 for (int i=0; i < Num_OpClasses; ++i) { 315 statFuBusy.subname(i, Enums::OpClassStrings[i]); 316 } 317 318 fuBusy 319 .init(numThreads) 320 .name(name() + ".fu_busy_cnt") 321 .desc("FU busy when requested") 322 .flags(total) 323 ; 324 325 fuBusyRate 326 .name(name() + ".fu_busy_rate") 327 .desc("FU busy rate (busy events/executed inst)") 328 .flags(total) 329 ; 330 fuBusyRate = fuBusy / iqInstsIssued; 331 332 for (ThreadID tid = 0; tid < numThreads; tid++) { 333 // Tell mem dependence unit to reg stats as well. 334 memDepUnit[tid].regStats(); 335 } 336 337 intInstQueueReads 338 .name(name() + ".int_inst_queue_reads") 339 .desc("Number of integer instruction queue reads") 340 .flags(total); 341 342 intInstQueueWrites 343 .name(name() + ".int_inst_queue_writes") 344 .desc("Number of integer instruction queue writes") 345 .flags(total); 346 347 intInstQueueWakeupAccesses 348 .name(name() + ".int_inst_queue_wakeup_accesses") 349 .desc("Number of integer instruction queue wakeup accesses") 350 .flags(total); 351 352 fpInstQueueReads 353 .name(name() + ".fp_inst_queue_reads") 354 .desc("Number of floating instruction queue reads") 355 .flags(total); 356 357 fpInstQueueWrites 358 .name(name() + ".fp_inst_queue_writes") 359 .desc("Number of floating instruction queue writes") 360 .flags(total); 361 362 fpInstQueueWakeupQccesses 363 .name(name() + ".fp_inst_queue_wakeup_accesses") 364 .desc("Number of floating instruction queue wakeup accesses") 365 .flags(total); 366 367 intAluAccesses 368 .name(name() + ".int_alu_accesses") 369 .desc("Number of integer alu accesses") 370 .flags(total); 371 372 fpAluAccesses 373 .name(name() + ".fp_alu_accesses") 374 .desc("Number of floating point alu accesses") 375 .flags(total); 376 377} 378 379template <class Impl> 380void 381InstructionQueue<Impl>::resetState() 382{ 383 //Initialize thread IQ counts 384 for (ThreadID tid = 0; tid <numThreads; tid++) { 385 count[tid] = 0; 386 instList[tid].clear(); 387 } 388 389 // Initialize the number of free IQ entries. 390 freeEntries = numEntries; 391 392 // Note that in actuality, the registers corresponding to the logical 393 // registers start off as ready. However this doesn't matter for the 394 // IQ as the instruction should have been correctly told if those 395 // registers are ready in rename. Thus it can all be initialized as 396 // unready. 397 for (int i = 0; i < numPhysRegs; ++i) { 398 regScoreboard[i] = false; 399 } 400 401 for (ThreadID tid = 0; tid < numThreads; ++tid) { 402 squashedSeqNum[tid] = 0; 403 } 404 405 for (int i = 0; i < Num_OpClasses; ++i) { 406 while (!readyInsts[i].empty()) 407 readyInsts[i].pop(); 408 queueOnList[i] = false; 409 readyIt[i] = listOrder.end(); 410 } 411 nonSpecInsts.clear(); 412 listOrder.clear(); 413 deferredMemInsts.clear(); 414} 415 416template <class Impl> 417void 418InstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 419{ 420 activeThreads = at_ptr; 421} 422 423template <class Impl> 424void 425InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 426{ 427 issueToExecuteQueue = i2e_ptr; 428} 429 430template <class Impl> 431void 432InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 433{ 434 timeBuffer = tb_ptr; 435 436 fromCommit = timeBuffer->getWire(-commitToIEWDelay); 437} 438 439template <class Impl> 440void 441InstructionQueue<Impl>::switchOut() 442{ 443/* 444 if (!instList[0].empty() || (numEntries != freeEntries) || 445 !readyInsts[0].empty() || !nonSpecInsts.empty() || !listOrder.empty()) { 446 dumpInsts(); 447// assert(0); 448 } 449*/ 450 resetState(); 451 dependGraph.reset(); 452 instsToExecute.clear(); 453 switchedOut = true; 454 for (ThreadID tid = 0; tid < numThreads; ++tid) { 455 memDepUnit[tid].switchOut(); 456 } 457} 458 459template <class Impl> 460void 461InstructionQueue<Impl>::takeOverFrom() 462{ 463 switchedOut = false; 464} 465 466template <class Impl> 467int 468InstructionQueue<Impl>::entryAmount(ThreadID num_threads) 469{ 470 if (iqPolicy == Partitioned) { 471 return numEntries / num_threads; 472 } else { 473 return 0; 474 } 475} 476 477 478template <class Impl> 479void 480InstructionQueue<Impl>::resetEntries() 481{ 482 if (iqPolicy != Dynamic || numThreads > 1) { 483 int active_threads = activeThreads->size(); 484 485 list<ThreadID>::iterator threads = activeThreads->begin(); 486 list<ThreadID>::iterator end = activeThreads->end(); 487 488 while (threads != end) { 489 ThreadID tid = *threads++; 490 491 if (iqPolicy == Partitioned) { 492 maxEntries[tid] = numEntries / active_threads; 493 } else if(iqPolicy == Threshold && active_threads == 1) { 494 maxEntries[tid] = numEntries; 495 } 496 } 497 } 498} 499 500template <class Impl> 501unsigned 502InstructionQueue<Impl>::numFreeEntries() 503{ 504 return freeEntries; 505} 506 507template <class Impl> 508unsigned 509InstructionQueue<Impl>::numFreeEntries(ThreadID tid) 510{ 511 return maxEntries[tid] - count[tid]; 512} 513 514// Might want to do something more complex if it knows how many instructions 515// will be issued this cycle. 516template <class Impl> 517bool 518InstructionQueue<Impl>::isFull() 519{ 520 if (freeEntries == 0) { 521 return(true); 522 } else { 523 return(false); 524 } 525} 526 527template <class Impl> 528bool 529InstructionQueue<Impl>::isFull(ThreadID tid) 530{ 531 if (numFreeEntries(tid) == 0) { 532 return(true); 533 } else { 534 return(false); 535 } 536} 537 538template <class Impl> 539bool 540InstructionQueue<Impl>::hasReadyInsts() 541{ 542 if (!listOrder.empty()) { 543 return true; 544 } 545 546 for (int i = 0; i < Num_OpClasses; ++i) { 547 if (!readyInsts[i].empty()) { 548 return true; 549 } 550 } 551 552 return false; 553} 554 555template <class Impl> 556void 557InstructionQueue<Impl>::insert(DynInstPtr &new_inst) 558{ 559 new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 560 // Make sure the instruction is valid 561 assert(new_inst); 562 563 DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n", 564 new_inst->seqNum, new_inst->pcState()); 565 566 assert(freeEntries != 0); 567 568 instList[new_inst->threadNumber].push_back(new_inst); 569 570 --freeEntries; 571 572 new_inst->setInIQ(); 573 574 // Look through its source registers (physical regs), and mark any 575 // dependencies. 576 addToDependents(new_inst); 577 578 // Have this instruction set itself as the producer of its destination 579 // register(s). 580 addToProducers(new_inst); 581 582 if (new_inst->isMemRef()) { 583 memDepUnit[new_inst->threadNumber].insert(new_inst); 584 } else { 585 addIfReady(new_inst); 586 } 587 588 ++iqInstsAdded; 589 590 count[new_inst->threadNumber]++; 591 592 assert(freeEntries == (numEntries - countInsts())); 593} 594 595template <class Impl> 596void 597InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) 598{ 599 // @todo: Clean up this code; can do it by setting inst as unable 600 // to issue, then calling normal insert on the inst. 601 new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 602 603 assert(new_inst); 604 605 nonSpecInsts[new_inst->seqNum] = new_inst; 606 607 DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s " 608 "to the IQ.\n", 609 new_inst->seqNum, new_inst->pcState()); 610 611 assert(freeEntries != 0); 612 613 instList[new_inst->threadNumber].push_back(new_inst); 614 615 --freeEntries; 616 617 new_inst->setInIQ(); 618 619 // Have this instruction set itself as the producer of its destination 620 // register(s). 621 addToProducers(new_inst); 622 623 // If it's a memory instruction, add it to the memory dependency 624 // unit. 625 if (new_inst->isMemRef()) { 626 memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 627 } 628 629 ++iqNonSpecInstsAdded; 630 631 count[new_inst->threadNumber]++; 632 633 assert(freeEntries == (numEntries - countInsts())); 634} 635 636template <class Impl> 637void 638InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) 639{ 640 memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 641 642 insertNonSpec(barr_inst); 643} 644 645template <class Impl> 646typename Impl::DynInstPtr 647InstructionQueue<Impl>::getInstToExecute() 648{ 649 assert(!instsToExecute.empty()); 650 DynInstPtr inst = instsToExecute.front(); 651 instsToExecute.pop_front(); 652 if (inst->isFloating()){ 653 fpInstQueueReads++; 654 } else { 655 intInstQueueReads++; 656 } 657 return inst; 658} 659 660template <class Impl> 661void 662InstructionQueue<Impl>::addToOrderList(OpClass op_class) 663{ 664 assert(!readyInsts[op_class].empty()); 665 666 ListOrderEntry queue_entry; 667 668 queue_entry.queueType = op_class; 669 670 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 671 672 ListOrderIt list_it = listOrder.begin(); 673 ListOrderIt list_end_it = listOrder.end(); 674 675 while (list_it != list_end_it) { 676 if ((*list_it).oldestInst > queue_entry.oldestInst) { 677 break; 678 } 679 680 list_it++; 681 } 682 683 readyIt[op_class] = listOrder.insert(list_it, queue_entry); 684 queueOnList[op_class] = true; 685} 686 687template <class Impl> 688void 689InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 690{ 691 // Get iterator of next item on the list 692 // Delete the original iterator 693 // Determine if the next item is either the end of the list or younger 694 // than the new instruction. If so, then add in a new iterator right here. 695 // If not, then move along. 696 ListOrderEntry queue_entry; 697 OpClass op_class = (*list_order_it).queueType; 698 ListOrderIt next_it = list_order_it; 699 700 ++next_it; 701 702 queue_entry.queueType = op_class; 703 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 704 705 while (next_it != listOrder.end() && 706 (*next_it).oldestInst < queue_entry.oldestInst) { 707 ++next_it; 708 } 709 710 readyIt[op_class] = listOrder.insert(next_it, queue_entry); 711} 712 713template <class Impl> 714void 715InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 716{ 717 DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 718 // The CPU could have been sleeping until this op completed (*extremely* 719 // long latency op). Wake it if it was. This may be overkill. 720 if (isSwitchedOut()) { 721 DPRINTF(IQ, "FU completion not processed, IQ is switched out [sn:%lli]\n", 722 inst->seqNum); 723 return; 724 } 725 726 iewStage->wakeCPU(); 727 728 if (fu_idx > -1) 729 fuPool->freeUnitNextCycle(fu_idx); 730 731 // @todo: Ensure that these FU Completions happen at the beginning 732 // of a cycle, otherwise they could add too many instructions to 733 // the queue. 734 issueToExecuteQueue->access(-1)->size++; 735 instsToExecute.push_back(inst); 736} 737 738// @todo: Figure out a better way to remove the squashed items from the 739// lists. Checking the top item of each list to see if it's squashed 740// wastes time and forces jumps. 741template <class Impl> 742void 743InstructionQueue<Impl>::scheduleReadyInsts() 744{ 745 DPRINTF(IQ, "Attempting to schedule ready instructions from " 746 "the IQ.\n"); 747 748 IssueStruct *i2e_info = issueToExecuteQueue->access(0); 749 750 DynInstPtr deferred_mem_inst; 751 int total_deferred_mem_issued = 0; 752 while (total_deferred_mem_issued < totalWidth && 753 (deferred_mem_inst = getDeferredMemInstToExecute()) != 0) { 754 issueToExecuteQueue->access(0)->size++; 755 instsToExecute.push_back(deferred_mem_inst); 756 total_deferred_mem_issued++; 757 } 758 759 // Have iterator to head of the list 760 // While I haven't exceeded bandwidth or reached the end of the list, 761 // Try to get a FU that can do what this op needs. 762 // If successful, change the oldestInst to the new top of the list, put 763 // the queue in the proper place in the list. 764 // Increment the iterator. 765 // This will avoid trying to schedule a certain op class if there are no 766 // FUs that handle it. 767 ListOrderIt order_it = listOrder.begin(); 768 ListOrderIt order_end_it = listOrder.end(); 769 int total_issued = 0; 770 771 while (total_issued < (totalWidth - total_deferred_mem_issued) && 772 iewStage->canIssue() && 773 order_it != order_end_it) { 774 OpClass op_class = (*order_it).queueType; 775 776 assert(!readyInsts[op_class].empty()); 777 778 DynInstPtr issuing_inst = readyInsts[op_class].top(); 779 780 issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++; 781 782 assert(issuing_inst->seqNum == (*order_it).oldestInst); 783 784 if (issuing_inst->isSquashed()) { 785 readyInsts[op_class].pop(); 786 787 if (!readyInsts[op_class].empty()) { 788 moveToYoungerInst(order_it); 789 } else { 790 readyIt[op_class] = listOrder.end(); 791 queueOnList[op_class] = false; 792 } 793 794 listOrder.erase(order_it++); 795 796 ++iqSquashedInstsIssued; 797 798 continue; 799 } 800 801 int idx = -2; 802 int op_latency = 1; 803 ThreadID tid = issuing_inst->threadNumber; 804 805 if (op_class != No_OpClass) { 806 idx = fuPool->getUnit(op_class); 807 issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++; 808 if (idx > -1) { 809 op_latency = fuPool->getOpLatency(op_class); 810 } 811 } 812 813 // If we have an instruction that doesn't require a FU, or a 814 // valid FU, then schedule for execution. 815 if (idx == -2 || idx != -1) { 816 if (op_latency == 1) { 817 i2e_info->size++; 818 instsToExecute.push_back(issuing_inst); 819 820 // Add the FU onto the list of FU's to be freed next 821 // cycle if we used one. 822 if (idx >= 0) 823 fuPool->freeUnitNextCycle(idx); 824 } else { 825 int issue_latency = fuPool->getIssueLatency(op_class); 826 // Generate completion event for the FU 827 FUCompletion *execution = new FUCompletion(issuing_inst, 828 idx, this); 829 830 cpu->schedule(execution, curTick() + cpu->ticks(op_latency - 1)); 831 832 // @todo: Enforce that issue_latency == 1 or op_latency 833 if (issue_latency > 1) { 834 // If FU isn't pipelined, then it must be freed 835 // upon the execution completing. 836 execution->setFreeFU(); 837 } else { 838 // Add the FU onto the list of FU's to be freed next cycle. 839 fuPool->freeUnitNextCycle(idx); 840 } 841 } 842 843 DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 844 "[sn:%lli]\n", 845 tid, issuing_inst->pcState(), 846 issuing_inst->seqNum); 847 848 readyInsts[op_class].pop(); 849 850 if (!readyInsts[op_class].empty()) { 851 moveToYoungerInst(order_it); 852 } else { 853 readyIt[op_class] = listOrder.end(); 854 queueOnList[op_class] = false; 855 } 856 857 issuing_inst->setIssued(); 858 ++total_issued; 859 860#if TRACING_ON 861 issuing_inst->issueTick = curTick(); 862#endif 863 864 if (!issuing_inst->isMemRef()) { 865 // Memory instructions can not be freed from the IQ until they 866 // complete. 867 ++freeEntries; 868 count[tid]--; 869 issuing_inst->clearInIQ(); 870 } else { 871 memDepUnit[tid].issue(issuing_inst); 872 } 873 874 listOrder.erase(order_it++); 875 statIssuedInstType[tid][op_class]++; 876 iewStage->incrWb(issuing_inst->seqNum); 877 } else { 878 statFuBusy[op_class]++; 879 fuBusy[tid]++; 880 ++order_it; 881 } 882 } 883 884 numIssuedDist.sample(total_issued); 885 iqInstsIssued+= total_issued; 886 887 // If we issued any instructions, tell the CPU we had activity. 888 // @todo If the way deferred memory instructions are handeled due to 889 // translation changes then the deferredMemInsts condition should be removed 890 // from the code below. 891 if (total_issued || total_deferred_mem_issued || deferredMemInsts.size()) { 892 cpu->activityThisCycle(); 893 } else { 894 DPRINTF(IQ, "Not able to schedule any instructions.\n"); 895 } 896} 897 898template <class Impl> 899void 900InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 901{ 902 DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 903 "to execute.\n", inst); 904 905 NonSpecMapIt inst_it = nonSpecInsts.find(inst); 906 907 assert(inst_it != nonSpecInsts.end()); 908 909 ThreadID tid = (*inst_it).second->threadNumber; 910 911 (*inst_it).second->setAtCommit(); 912 913 (*inst_it).second->setCanIssue(); 914 915 if (!(*inst_it).second->isMemRef()) { 916 addIfReady((*inst_it).second); 917 } else { 918 memDepUnit[tid].nonSpecInstReady((*inst_it).second); 919 } 920 921 (*inst_it).second = NULL; 922 923 nonSpecInsts.erase(inst_it); 924} 925 926template <class Impl> 927void 928InstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 929{ 930 DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 931 tid,inst); 932 933 ListIt iq_it = instList[tid].begin(); 934 935 while (iq_it != instList[tid].end() && 936 (*iq_it)->seqNum <= inst) { 937 ++iq_it; 938 instList[tid].pop_front(); 939 } 940 941 assert(freeEntries == (numEntries - countInsts())); 942} 943 944template <class Impl> 945int 946InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 947{ 948 int dependents = 0; 949 950 // The instruction queue here takes care of both floating and int ops 951 if (completed_inst->isFloating()) { 952 fpInstQueueWakeupQccesses++; 953 } else { 954 intInstQueueWakeupAccesses++; 955 } 956 957 DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 958 959 assert(!completed_inst->isSquashed()); 960 961 // Tell the memory dependence unit to wake any dependents on this 962 // instruction if it is a memory instruction. Also complete the memory 963 // instruction at this point since we know it executed without issues. 964 // @todo: Might want to rename "completeMemInst" to something that 965 // indicates that it won't need to be replayed, and call this 966 // earlier. Might not be a big deal. 967 if (completed_inst->isMemRef()) { 968 memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 969 completeMemInst(completed_inst); 970 } else if (completed_inst->isMemBarrier() || 971 completed_inst->isWriteBarrier()) { 972 memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 973 } 974 975 for (int dest_reg_idx = 0; 976 dest_reg_idx < completed_inst->numDestRegs(); 977 dest_reg_idx++) 978 { 979 PhysRegIndex dest_reg = 980 completed_inst->renamedDestRegIdx(dest_reg_idx); 981 982 // Special case of uniq or control registers. They are not 983 // handled by the IQ and thus have no dependency graph entry. 984 // @todo Figure out a cleaner way to handle this. 985 if (dest_reg >= numPhysRegs) { 986 DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg, 987 numPhysRegs); 988 continue; 989 } 990 991 DPRINTF(IQ, "Waking any dependents on register %i.\n", 992 (int) dest_reg); 993 994 //Go through the dependency chain, marking the registers as 995 //ready within the waiting instructions. 996 DynInstPtr dep_inst = dependGraph.pop(dest_reg); 997 998 while (dep_inst) { 999 DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] " 1000 "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 1001 1002 // Might want to give more information to the instruction 1003 // so that it knows which of its source registers is 1004 // ready. However that would mean that the dependency 1005 // graph entries would need to hold the src_reg_idx. 1006 dep_inst->markSrcRegReady(); 1007 1008 addIfReady(dep_inst); 1009 1010 dep_inst = dependGraph.pop(dest_reg); 1011 1012 ++dependents; 1013 } 1014 1015 // Reset the head node now that all of its dependents have 1016 // been woken up. 1017 assert(dependGraph.empty(dest_reg)); 1018 dependGraph.clearInst(dest_reg); 1019 1020 // Mark the scoreboard as having that register ready. 1021 regScoreboard[dest_reg] = true; 1022 } 1023 return dependents; 1024} 1025 1026template <class Impl> 1027void 1028InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 1029{ 1030 OpClass op_class = ready_inst->opClass(); 1031 1032 readyInsts[op_class].push(ready_inst); 1033 1034 // Will need to reorder the list if either a queue is not on the list, 1035 // or it has an older instruction than last time. 1036 if (!queueOnList[op_class]) { 1037 addToOrderList(op_class); 1038 } else if (readyInsts[op_class].top()->seqNum < 1039 (*readyIt[op_class]).oldestInst) { 1040 listOrder.erase(readyIt[op_class]); 1041 addToOrderList(op_class); 1042 } 1043 1044 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 1045 "the ready list, PC %s opclass:%i [sn:%lli].\n", 1046 ready_inst->pcState(), op_class, ready_inst->seqNum); 1047} 1048 1049template <class Impl> 1050void 1051InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 1052{ 1053 DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 1054 1055 // Reset DTB translation state 1056 resched_inst->translationStarted = false; 1057 resched_inst->translationCompleted = false; 1058 1059 resched_inst->clearCanIssue(); 1060 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 1061} 1062 1063template <class Impl> 1064void 1065InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 1066{ 1067 memDepUnit[replay_inst->threadNumber].replay(replay_inst); 1068} 1069 1070template <class Impl> 1071void 1072InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 1073{ 1074 ThreadID tid = completed_inst->threadNumber; 1075 1076 DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n", 1077 completed_inst->pcState(), completed_inst->seqNum); 1078 1079 ++freeEntries; 1080 1081 completed_inst->memOpDone = true; 1082 1083 memDepUnit[tid].completed(completed_inst); 1084 count[tid]--; 1085} 1086 1087template <class Impl> 1088void 1089InstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst) 1090{ 1091 deferredMemInsts.push_back(deferred_inst); 1092} 1093 1094template <class Impl> 1095typename Impl::DynInstPtr 1096InstructionQueue<Impl>::getDeferredMemInstToExecute() 1097{ 1098 for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); 1099 ++it) { 1100 if ((*it)->translationCompleted || (*it)->isSquashed()) { 1101 DynInstPtr ret = *it; 1102 deferredMemInsts.erase(it); 1103 return ret; 1104 } 1105 } 1106 return NULL; 1107} 1108 1109template <class Impl> 1110void 1111InstructionQueue<Impl>::violation(DynInstPtr &store, 1112 DynInstPtr &faulting_load) 1113{ 1114 intInstQueueWrites++; 1115 memDepUnit[store->threadNumber].violation(store, faulting_load); 1116} 1117 1118template <class Impl> 1119void 1120InstructionQueue<Impl>::squash(ThreadID tid) 1121{ 1122 DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 1123 "the IQ.\n", tid); 1124 1125 // Read instruction sequence number of last instruction out of the 1126 // time buffer. 1127 squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 1128 1129 // Call doSquash if there are insts in the IQ 1130 if (count[tid] > 0) { 1131 doSquash(tid); 1132 } 1133 1134 // Also tell the memory dependence unit to squash. 1135 memDepUnit[tid].squash(squashedSeqNum[tid], tid); 1136} 1137 1138template <class Impl> 1139void 1140InstructionQueue<Impl>::doSquash(ThreadID tid) 1141{ 1142 // Start at the tail. 1143 ListIt squash_it = instList[tid].end(); 1144 --squash_it; 1145 1146 DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 1147 tid, squashedSeqNum[tid]); 1148 1149 // Squash any instructions younger than the squashed sequence number 1150 // given. 1151 while (squash_it != instList[tid].end() && 1152 (*squash_it)->seqNum > squashedSeqNum[tid]) { 1153 1154 DynInstPtr squashed_inst = (*squash_it); 1155 squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 1156 1157 // Only handle the instruction if it actually is in the IQ and 1158 // hasn't already been squashed in the IQ. 1159 if (squashed_inst->threadNumber != tid || 1160 squashed_inst->isSquashedInIQ()) { 1161 --squash_it; 1162 continue; 1163 } 1164 1165 if (!squashed_inst->isIssued() || 1166 (squashed_inst->isMemRef() && 1167 !squashed_inst->memOpDone)) { 1168 1169 DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", 1170 tid, squashed_inst->seqNum, squashed_inst->pcState()); 1171 1172 // Remove the instruction from the dependency list. 1173 if (!squashed_inst->isNonSpeculative() && 1174 !squashed_inst->isStoreConditional() && 1175 !squashed_inst->isMemBarrier() && 1176 !squashed_inst->isWriteBarrier()) { 1177 1178 for (int src_reg_idx = 0; 1179 src_reg_idx < squashed_inst->numSrcRegs(); 1180 src_reg_idx++) 1181 { 1182 PhysRegIndex src_reg = 1183 squashed_inst->renamedSrcRegIdx(src_reg_idx); 1184 1185 // Only remove it from the dependency graph if it 1186 // was placed there in the first place. 1187 1188 // Instead of doing a linked list traversal, we 1189 // can just remove these squashed instructions 1190 // either at issue time, or when the register is 1191 // overwritten. The only downside to this is it 1192 // leaves more room for error. 1193 1194 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 1195 src_reg < numPhysRegs) { 1196 dependGraph.remove(src_reg, squashed_inst); 1197 } 1198 1199 1200 ++iqSquashedOperandsExamined; 1201 } 1202 } else if (!squashed_inst->isStoreConditional() || 1203 !squashed_inst->isCompleted()) { 1204 NonSpecMapIt ns_inst_it = 1205 nonSpecInsts.find(squashed_inst->seqNum); 1206 1207 if (ns_inst_it == nonSpecInsts.end()) { 1208 assert(squashed_inst->getFault() != NoFault); 1209 } else { 1210 1211 (*ns_inst_it).second = NULL; 1212 1213 nonSpecInsts.erase(ns_inst_it); 1214 1215 ++iqSquashedNonSpecRemoved; 1216 } 1217 } 1218 1219 // Might want to also clear out the head of the dependency graph. 1220 1221 // Mark it as squashed within the IQ. 1222 squashed_inst->setSquashedInIQ(); 1223 1224 // @todo: Remove this hack where several statuses are set so the 1225 // inst will flow through the rest of the pipeline. 1226 squashed_inst->setIssued(); 1227 squashed_inst->setCanCommit(); 1228 squashed_inst->clearInIQ(); 1229 1230 //Update Thread IQ Count 1231 count[squashed_inst->threadNumber]--; 1232 1233 ++freeEntries; 1234 } 1235 1236 instList[tid].erase(squash_it--); 1237 ++iqSquashedInstsExamined; 1238 } 1239} 1240 1241template <class Impl> 1242bool 1243InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 1244{ 1245 // Loop through the instruction's source registers, adding 1246 // them to the dependency list if they are not ready. 1247 int8_t total_src_regs = new_inst->numSrcRegs(); 1248 bool return_val = false; 1249 1250 for (int src_reg_idx = 0; 1251 src_reg_idx < total_src_regs; 1252 src_reg_idx++) 1253 { 1254 // Only add it to the dependency graph if it's not ready. 1255 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 1256 PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 1257 1258 // Check the IQ's scoreboard to make sure the register 1259 // hasn't become ready while the instruction was in flight 1260 // between stages. Only if it really isn't ready should 1261 // it be added to the dependency graph. 1262 if (src_reg >= numPhysRegs) { 1263 continue; 1264 } else if (regScoreboard[src_reg] == false) { 1265 DPRINTF(IQ, "Instruction PC %s has src reg %i that " 1266 "is being added to the dependency chain.\n", 1267 new_inst->pcState(), src_reg); 1268 1269 dependGraph.insert(src_reg, new_inst); 1270 1271 // Change the return value to indicate that something 1272 // was added to the dependency graph. 1273 return_val = true; 1274 } else { 1275 DPRINTF(IQ, "Instruction PC %s has src reg %i that " 1276 "became ready before it reached the IQ.\n", 1277 new_inst->pcState(), src_reg); 1278 // Mark a register ready within the instruction. 1279 new_inst->markSrcRegReady(src_reg_idx); 1280 } 1281 } 1282 } 1283 1284 return return_val; 1285} 1286 1287template <class Impl> 1288void 1289InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) 1290{ 1291 // Nothing really needs to be marked when an instruction becomes 1292 // the producer of a register's value, but for convenience a ptr 1293 // to the producing instruction will be placed in the head node of 1294 // the dependency links. 1295 int8_t total_dest_regs = new_inst->numDestRegs(); 1296 1297 for (int dest_reg_idx = 0; 1298 dest_reg_idx < total_dest_regs; 1299 dest_reg_idx++) 1300 { 1301 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 1302 1303 // Instructions that use the misc regs will have a reg number 1304 // higher than the normal physical registers. In this case these 1305 // registers are not renamed, and there is no need to track 1306 // dependencies as these instructions must be executed at commit. 1307 if (dest_reg >= numPhysRegs) { 1308 continue; 1309 } 1310 1311 if (!dependGraph.empty(dest_reg)) { 1312 dependGraph.dump(); 1313 panic("Dependency graph %i not empty!", dest_reg); 1314 } 1315 1316 dependGraph.setInst(dest_reg, new_inst); 1317 1318 // Mark the scoreboard to say it's not yet ready. 1319 regScoreboard[dest_reg] = false; 1320 } 1321} 1322 1323template <class Impl> 1324void 1325InstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 1326{ 1327 // If the instruction now has all of its source registers 1328 // available, then add it to the list of ready instructions. 1329 if (inst->readyToIssue()) { 1330 1331 //Add the instruction to the proper ready list. 1332 if (inst->isMemRef()) { 1333 1334 DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 1335 1336 // Message to the mem dependence unit that this instruction has 1337 // its registers ready. 1338 memDepUnit[inst->threadNumber].regsReady(inst); 1339 1340 return; 1341 } 1342 1343 OpClass op_class = inst->opClass(); 1344 1345 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 1346 "the ready list, PC %s opclass:%i [sn:%lli].\n", 1347 inst->pcState(), op_class, inst->seqNum); 1348 1349 readyInsts[op_class].push(inst); 1350 1351 // Will need to reorder the list if either a queue is not on the list, 1352 // or it has an older instruction than last time. 1353 if (!queueOnList[op_class]) { 1354 addToOrderList(op_class); 1355 } else if (readyInsts[op_class].top()->seqNum < 1356 (*readyIt[op_class]).oldestInst) { 1357 listOrder.erase(readyIt[op_class]); 1358 addToOrderList(op_class); 1359 } 1360 } 1361} 1362 1363template <class Impl> 1364int 1365InstructionQueue<Impl>::countInsts() 1366{ 1367#if 0 1368 //ksewell:This works but definitely could use a cleaner write 1369 //with a more intuitive way of counting. Right now it's 1370 //just brute force .... 1371 // Change the #if if you want to use this method. 1372 int total_insts = 0; 1373 1374 for (ThreadID tid = 0; tid < numThreads; ++tid) { 1375 ListIt count_it = instList[tid].begin(); 1376 1377 while (count_it != instList[tid].end()) { 1378 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 1379 if (!(*count_it)->isIssued()) { 1380 ++total_insts; 1381 } else if ((*count_it)->isMemRef() && 1382 !(*count_it)->memOpDone) { 1383 // Loads that have not been marked as executed still count 1384 // towards the total instructions. 1385 ++total_insts; 1386 } 1387 } 1388 1389 ++count_it; 1390 } 1391 } 1392 1393 return total_insts; 1394#else 1395 return numEntries - freeEntries; 1396#endif 1397} 1398 1399template <class Impl> 1400void 1401InstructionQueue<Impl>::dumpLists() 1402{ 1403 for (int i = 0; i < Num_OpClasses; ++i) { 1404 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 1405 1406 cprintf("\n"); 1407 } 1408 1409 cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 1410 1411 NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 1412 NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 1413 1414 cprintf("Non speculative list: "); 1415 1416 while (non_spec_it != non_spec_end_it) { 1417 cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(), 1418 (*non_spec_it).second->seqNum); 1419 ++non_spec_it; 1420 } 1421 1422 cprintf("\n"); 1423 1424 ListOrderIt list_order_it = listOrder.begin(); 1425 ListOrderIt list_order_end_it = listOrder.end(); 1426 int i = 1; 1427 1428 cprintf("List order: "); 1429 1430 while (list_order_it != list_order_end_it) { 1431 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 1432 (*list_order_it).oldestInst); 1433 1434 ++list_order_it; 1435 ++i; 1436 } 1437 1438 cprintf("\n"); 1439} 1440 1441 1442template <class Impl> 1443void 1444InstructionQueue<Impl>::dumpInsts() 1445{ 1446 for (ThreadID tid = 0; tid < numThreads; ++tid) { 1447 int num = 0; 1448 int valid_num = 0; 1449 ListIt inst_list_it = instList[tid].begin(); 1450 1451 while (inst_list_it != instList[tid].end()) { 1452 cprintf("Instruction:%i\n", num); 1453 if (!(*inst_list_it)->isSquashed()) { 1454 if (!(*inst_list_it)->isIssued()) { 1455 ++valid_num; 1456 cprintf("Count:%i\n", valid_num); 1457 } else if ((*inst_list_it)->isMemRef() && 1458 !(*inst_list_it)->memOpDone) { 1459 // Loads that have not been marked as executed 1460 // still count towards the total instructions. 1461 ++valid_num; 1462 cprintf("Count:%i\n", valid_num); 1463 } 1464 } 1465 1466 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 1467 "Issued:%i\nSquashed:%i\n", 1468 (*inst_list_it)->pcState(), 1469 (*inst_list_it)->seqNum, 1470 (*inst_list_it)->threadNumber, 1471 (*inst_list_it)->isIssued(), 1472 (*inst_list_it)->isSquashed()); 1473 1474 if ((*inst_list_it)->isMemRef()) { 1475 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 1476 } 1477 1478 cprintf("\n"); 1479 1480 inst_list_it++; 1481 ++num; 1482 } 1483 } 1484 1485 cprintf("Insts to Execute list:\n"); 1486 1487 int num = 0; 1488 int valid_num = 0; 1489 ListIt inst_list_it = instsToExecute.begin(); 1490 1491 while (inst_list_it != instsToExecute.end()) 1492 { 1493 cprintf("Instruction:%i\n", 1494 num); 1495 if (!(*inst_list_it)->isSquashed()) { 1496 if (!(*inst_list_it)->isIssued()) { 1497 ++valid_num; 1498 cprintf("Count:%i\n", valid_num); 1499 } else if ((*inst_list_it)->isMemRef() && 1500 !(*inst_list_it)->memOpDone) { 1501 // Loads that have not been marked as executed 1502 // still count towards the total instructions. 1503 ++valid_num; 1504 cprintf("Count:%i\n", valid_num); 1505 } 1506 } 1507 1508 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 1509 "Issued:%i\nSquashed:%i\n", 1510 (*inst_list_it)->pcState(), 1511 (*inst_list_it)->seqNum, 1512 (*inst_list_it)->threadNumber, 1513 (*inst_list_it)->isIssued(), 1514 (*inst_list_it)->isSquashed()); 1515 1516 if ((*inst_list_it)->isMemRef()) { 1517 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 1518 } 1519 1520 cprintf("\n"); 1521 1522 inst_list_it++; 1523 ++num; 1524 } 1525} 1526