inst_queue_impl.hh revision 4318
16019Shines@cs.fsu.edu/* 211577SDylan.Johnson@ARM.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 37399SAli.Saidi@ARM.com * All rights reserved. 47399SAli.Saidi@ARM.com * 57399SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 67399SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77399SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87399SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97399SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107399SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117399SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127399SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137399SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 146019Shines@cs.fsu.edu * this software without specific prior written permission. 156019Shines@cs.fsu.edu * 166019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * Authors: Kevin Lim 296019Shines@cs.fsu.edu * Korey Sewell 306019Shines@cs.fsu.edu */ 316019Shines@cs.fsu.edu 326019Shines@cs.fsu.edu#include <limits> 336019Shines@cs.fsu.edu#include <vector> 346019Shines@cs.fsu.edu 356019Shines@cs.fsu.edu#include "sim/core.hh" 366019Shines@cs.fsu.edu 376019Shines@cs.fsu.edu#include "cpu/o3/fu_pool.hh" 386019Shines@cs.fsu.edu#include "cpu/o3/inst_queue.hh" 396019Shines@cs.fsu.edu 407399SAli.Saidi@ARM.comtemplate <class Impl> 416019Shines@cs.fsu.eduInstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 426019Shines@cs.fsu.edu int fu_idx, 436019Shines@cs.fsu.edu InstructionQueue<Impl> *iq_ptr) 446019Shines@cs.fsu.edu : Event(&mainEventQueue, Stat_Event_Pri), 456019Shines@cs.fsu.edu inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 466019Shines@cs.fsu.edu{ 476019Shines@cs.fsu.edu this->setFlags(Event::AutoDelete); 488229Snate@binkert.org} 496019Shines@cs.fsu.edu 506019Shines@cs.fsu.edutemplate <class Impl> 5110687SAndreas.Sandberg@ARM.comvoid 526019Shines@cs.fsu.eduInstructionQueue<Impl>::FUCompletion::process() 536019Shines@cs.fsu.edu{ 546116Snate@binkert.org iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 5510463SAndreas.Sandberg@ARM.com inst = NULL; 566019Shines@cs.fsu.edu} 576019Shines@cs.fsu.edu 586019Shines@cs.fsu.edu 596019Shines@cs.fsu.edutemplate <class Impl> 606019Shines@cs.fsu.educonst char * 617404SAli.Saidi@ARM.comInstructionQueue<Impl>::FUCompletion::description() 6210037SARM gem5 Developers{ 6310037SARM gem5 Developers return "Functional unit completion event"; 6411395Sandreas.sandberg@arm.com} 6511395Sandreas.sandberg@arm.com 6611395Sandreas.sandberg@arm.comtemplate <class Impl> 6711395Sandreas.sandberg@arm.comInstructionQueue<Impl>::InstructionQueue(Params *params) 6811395Sandreas.sandberg@arm.com : fuPool(params->fuPool), 6911395Sandreas.sandberg@arm.com numEntries(params->numIQEntries), 7011395Sandreas.sandberg@arm.com totalWidth(params->issueWidth), 7111395Sandreas.sandberg@arm.com numPhysIntRegs(params->numPhysIntRegs), 7211395Sandreas.sandberg@arm.com numPhysFloatRegs(params->numPhysFloatRegs), 7311395Sandreas.sandberg@arm.com commitToIEWDelay(params->commitToIEWDelay) 7411395Sandreas.sandberg@arm.com{ 7511395Sandreas.sandberg@arm.com assert(fuPool); 7611395Sandreas.sandberg@arm.com 7711395Sandreas.sandberg@arm.com switchedOut = false; 7811395Sandreas.sandberg@arm.com 7911395Sandreas.sandberg@arm.com numThreads = params->numberOfThreads; 8011395Sandreas.sandberg@arm.com 8111395Sandreas.sandberg@arm.com // Set the number of physical registers as the number of int + float 8211395Sandreas.sandberg@arm.com numPhysRegs = numPhysIntRegs + numPhysFloatRegs; 8311395Sandreas.sandberg@arm.com 8411395Sandreas.sandberg@arm.com //Create an entry for each physical register within the 8511395Sandreas.sandberg@arm.com //dependency graph. 8611395Sandreas.sandberg@arm.com dependGraph.resize(numPhysRegs); 8711395Sandreas.sandberg@arm.com 8811395Sandreas.sandberg@arm.com // Resize the register scoreboard. 8911395Sandreas.sandberg@arm.com regScoreboard.resize(numPhysRegs); 9011395Sandreas.sandberg@arm.com 9111395Sandreas.sandberg@arm.com //Initialize Mem Dependence Units 9211395Sandreas.sandberg@arm.com for (int i = 0; i < numThreads; i++) { 9311395Sandreas.sandberg@arm.com memDepUnit[i].init(params,i); 9411395Sandreas.sandberg@arm.com memDepUnit[i].setIQ(this); 9511395Sandreas.sandberg@arm.com } 9611395Sandreas.sandberg@arm.com 9711395Sandreas.sandberg@arm.com resetState(); 9811395Sandreas.sandberg@arm.com 9911395Sandreas.sandberg@arm.com std::string policy = params->smtIQPolicy; 10011395Sandreas.sandberg@arm.com 1017404SAli.Saidi@ARM.com //Convert string to lowercase 1026019Shines@cs.fsu.edu std::transform(policy.begin(), policy.end(), policy.begin(), 1036019Shines@cs.fsu.edu (int(*)(int)) tolower); 1047294Sgblack@eecs.umich.edu 1057294Sgblack@eecs.umich.edu //Figure out resource sharing policy 10610037SARM gem5 Developers if (policy == "dynamic") { 1077294Sgblack@eecs.umich.edu iqPolicy = Dynamic; 1087294Sgblack@eecs.umich.edu 1097294Sgblack@eecs.umich.edu //Set Max Entries to Total ROB Capacity 11010037SARM gem5 Developers for (int i = 0; i < numThreads; i++) { 11110037SARM gem5 Developers maxEntries[i] = numEntries; 11210037SARM gem5 Developers } 11310037SARM gem5 Developers 1147294Sgblack@eecs.umich.edu } else if (policy == "partitioned") { 11510037SARM gem5 Developers iqPolicy = Partitioned; 1167404SAli.Saidi@ARM.com 11710037SARM gem5 Developers //@todo:make work if part_amt doesnt divide evenly. 1187294Sgblack@eecs.umich.edu int part_amt = numEntries / numThreads; 1197294Sgblack@eecs.umich.edu 1207294Sgblack@eecs.umich.edu //Divide ROB up evenly 12110037SARM gem5 Developers for (int i = 0; i < numThreads; i++) { 12210037SARM gem5 Developers maxEntries[i] = part_amt; 12310037SARM gem5 Developers } 12410037SARM gem5 Developers 12510037SARM gem5 Developers/* 12610037SARM gem5 Developers DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 12710037SARM gem5 Developers "%i entries per thread.\n",part_amt); 12810037SARM gem5 Developers*/ 12910037SARM gem5 Developers 13011577SDylan.Johnson@ARM.com } else if (policy == "threshold") { 13111577SDylan.Johnson@ARM.com iqPolicy = Threshold; 13211577SDylan.Johnson@ARM.com 13311577SDylan.Johnson@ARM.com double threshold = (double)params->smtIQThreshold / 100; 13411577SDylan.Johnson@ARM.com 13511577SDylan.Johnson@ARM.com int thresholdIQ = (int)((double)threshold * numEntries); 13611577SDylan.Johnson@ARM.com 13711577SDylan.Johnson@ARM.com //Divide up by threshold amount 13811577SDylan.Johnson@ARM.com for (int i = 0; i < numThreads; i++) { 13911577SDylan.Johnson@ARM.com maxEntries[i] = thresholdIQ; 14011577SDylan.Johnson@ARM.com } 1417294Sgblack@eecs.umich.edu 1426019Shines@cs.fsu.edu/* 14310037SARM gem5 Developers DPRINTF(IQ, "IQ sharing policy set to Threshold:" 14410037SARM gem5 Developers "%i entries per thread.\n",thresholdIQ); 14510037SARM gem5 Developers*/ 14610037SARM gem5 Developers } else { 14710037SARM gem5 Developers assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 14810037SARM gem5 Developers "Partitioned, Threshold}"); 14910037SARM gem5 Developers } 1507436Sdam.sunwoo@arm.com} 1517404SAli.Saidi@ARM.com 15210037SARM gem5 Developerstemplate <class Impl> 15310037SARM gem5 DevelopersInstructionQueue<Impl>::~InstructionQueue() 1546019Shines@cs.fsu.edu{ 15511395Sandreas.sandberg@arm.com dependGraph.reset(); 15611395Sandreas.sandberg@arm.com#ifdef DEBUG 1577399SAli.Saidi@ARM.com cprintf("Nodes traversed: %i, removed: %i\n", 1587734SAli.Saidi@ARM.com dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1597734SAli.Saidi@ARM.com#endif 1607734SAli.Saidi@ARM.com} 1617734SAli.Saidi@ARM.com 1627734SAli.Saidi@ARM.comtemplate <class Impl> 1637734SAli.Saidi@ARM.comstd::string 1647734SAli.Saidi@ARM.comInstructionQueue<Impl>::name() const 1657734SAli.Saidi@ARM.com{ 1667734SAli.Saidi@ARM.com return cpu->name() + ".iq"; 1677734SAli.Saidi@ARM.com} 1687734SAli.Saidi@ARM.com 1697734SAli.Saidi@ARM.comtemplate <class Impl> 1707734SAli.Saidi@ARM.comvoid 1717734SAli.Saidi@ARM.comInstructionQueue<Impl>::regStats() 1727734SAli.Saidi@ARM.com{ 1737734SAli.Saidi@ARM.com using namespace Stats; 1747734SAli.Saidi@ARM.com iqInstsAdded 1757734SAli.Saidi@ARM.com .name(name() + ".iqInstsAdded") 1767734SAli.Saidi@ARM.com .desc("Number of instructions added to the IQ (excludes non-spec)") 1777734SAli.Saidi@ARM.com .prereq(iqInstsAdded); 1786019Shines@cs.fsu.edu 1796019Shines@cs.fsu.edu iqNonSpecInstsAdded 1806019Shines@cs.fsu.edu .name(name() + ".iqNonSpecInstsAdded") 1816019Shines@cs.fsu.edu .desc("Number of non-speculative instructions added to the IQ") 18210463SAndreas.Sandberg@ARM.com .prereq(iqNonSpecInstsAdded); 18310463SAndreas.Sandberg@ARM.com 18410463SAndreas.Sandberg@ARM.com iqInstsIssued 1857697SAli.Saidi@ARM.com .name(name() + ".iqInstsIssued") 1867404SAli.Saidi@ARM.com .desc("Number of instructions issued") 1876019Shines@cs.fsu.edu .prereq(iqInstsIssued); 18810037SARM gem5 Developers 18910037SARM gem5 Developers iqIntInstsIssued 1906019Shines@cs.fsu.edu .name(name() + ".iqIntInstsIssued") 1919535Smrinmoy.ghosh@arm.com .desc("Number of integer instructions issued") 1929535Smrinmoy.ghosh@arm.com .prereq(iqIntInstsIssued); 1939535Smrinmoy.ghosh@arm.com 19410037SARM gem5 Developers iqFloatInstsIssued 19510037SARM gem5 Developers .name(name() + ".iqFloatInstsIssued") 19610037SARM gem5 Developers .desc("Number of float instructions issued") 1979535Smrinmoy.ghosh@arm.com .prereq(iqFloatInstsIssued); 19810037SARM gem5 Developers 19910037SARM gem5 Developers iqBranchInstsIssued 2009535Smrinmoy.ghosh@arm.com .name(name() + ".iqBranchInstsIssued") 20110037SARM gem5 Developers .desc("Number of branch instructions issued") 20210037SARM gem5 Developers .prereq(iqBranchInstsIssued); 20310037SARM gem5 Developers 2049535Smrinmoy.ghosh@arm.com iqMemInstsIssued 2056019Shines@cs.fsu.edu .name(name() + ".iqMemInstsIssued") 20610037SARM gem5 Developers .desc("Number of memory instructions issued") 20711169Sandreas.hansson@arm.com .prereq(iqMemInstsIssued); 20810194SGeoffrey.Blake@arm.com 20910037SARM gem5 Developers iqMiscInstsIssued 21011169Sandreas.hansson@arm.com .name(name() + ".iqMiscInstsIssued") 21110037SARM gem5 Developers .desc("Number of miscellaneous instructions issued") 21211395Sandreas.sandberg@arm.com .prereq(iqMiscInstsIssued); 21311395Sandreas.sandberg@arm.com 21410717Sandreas.hansson@arm.com iqSquashedInstsIssued 21510717Sandreas.hansson@arm.com .name(name() + ".iqSquashedInstsIssued") 21610717Sandreas.hansson@arm.com .desc("Number of squashed instructions issued") 21710037SARM gem5 Developers .prereq(iqSquashedInstsIssued); 2186019Shines@cs.fsu.edu 2196019Shines@cs.fsu.edu iqSquashedInstsExamined 2207404SAli.Saidi@ARM.com .name(name() + ".iqSquashedInstsExamined") 2217404SAli.Saidi@ARM.com .desc("Number of squashed instructions iterated over during squash;" 22210037SARM gem5 Developers " mainly for profiling") 22310037SARM gem5 Developers .prereq(iqSquashedInstsExamined); 22410037SARM gem5 Developers 22510037SARM gem5 Developers iqSquashedOperandsExamined 22610037SARM gem5 Developers .name(name() + ".iqSquashedOperandsExamined") 22710037SARM gem5 Developers .desc("Number of squashed operands that are examined and possibly " 22810037SARM gem5 Developers "removed from graph") 22910037SARM gem5 Developers .prereq(iqSquashedOperandsExamined); 23010037SARM gem5 Developers 23110037SARM gem5 Developers iqSquashedNonSpecRemoved 23210037SARM gem5 Developers .name(name() + ".iqSquashedNonSpecRemoved") 23310037SARM gem5 Developers .desc("Number of squashed non-spec instructions that were removed") 23410037SARM gem5 Developers .prereq(iqSquashedNonSpecRemoved); 23510037SARM gem5 Developers/* 23610037SARM gem5 Developers queueResDist 23710037SARM gem5 Developers .init(Num_OpClasses, 0, 99, 2) 23810037SARM gem5 Developers .name(name() + ".IQ:residence:") 23910037SARM gem5 Developers .desc("cycles from dispatch to issue") 24010037SARM gem5 Developers .flags(total | pdf | cdf ) 24110037SARM gem5 Developers ; 24210037SARM gem5 Developers for (int i = 0; i < Num_OpClasses; ++i) { 24310037SARM gem5 Developers queueResDist.subname(i, opClassStrings[i]); 24410037SARM gem5 Developers } 24510037SARM gem5 Developers*/ 24610037SARM gem5 Developers numIssuedDist 24710037SARM gem5 Developers .init(0,totalWidth,1) 24810037SARM gem5 Developers .name(name() + ".ISSUE:issued_per_cycle") 24910037SARM gem5 Developers .desc("Number of insts issued each cycle") 25010037SARM gem5 Developers .flags(pdf) 25111169Sandreas.hansson@arm.com ; 25210037SARM gem5 Developers/* 25310037SARM gem5 Developers dist_unissued 25410037SARM gem5 Developers .init(Num_OpClasses+2) 25510037SARM gem5 Developers .name(name() + ".ISSUE:unissued_cause") 2567404SAli.Saidi@ARM.com .desc("Reason ready instruction not issued") 2577404SAli.Saidi@ARM.com .flags(pdf | dist) 2587404SAli.Saidi@ARM.com ; 2597404SAli.Saidi@ARM.com for (int i=0; i < (Num_OpClasses + 2); ++i) { 26010037SARM gem5 Developers dist_unissued.subname(i, unissued_names[i]); 2617404SAli.Saidi@ARM.com } 26210037SARM gem5 Developers*/ 26310037SARM gem5 Developers statIssuedInstType 2647404SAli.Saidi@ARM.com .init(numThreads,Num_OpClasses) 2657404SAli.Saidi@ARM.com .name(name() + ".ISSUE:FU_type") 2667404SAli.Saidi@ARM.com .desc("Type of FU issued") 26710037SARM gem5 Developers .flags(total | pdf | dist) 2687404SAli.Saidi@ARM.com ; 26910037SARM gem5 Developers statIssuedInstType.ysubnames(opClassStrings); 2707404SAli.Saidi@ARM.com 2717404SAli.Saidi@ARM.com // 2727404SAli.Saidi@ARM.com // How long did instructions for a particular FU type wait prior to issue 27310037SARM gem5 Developers // 27410037SARM gem5 Developers/* 2757404SAli.Saidi@ARM.com issueDelayDist 27610037SARM gem5 Developers .init(Num_OpClasses,0,99,2) 2777404SAli.Saidi@ARM.com .name(name() + ".ISSUE:") 27811584SDylan.Johnson@ARM.com .desc("cycles from operands ready to issue") 27911584SDylan.Johnson@ARM.com .flags(pdf | cdf) 28011584SDylan.Johnson@ARM.com ; 28111584SDylan.Johnson@ARM.com 28211584SDylan.Johnson@ARM.com for (int i=0; i<Num_OpClasses; ++i) { 28311584SDylan.Johnson@ARM.com std::stringstream subname; 28411584SDylan.Johnson@ARM.com subname << opClassStrings[i] << "_delay"; 28511584SDylan.Johnson@ARM.com issueDelayDist.subname(i, subname.str()); 28611584SDylan.Johnson@ARM.com } 28711584SDylan.Johnson@ARM.com*/ 28811584SDylan.Johnson@ARM.com issueRate 28911584SDylan.Johnson@ARM.com .name(name() + ".ISSUE:rate") 29011584SDylan.Johnson@ARM.com .desc("Inst issue rate") 29110037SARM gem5 Developers .flags(total) 2927404SAli.Saidi@ARM.com ; 29311169Sandreas.hansson@arm.com issueRate = iqInstsIssued / cpu->numCycles; 2946019Shines@cs.fsu.edu 29510037SARM gem5 Developers statFuBusy 29610037SARM gem5 Developers .init(Num_OpClasses) 2976019Shines@cs.fsu.edu .name(name() + ".ISSUE:fu_full") 2986019Shines@cs.fsu.edu .desc("attempts to use FU when none available") 2997694SAli.Saidi@ARM.com .flags(pdf | dist) 3007694SAli.Saidi@ARM.com ; 3017694SAli.Saidi@ARM.com for (int i=0; i < Num_OpClasses; ++i) { 3027694SAli.Saidi@ARM.com statFuBusy.subname(i, opClassStrings[i]); 3037694SAli.Saidi@ARM.com } 3047694SAli.Saidi@ARM.com 3057694SAli.Saidi@ARM.com fuBusy 3067694SAli.Saidi@ARM.com .init(numThreads) 3077694SAli.Saidi@ARM.com .name(name() + ".ISSUE:fu_busy_cnt") 3087694SAli.Saidi@ARM.com .desc("FU busy when requested") 3098733Sgeoffrey.blake@arm.com .flags(total) 3108733Sgeoffrey.blake@arm.com ; 3118733Sgeoffrey.blake@arm.com 3128733Sgeoffrey.blake@arm.com fuBusyRate 31310037SARM gem5 Developers .name(name() + ".ISSUE:fu_busy_rate") 31412419Sgabeblack@google.com .desc("FU busy rate (busy events/executed inst)") 31512419Sgabeblack@google.com .flags(total) 31612419Sgabeblack@google.com ; 31712419Sgabeblack@google.com fuBusyRate = fuBusy / iqInstsIssued; 31812419Sgabeblack@google.com 31912419Sgabeblack@google.com for ( int i=0; i < numThreads; i++) { 3208733Sgeoffrey.blake@arm.com // Tell mem dependence unit to reg stats as well. 3217436Sdam.sunwoo@arm.com memDepUnit[i].regStats(); 3227436Sdam.sunwoo@arm.com } 3237436Sdam.sunwoo@arm.com} 32410037SARM gem5 Developers 3257436Sdam.sunwoo@arm.comtemplate <class Impl> 3267436Sdam.sunwoo@arm.comvoid 3277436Sdam.sunwoo@arm.comInstructionQueue<Impl>::resetState() 32810037SARM gem5 Developers{ 32910037SARM gem5 Developers //Initialize thread IQ counts 3307436Sdam.sunwoo@arm.com for (int i = 0; i <numThreads; i++) { 3317436Sdam.sunwoo@arm.com count[i] = 0; 3327436Sdam.sunwoo@arm.com instList[i].clear(); 3337436Sdam.sunwoo@arm.com } 3347436Sdam.sunwoo@arm.com 3357404SAli.Saidi@ARM.com // Initialize the number of free IQ entries. 3368733Sgeoffrey.blake@arm.com freeEntries = numEntries; 33710037SARM gem5 Developers 3387404SAli.Saidi@ARM.com // Note that in actuality, the registers corresponding to the logical 3397404SAli.Saidi@ARM.com // registers start off as ready. However this doesn't matter for the 34010037SARM gem5 Developers // IQ as the instruction should have been correctly told if those 34112406Sgabeblack@google.com // registers are ready in rename. Thus it can all be initialized as 34212406Sgabeblack@google.com // unready. 34312406Sgabeblack@google.com for (int i = 0; i < numPhysRegs; ++i) { 34412406Sgabeblack@google.com regScoreboard[i] = false; 34512406Sgabeblack@google.com } 34612406Sgabeblack@google.com 34712406Sgabeblack@google.com for (int i = 0; i < numThreads; ++i) { 34812406Sgabeblack@google.com squashedSeqNum[i] = 0; 34910037SARM gem5 Developers } 35012406Sgabeblack@google.com 35112406Sgabeblack@google.com for (int i = 0; i < Num_OpClasses; ++i) { 35212406Sgabeblack@google.com while (!readyInsts[i].empty()) 35312406Sgabeblack@google.com readyInsts[i].pop(); 35412406Sgabeblack@google.com queueOnList[i] = false; 35512406Sgabeblack@google.com readyIt[i] = listOrder.end(); 35612406Sgabeblack@google.com } 35710037SARM gem5 Developers nonSpecInsts.clear(); 35810037SARM gem5 Developers listOrder.clear(); 35910037SARM gem5 Developers} 36012406Sgabeblack@google.com 36112406Sgabeblack@google.comtemplate <class Impl> 3626116Snate@binkert.orgvoid 36311168Sandreas.hansson@arm.comInstructionQueue<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 3649439SAndreas.Sandberg@ARM.com{ 3656019Shines@cs.fsu.edu activeThreads = at_ptr; 36611168Sandreas.hansson@arm.com} 36711168Sandreas.hansson@arm.com 3686019Shines@cs.fsu.edutemplate <class Impl> 36911169Sandreas.hansson@arm.comvoid 3707749SAli.Saidi@ARM.comInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 37111168Sandreas.hansson@arm.com{ 37210463SAndreas.Sandberg@ARM.com issueToExecuteQueue = i2e_ptr; 3738922Swilliam.wang@arm.com} 3748922Swilliam.wang@arm.com 3758922Swilliam.wang@arm.comtemplate <class Impl> 3768922Swilliam.wang@arm.comvoid 3778922Swilliam.wang@arm.comInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3788922Swilliam.wang@arm.com{ 3798922Swilliam.wang@arm.com timeBuffer = tb_ptr; 3808922Swilliam.wang@arm.com 3818922Swilliam.wang@arm.com fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3828922Swilliam.wang@arm.com} 38311169Sandreas.hansson@arm.com 3847781SAli.Saidi@ARM.comtemplate <class Impl> 3857749SAli.Saidi@ARM.comvoid 3867749SAli.Saidi@ARM.comInstructionQueue<Impl>::switchOut() 3877749SAli.Saidi@ARM.com{ 3887749SAli.Saidi@ARM.com/* 3897749SAli.Saidi@ARM.com if (!instList[0].empty() || (numEntries != freeEntries) || 39010854SNathanael.Premillieu@arm.com !readyInsts[0].empty() || !nonSpecInsts.empty() || !listOrder.empty()) { 39110037SARM gem5 Developers dumpInsts(); 39210037SARM gem5 Developers// assert(0); 3937749SAli.Saidi@ARM.com } 39410037SARM gem5 Developers*/ 3957749SAli.Saidi@ARM.com resetState(); 39610037SARM gem5 Developers dependGraph.reset(); 39710037SARM gem5 Developers instsToExecute.clear(); 39810037SARM gem5 Developers switchedOut = true; 39910037SARM gem5 Developers for (int i = 0; i < numThreads; ++i) { 40010037SARM gem5 Developers memDepUnit[i].switchOut(); 4017749SAli.Saidi@ARM.com } 4027749SAli.Saidi@ARM.com} 40310037SARM gem5 Developers 4047749SAli.Saidi@ARM.comtemplate <class Impl> 4057749SAli.Saidi@ARM.comvoid 40611152Smitch.hayenga@arm.comInstructionQueue<Impl>::takeOverFrom() 40710037SARM gem5 Developers{ 40810037SARM gem5 Developers switchedOut = false; 40910037SARM gem5 Developers} 41010037SARM gem5 Developers 41110037SARM gem5 Developerstemplate <class Impl> 41210037SARM gem5 Developersint 41310037SARM gem5 DevelopersInstructionQueue<Impl>::entryAmount(int num_threads) 41412005Sandreas.sandberg@arm.com{ 41512005Sandreas.sandberg@arm.com if (iqPolicy == Partitioned) { 41610037SARM gem5 Developers return numEntries / num_threads; 41710037SARM gem5 Developers } else { 41810037SARM gem5 Developers return 0; 4197749SAli.Saidi@ARM.com } 4208299Schander.sudanthi@arm.com} 4218299Schander.sudanthi@arm.com 4228299Schander.sudanthi@arm.com 4238299Schander.sudanthi@arm.comtemplate <class Impl> 4248299Schander.sudanthi@arm.comvoid 4257749SAli.Saidi@ARM.comInstructionQueue<Impl>::resetEntries() 42610037SARM gem5 Developers{ 42710037SARM gem5 Developers if (iqPolicy != Dynamic || numThreads > 1) { 42810037SARM gem5 Developers int active_threads = activeThreads->size(); 42910037SARM gem5 Developers 43010037SARM gem5 Developers std::list<unsigned>::iterator threads = activeThreads->begin(); 43110037SARM gem5 Developers std::list<unsigned>::iterator end = activeThreads->end(); 43210037SARM gem5 Developers 43310037SARM gem5 Developers while (threads != end) { 43410037SARM gem5 Developers unsigned tid = *threads++; 43510037SARM gem5 Developers 43610037SARM gem5 Developers if (iqPolicy == Partitioned) { 43710037SARM gem5 Developers maxEntries[tid] = numEntries / active_threads; 43810037SARM gem5 Developers } else if(iqPolicy == Threshold && active_threads == 1) { 43911395Sandreas.sandberg@arm.com maxEntries[tid] = numEntries; 44011395Sandreas.sandberg@arm.com } 44111395Sandreas.sandberg@arm.com } 44211395Sandreas.sandberg@arm.com } 44311395Sandreas.sandberg@arm.com} 44411395Sandreas.sandberg@arm.com 44511395Sandreas.sandberg@arm.comtemplate <class Impl> 4466019Shines@cs.fsu.eduunsigned 4476019Shines@cs.fsu.eduInstructionQueue<Impl>::numFreeEntries() 4487811Ssteve.reinhardt@amd.com{ 4496019Shines@cs.fsu.edu return freeEntries; 4506019Shines@cs.fsu.edu} 451 452template <class Impl> 453unsigned 454InstructionQueue<Impl>::numFreeEntries(unsigned tid) 455{ 456 return maxEntries[tid] - count[tid]; 457} 458 459// Might want to do something more complex if it knows how many instructions 460// will be issued this cycle. 461template <class Impl> 462bool 463InstructionQueue<Impl>::isFull() 464{ 465 if (freeEntries == 0) { 466 return(true); 467 } else { 468 return(false); 469 } 470} 471 472template <class Impl> 473bool 474InstructionQueue<Impl>::isFull(unsigned tid) 475{ 476 if (numFreeEntries(tid) == 0) { 477 return(true); 478 } else { 479 return(false); 480 } 481} 482 483template <class Impl> 484bool 485InstructionQueue<Impl>::hasReadyInsts() 486{ 487 if (!listOrder.empty()) { 488 return true; 489 } 490 491 for (int i = 0; i < Num_OpClasses; ++i) { 492 if (!readyInsts[i].empty()) { 493 return true; 494 } 495 } 496 497 return false; 498} 499 500template <class Impl> 501void 502InstructionQueue<Impl>::insert(DynInstPtr &new_inst) 503{ 504 // Make sure the instruction is valid 505 assert(new_inst); 506 507 DPRINTF(IQ, "Adding instruction [sn:%lli] PC %#x to the IQ.\n", 508 new_inst->seqNum, new_inst->readPC()); 509 510 assert(freeEntries != 0); 511 512 instList[new_inst->threadNumber].push_back(new_inst); 513 514 --freeEntries; 515 516 new_inst->setInIQ(); 517 518 // Look through its source registers (physical regs), and mark any 519 // dependencies. 520 addToDependents(new_inst); 521 522 // Have this instruction set itself as the producer of its destination 523 // register(s). 524 addToProducers(new_inst); 525 526 if (new_inst->isMemRef()) { 527 memDepUnit[new_inst->threadNumber].insert(new_inst); 528 } else { 529 addIfReady(new_inst); 530 } 531 532 ++iqInstsAdded; 533 534 count[new_inst->threadNumber]++; 535 536 assert(freeEntries == (numEntries - countInsts())); 537} 538 539template <class Impl> 540void 541InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) 542{ 543 // @todo: Clean up this code; can do it by setting inst as unable 544 // to issue, then calling normal insert on the inst. 545 546 assert(new_inst); 547 548 nonSpecInsts[new_inst->seqNum] = new_inst; 549 550 DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %#x " 551 "to the IQ.\n", 552 new_inst->seqNum, new_inst->readPC()); 553 554 assert(freeEntries != 0); 555 556 instList[new_inst->threadNumber].push_back(new_inst); 557 558 --freeEntries; 559 560 new_inst->setInIQ(); 561 562 // Have this instruction set itself as the producer of its destination 563 // register(s). 564 addToProducers(new_inst); 565 566 // If it's a memory instruction, add it to the memory dependency 567 // unit. 568 if (new_inst->isMemRef()) { 569 memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 570 } 571 572 ++iqNonSpecInstsAdded; 573 574 count[new_inst->threadNumber]++; 575 576 assert(freeEntries == (numEntries - countInsts())); 577} 578 579template <class Impl> 580void 581InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) 582{ 583 memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 584 585 insertNonSpec(barr_inst); 586} 587 588template <class Impl> 589typename Impl::DynInstPtr 590InstructionQueue<Impl>::getInstToExecute() 591{ 592 assert(!instsToExecute.empty()); 593 DynInstPtr inst = instsToExecute.front(); 594 instsToExecute.pop_front(); 595 return inst; 596} 597 598template <class Impl> 599void 600InstructionQueue<Impl>::addToOrderList(OpClass op_class) 601{ 602 assert(!readyInsts[op_class].empty()); 603 604 ListOrderEntry queue_entry; 605 606 queue_entry.queueType = op_class; 607 608 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 609 610 ListOrderIt list_it = listOrder.begin(); 611 ListOrderIt list_end_it = listOrder.end(); 612 613 while (list_it != list_end_it) { 614 if ((*list_it).oldestInst > queue_entry.oldestInst) { 615 break; 616 } 617 618 list_it++; 619 } 620 621 readyIt[op_class] = listOrder.insert(list_it, queue_entry); 622 queueOnList[op_class] = true; 623} 624 625template <class Impl> 626void 627InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 628{ 629 // Get iterator of next item on the list 630 // Delete the original iterator 631 // Determine if the next item is either the end of the list or younger 632 // than the new instruction. If so, then add in a new iterator right here. 633 // If not, then move along. 634 ListOrderEntry queue_entry; 635 OpClass op_class = (*list_order_it).queueType; 636 ListOrderIt next_it = list_order_it; 637 638 ++next_it; 639 640 queue_entry.queueType = op_class; 641 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 642 643 while (next_it != listOrder.end() && 644 (*next_it).oldestInst < queue_entry.oldestInst) { 645 ++next_it; 646 } 647 648 readyIt[op_class] = listOrder.insert(next_it, queue_entry); 649} 650 651template <class Impl> 652void 653InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 654{ 655 DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 656 // The CPU could have been sleeping until this op completed (*extremely* 657 // long latency op). Wake it if it was. This may be overkill. 658 if (isSwitchedOut()) { 659 DPRINTF(IQ, "FU completion not processed, IQ is switched out [sn:%lli]\n", 660 inst->seqNum); 661 return; 662 } 663 664 iewStage->wakeCPU(); 665 666 if (fu_idx > -1) 667 fuPool->freeUnitNextCycle(fu_idx); 668 669 // @todo: Ensure that these FU Completions happen at the beginning 670 // of a cycle, otherwise they could add too many instructions to 671 // the queue. 672 issueToExecuteQueue->access(0)->size++; 673 instsToExecute.push_back(inst); 674} 675 676// @todo: Figure out a better way to remove the squashed items from the 677// lists. Checking the top item of each list to see if it's squashed 678// wastes time and forces jumps. 679template <class Impl> 680void 681InstructionQueue<Impl>::scheduleReadyInsts() 682{ 683 DPRINTF(IQ, "Attempting to schedule ready instructions from " 684 "the IQ.\n"); 685 686 IssueStruct *i2e_info = issueToExecuteQueue->access(0); 687 688 // Have iterator to head of the list 689 // While I haven't exceeded bandwidth or reached the end of the list, 690 // Try to get a FU that can do what this op needs. 691 // If successful, change the oldestInst to the new top of the list, put 692 // the queue in the proper place in the list. 693 // Increment the iterator. 694 // This will avoid trying to schedule a certain op class if there are no 695 // FUs that handle it. 696 ListOrderIt order_it = listOrder.begin(); 697 ListOrderIt order_end_it = listOrder.end(); 698 int total_issued = 0; 699 700 while (total_issued < totalWidth && 701 iewStage->canIssue() && 702 order_it != order_end_it) { 703 OpClass op_class = (*order_it).queueType; 704 705 assert(!readyInsts[op_class].empty()); 706 707 DynInstPtr issuing_inst = readyInsts[op_class].top(); 708 709 assert(issuing_inst->seqNum == (*order_it).oldestInst); 710 711 if (issuing_inst->isSquashed()) { 712 readyInsts[op_class].pop(); 713 714 if (!readyInsts[op_class].empty()) { 715 moveToYoungerInst(order_it); 716 } else { 717 readyIt[op_class] = listOrder.end(); 718 queueOnList[op_class] = false; 719 } 720 721 listOrder.erase(order_it++); 722 723 ++iqSquashedInstsIssued; 724 725 continue; 726 } 727 728 int idx = -2; 729 int op_latency = 1; 730 int tid = issuing_inst->threadNumber; 731 732 if (op_class != No_OpClass) { 733 idx = fuPool->getUnit(op_class); 734 735 if (idx > -1) { 736 op_latency = fuPool->getOpLatency(op_class); 737 } 738 } 739 740 // If we have an instruction that doesn't require a FU, or a 741 // valid FU, then schedule for execution. 742 if (idx == -2 || idx != -1) { 743 if (op_latency == 1) { 744 i2e_info->size++; 745 instsToExecute.push_back(issuing_inst); 746 747 // Add the FU onto the list of FU's to be freed next 748 // cycle if we used one. 749 if (idx >= 0) 750 fuPool->freeUnitNextCycle(idx); 751 } else { 752 int issue_latency = fuPool->getIssueLatency(op_class); 753 // Generate completion event for the FU 754 FUCompletion *execution = new FUCompletion(issuing_inst, 755 idx, this); 756 757 execution->schedule(curTick + cpu->cycles(issue_latency - 1)); 758 759 // @todo: Enforce that issue_latency == 1 or op_latency 760 if (issue_latency > 1) { 761 // If FU isn't pipelined, then it must be freed 762 // upon the execution completing. 763 execution->setFreeFU(); 764 } else { 765 // Add the FU onto the list of FU's to be freed next cycle. 766 fuPool->freeUnitNextCycle(idx); 767 } 768 } 769 770 DPRINTF(IQ, "Thread %i: Issuing instruction PC %#x " 771 "[sn:%lli]\n", 772 tid, issuing_inst->readPC(), 773 issuing_inst->seqNum); 774 775 readyInsts[op_class].pop(); 776 777 if (!readyInsts[op_class].empty()) { 778 moveToYoungerInst(order_it); 779 } else { 780 readyIt[op_class] = listOrder.end(); 781 queueOnList[op_class] = false; 782 } 783 784 issuing_inst->setIssued(); 785 ++total_issued; 786 787 if (!issuing_inst->isMemRef()) { 788 // Memory instructions can not be freed from the IQ until they 789 // complete. 790 ++freeEntries; 791 count[tid]--; 792 issuing_inst->clearInIQ(); 793 } else { 794 memDepUnit[tid].issue(issuing_inst); 795 } 796 797 listOrder.erase(order_it++); 798 statIssuedInstType[tid][op_class]++; 799 iewStage->incrWb(issuing_inst->seqNum); 800 } else { 801 statFuBusy[op_class]++; 802 fuBusy[tid]++; 803 ++order_it; 804 } 805 } 806 807 numIssuedDist.sample(total_issued); 808 iqInstsIssued+= total_issued; 809 810 // If we issued any instructions, tell the CPU we had activity. 811 if (total_issued) { 812 cpu->activityThisCycle(); 813 } else { 814 DPRINTF(IQ, "Not able to schedule any instructions.\n"); 815 } 816} 817 818template <class Impl> 819void 820InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 821{ 822 DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 823 "to execute.\n", inst); 824 825 NonSpecMapIt inst_it = nonSpecInsts.find(inst); 826 827 assert(inst_it != nonSpecInsts.end()); 828 829 unsigned tid = (*inst_it).second->threadNumber; 830 831 (*inst_it).second->setAtCommit(); 832 833 (*inst_it).second->setCanIssue(); 834 835 if (!(*inst_it).second->isMemRef()) { 836 addIfReady((*inst_it).second); 837 } else { 838 memDepUnit[tid].nonSpecInstReady((*inst_it).second); 839 } 840 841 (*inst_it).second = NULL; 842 843 nonSpecInsts.erase(inst_it); 844} 845 846template <class Impl> 847void 848InstructionQueue<Impl>::commit(const InstSeqNum &inst, unsigned tid) 849{ 850 DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 851 tid,inst); 852 853 ListIt iq_it = instList[tid].begin(); 854 855 while (iq_it != instList[tid].end() && 856 (*iq_it)->seqNum <= inst) { 857 ++iq_it; 858 instList[tid].pop_front(); 859 } 860 861 assert(freeEntries == (numEntries - countInsts())); 862} 863 864template <class Impl> 865int 866InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 867{ 868 int dependents = 0; 869 870 DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 871 872 assert(!completed_inst->isSquashed()); 873 874 // Tell the memory dependence unit to wake any dependents on this 875 // instruction if it is a memory instruction. Also complete the memory 876 // instruction at this point since we know it executed without issues. 877 // @todo: Might want to rename "completeMemInst" to something that 878 // indicates that it won't need to be replayed, and call this 879 // earlier. Might not be a big deal. 880 if (completed_inst->isMemRef()) { 881 memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 882 completeMemInst(completed_inst); 883 } else if (completed_inst->isMemBarrier() || 884 completed_inst->isWriteBarrier()) { 885 memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 886 } 887 888 for (int dest_reg_idx = 0; 889 dest_reg_idx < completed_inst->numDestRegs(); 890 dest_reg_idx++) 891 { 892 PhysRegIndex dest_reg = 893 completed_inst->renamedDestRegIdx(dest_reg_idx); 894 895 // Special case of uniq or control registers. They are not 896 // handled by the IQ and thus have no dependency graph entry. 897 // @todo Figure out a cleaner way to handle this. 898 if (dest_reg >= numPhysRegs) { 899 continue; 900 } 901 902 DPRINTF(IQ, "Waking any dependents on register %i.\n", 903 (int) dest_reg); 904 905 //Go through the dependency chain, marking the registers as 906 //ready within the waiting instructions. 907 DynInstPtr dep_inst = dependGraph.pop(dest_reg); 908 909 while (dep_inst) { 910 DPRINTF(IQ, "Waking up a dependent instruction, PC%#x.\n", 911 dep_inst->readPC()); 912 913 // Might want to give more information to the instruction 914 // so that it knows which of its source registers is 915 // ready. However that would mean that the dependency 916 // graph entries would need to hold the src_reg_idx. 917 dep_inst->markSrcRegReady(); 918 919 addIfReady(dep_inst); 920 921 dep_inst = dependGraph.pop(dest_reg); 922 923 ++dependents; 924 } 925 926 // Reset the head node now that all of its dependents have 927 // been woken up. 928 assert(dependGraph.empty(dest_reg)); 929 dependGraph.clearInst(dest_reg); 930 931 // Mark the scoreboard as having that register ready. 932 regScoreboard[dest_reg] = true; 933 } 934 return dependents; 935} 936 937template <class Impl> 938void 939InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 940{ 941 OpClass op_class = ready_inst->opClass(); 942 943 readyInsts[op_class].push(ready_inst); 944 945 // Will need to reorder the list if either a queue is not on the list, 946 // or it has an older instruction than last time. 947 if (!queueOnList[op_class]) { 948 addToOrderList(op_class); 949 } else if (readyInsts[op_class].top()->seqNum < 950 (*readyIt[op_class]).oldestInst) { 951 listOrder.erase(readyIt[op_class]); 952 addToOrderList(op_class); 953 } 954 955 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 956 "the ready list, PC %#x opclass:%i [sn:%lli].\n", 957 ready_inst->readPC(), op_class, ready_inst->seqNum); 958} 959 960template <class Impl> 961void 962InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 963{ 964 DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 965 resched_inst->clearCanIssue(); 966 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 967} 968 969template <class Impl> 970void 971InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 972{ 973 memDepUnit[replay_inst->threadNumber].replay(replay_inst); 974} 975 976template <class Impl> 977void 978InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 979{ 980 int tid = completed_inst->threadNumber; 981 982 DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n", 983 completed_inst->readPC(), completed_inst->seqNum); 984 985 ++freeEntries; 986 987 completed_inst->memOpDone = true; 988 989 memDepUnit[tid].completed(completed_inst); 990 count[tid]--; 991} 992 993template <class Impl> 994void 995InstructionQueue<Impl>::violation(DynInstPtr &store, 996 DynInstPtr &faulting_load) 997{ 998 memDepUnit[store->threadNumber].violation(store, faulting_load); 999} 1000 1001template <class Impl> 1002void 1003InstructionQueue<Impl>::squash(unsigned tid) 1004{ 1005 DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 1006 "the IQ.\n", tid); 1007 1008 // Read instruction sequence number of last instruction out of the 1009 // time buffer. 1010#if ISA_HAS_DELAY_SLOT 1011 squashedSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum; 1012#else 1013 squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 1014#endif 1015 1016 // Call doSquash if there are insts in the IQ 1017 if (count[tid] > 0) { 1018 doSquash(tid); 1019 } 1020 1021 // Also tell the memory dependence unit to squash. 1022 memDepUnit[tid].squash(squashedSeqNum[tid], tid); 1023} 1024 1025template <class Impl> 1026void 1027InstructionQueue<Impl>::doSquash(unsigned tid) 1028{ 1029 // Start at the tail. 1030 ListIt squash_it = instList[tid].end(); 1031 --squash_it; 1032 1033 DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 1034 tid, squashedSeqNum[tid]); 1035 1036 // Squash any instructions younger than the squashed sequence number 1037 // given. 1038 while (squash_it != instList[tid].end() && 1039 (*squash_it)->seqNum > squashedSeqNum[tid]) { 1040 1041 DynInstPtr squashed_inst = (*squash_it); 1042 1043 // Only handle the instruction if it actually is in the IQ and 1044 // hasn't already been squashed in the IQ. 1045 if (squashed_inst->threadNumber != tid || 1046 squashed_inst->isSquashedInIQ()) { 1047 --squash_it; 1048 continue; 1049 } 1050 1051 if (!squashed_inst->isIssued() || 1052 (squashed_inst->isMemRef() && 1053 !squashed_inst->memOpDone)) { 1054 1055 DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x " 1056 "squashed.\n", 1057 tid, squashed_inst->seqNum, squashed_inst->readPC()); 1058 1059 // Remove the instruction from the dependency list. 1060 if (!squashed_inst->isNonSpeculative() && 1061 !squashed_inst->isStoreConditional() && 1062 !squashed_inst->isMemBarrier() && 1063 !squashed_inst->isWriteBarrier()) { 1064 1065 for (int src_reg_idx = 0; 1066 src_reg_idx < squashed_inst->numSrcRegs(); 1067 src_reg_idx++) 1068 { 1069 PhysRegIndex src_reg = 1070 squashed_inst->renamedSrcRegIdx(src_reg_idx); 1071 1072 // Only remove it from the dependency graph if it 1073 // was placed there in the first place. 1074 1075 // Instead of doing a linked list traversal, we 1076 // can just remove these squashed instructions 1077 // either at issue time, or when the register is 1078 // overwritten. The only downside to this is it 1079 // leaves more room for error. 1080 1081 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 1082 src_reg < numPhysRegs) { 1083 dependGraph.remove(src_reg, squashed_inst); 1084 } 1085 1086 1087 ++iqSquashedOperandsExamined; 1088 } 1089 } else if (!squashed_inst->isStoreConditional() || 1090 !squashed_inst->isCompleted()) { 1091 NonSpecMapIt ns_inst_it = 1092 nonSpecInsts.find(squashed_inst->seqNum); 1093 assert(ns_inst_it != nonSpecInsts.end()); 1094 if (ns_inst_it == nonSpecInsts.end()) { 1095 assert(squashed_inst->getFault() != NoFault); 1096 } else { 1097 1098 (*ns_inst_it).second = NULL; 1099 1100 nonSpecInsts.erase(ns_inst_it); 1101 1102 ++iqSquashedNonSpecRemoved; 1103 } 1104 } 1105 1106 // Might want to also clear out the head of the dependency graph. 1107 1108 // Mark it as squashed within the IQ. 1109 squashed_inst->setSquashedInIQ(); 1110 1111 // @todo: Remove this hack where several statuses are set so the 1112 // inst will flow through the rest of the pipeline. 1113 squashed_inst->setIssued(); 1114 squashed_inst->setCanCommit(); 1115 squashed_inst->clearInIQ(); 1116 1117 //Update Thread IQ Count 1118 count[squashed_inst->threadNumber]--; 1119 1120 ++freeEntries; 1121 } 1122 1123 instList[tid].erase(squash_it--); 1124 ++iqSquashedInstsExamined; 1125 } 1126} 1127 1128template <class Impl> 1129bool 1130InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 1131{ 1132 // Loop through the instruction's source registers, adding 1133 // them to the dependency list if they are not ready. 1134 int8_t total_src_regs = new_inst->numSrcRegs(); 1135 bool return_val = false; 1136 1137 for (int src_reg_idx = 0; 1138 src_reg_idx < total_src_regs; 1139 src_reg_idx++) 1140 { 1141 // Only add it to the dependency graph if it's not ready. 1142 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 1143 PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 1144 1145 // Check the IQ's scoreboard to make sure the register 1146 // hasn't become ready while the instruction was in flight 1147 // between stages. Only if it really isn't ready should 1148 // it be added to the dependency graph. 1149 if (src_reg >= numPhysRegs) { 1150 continue; 1151 } else if (regScoreboard[src_reg] == false) { 1152 DPRINTF(IQ, "Instruction PC %#x has src reg %i that " 1153 "is being added to the dependency chain.\n", 1154 new_inst->readPC(), src_reg); 1155 1156 dependGraph.insert(src_reg, new_inst); 1157 1158 // Change the return value to indicate that something 1159 // was added to the dependency graph. 1160 return_val = true; 1161 } else { 1162 DPRINTF(IQ, "Instruction PC %#x has src reg %i that " 1163 "became ready before it reached the IQ.\n", 1164 new_inst->readPC(), src_reg); 1165 // Mark a register ready within the instruction. 1166 new_inst->markSrcRegReady(src_reg_idx); 1167 } 1168 } 1169 } 1170 1171 return return_val; 1172} 1173 1174template <class Impl> 1175void 1176InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) 1177{ 1178 // Nothing really needs to be marked when an instruction becomes 1179 // the producer of a register's value, but for convenience a ptr 1180 // to the producing instruction will be placed in the head node of 1181 // the dependency links. 1182 int8_t total_dest_regs = new_inst->numDestRegs(); 1183 1184 for (int dest_reg_idx = 0; 1185 dest_reg_idx < total_dest_regs; 1186 dest_reg_idx++) 1187 { 1188 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 1189 1190 // Instructions that use the misc regs will have a reg number 1191 // higher than the normal physical registers. In this case these 1192 // registers are not renamed, and there is no need to track 1193 // dependencies as these instructions must be executed at commit. 1194 if (dest_reg >= numPhysRegs) { 1195 continue; 1196 } 1197 1198 if (!dependGraph.empty(dest_reg)) { 1199 dependGraph.dump(); 1200 panic("Dependency graph %i not empty!", dest_reg); 1201 } 1202 1203 dependGraph.setInst(dest_reg, new_inst); 1204 1205 // Mark the scoreboard to say it's not yet ready. 1206 regScoreboard[dest_reg] = false; 1207 } 1208} 1209 1210template <class Impl> 1211void 1212InstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 1213{ 1214 // If the instruction now has all of its source registers 1215 // available, then add it to the list of ready instructions. 1216 if (inst->readyToIssue()) { 1217 1218 //Add the instruction to the proper ready list. 1219 if (inst->isMemRef()) { 1220 1221 DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 1222 1223 // Message to the mem dependence unit that this instruction has 1224 // its registers ready. 1225 memDepUnit[inst->threadNumber].regsReady(inst); 1226 1227 return; 1228 } 1229 1230 OpClass op_class = inst->opClass(); 1231 1232 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 1233 "the ready list, PC %#x opclass:%i [sn:%lli].\n", 1234 inst->readPC(), op_class, inst->seqNum); 1235 1236 readyInsts[op_class].push(inst); 1237 1238 // Will need to reorder the list if either a queue is not on the list, 1239 // or it has an older instruction than last time. 1240 if (!queueOnList[op_class]) { 1241 addToOrderList(op_class); 1242 } else if (readyInsts[op_class].top()->seqNum < 1243 (*readyIt[op_class]).oldestInst) { 1244 listOrder.erase(readyIt[op_class]); 1245 addToOrderList(op_class); 1246 } 1247 } 1248} 1249 1250template <class Impl> 1251int 1252InstructionQueue<Impl>::countInsts() 1253{ 1254#if 0 1255 //ksewell:This works but definitely could use a cleaner write 1256 //with a more intuitive way of counting. Right now it's 1257 //just brute force .... 1258 // Change the #if if you want to use this method. 1259 int total_insts = 0; 1260 1261 for (int i = 0; i < numThreads; ++i) { 1262 ListIt count_it = instList[i].begin(); 1263 1264 while (count_it != instList[i].end()) { 1265 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 1266 if (!(*count_it)->isIssued()) { 1267 ++total_insts; 1268 } else if ((*count_it)->isMemRef() && 1269 !(*count_it)->memOpDone) { 1270 // Loads that have not been marked as executed still count 1271 // towards the total instructions. 1272 ++total_insts; 1273 } 1274 } 1275 1276 ++count_it; 1277 } 1278 } 1279 1280 return total_insts; 1281#else 1282 return numEntries - freeEntries; 1283#endif 1284} 1285 1286template <class Impl> 1287void 1288InstructionQueue<Impl>::dumpLists() 1289{ 1290 for (int i = 0; i < Num_OpClasses; ++i) { 1291 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 1292 1293 cprintf("\n"); 1294 } 1295 1296 cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 1297 1298 NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 1299 NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 1300 1301 cprintf("Non speculative list: "); 1302 1303 while (non_spec_it != non_spec_end_it) { 1304 cprintf("%#x [sn:%lli]", (*non_spec_it).second->readPC(), 1305 (*non_spec_it).second->seqNum); 1306 ++non_spec_it; 1307 } 1308 1309 cprintf("\n"); 1310 1311 ListOrderIt list_order_it = listOrder.begin(); 1312 ListOrderIt list_order_end_it = listOrder.end(); 1313 int i = 1; 1314 1315 cprintf("List order: "); 1316 1317 while (list_order_it != list_order_end_it) { 1318 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 1319 (*list_order_it).oldestInst); 1320 1321 ++list_order_it; 1322 ++i; 1323 } 1324 1325 cprintf("\n"); 1326} 1327 1328 1329template <class Impl> 1330void 1331InstructionQueue<Impl>::dumpInsts() 1332{ 1333 for (int i = 0; i < numThreads; ++i) { 1334 int num = 0; 1335 int valid_num = 0; 1336 ListIt inst_list_it = instList[i].begin(); 1337 1338 while (inst_list_it != instList[i].end()) 1339 { 1340 cprintf("Instruction:%i\n", 1341 num); 1342 if (!(*inst_list_it)->isSquashed()) { 1343 if (!(*inst_list_it)->isIssued()) { 1344 ++valid_num; 1345 cprintf("Count:%i\n", valid_num); 1346 } else if ((*inst_list_it)->isMemRef() && 1347 !(*inst_list_it)->memOpDone) { 1348 // Loads that have not been marked as executed 1349 // still count towards the total instructions. 1350 ++valid_num; 1351 cprintf("Count:%i\n", valid_num); 1352 } 1353 } 1354 1355 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n" 1356 "Issued:%i\nSquashed:%i\n", 1357 (*inst_list_it)->readPC(), 1358 (*inst_list_it)->seqNum, 1359 (*inst_list_it)->threadNumber, 1360 (*inst_list_it)->isIssued(), 1361 (*inst_list_it)->isSquashed()); 1362 1363 if ((*inst_list_it)->isMemRef()) { 1364 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 1365 } 1366 1367 cprintf("\n"); 1368 1369 inst_list_it++; 1370 ++num; 1371 } 1372 } 1373 1374 cprintf("Insts to Execute list:\n"); 1375 1376 int num = 0; 1377 int valid_num = 0; 1378 ListIt inst_list_it = instsToExecute.begin(); 1379 1380 while (inst_list_it != instsToExecute.end()) 1381 { 1382 cprintf("Instruction:%i\n", 1383 num); 1384 if (!(*inst_list_it)->isSquashed()) { 1385 if (!(*inst_list_it)->isIssued()) { 1386 ++valid_num; 1387 cprintf("Count:%i\n", valid_num); 1388 } else if ((*inst_list_it)->isMemRef() && 1389 !(*inst_list_it)->memOpDone) { 1390 // Loads that have not been marked as executed 1391 // still count towards the total instructions. 1392 ++valid_num; 1393 cprintf("Count:%i\n", valid_num); 1394 } 1395 } 1396 1397 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n" 1398 "Issued:%i\nSquashed:%i\n", 1399 (*inst_list_it)->readPC(), 1400 (*inst_list_it)->seqNum, 1401 (*inst_list_it)->threadNumber, 1402 (*inst_list_it)->isIssued(), 1403 (*inst_list_it)->isSquashed()); 1404 1405 if ((*inst_list_it)->isMemRef()) { 1406 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 1407 } 1408 1409 cprintf("\n"); 1410 1411 inst_list_it++; 1412 ++num; 1413 } 1414} 1415