inst_queue_impl.hh revision 2333
12686Sksewell@umich.edu/* 22100SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 32754Sksewell@umich.edu * All rights reserved. 42706Sksewell@umich.edu * 52706Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 62706Sksewell@umich.edu * modification, are permitted provided that the following conditions are 72706Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 82706Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 92706Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 102706Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 112706Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 122706Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 132706Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 142706Sksewell@umich.edu * this software without specific prior written permission. 152706Sksewell@umich.edu * 162706Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172706Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182706Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192706Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202706Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212706Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222706Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232706Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242706Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252706Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262706Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272706Sksewell@umich.edu */ 282706Sksewell@umich.edu 292706Sksewell@umich.edu#include <limits> 302706Sksewell@umich.edu#include <vector> 312022SN/A 322022SN/A#include "sim/root.hh" 332043SN/A 342024SN/A#include "cpu/o3/fu_pool.hh" 352024SN/A#include "cpu/o3/inst_queue.hh" 362043SN/A 372686Sksewell@umich.eduusing namespace std; 382024SN/A 392022SN/Atemplate <class Impl> 402083SN/AInstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 412686Sksewell@umich.edu int fu_idx, 422101SN/A InstructionQueue<Impl> *iq_ptr) 432043SN/A : Event(&mainEventQueue, Stat_Event_Pri), 442043SN/A inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 452101SN/A{ 462101SN/A this->setFlags(Event::AutoDelete); 472686Sksewell@umich.edu} 482686Sksewell@umich.edu 492101SN/Atemplate <class Impl> 502101SN/Avoid 512101SN/AInstructionQueue<Impl>::FUCompletion::process() 522046SN/A{ 532686Sksewell@umich.edu iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 542686Sksewell@umich.edu inst = NULL; 552686Sksewell@umich.edu} 562470SN/A 572686Sksewell@umich.edu 582686Sksewell@umich.edutemplate <class Impl> 592686Sksewell@umich.educonst char * 602686Sksewell@umich.eduInstructionQueue<Impl>::FUCompletion::description() 612686Sksewell@umich.edu{ 622686Sksewell@umich.edu return "Functional unit completion event"; 632470SN/A} 642241SN/A 652101SN/Atemplate <class Impl> 662495SN/AInstructionQueue<Impl>::InstructionQueue(Params *params) 672495SN/A : dcacheInterface(params->dcacheInterface), 682495SN/A fuPool(params->fuPool), 692101SN/A numEntries(params->numIQEntries), 702495SN/A totalWidth(params->issueWidth), 712495SN/A numPhysIntRegs(params->numPhysIntRegs), 722495SN/A numPhysFloatRegs(params->numPhysFloatRegs), 732101SN/A commitToIEWDelay(params->commitToIEWDelay) 742101SN/A{ 752495SN/A assert(fuPool); 762495SN/A 772495SN/A switchedOut = false; 782495SN/A 792495SN/A numThreads = params->numberOfThreads; 802495SN/A 812495SN/A // Set the number of physical registers as the number of int + float 822495SN/A numPhysRegs = numPhysIntRegs + numPhysFloatRegs; 832495SN/A 842495SN/A DPRINTF(IQ, "There are %i physical registers.\n", numPhysRegs); 852495SN/A 862495SN/A //Create an entry for each physical register within the 872495SN/A //dependency graph. 882101SN/A dependGraph.resize(numPhysRegs); 892101SN/A 902101SN/A // Resize the register scoreboard. 912101SN/A regScoreboard.resize(numPhysRegs); 922101SN/A 932101SN/A //Initialize Mem Dependence Units 942101SN/A for (int i = 0; i < numThreads; i++) { 952101SN/A memDepUnit[i].init(params,i); 962101SN/A memDepUnit[i].setIQ(this); 972101SN/A } 982495SN/A 992495SN/A resetState(); 1002495SN/A 1012495SN/A string policy = params->smtIQPolicy; 1022495SN/A 1032495SN/A //Convert string to lowercase 1042495SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1052495SN/A (int(*)(int)) tolower); 1062495SN/A 1072495SN/A //Figure out resource sharing policy 1082495SN/A if (policy == "dynamic") { 1092495SN/A iqPolicy = Dynamic; 1102495SN/A 1112495SN/A //Set Max Entries to Total ROB Capacity 1122495SN/A for (int i = 0; i < numThreads; i++) { 1132043SN/A maxEntries[i] = numEntries; 1142043SN/A } 1152025SN/A 1162043SN/A } else if (policy == "partitioned") { 1172686Sksewell@umich.edu iqPolicy = Partitioned; 1182686Sksewell@umich.edu 1192123SN/A //@todo:make work if part_amt doesnt divide evenly. 1202101SN/A int part_amt = numEntries / numThreads; 1212686Sksewell@umich.edu 1222686Sksewell@umich.edu //Divide ROB up evenly 1232101SN/A for (int i = 0; i < numThreads; i++) { 1242042SN/A maxEntries[i] = part_amt; 1252101SN/A } 1262686Sksewell@umich.edu 1272686Sksewell@umich.edu DPRINTF(Fetch, "IQ sharing policy set to Partitioned:" 1282686Sksewell@umich.edu "%i entries per thread.\n",part_amt); 1292686Sksewell@umich.edu 1302101SN/A } else if (policy == "threshold") { 1312101SN/A iqPolicy = Threshold; 1322042SN/A 1332101SN/A double threshold = (double)params->smtIQThreshold / 100; 1342686Sksewell@umich.edu 1352686Sksewell@umich.edu int thresholdIQ = (int)((double)threshold * numEntries); 1362965Sksewell@umich.edu 1372965Sksewell@umich.edu //Divide up by threshold amount 1382686Sksewell@umich.edu for (int i = 0; i < numThreads; i++) { 1392101SN/A maxEntries[i] = thresholdIQ; 1402083SN/A } 1412686Sksewell@umich.edu 1422686Sksewell@umich.edu DPRINTF(Fetch, "IQ sharing policy set to Threshold:" 1432101SN/A "%i entries per thread.\n",thresholdIQ); 1442043SN/A } else { 1452025SN/A assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 1462043SN/A "Partitioned, Threshold}"); 1472686Sksewell@umich.edu } 1482616SN/A} 1492616SN/A 1502616SN/Atemplate <class Impl> 1512616SN/AInstructionQueue<Impl>::~InstructionQueue() 1522101SN/A{ 1532083SN/A dependGraph.reset(); 1542025SN/A cprintf("Nodes traversed: %i, removed: %i\n", 1552043SN/A dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1562686Sksewell@umich.edu} 1572686Sksewell@umich.edu 1582686Sksewell@umich.edutemplate <class Impl> 1592686Sksewell@umich.edustd::string 1602025SN/AInstructionQueue<Impl>::name() const 1612686Sksewell@umich.edu{ 1622742Sksewell@umich.edu return cpu->name() + ".iq"; 1632742Sksewell@umich.edu} 1642742Sksewell@umich.edu 1652742Sksewell@umich.edutemplate <class Impl> 1662742Sksewell@umich.eduvoid 1672742Sksewell@umich.eduInstructionQueue<Impl>::regStats() 1682742Sksewell@umich.edu{ 1692742Sksewell@umich.edu using namespace Stats; 1702742Sksewell@umich.edu iqInstsAdded 1712742Sksewell@umich.edu .name(name() + ".iqInstsAdded") 1722101SN/A .desc("Number of instructions added to the IQ (excludes non-spec)") 1732084SN/A .prereq(iqInstsAdded); 1742025SN/A 1752495SN/A iqNonSpecInstsAdded 1762495SN/A .name(name() + ".iqNonSpecInstsAdded") 1772495SN/A .desc("Number of non-speculative instructions added to the IQ") 1782616SN/A .prereq(iqNonSpecInstsAdded); 1792495SN/A 1802616SN/A iqInstsIssued 1812495SN/A .name(name() + ".iqInstsIssued") 1822495SN/A .desc("Number of instructions issued") 1832495SN/A .prereq(iqInstsIssued); 1842495SN/A 1852495SN/A iqIntInstsIssued 1862495SN/A .name(name() + ".iqIntInstsIssued") 1872101SN/A .desc("Number of integer instructions issued") 1882043SN/A .prereq(iqIntInstsIssued); 1892025SN/A 1902495SN/A iqFloatInstsIssued 1912495SN/A .name(name() + ".iqFloatInstsIssued") 1922495SN/A .desc("Number of float instructions issued") 1932495SN/A .prereq(iqFloatInstsIssued); 1942495SN/A 1952495SN/A iqBranchInstsIssued 1962101SN/A .name(name() + ".iqBranchInstsIssued") 1972084SN/A .desc("Number of branch instructions issued") 1982024SN/A .prereq(iqBranchInstsIssued); 1992043SN/A 2002239SN/A iqMemInstsIssued 2012239SN/A .name(name() + ".iqMemInstsIssued") 2022101SN/A .desc("Number of memory instructions issued") 2032101SN/A .prereq(iqMemInstsIssued); 2042101SN/A 2052101SN/A iqMiscInstsIssued 2062101SN/A .name(name() + ".iqMiscInstsIssued") 2072101SN/A .desc("Number of miscellaneous instructions issued") 2082043SN/A .prereq(iqMiscInstsIssued); 2092043SN/A 2102025SN/A iqSquashedInstsIssued 2112043SN/A .name(name() + ".iqSquashedInstsIssued") 2122043SN/A .desc("Number of squashed instructions issued") 2132101SN/A .prereq(iqSquashedInstsIssued); 2142101SN/A 2152101SN/A iqSquashedInstsExamined 2162686Sksewell@umich.edu .name(name() + ".iqSquashedInstsExamined") 2172686Sksewell@umich.edu .desc("Number of squashed instructions iterated over during squash;" 2182101SN/A " mainly for profiling") 2192043SN/A .prereq(iqSquashedInstsExamined); 2202025SN/A 2212043SN/A iqSquashedOperandsExamined 2222239SN/A .name(name() + ".iqSquashedOperandsExamined") 2232101SN/A .desc("Number of squashed operands that are examined and possibly " 2242104SN/A "removed from graph") 2252101SN/A .prereq(iqSquashedOperandsExamined); 2262101SN/A 2272101SN/A iqSquashedNonSpecRemoved 2282101SN/A .name(name() + ".iqSquashedNonSpecRemoved") 2292101SN/A .desc("Number of squashed non-spec instructions that were removed") 2302043SN/A .prereq(iqSquashedNonSpecRemoved); 2312043SN/A 2322043SN/A queueResDist 2332101SN/A .init(Num_OpClasses, 0, 99, 2) 2342686Sksewell@umich.edu .name(name() + ".IQ:residence:") 2352686Sksewell@umich.edu .desc("cycles from dispatch to issue") 2362686Sksewell@umich.edu .flags(total | pdf | cdf ) 2372686Sksewell@umich.edu ; 2382686Sksewell@umich.edu for (int i = 0; i < Num_OpClasses; ++i) { 2392686Sksewell@umich.edu queueResDist.subname(i, opClassStrings[i]); 2402686Sksewell@umich.edu } 2412101SN/A numIssuedDist 2422043SN/A .init(0,totalWidth,1) 2432043SN/A .name(name() + ".ISSUE:issued_per_cycle") 2442043SN/A .desc("Number of insts issued each cycle") 2452101SN/A .flags(pdf) 2462101SN/A ; 2472101SN/A/* 2482043SN/A dist_unissued 2492043SN/A .init(Num_OpClasses+2) 2502043SN/A .name(name() + ".ISSUE:unissued_cause") 2512123SN/A .desc("Reason ready instruction not issued") 2522239SN/A .flags(pdf | dist) 2532686Sksewell@umich.edu ; 2542686Sksewell@umich.edu for (int i=0; i < (Num_OpClasses + 2); ++i) { 2552043SN/A dist_unissued.subname(i, unissued_names[i]); 2562043SN/A } 2572100SN/A*/ 2582686Sksewell@umich.edu statIssuedInstType 2592686Sksewell@umich.edu .init(numThreads,Num_OpClasses) 2602686Sksewell@umich.edu .name(name() + ".ISSUE:FU_type") 2612686Sksewell@umich.edu .desc("Type of FU issued") 2622239SN/A .flags(total | pdf | dist) 2632686Sksewell@umich.edu ; 2642686Sksewell@umich.edu statIssuedInstType.ysubnames(opClassStrings); 2652043SN/A 2662084SN/A // 2672024SN/A // How long did instructions for a particular FU type wait prior to issue 2682101SN/A // 2692686Sksewell@umich.edu 2702239SN/A issueDelayDist 2712239SN/A .init(Num_OpClasses,0,99,2) 2722239SN/A .name(name() + ".ISSUE:") 2732495SN/A .desc("cycles from operands ready to issue") 2742495SN/A .flags(pdf | cdf) 2752495SN/A ; 2762495SN/A 2772495SN/A for (int i=0; i<Num_OpClasses; ++i) { 2782495SN/A stringstream subname; 2792495SN/A subname << opClassStrings[i] << "_delay"; 2802495SN/A issueDelayDist.subname(i, subname.str()); 2812084SN/A } 2822084SN/A 2832024SN/A issueRate 2842101SN/A .name(name() + ".ISSUE:rate") 2852101SN/A .desc("Inst issue rate") 2862101SN/A .flags(total) 2872101SN/A ; 2882686Sksewell@umich.edu issueRate = iqInstsIssued / cpu->numCycles; 2892686Sksewell@umich.edu/* 2902686Sksewell@umich.edu issue_stores 2912686Sksewell@umich.edu .name(name() + ".ISSUE:stores") 2922052SN/A .desc("Number of stores issued") 2932686Sksewell@umich.edu .flags(total) 2942686Sksewell@umich.edu ; 2952686Sksewell@umich.edu issue_stores = exe_refs - exe_loads; 2962101SN/A*/ 2972101SN/A/* 2982686Sksewell@umich.edu issue_op_rate 2992686Sksewell@umich.edu .name(name() + ".ISSUE:op_rate") 3002101SN/A .desc("Operation issue rate") 3012101SN/A .flags(total) 3022686Sksewell@umich.edu ; 3032686Sksewell@umich.edu issue_op_rate = issued_ops / numCycles; 3042686Sksewell@umich.edu*/ 3052686Sksewell@umich.edu statFuBusy 3062686Sksewell@umich.edu .init(Num_OpClasses) 3072686Sksewell@umich.edu .name(name() + ".ISSUE:fu_full") 3082101SN/A .desc("attempts to use FU when none available") 3092101SN/A .flags(pdf | dist) 3102686Sksewell@umich.edu ; 3112027SN/A for (int i=0; i < Num_OpClasses; ++i) { 3122686Sksewell@umich.edu statFuBusy.subname(i, opClassStrings[i]); 3132686Sksewell@umich.edu } 3142686Sksewell@umich.edu 3152101SN/A fuBusy 3162101SN/A .init(numThreads) 3172101SN/A .name(name() + ".ISSUE:fu_busy_cnt") 3182101SN/A .desc("FU busy when requested") 3192101SN/A .flags(total) 3202686Sksewell@umich.edu ; 3212686Sksewell@umich.edu 3222686Sksewell@umich.edu fuBusyRate 3232686Sksewell@umich.edu .name(name() + ".ISSUE:fu_busy_rate") 3242686Sksewell@umich.edu .desc("FU busy rate (busy events/executed inst)") 3252101SN/A .flags(total) 3262101SN/A ; 3272101SN/A fuBusyRate = fuBusy / iqInstsIssued; 3282101SN/A 3292101SN/A for ( int i=0; i < numThreads; i++) { 3302101SN/A // Tell mem dependence unit to reg stats as well. 3312043SN/A memDepUnit[i].regStats(); 3322027SN/A } 3332101SN/A} 3342101SN/A 3352041SN/Atemplate <class Impl> 3362101SN/Avoid 3372101SN/AInstructionQueue<Impl>::resetState() 3382686Sksewell@umich.edu{ 3392742Sksewell@umich.edu //Initialize thread IQ counts 3402495SN/A for (int i = 0; i <numThreads; i++) { 3412495SN/A count[i] = 0; 3422573SN/A instList[i].clear(); 3432573SN/A } 3442573SN/A 3452616SN/A // Initialize the number of free IQ entries. 3462573SN/A freeEntries = numEntries; 3472573SN/A 3482616SN/A // Note that in actuality, the registers corresponding to the logical 3492573SN/A // registers start off as ready. However this doesn't matter for the 3502573SN/A // IQ as the instruction should have been correctly told if those 3512616SN/A // registers are ready in rename. Thus it can all be initialized as 3522573SN/A // unready. 3532573SN/A for (int i = 0; i < numPhysRegs; ++i) { 3542616SN/A regScoreboard[i] = false; 3552573SN/A } 3562573SN/A 3572616SN/A for (int i = 0; i < numThreads; ++i) { 3582573SN/A squashedSeqNum[i] = 0; 3592573SN/A } 3602686Sksewell@umich.edu 3612573SN/A for (int i = 0; i < Num_OpClasses; ++i) { 3622573SN/A while (!readyInsts[i].empty()) 3632573SN/A readyInsts[i].pop(); 3642686Sksewell@umich.edu queueOnList[i] = false; 3652686Sksewell@umich.edu readyIt[i] = listOrder.end(); 3662686Sksewell@umich.edu } 3672686Sksewell@umich.edu nonSpecInsts.clear(); 3682573SN/A listOrder.clear(); 3692573SN/A} 3702573SN/A 3712573SN/Atemplate <class Impl> 3722616SN/Avoid 3732616SN/AInstructionQueue<Impl>::setActiveThreads(list<unsigned> *at_ptr) 3742616SN/A{ 3752573SN/A DPRINTF(IQ, "Setting active threads list pointer.\n"); 3762573SN/A activeThreads = at_ptr; 3772573SN/A} 3782616SN/A 3792573SN/Atemplate <class Impl> 3802616SN/Avoid 3812573SN/AInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 3822616SN/A{ 3832573SN/A DPRINTF(IQ, "Set the issue to execute queue.\n"); 3842573SN/A issueToExecuteQueue = i2e_ptr; 3852573SN/A} 3862616SN/A 3872573SN/Atemplate <class Impl> 3882616SN/Avoid 3892573SN/AInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3902616SN/A{ 3912573SN/A DPRINTF(IQ, "Set the time buffer.\n"); 3922573SN/A timeBuffer = tb_ptr; 3932573SN/A 3942573SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3952616SN/A} 3962573SN/A 3972573SN/Atemplate <class Impl> 3982573SN/Avoid 3992495SN/AInstructionQueue<Impl>::switchOut() 4002616SN/A{ 4012495SN/A resetState(); 4022495SN/A dependGraph.reset(); 4032686Sksewell@umich.edu switchedOut = true; 4042686Sksewell@umich.edu for (int i = 0; i < numThreads; ++i) { 4052686Sksewell@umich.edu memDepUnit[i].switchOut(); 4062686Sksewell@umich.edu } 4072686Sksewell@umich.edu} 4082686Sksewell@umich.edu 4092686Sksewell@umich.edutemplate <class Impl> 4102101SN/Avoid 4112101SN/AInstructionQueue<Impl>::takeOverFrom() 4122025SN/A{ 4132101SN/A switchedOut = false; 4142686Sksewell@umich.edu} 4152686Sksewell@umich.edu 4162686Sksewell@umich.edutemplate <class Impl> 4172686Sksewell@umich.eduint 4182686Sksewell@umich.eduInstructionQueue<Impl>::entryAmount(int num_threads) 4192686Sksewell@umich.edu{ 4202101SN/A if (iqPolicy == Partitioned) { 4212686Sksewell@umich.edu return numEntries / num_threads; 4222686Sksewell@umich.edu } else { 4232686Sksewell@umich.edu return 0; 4242686Sksewell@umich.edu } 4252686Sksewell@umich.edu} 4262101SN/A 4272101SN/A 4282101SN/Atemplate <class Impl> 4292043SN/Avoid 4302027SN/AInstructionQueue<Impl>::resetEntries() 4312101SN/A{ 4322101SN/A if (iqPolicy != Dynamic || numThreads > 1) { 4332101SN/A int active_threads = (*activeThreads).size(); 4342686Sksewell@umich.edu 4352572SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 4362572SN/A list<unsigned>::iterator list_end = (*activeThreads).end(); 4372101SN/A 4382601SN/A while (threads != list_end) { 4392601SN/A if (iqPolicy == Partitioned) { 4402601SN/A maxEntries[*threads++] = numEntries / active_threads; 4412601SN/A } else if(iqPolicy == Threshold && active_threads == 1) { 4422601SN/A maxEntries[*threads++] = numEntries; 4432601SN/A } 4442686Sksewell@umich.edu } 4452101SN/A } 4462742Sksewell@umich.edu} 4472742Sksewell@umich.edu 4482101SN/Atemplate <class Impl> 4492027SN/Aunsigned 4502572SN/AInstructionQueue<Impl>::numFreeEntries() 4512686Sksewell@umich.edu{ 4522686Sksewell@umich.edu return freeEntries; 4532686Sksewell@umich.edu} 4542686Sksewell@umich.edu 4552686Sksewell@umich.edutemplate <class Impl> 4562686Sksewell@umich.eduunsigned 4572686Sksewell@umich.eduInstructionQueue<Impl>::numFreeEntries(unsigned tid) 4582686Sksewell@umich.edu{ 4592686Sksewell@umich.edu return maxEntries[tid] - count[tid]; 4602686Sksewell@umich.edu} 4612686Sksewell@umich.edu 4622686Sksewell@umich.edu// Might want to do something more complex if it knows how many instructions 4632686Sksewell@umich.edu// will be issued this cycle. 4642686Sksewell@umich.edutemplate <class Impl> 4652686Sksewell@umich.edubool 4662686Sksewell@umich.eduInstructionQueue<Impl>::isFull() 4672686Sksewell@umich.edu{ 4682101SN/A if (freeEntries == 0) { 4692101SN/A return(true); 4702027SN/A } else { 4712572SN/A return(false); 4722101SN/A } 4732686Sksewell@umich.edu} 4742686Sksewell@umich.edu 4752686Sksewell@umich.edutemplate <class Impl> 4762101SN/Abool 4772101SN/AInstructionQueue<Impl>::isFull(unsigned tid) 4782027SN/A{ 4792686Sksewell@umich.edu if (numFreeEntries(tid) == 0) { 4802686Sksewell@umich.edu return(true); 4812686Sksewell@umich.edu } else { 4822686Sksewell@umich.edu return(false); 4832686Sksewell@umich.edu } 4842602SN/A} 4852602SN/A 4862602SN/Atemplate <class Impl> 4872101SN/Abool 4882101SN/AInstructionQueue<Impl>::hasReadyInsts() 4892027SN/A{ 4902572SN/A if (!listOrder.empty()) { 4912603SN/A return true; 4922686Sksewell@umich.edu } 4932686Sksewell@umich.edu 4942686Sksewell@umich.edu for (int i = 0; i < Num_OpClasses; ++i) { 4952101SN/A if (!readyInsts[i].empty()) { 4962055SN/A return true; 4972686Sksewell@umich.edu } 4982686Sksewell@umich.edu } 4992686Sksewell@umich.edu 5002101SN/A return false; 5012101SN/A} 5022602SN/A 5032602SN/Atemplate <class Impl> 5042603SN/Avoid 5052686Sksewell@umich.eduInstructionQueue<Impl>::insert(DynInstPtr &new_inst) 5062686Sksewell@umich.edu{ 5072686Sksewell@umich.edu // Make sure the instruction is valid 5082686Sksewell@umich.edu assert(new_inst); 5092686Sksewell@umich.edu 5102686Sksewell@umich.edu DPRINTF(IQ, "Adding instruction [sn:%lli] PC %#x to the IQ.\n", 5112686Sksewell@umich.edu new_inst->seqNum, new_inst->readPC()); 5122686Sksewell@umich.edu 5132686Sksewell@umich.edu assert(freeEntries != 0); 5142686Sksewell@umich.edu 5152686Sksewell@umich.edu instList[new_inst->threadNumber].push_back(new_inst); 5162686Sksewell@umich.edu 5172686Sksewell@umich.edu --freeEntries; 5182686Sksewell@umich.edu 5192686Sksewell@umich.edu new_inst->setInIQ(); 5202686Sksewell@umich.edu 5212602SN/A // Look through its source registers (physical regs), and mark any 5222602SN/A // dependencies. 5232602SN/A addToDependents(new_inst); 5242602SN/A 5252686Sksewell@umich.edu // Have this instruction set itself as the producer of its destination 5262686Sksewell@umich.edu // register(s). 5272686Sksewell@umich.edu addToProducers(new_inst); 5282686Sksewell@umich.edu 5292686Sksewell@umich.edu if (new_inst->isMemRef()) { 5302686Sksewell@umich.edu memDepUnit[new_inst->threadNumber].insert(new_inst); 5312686Sksewell@umich.edu } else { 5322686Sksewell@umich.edu addIfReady(new_inst); 5332686Sksewell@umich.edu } 5342686Sksewell@umich.edu 5352686Sksewell@umich.edu ++iqInstsAdded; 5362686Sksewell@umich.edu 5372686Sksewell@umich.edu count[new_inst->threadNumber]++; 5382686Sksewell@umich.edu 5392686Sksewell@umich.edu assert(freeEntries == (numEntries - countInsts())); 5402686Sksewell@umich.edu} 5412686Sksewell@umich.edu 5422602SN/Atemplate <class Impl> 5432602SN/Avoid 5442101SN/AInstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) 5452055SN/A{ 5462101SN/A // @todo: Clean up this code; can do it by setting inst as unable 5472572SN/A // to issue, then calling normal insert on the inst. 5482572SN/A 5492101SN/A assert(new_inst); 5502686Sksewell@umich.edu 5512686Sksewell@umich.edu nonSpecInsts[new_inst->seqNum] = new_inst; 5522686Sksewell@umich.edu 5532686Sksewell@umich.edu DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %#x " 5542686Sksewell@umich.edu "to the IQ.\n", 5552686Sksewell@umich.edu new_inst->seqNum, new_inst->readPC()); 5562686Sksewell@umich.edu 5572101SN/A assert(freeEntries != 0); 5582742Sksewell@umich.edu 5592742Sksewell@umich.edu instList[new_inst->threadNumber].push_back(new_inst); 5602101SN/A 5612027SN/A --freeEntries; 5622572SN/A 5632686Sksewell@umich.edu new_inst->setInIQ(); 5642686Sksewell@umich.edu 5652686Sksewell@umich.edu // Have this instruction set itself as the producer of its destination 5662686Sksewell@umich.edu // register(s). 5672686Sksewell@umich.edu addToProducers(new_inst); 5682686Sksewell@umich.edu 5692686Sksewell@umich.edu // If it's a memory instruction, add it to the memory dependency 5702686Sksewell@umich.edu // unit. 5712686Sksewell@umich.edu if (new_inst->isMemRef()) { 5722686Sksewell@umich.edu memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 5732686Sksewell@umich.edu } 5742686Sksewell@umich.edu 5752686Sksewell@umich.edu ++iqNonSpecInstsAdded; 5762686Sksewell@umich.edu 5772686Sksewell@umich.edu count[new_inst->threadNumber]++; 5782686Sksewell@umich.edu 5792686Sksewell@umich.edu assert(freeEntries == (numEntries - countInsts())); 5802101SN/A} 5812101SN/A 5822027SN/Atemplate <class Impl> 5832572SN/Avoid 5842101SN/AInstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) 5852686Sksewell@umich.edu{ 5862686Sksewell@umich.edu memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 5872686Sksewell@umich.edu 5882686Sksewell@umich.edu insertNonSpec(barr_inst); 5892686Sksewell@umich.edu} 5902686Sksewell@umich.edu 5912686Sksewell@umich.edutemplate <class Impl> 5922101SN/Atypename Impl::DynInstPtr 5932101SN/AInstructionQueue<Impl>::getInstToExecute() 5942027SN/A{ 5952101SN/A assert(!instsToExecute.empty()); 5962686Sksewell@umich.edu DynInstPtr inst = instsToExecute.front(); 5972686Sksewell@umich.edu instsToExecute.pop_front(); 5982101SN/A return inst; 5992027SN/A} 6002605SN/A 6012686Sksewell@umich.edutemplate <class Impl> 6022605SN/Avoid 6032101SN/AInstructionQueue<Impl>::addToOrderList(OpClass op_class) 6042101SN/A{ 6052027SN/A assert(!readyInsts[op_class].empty()); 6062572SN/A 6072686Sksewell@umich.edu ListOrderEntry queue_entry; 6082686Sksewell@umich.edu 6092686Sksewell@umich.edu queue_entry.queueType = op_class; 6102686Sksewell@umich.edu 6112101SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 6122101SN/A 6132602SN/A ListOrderIt list_it = listOrder.begin(); 6142602SN/A ListOrderIt list_end_it = listOrder.end(); 6152604SN/A 6162686Sksewell@umich.edu while (list_it != list_end_it) { 6172686Sksewell@umich.edu if ((*list_it).oldestInst > queue_entry.oldestInst) { 6182686Sksewell@umich.edu break; 6192686Sksewell@umich.edu } 6202686Sksewell@umich.edu 6212686Sksewell@umich.edu list_it++; 6222686Sksewell@umich.edu } 6232686Sksewell@umich.edu 6242686Sksewell@umich.edu readyIt[op_class] = listOrder.insert(list_it, queue_entry); 6252686Sksewell@umich.edu queueOnList[op_class] = true; 6262686Sksewell@umich.edu} 6272686Sksewell@umich.edu 6282686Sksewell@umich.edutemplate <class Impl> 6292686Sksewell@umich.eduvoid 6302686Sksewell@umich.eduInstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 6312686Sksewell@umich.edu{ 6322602SN/A // Get iterator of next item on the list 6332602SN/A // Delete the original iterator 6342602SN/A // Determine if the next item is either the end of the list or younger 6352602SN/A // than the new instruction. If so, then add in a new iterator right here. 6362686Sksewell@umich.edu // If not, then move along. 6372686Sksewell@umich.edu ListOrderEntry queue_entry; 6382686Sksewell@umich.edu OpClass op_class = (*list_order_it).queueType; 6392686Sksewell@umich.edu ListOrderIt next_it = list_order_it; 6402686Sksewell@umich.edu 6412686Sksewell@umich.edu ++next_it; 6422686Sksewell@umich.edu 6432686Sksewell@umich.edu queue_entry.queueType = op_class; 6442686Sksewell@umich.edu queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 6452686Sksewell@umich.edu 6462686Sksewell@umich.edu while (next_it != listOrder.end() && 6472686Sksewell@umich.edu (*next_it).oldestInst < queue_entry.oldestInst) { 6482686Sksewell@umich.edu ++next_it; 6492686Sksewell@umich.edu } 6502686Sksewell@umich.edu 6512686Sksewell@umich.edu readyIt[op_class] = listOrder.insert(next_it, queue_entry); 6522686Sksewell@umich.edu} 6532602SN/A 6542602SN/Atemplate <class Impl> 6552101SN/Avoid 6562027SN/AInstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 6572101SN/A{ 6582101SN/A // The CPU could have been sleeping until this op completed (*extremely* 6592605SN/A // long latency op). Wake it if it was. This may be overkill. 6602686Sksewell@umich.edu if (isSwitchedOut()) { 6612686Sksewell@umich.edu return; 6622686Sksewell@umich.edu } 6632101SN/A 6642101SN/A iewStage->wakeCPU(); 6652027SN/A 6662101SN/A if (fu_idx > -1) 6672101SN/A fuPool->freeUnitNextCycle(fu_idx); 6682101SN/A 6692101SN/A // @todo: Ensure that these FU Completions happen at the beginning 6702686Sksewell@umich.edu // of a cycle, otherwise they could add too many instructions to 6712686Sksewell@umich.edu // the queue. 6722686Sksewell@umich.edu // @todo: This could break if there's multiple multi-cycle ops 6732686Sksewell@umich.edu // finishing on this cycle. Maybe implement something like 6742101SN/A // instToCommit in iew_impl.hh. 6752101SN/A issueToExecuteQueue->access(0)->size++; 6762101SN/A instsToExecute.push_back(inst); 6772101SN/A// int &size = issueToExecuteQueue->access(0)->size; 6782101SN/A 6792101SN/A// issueToExecuteQueue->access(0)->insts[size++] = inst; 6802572SN/A} 6812572SN/A 6822101SN/A// @todo: Figure out a better way to remove the squashed items from the 6832605SN/A// lists. Checking the top item of each list to see if it's squashed 6842607SN/A// wastes time and forces jumps. 6852607SN/Atemplate <class Impl> 6862101SN/Avoid 6872605SN/AInstructionQueue<Impl>::scheduleReadyInsts() 6882607SN/A{ 6892607SN/A DPRINTF(IQ, "Attempting to schedule ready instructions from " 6902101SN/A "the IQ.\n"); 6912605SN/A 6922607SN/A IssueStruct *i2e_info = issueToExecuteQueue->access(0); 6932607SN/A 6942101SN/A // Have iterator to head of the list 6952605SN/A // While I haven't exceeded bandwidth or reached the end of the list, 6962607SN/A // Try to get a FU that can do what this op needs. 6972607SN/A // If successful, change the oldestInst to the new top of the list, put 6982101SN/A // the queue in the proper place in the list. 6992605SN/A // Increment the iterator. 7002607SN/A // This will avoid trying to schedule a certain op class if there are no 7012607SN/A // FUs that handle it. 7022101SN/A ListOrderIt order_it = listOrder.begin(); 7032605SN/A ListOrderIt order_end_it = listOrder.end(); 7042686Sksewell@umich.edu int total_issued = 0; 7052686Sksewell@umich.edu 7062101SN/A while (total_issued < totalWidth && 7072101SN/A order_it != order_end_it) { 7082101SN/A OpClass op_class = (*order_it).queueType; 7092101SN/A 7102572SN/A assert(!readyInsts[op_class].empty()); 7112101SN/A 7122101SN/A DynInstPtr issuing_inst = readyInsts[op_class].top(); 7132607SN/A 7142686Sksewell@umich.edu assert(issuing_inst->seqNum == (*order_it).oldestInst); 7152686Sksewell@umich.edu 7162686Sksewell@umich.edu if (issuing_inst->isSquashed()) { 7172686Sksewell@umich.edu readyInsts[op_class].pop(); 7182607SN/A 7192607SN/A if (!readyInsts[op_class].empty()) { 7202686Sksewell@umich.edu moveToYoungerInst(order_it); 7212686Sksewell@umich.edu } else { 7222686Sksewell@umich.edu readyIt[op_class] = listOrder.end(); 7232686Sksewell@umich.edu queueOnList[op_class] = false; 7242607SN/A } 7252101SN/A 7262101SN/A listOrder.erase(order_it++); 7272101SN/A 7282605SN/A ++iqSquashedInstsIssued; 7292607SN/A 7302686Sksewell@umich.edu continue; 7312686Sksewell@umich.edu } 7322686Sksewell@umich.edu 7332686Sksewell@umich.edu int idx = -2; 7342607SN/A int op_latency = 1; 7352607SN/A int tid = issuing_inst->threadNumber; 7362686Sksewell@umich.edu 7372686Sksewell@umich.edu if (op_class != No_OpClass) { 7382686Sksewell@umich.edu idx = fuPool->getUnit(op_class); 7392686Sksewell@umich.edu 7402607SN/A if (idx > -1) { 7412135SN/A op_latency = fuPool->getOpLatency(op_class); 7422135SN/A } 7432101SN/A } 7442101SN/A 7452572SN/A if (idx == -2 || idx != -1) { 7462686Sksewell@umich.edu if (op_latency == 1) { 7472101SN/A// i2e_info->insts[exec_queue_slot++] = issuing_inst; 7482101SN/A i2e_info->size++; 7492572SN/A instsToExecute.push_back(issuing_inst); 7502686Sksewell@umich.edu 7512686Sksewell@umich.edu // Add the FU onto the list of FU's to be freed next 7522101SN/A // cycle if we used one. 7532686Sksewell@umich.edu if (idx >= 0) 7542686Sksewell@umich.edu fuPool->freeUnitNextCycle(idx); 7552686Sksewell@umich.edu } else { 7562686Sksewell@umich.edu int issue_latency = fuPool->getIssueLatency(op_class); 7572686Sksewell@umich.edu // Generate completion event for the FU 7582686Sksewell@umich.edu FUCompletion *execution = new FUCompletion(issuing_inst, 7592686Sksewell@umich.edu idx, this); 7602686Sksewell@umich.edu 7612686Sksewell@umich.edu execution->schedule(curTick + cpu->cycles(issue_latency - 1)); 7622686Sksewell@umich.edu 7632686Sksewell@umich.edu // @todo: Enforce that issue_latency == 1 or op_latency 7642686Sksewell@umich.edu if (issue_latency > 1) { 7652101SN/A execution->setFreeFU(); 7662101SN/A } else { 7672602SN/A // @todo: Not sure I'm accounting for the 7682602SN/A // multi-cycle op in a pipelined FU properly, or 7692608SN/A // the number of instructions issued in one cycle. 7702686Sksewell@umich.edu// i2e_info->insts[exec_queue_slot++] = issuing_inst; 7712686Sksewell@umich.edu// i2e_info->size++; 7722686Sksewell@umich.edu 7732686Sksewell@umich.edu // Add the FU onto the list of FU's to be freed next cycle. 7742686Sksewell@umich.edu fuPool->freeUnitNextCycle(idx); 7752686Sksewell@umich.edu } 7762686Sksewell@umich.edu } 7772686Sksewell@umich.edu 7782686Sksewell@umich.edu DPRINTF(IQ, "Thread %i: Issuing instruction PC %#x " 7792686Sksewell@umich.edu "[sn:%lli]\n", 7802686Sksewell@umich.edu tid, issuing_inst->readPC(), 7812686Sksewell@umich.edu issuing_inst->seqNum); 7822686Sksewell@umich.edu 7832686Sksewell@umich.edu readyInsts[op_class].pop(); 7842686Sksewell@umich.edu 7852686Sksewell@umich.edu if (!readyInsts[op_class].empty()) { 7862686Sksewell@umich.edu moveToYoungerInst(order_it); 7872686Sksewell@umich.edu } else { 7882686Sksewell@umich.edu readyIt[op_class] = listOrder.end(); 7892686Sksewell@umich.edu queueOnList[op_class] = false; 7902686Sksewell@umich.edu } 7912686Sksewell@umich.edu 7922602SN/A issuing_inst->setIssued(); 7932602SN/A ++total_issued; 7942602SN/A 7952602SN/A if (!issuing_inst->isMemRef()) { 7962686Sksewell@umich.edu // Memory instructions can not be freed from the IQ until they 7972686Sksewell@umich.edu // complete. 7982686Sksewell@umich.edu ++freeEntries; 7992686Sksewell@umich.edu count[tid]--; 8002686Sksewell@umich.edu issuing_inst->removeInIQ(); 8012686Sksewell@umich.edu } else { 8022686Sksewell@umich.edu memDepUnit[tid].issue(issuing_inst); 8032686Sksewell@umich.edu } 8042686Sksewell@umich.edu 8052686Sksewell@umich.edu listOrder.erase(order_it++); 8062686Sksewell@umich.edu statIssuedInstType[tid][op_class]++; 8072686Sksewell@umich.edu } else { 8082686Sksewell@umich.edu statFuBusy[op_class]++; 8092686Sksewell@umich.edu fuBusy[tid]++; 8102686Sksewell@umich.edu ++order_it; 8112686Sksewell@umich.edu } 8122686Sksewell@umich.edu } 8132686Sksewell@umich.edu 8142686Sksewell@umich.edu numIssuedDist.sample(total_issued); 8152686Sksewell@umich.edu iqInstsIssued+= total_issued; 8162686Sksewell@umich.edu 8172686Sksewell@umich.edu if (total_issued) { 8182686Sksewell@umich.edu cpu->activityThisCycle(); 8192686Sksewell@umich.edu } else { 8202602SN/A DPRINTF(IQ, "Not able to schedule any instructions.\n"); 8212602SN/A } 8222101SN/A} 8232101SN/A 8242101SN/Atemplate <class Impl> 8252101SN/Avoid 8262101SN/AInstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 8272101SN/A{ 8282101SN/A DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 8292686Sksewell@umich.edu "to execute.\n", inst); 8302686Sksewell@umich.edu 8312686Sksewell@umich.edu NonSpecMapIt inst_it = nonSpecInsts.find(inst); 8322101SN/A 8332101SN/A assert(inst_it != nonSpecInsts.end()); 8342101SN/A 8352101SN/A unsigned tid = (*inst_it).second->threadNumber; 8362101SN/A 8372101SN/A (*inst_it).second->setCanIssue(); 8382101SN/A 8392101SN/A if (!(*inst_it).second->isMemRef()) { 8402686Sksewell@umich.edu addIfReady((*inst_it).second); 8412686Sksewell@umich.edu } else { 8422101SN/A memDepUnit[tid].nonSpecInstReady((*inst_it).second); 8432101SN/A } 8442101SN/A 8452101SN/A (*inst_it).second = NULL; 8462686Sksewell@umich.edu 8472101SN/A nonSpecInsts.erase(inst_it); 8482101SN/A} 8492101SN/A 8502101SN/Atemplate <class Impl> 8512101SN/Avoid 8522101SN/AInstructionQueue<Impl>::commit(const InstSeqNum &inst, unsigned tid) 8532101SN/A{ 8542101SN/A DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 8552101SN/A tid,inst); 8562101SN/A 8572101SN/A ListIt iq_it = instList[tid].begin(); 8582101SN/A 8592101SN/A while (iq_it != instList[tid].end() && 8602686Sksewell@umich.edu (*iq_it)->seqNum <= inst) { 8612742Sksewell@umich.edu ++iq_it; 8622742Sksewell@umich.edu instList[tid].pop_front(); 8632750Sksewell@umich.edu } 8642742Sksewell@umich.edu 8652101SN/A assert(freeEntries == (numEntries - countInsts())); 8662043SN/A} 8672027SN/A 8682101SN/Atemplate <class Impl> 8692686Sksewell@umich.eduint 8702742Sksewell@umich.eduInstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 8712742Sksewell@umich.edu{ 8722742Sksewell@umich.edu int dependents = 0; 8732742Sksewell@umich.edu 8742046SN/A DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 8752084SN/A 8762686Sksewell@umich.edu assert(!completed_inst->isSquashed()); 8772101SN/A 8782027SN/A // Tell the memory dependence unit to wake any dependents on this 8792686Sksewell@umich.edu // instruction if it is a memory instruction. Also complete the memory 8802686Sksewell@umich.edu // instruction at this point since we know it executed without issues. 8812686Sksewell@umich.edu // @todo: Might want to rename "completeMemInst" to something that 8822686Sksewell@umich.edu // indicates that it won't need to be replayed, and call this 8832686Sksewell@umich.edu // earlier. Might not be a big deal. 8842686Sksewell@umich.edu if (completed_inst->isMemRef()) { 8852686Sksewell@umich.edu memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 8862686Sksewell@umich.edu completeMemInst(completed_inst); 8872686Sksewell@umich.edu } else if (completed_inst->isMemBarrier() || 8882686Sksewell@umich.edu completed_inst->isWriteBarrier()) { 8892686Sksewell@umich.edu memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 8902686Sksewell@umich.edu } 8912686Sksewell@umich.edu 8922686Sksewell@umich.edu for (int dest_reg_idx = 0; 8932686Sksewell@umich.edu dest_reg_idx < completed_inst->numDestRegs(); 8942686Sksewell@umich.edu dest_reg_idx++) 8952027SN/A { 8962686Sksewell@umich.edu PhysRegIndex dest_reg = 8972686Sksewell@umich.edu completed_inst->renamedDestRegIdx(dest_reg_idx); 8982686Sksewell@umich.edu 8992686Sksewell@umich.edu // Special case of uniq or control registers. They are not 9002686Sksewell@umich.edu // handled by the IQ and thus have no dependency graph entry. 9012686Sksewell@umich.edu // @todo Figure out a cleaner way to handle this. 9022686Sksewell@umich.edu if (dest_reg >= numPhysRegs) { 9032686Sksewell@umich.edu continue; 9042686Sksewell@umich.edu } 9052027SN/A 9062686Sksewell@umich.edu DPRINTF(IQ, "Waking any dependents on register %i.\n", 9072686Sksewell@umich.edu (int) dest_reg); 9082686Sksewell@umich.edu 9092686Sksewell@umich.edu //Go through the dependency chain, marking the registers as 9102686Sksewell@umich.edu //ready within the waiting instructions. 9112686Sksewell@umich.edu DynInstPtr dep_inst = dependGraph.pop(dest_reg); 9122686Sksewell@umich.edu 9132686Sksewell@umich.edu while (dep_inst) { 9142027SN/A DPRINTF(IQ, "Waking up a dependent instruction, PC%#x.\n", 9152686Sksewell@umich.edu dep_inst->readPC()); 9162686Sksewell@umich.edu 9172686Sksewell@umich.edu // Might want to give more information to the instruction 9182686Sksewell@umich.edu // so that it knows which of its source registers is 9192686Sksewell@umich.edu // ready. However that would mean that the dependency 9202686Sksewell@umich.edu // graph entries would need to hold the src_reg_idx. 9212686Sksewell@umich.edu dep_inst->markSrcRegReady(); 9222686Sksewell@umich.edu 9232027SN/A addIfReady(dep_inst); 9242686Sksewell@umich.edu 9252686Sksewell@umich.edu dep_inst = dependGraph.pop(dest_reg); 9262686Sksewell@umich.edu 9272686Sksewell@umich.edu ++dependents; 9282686Sksewell@umich.edu } 9292686Sksewell@umich.edu 9302686Sksewell@umich.edu // Reset the head node now that all of its dependents have 9312046SN/A // been woken up. 9322686Sksewell@umich.edu assert(dependGraph.empty(dest_reg)); 9332101SN/A dependGraph.clearInst(dest_reg); 9342043SN/A 9352025SN/A // Mark the scoreboard as having that register ready. 9362686Sksewell@umich.edu regScoreboard[dest_reg] = true; 9372686Sksewell@umich.edu } 9382686Sksewell@umich.edu return dependents; 9392686Sksewell@umich.edu} 9402686Sksewell@umich.edu 9412046SN/Atemplate <class Impl> 9422084SN/Avoid 9432024SN/AInstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 9442686Sksewell@umich.edu{ 9452043SN/A OpClass op_class = ready_inst->opClass(); 9462043SN/A 9472686Sksewell@umich.edu readyInsts[op_class].push(ready_inst); 9482686Sksewell@umich.edu 9492686Sksewell@umich.edu // Will need to reorder the list if either a queue is not on the list, 9502686Sksewell@umich.edu // or it has an older instruction than last time. 9512027SN/A if (!queueOnList[op_class]) { 9522686Sksewell@umich.edu addToOrderList(op_class); 9532686Sksewell@umich.edu } else if (readyInsts[op_class].top()->seqNum < 9542686Sksewell@umich.edu (*readyIt[op_class]).oldestInst) { 9552686Sksewell@umich.edu listOrder.erase(readyIt[op_class]); 9562686Sksewell@umich.edu addToOrderList(op_class); 9572686Sksewell@umich.edu } 9582686Sksewell@umich.edu 9592686Sksewell@umich.edu DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 9602686Sksewell@umich.edu "the ready list, PC %#x opclass:%i [sn:%lli].\n", 9612686Sksewell@umich.edu ready_inst->readPC(), op_class, ready_inst->seqNum); 9622686Sksewell@umich.edu} 9632686Sksewell@umich.edu 9642686Sksewell@umich.edutemplate <class Impl> 9652043SN/Avoid 9662043SN/AInstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 9672027SN/A{ 9682043SN/A memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 9692101SN/A} 9702686Sksewell@umich.edu 9712686Sksewell@umich.edutemplate <class Impl> 9722686Sksewell@umich.eduvoid 9732686Sksewell@umich.eduInstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 9742686Sksewell@umich.edu{ 9752686Sksewell@umich.edu memDepUnit[replay_inst->threadNumber].replay(replay_inst); 9762686Sksewell@umich.edu} 9772686Sksewell@umich.edu 9782686Sksewell@umich.edutemplate <class Impl> 9792686Sksewell@umich.eduvoid 9802686Sksewell@umich.eduInstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 9812686Sksewell@umich.edu{ 9822686Sksewell@umich.edu int tid = completed_inst->threadNumber; 9832686Sksewell@umich.edu 9842686Sksewell@umich.edu DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n", 9852686Sksewell@umich.edu completed_inst->readPC(), completed_inst->seqNum); 9862686Sksewell@umich.edu 9872686Sksewell@umich.edu ++freeEntries; 9882101SN/A 9892043SN/A completed_inst->memOpDone = true; 9902027SN/A 9912043SN/A memDepUnit[tid].completed(completed_inst); 9922686Sksewell@umich.edu 9932043SN/A count[tid]--; 9942043SN/A} 9952024SN/A 9962686Sksewell@umich.edutemplate <class Impl> 9972686Sksewell@umich.eduvoid 9982043SN/AInstructionQueue<Impl>::violation(DynInstPtr &store, 9992101SN/A DynInstPtr &faulting_load) 10002686Sksewell@umich.edu{ 10012742Sksewell@umich.edu memDepUnit[store->threadNumber].violation(store, faulting_load); 10022686Sksewell@umich.edu} 10032686Sksewell@umich.edu 10042686Sksewell@umich.edutemplate <class Impl> 10052686Sksewell@umich.eduvoid 10062046SN/AInstructionQueue<Impl>::squash(unsigned tid) 10072101SN/A{ 10082026SN/A DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 10092101SN/A "the IQ.\n", tid); 10102686Sksewell@umich.edu 10112084SN/A // Read instruction sequence number of last instruction out of the 10122084SN/A // time buffer. 10132061SN/A squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 10142101SN/A 10152061SN/A // Call doSquash if there are insts in the IQ 10162101SN/A if (count[tid] > 0) { 10172101SN/A doSquash(tid); 10182046SN/A } 10192686Sksewell@umich.edu 10202686Sksewell@umich.edu // Also tell the memory dependence unit to squash. 10212686Sksewell@umich.edu memDepUnit[tid].squash(squashedSeqNum[tid], tid); 10222686Sksewell@umich.edu} 10232686Sksewell@umich.edu 10242742Sksewell@umich.edutemplate <class Impl> 10252742Sksewell@umich.eduvoid 10262046SN/AInstructionQueue<Impl>::doSquash(unsigned tid) 10272101SN/A{ 10282043SN/A // Start at the tail. 10292101SN/A ListIt squash_it = instList[tid].end(); 10302686Sksewell@umich.edu --squash_it; 10312101SN/A 10322043SN/A DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 10332084SN/A tid, squashedSeqNum[tid]); 10342024SN/A 10352686Sksewell@umich.edu // Squash any instructions younger than the squashed sequence number 10362124SN/A // given. 10372239SN/A while (squash_it != instList[tid].end() && 10382239SN/A (*squash_it)->seqNum > squashedSeqNum[tid]) { 10392479SN/A 10402239SN/A DynInstPtr squashed_inst = (*squash_it); 10412239SN/A 10422686Sksewell@umich.edu // Only handle the instruction if it actually is in the IQ and 10432495SN/A // hasn't already been squashed in the IQ. 10442686Sksewell@umich.edu if (squashed_inst->threadNumber != tid || 10452686Sksewell@umich.edu squashed_inst->isSquashedInIQ()) { 10462686Sksewell@umich.edu --squash_it; 10472686Sksewell@umich.edu continue; 10482686Sksewell@umich.edu } 10492686Sksewell@umich.edu 10502686Sksewell@umich.edu if (!squashed_inst->isIssued() || 10512686Sksewell@umich.edu (squashed_inst->isMemRef() && 10522686Sksewell@umich.edu !squashed_inst->memOpDone)) { 10532084SN/A 10542084SN/A // Remove the instruction from the dependency list. 10552024SN/A if (!squashed_inst->isNonSpeculative() && 10562686Sksewell@umich.edu !squashed_inst->isMemBarrier() && 10572124SN/A !squashed_inst->isWriteBarrier()) { 10582124SN/A 10592124SN/A for (int src_reg_idx = 0; 10602479SN/A src_reg_idx < squashed_inst->numSrcRegs(); 10612084SN/A src_reg_idx++) 10622024SN/A { 10632686Sksewell@umich.edu PhysRegIndex src_reg = 10642686Sksewell@umich.edu squashed_inst->renamedSrcRegIdx(src_reg_idx); 10652686Sksewell@umich.edu 10662686Sksewell@umich.edu // Only remove it from the dependency graph if it 10672686Sksewell@umich.edu // was placed there in the first place. 10682686Sksewell@umich.edu 10692686Sksewell@umich.edu // Instead of doing a linked list traversal, we 10702686Sksewell@umich.edu // can just remove these squashed instructions 10712686Sksewell@umich.edu // either at issue time, or when the register is 10722686Sksewell@umich.edu // overwritten. The only downside to this is it 10732084SN/A // leaves more room for error. 10742024SN/A 10752686Sksewell@umich.edu if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 10762084SN/A src_reg < numPhysRegs) { 10772024SN/A dependGraph.remove(src_reg, squashed_inst); 10782686Sksewell@umich.edu } 10792686Sksewell@umich.edu 10802686Sksewell@umich.edu 10812686Sksewell@umich.edu ++iqSquashedOperandsExamined; 10822573SN/A } 10832084SN/A } else { 10842686Sksewell@umich.edu NonSpecMapIt ns_inst_it = 10852686Sksewell@umich.edu nonSpecInsts.find(squashed_inst->seqNum); 10862084SN/A assert(ns_inst_it != nonSpecInsts.end()); 10872024SN/A 10882239SN/A (*ns_inst_it).second = NULL; 10892686Sksewell@umich.edu 10902686Sksewell@umich.edu nonSpecInsts.erase(ns_inst_it); 10912686Sksewell@umich.edu 10922686Sksewell@umich.edu ++iqSquashedNonSpecRemoved; 10932935Sksewell@umich.edu } 10942055SN/A 10952686Sksewell@umich.edu // Might want to also clear out the head of the dependency graph. 10962573SN/A 10972573SN/A // Mark it as squashed within the IQ. 10982084SN/A squashed_inst->setSquashedInIQ(); 10992027SN/A 11002024SN/A // @todo: Remove this hack where several statuses are set so the 11012022SN/A // inst will flow through the rest of the pipeline. 11022027SN/A squashed_inst->setIssued(); 1103 squashed_inst->setCanCommit(); 1104 squashed_inst->removeInIQ(); 1105 1106 //Update Thread IQ Count 1107 count[squashed_inst->threadNumber]--; 1108 1109 ++freeEntries; 1110 1111 DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x " 1112 "squashed.\n", 1113 tid, squashed_inst->seqNum, squashed_inst->readPC()); 1114 } 1115 1116 instList[tid].erase(squash_it--); 1117 ++iqSquashedInstsExamined; 1118 } 1119} 1120 1121template <class Impl> 1122bool 1123InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 1124{ 1125 // Loop through the instruction's source registers, adding 1126 // them to the dependency list if they are not ready. 1127 int8_t total_src_regs = new_inst->numSrcRegs(); 1128 bool return_val = false; 1129 1130 for (int src_reg_idx = 0; 1131 src_reg_idx < total_src_regs; 1132 src_reg_idx++) 1133 { 1134 // Only add it to the dependency graph if it's not ready. 1135 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 1136 PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 1137 1138 // Check the IQ's scoreboard to make sure the register 1139 // hasn't become ready while the instruction was in flight 1140 // between stages. Only if it really isn't ready should 1141 // it be added to the dependency graph. 1142 if (src_reg >= numPhysRegs) { 1143 continue; 1144 } else if (regScoreboard[src_reg] == false) { 1145 DPRINTF(IQ, "Instruction PC %#x has src reg %i that " 1146 "is being added to the dependency chain.\n", 1147 new_inst->readPC(), src_reg); 1148 1149 dependGraph.insert(src_reg, new_inst); 1150 1151 // Change the return value to indicate that something 1152 // was added to the dependency graph. 1153 return_val = true; 1154 } else { 1155 DPRINTF(IQ, "Instruction PC %#x has src reg %i that " 1156 "became ready before it reached the IQ.\n", 1157 new_inst->readPC(), src_reg); 1158 // Mark a register ready within the instruction. 1159 new_inst->markSrcRegReady(src_reg_idx); 1160 } 1161 } 1162 } 1163 1164 return return_val; 1165} 1166 1167template <class Impl> 1168void 1169InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) 1170{ 1171 // Nothing really needs to be marked when an instruction becomes 1172 // the producer of a register's value, but for convenience a ptr 1173 // to the producing instruction will be placed in the head node of 1174 // the dependency links. 1175 int8_t total_dest_regs = new_inst->numDestRegs(); 1176 1177 for (int dest_reg_idx = 0; 1178 dest_reg_idx < total_dest_regs; 1179 dest_reg_idx++) 1180 { 1181 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 1182 1183 // Instructions that use the misc regs will have a reg number 1184 // higher than the normal physical registers. In this case these 1185 // registers are not renamed, and there is no need to track 1186 // dependencies as these instructions must be executed at commit. 1187 if (dest_reg >= numPhysRegs) { 1188 continue; 1189 } 1190 1191 if (!dependGraph.empty(dest_reg)) { 1192 dependGraph.dump(); 1193 panic("Dependency graph %i not empty!", dest_reg); 1194 } 1195 1196 dependGraph.setInst(dest_reg, new_inst); 1197 1198 // Mark the scoreboard to say it's not yet ready. 1199 regScoreboard[dest_reg] = false; 1200 } 1201} 1202 1203template <class Impl> 1204void 1205InstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 1206{ 1207 // If the instruction now has all of its source registers 1208 // available, then add it to the list of ready instructions. 1209 if (inst->readyToIssue()) { 1210 1211 //Add the instruction to the proper ready list. 1212 if (inst->isMemRef()) { 1213 1214 DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 1215 1216 // Message to the mem dependence unit that this instruction has 1217 // its registers ready. 1218 memDepUnit[inst->threadNumber].regsReady(inst); 1219 1220 return; 1221 } 1222 1223 OpClass op_class = inst->opClass(); 1224 1225 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 1226 "the ready list, PC %#x opclass:%i [sn:%lli].\n", 1227 inst->readPC(), op_class, inst->seqNum); 1228 1229 readyInsts[op_class].push(inst); 1230 1231 // Will need to reorder the list if either a queue is not on the list, 1232 // or it has an older instruction than last time. 1233 if (!queueOnList[op_class]) { 1234 addToOrderList(op_class); 1235 } else if (readyInsts[op_class].top()->seqNum < 1236 (*readyIt[op_class]).oldestInst) { 1237 listOrder.erase(readyIt[op_class]); 1238 addToOrderList(op_class); 1239 } 1240 } 1241} 1242 1243template <class Impl> 1244int 1245InstructionQueue<Impl>::countInsts() 1246{ 1247 //ksewell:This works but definitely could use a cleaner write 1248 //with a more intuitive way of counting. Right now it's 1249 //just brute force .... 1250 1251#if 0 1252 int total_insts = 0; 1253 1254 for (int i = 0; i < numThreads; ++i) { 1255 ListIt count_it = instList[i].begin(); 1256 1257 while (count_it != instList[i].end()) { 1258 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 1259 if (!(*count_it)->isIssued()) { 1260 ++total_insts; 1261 } else if ((*count_it)->isMemRef() && 1262 !(*count_it)->memOpDone) { 1263 // Loads that have not been marked as executed still count 1264 // towards the total instructions. 1265 ++total_insts; 1266 } 1267 } 1268 1269 ++count_it; 1270 } 1271 } 1272 1273 return total_insts; 1274#else 1275 return numEntries - freeEntries; 1276#endif 1277} 1278 1279template <class Impl> 1280void 1281InstructionQueue<Impl>::dumpLists() 1282{ 1283 for (int i = 0; i < Num_OpClasses; ++i) { 1284 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 1285 1286 cprintf("\n"); 1287 } 1288 1289 cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 1290 1291 NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 1292 NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 1293 1294 cprintf("Non speculative list: "); 1295 1296 while (non_spec_it != non_spec_end_it) { 1297 cprintf("%#x [sn:%lli]", (*non_spec_it).second->readPC(), 1298 (*non_spec_it).second->seqNum); 1299 ++non_spec_it; 1300 } 1301 1302 cprintf("\n"); 1303 1304 ListOrderIt list_order_it = listOrder.begin(); 1305 ListOrderIt list_order_end_it = listOrder.end(); 1306 int i = 1; 1307 1308 cprintf("List order: "); 1309 1310 while (list_order_it != list_order_end_it) { 1311 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 1312 (*list_order_it).oldestInst); 1313 1314 ++list_order_it; 1315 ++i; 1316 } 1317 1318 cprintf("\n"); 1319} 1320 1321 1322template <class Impl> 1323void 1324InstructionQueue<Impl>::dumpInsts() 1325{ 1326 for (int i = 0; i < numThreads; ++i) { 1327 int num = 0; 1328 int valid_num = 0; 1329 ListIt inst_list_it = instList[i].begin(); 1330 1331 while (inst_list_it != instList[i].end()) 1332 { 1333 cprintf("Instruction:%i\n", 1334 num); 1335 if (!(*inst_list_it)->isSquashed()) { 1336 if (!(*inst_list_it)->isIssued()) { 1337 ++valid_num; 1338 cprintf("Count:%i\n", valid_num); 1339 } else if ((*inst_list_it)->isMemRef() && 1340 !(*inst_list_it)->memOpDone) { 1341 // Loads that have not been marked as executed 1342 // still count towards the total instructions. 1343 ++valid_num; 1344 cprintf("Count:%i\n", valid_num); 1345 } 1346 } 1347 1348 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n" 1349 "Issued:%i\nSquashed:%i\n", 1350 (*inst_list_it)->readPC(), 1351 (*inst_list_it)->seqNum, 1352 (*inst_list_it)->threadNumber, 1353 (*inst_list_it)->isIssued(), 1354 (*inst_list_it)->isSquashed()); 1355 1356 if ((*inst_list_it)->isMemRef()) { 1357 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 1358 } 1359 1360 cprintf("\n"); 1361 1362 inst_list_it++; 1363 ++num; 1364 } 1365 } 1366} 1367