inst_queue_impl.hh revision 9944
112697Santhony.gutierrez@amd.com/* 212697Santhony.gutierrez@amd.com * Copyright (c) 2011-2012 ARM Limited 311308Santhony.gutierrez@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 412697Santhony.gutierrez@amd.com * All rights reserved. 511308Santhony.gutierrez@amd.com * 612697Santhony.gutierrez@amd.com * The license below extends only to copyright in the software and shall 712697Santhony.gutierrez@amd.com * not be construed as granting a license to any other intellectual 811308Santhony.gutierrez@amd.com * property including but not limited to intellectual property relating 912697Santhony.gutierrez@amd.com * to a hardware implementation of the functionality of the software 1012697Santhony.gutierrez@amd.com * licensed hereunder. You may use the software subject to the license 1111308Santhony.gutierrez@amd.com * terms below provided that you ensure that this notice is replicated 1212697Santhony.gutierrez@amd.com * unmodified and in its entirety in all distributions of the software, 1312697Santhony.gutierrez@amd.com * modified or unmodified, in source code or in binary form. 1412697Santhony.gutierrez@amd.com * 1511308Santhony.gutierrez@amd.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 1612697Santhony.gutierrez@amd.com * All rights reserved. 1712697Santhony.gutierrez@amd.com * 1812697Santhony.gutierrez@amd.com * Redistribution and use in source and binary forms, with or without 1911308Santhony.gutierrez@amd.com * modification, are permitted provided that the following conditions are 2012697Santhony.gutierrez@amd.com * met: redistributions of source code must retain the above copyright 2112697Santhony.gutierrez@amd.com * notice, this list of conditions and the following disclaimer; 2212697Santhony.gutierrez@amd.com * redistributions in binary form must reproduce the above copyright 2312697Santhony.gutierrez@amd.com * notice, this list of conditions and the following disclaimer in the 2412697Santhony.gutierrez@amd.com * documentation and/or other materials provided with the distribution; 2512697Santhony.gutierrez@amd.com * neither the name of the copyright holders nor the names of its 2612697Santhony.gutierrez@amd.com * contributors may be used to endorse or promote products derived from 2712697Santhony.gutierrez@amd.com * this software without specific prior written permission. 2812697Santhony.gutierrez@amd.com * 2912697Santhony.gutierrez@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3012697Santhony.gutierrez@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3111308Santhony.gutierrez@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3212697Santhony.gutierrez@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3311308Santhony.gutierrez@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3411308Santhony.gutierrez@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3511308Santhony.gutierrez@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3611308Santhony.gutierrez@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3711308Santhony.gutierrez@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3813400Sodanrc@yahoo.com.br * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3911308Santhony.gutierrez@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4011308Santhony.gutierrez@amd.com * 4111308Santhony.gutierrez@amd.com * Authors: Kevin Lim 4213400Sodanrc@yahoo.com.br * Korey Sewell 4313400Sodanrc@yahoo.com.br */ 4411670Sandreas.hansson@arm.com 4511670Sandreas.hansson@arm.com#ifndef __CPU_O3_INST_QUEUE_IMPL_HH__ 4611308Santhony.gutierrez@amd.com#define __CPU_O3_INST_QUEUE_IMPL_HH__ 4711308Santhony.gutierrez@amd.com 4811308Santhony.gutierrez@amd.com#include <limits> 4911308Santhony.gutierrez@amd.com#include <vector> 5011308Santhony.gutierrez@amd.com 5111308Santhony.gutierrez@amd.com#include "cpu/o3/fu_pool.hh" 5211308Santhony.gutierrez@amd.com#include "cpu/o3/inst_queue.hh" 5311308Santhony.gutierrez@amd.com#include "debug/IQ.hh" 5411308Santhony.gutierrez@amd.com#include "enums/OpClass.hh" 5511308Santhony.gutierrez@amd.com#include "params/DerivO3CPU.hh" 5611308Santhony.gutierrez@amd.com#include "sim/core.hh" 5711308Santhony.gutierrez@amd.com 5811308Santhony.gutierrez@amd.com// clang complains about std::set being overloaded with Packet::set if 5911308Santhony.gutierrez@amd.com// we open up the entire namespace std 6011308Santhony.gutierrez@amd.comusing std::list; 6111308Santhony.gutierrez@amd.com 6211308Santhony.gutierrez@amd.comtemplate <class Impl> 6311308Santhony.gutierrez@amd.comInstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 6411308Santhony.gutierrez@amd.com int fu_idx, InstructionQueue<Impl> *iq_ptr) 6511308Santhony.gutierrez@amd.com : Event(Stat_Event_Pri, AutoDelete), 6611308Santhony.gutierrez@amd.com inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 6711308Santhony.gutierrez@amd.com{ 6811308Santhony.gutierrez@amd.com} 6911308Santhony.gutierrez@amd.com 7011308Santhony.gutierrez@amd.comtemplate <class Impl> 7111308Santhony.gutierrez@amd.comvoid 7211308Santhony.gutierrez@amd.comInstructionQueue<Impl>::FUCompletion::process() 7311308Santhony.gutierrez@amd.com{ 7411308Santhony.gutierrez@amd.com iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 7511308Santhony.gutierrez@amd.com inst = NULL; 7611308Santhony.gutierrez@amd.com} 7711308Santhony.gutierrez@amd.com 7811308Santhony.gutierrez@amd.com 7911308Santhony.gutierrez@amd.comtemplate <class Impl> 8011308Santhony.gutierrez@amd.comconst char * 8111308Santhony.gutierrez@amd.comInstructionQueue<Impl>::FUCompletion::description() const 8211308Santhony.gutierrez@amd.com{ 8311308Santhony.gutierrez@amd.com return "Functional unit completion"; 8411308Santhony.gutierrez@amd.com} 8511308Santhony.gutierrez@amd.com 8611308Santhony.gutierrez@amd.comtemplate <class Impl> 8711308Santhony.gutierrez@amd.comInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 8811308Santhony.gutierrez@amd.com DerivO3CPUParams *params) 8911308Santhony.gutierrez@amd.com : cpu(cpu_ptr), 9011308Santhony.gutierrez@amd.com iewStage(iew_ptr), 9111308Santhony.gutierrez@amd.com fuPool(params->fuPool), 9211308Santhony.gutierrez@amd.com numEntries(params->numIQEntries), 9311308Santhony.gutierrez@amd.com totalWidth(params->issueWidth), 9411308Santhony.gutierrez@amd.com commitToIEWDelay(params->commitToIEWDelay) 9511308Santhony.gutierrez@amd.com{ 9611308Santhony.gutierrez@amd.com assert(fuPool); 9711308Santhony.gutierrez@amd.com 9811308Santhony.gutierrez@amd.com numThreads = params->numThreads; 9911308Santhony.gutierrez@amd.com 10011308Santhony.gutierrez@amd.com // Set the number of total physical registers 10111308Santhony.gutierrez@amd.com numPhysRegs = params->numPhysIntRegs + params->numPhysFloatRegs + 10211308Santhony.gutierrez@amd.com params->numPhysCCRegs; 10311308Santhony.gutierrez@amd.com 10411308Santhony.gutierrez@amd.com //Create an entry for each physical register within the 10511308Santhony.gutierrez@amd.com //dependency graph. 10611308Santhony.gutierrez@amd.com dependGraph.resize(numPhysRegs); 10711308Santhony.gutierrez@amd.com 10811308Santhony.gutierrez@amd.com // Resize the register scoreboard. 10911308Santhony.gutierrez@amd.com regScoreboard.resize(numPhysRegs); 11011308Santhony.gutierrez@amd.com 11111308Santhony.gutierrez@amd.com //Initialize Mem Dependence Units 11211308Santhony.gutierrez@amd.com for (ThreadID tid = 0; tid < numThreads; tid++) { 11311308Santhony.gutierrez@amd.com memDepUnit[tid].init(params, tid); 11411308Santhony.gutierrez@amd.com memDepUnit[tid].setIQ(this); 11511308Santhony.gutierrez@amd.com } 11611308Santhony.gutierrez@amd.com 11711308Santhony.gutierrez@amd.com resetState(); 11811308Santhony.gutierrez@amd.com 11911308Santhony.gutierrez@amd.com std::string policy = params->smtIQPolicy; 12011308Santhony.gutierrez@amd.com 12111308Santhony.gutierrez@amd.com //Convert string to lowercase 12211308Santhony.gutierrez@amd.com std::transform(policy.begin(), policy.end(), policy.begin(), 12311308Santhony.gutierrez@amd.com (int(*)(int)) tolower); 12411308Santhony.gutierrez@amd.com 12511308Santhony.gutierrez@amd.com //Figure out resource sharing policy 12611308Santhony.gutierrez@amd.com if (policy == "dynamic") { 12711308Santhony.gutierrez@amd.com iqPolicy = Dynamic; 12811308Santhony.gutierrez@amd.com 12911308Santhony.gutierrez@amd.com //Set Max Entries to Total ROB Capacity 13011308Santhony.gutierrez@amd.com for (ThreadID tid = 0; tid < numThreads; tid++) { 13111308Santhony.gutierrez@amd.com maxEntries[tid] = numEntries; 13211308Santhony.gutierrez@amd.com } 13311308Santhony.gutierrez@amd.com 13411308Santhony.gutierrez@amd.com } else if (policy == "partitioned") { 13511308Santhony.gutierrez@amd.com iqPolicy = Partitioned; 13611308Santhony.gutierrez@amd.com 13711308Santhony.gutierrez@amd.com //@todo:make work if part_amt doesnt divide evenly. 13811308Santhony.gutierrez@amd.com int part_amt = numEntries / numThreads; 13911308Santhony.gutierrez@amd.com 14011308Santhony.gutierrez@amd.com //Divide ROB up evenly 14111308Santhony.gutierrez@amd.com for (ThreadID tid = 0; tid < numThreads; tid++) { 14211308Santhony.gutierrez@amd.com maxEntries[tid] = part_amt; 14311308Santhony.gutierrez@amd.com } 14411308Santhony.gutierrez@amd.com 14511308Santhony.gutierrez@amd.com DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 14611308Santhony.gutierrez@amd.com "%i entries per thread.\n",part_amt); 14711308Santhony.gutierrez@amd.com } else if (policy == "threshold") { 14811308Santhony.gutierrez@amd.com iqPolicy = Threshold; 14911308Santhony.gutierrez@amd.com 15011308Santhony.gutierrez@amd.com double threshold = (double)params->smtIQThreshold / 100; 15111308Santhony.gutierrez@amd.com 15211308Santhony.gutierrez@amd.com int thresholdIQ = (int)((double)threshold * numEntries); 15311308Santhony.gutierrez@amd.com 15411308Santhony.gutierrez@amd.com //Divide up by threshold amount 15511308Santhony.gutierrez@amd.com for (ThreadID tid = 0; tid < numThreads; tid++) { 15611308Santhony.gutierrez@amd.com maxEntries[tid] = thresholdIQ; 15711308Santhony.gutierrez@amd.com } 15811308Santhony.gutierrez@amd.com 15911308Santhony.gutierrez@amd.com DPRINTF(IQ, "IQ sharing policy set to Threshold:" 16011308Santhony.gutierrez@amd.com "%i entries per thread.\n",thresholdIQ); 16111308Santhony.gutierrez@amd.com } else { 16211308Santhony.gutierrez@amd.com assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 16311308Santhony.gutierrez@amd.com "Partitioned, Threshold}"); 16411308Santhony.gutierrez@amd.com } 16511308Santhony.gutierrez@amd.com} 16611308Santhony.gutierrez@amd.com 16711308Santhony.gutierrez@amd.comtemplate <class Impl> 16811308Santhony.gutierrez@amd.comInstructionQueue<Impl>::~InstructionQueue() 16911308Santhony.gutierrez@amd.com{ 17011308Santhony.gutierrez@amd.com dependGraph.reset(); 17112065Snikos.nikoleris@arm.com#ifdef DEBUG 17211308Santhony.gutierrez@amd.com cprintf("Nodes traversed: %i, removed: %i\n", 17311308Santhony.gutierrez@amd.com dependGraph.nodesTraversed, dependGraph.nodesRemoved); 17411308Santhony.gutierrez@amd.com#endif 17511308Santhony.gutierrez@amd.com} 17612065Snikos.nikoleris@arm.com 17712065Snikos.nikoleris@arm.comtemplate <class Impl> 17811308Santhony.gutierrez@amd.comstd::string 17911308Santhony.gutierrez@amd.comInstructionQueue<Impl>::name() const 18011308Santhony.gutierrez@amd.com{ 18111308Santhony.gutierrez@amd.com return cpu->name() + ".iq"; 18211308Santhony.gutierrez@amd.com} 18311308Santhony.gutierrez@amd.com 18411308Santhony.gutierrez@amd.comtemplate <class Impl> 18511308Santhony.gutierrez@amd.comvoid 18611308Santhony.gutierrez@amd.comInstructionQueue<Impl>::regStats() 18711308Santhony.gutierrez@amd.com{ 18811308Santhony.gutierrez@amd.com using namespace Stats; 18911308Santhony.gutierrez@amd.com iqInstsAdded 19011308Santhony.gutierrez@amd.com .name(name() + ".iqInstsAdded") 19111308Santhony.gutierrez@amd.com .desc("Number of instructions added to the IQ (excludes non-spec)") 19211308Santhony.gutierrez@amd.com .prereq(iqInstsAdded); 19311308Santhony.gutierrez@amd.com 19411308Santhony.gutierrez@amd.com iqNonSpecInstsAdded 19511308Santhony.gutierrez@amd.com .name(name() + ".iqNonSpecInstsAdded") 19611308Santhony.gutierrez@amd.com .desc("Number of non-speculative instructions added to the IQ") 19711308Santhony.gutierrez@amd.com .prereq(iqNonSpecInstsAdded); 19811308Santhony.gutierrez@amd.com 19911308Santhony.gutierrez@amd.com iqInstsIssued 20011308Santhony.gutierrez@amd.com .name(name() + ".iqInstsIssued") 20111308Santhony.gutierrez@amd.com .desc("Number of instructions issued") 20211308Santhony.gutierrez@amd.com .prereq(iqInstsIssued); 20311308Santhony.gutierrez@amd.com 20411308Santhony.gutierrez@amd.com iqIntInstsIssued 20511308Santhony.gutierrez@amd.com .name(name() + ".iqIntInstsIssued") 20611308Santhony.gutierrez@amd.com .desc("Number of integer instructions issued") 20711308Santhony.gutierrez@amd.com .prereq(iqIntInstsIssued); 20811308Santhony.gutierrez@amd.com 20911308Santhony.gutierrez@amd.com iqFloatInstsIssued 21011308Santhony.gutierrez@amd.com .name(name() + ".iqFloatInstsIssued") 21111308Santhony.gutierrez@amd.com .desc("Number of float instructions issued") 21211308Santhony.gutierrez@amd.com .prereq(iqFloatInstsIssued); 21312598Snikos.nikoleris@arm.com 21412598Snikos.nikoleris@arm.com iqBranchInstsIssued 21511308Santhony.gutierrez@amd.com .name(name() + ".iqBranchInstsIssued") 21611308Santhony.gutierrez@amd.com .desc("Number of branch instructions issued") 21711308Santhony.gutierrez@amd.com .prereq(iqBranchInstsIssued); 21811308Santhony.gutierrez@amd.com 21911308Santhony.gutierrez@amd.com iqMemInstsIssued 22011308Santhony.gutierrez@amd.com .name(name() + ".iqMemInstsIssued") 22111308Santhony.gutierrez@amd.com .desc("Number of memory instructions issued") 22211308Santhony.gutierrez@amd.com .prereq(iqMemInstsIssued); 22311308Santhony.gutierrez@amd.com 22411308Santhony.gutierrez@amd.com iqMiscInstsIssued 22511308Santhony.gutierrez@amd.com .name(name() + ".iqMiscInstsIssued") 22611308Santhony.gutierrez@amd.com .desc("Number of miscellaneous instructions issued") 22711308Santhony.gutierrez@amd.com .prereq(iqMiscInstsIssued); 22811308Santhony.gutierrez@amd.com 22911308Santhony.gutierrez@amd.com iqSquashedInstsIssued 23011308Santhony.gutierrez@amd.com .name(name() + ".iqSquashedInstsIssued") 23111308Santhony.gutierrez@amd.com .desc("Number of squashed instructions issued") 23211308Santhony.gutierrez@amd.com .prereq(iqSquashedInstsIssued); 23311308Santhony.gutierrez@amd.com 23411308Santhony.gutierrez@amd.com iqSquashedInstsExamined 23511308Santhony.gutierrez@amd.com .name(name() + ".iqSquashedInstsExamined") 23611308Santhony.gutierrez@amd.com .desc("Number of squashed instructions iterated over during squash;" 23711308Santhony.gutierrez@amd.com " mainly for profiling") 23811308Santhony.gutierrez@amd.com .prereq(iqSquashedInstsExamined); 23911308Santhony.gutierrez@amd.com 24012065Snikos.nikoleris@arm.com iqSquashedOperandsExamined 24112065Snikos.nikoleris@arm.com .name(name() + ".iqSquashedOperandsExamined") 24212065Snikos.nikoleris@arm.com .desc("Number of squashed operands that are examined and possibly " 24312065Snikos.nikoleris@arm.com "removed from graph") 24412065Snikos.nikoleris@arm.com .prereq(iqSquashedOperandsExamined); 24512065Snikos.nikoleris@arm.com 24612065Snikos.nikoleris@arm.com iqSquashedNonSpecRemoved 24712065Snikos.nikoleris@arm.com .name(name() + ".iqSquashedNonSpecRemoved") 24812065Snikos.nikoleris@arm.com .desc("Number of squashed non-spec instructions that were removed") 24912065Snikos.nikoleris@arm.com .prereq(iqSquashedNonSpecRemoved); 25012065Snikos.nikoleris@arm.com/* 25111308Santhony.gutierrez@amd.com queueResDist 25212065Snikos.nikoleris@arm.com .init(Num_OpClasses, 0, 99, 2) 25312065Snikos.nikoleris@arm.com .name(name() + ".IQ:residence:") 25412065Snikos.nikoleris@arm.com .desc("cycles from dispatch to issue") 25512065Snikos.nikoleris@arm.com .flags(total | pdf | cdf ) 25612065Snikos.nikoleris@arm.com ; 25712065Snikos.nikoleris@arm.com for (int i = 0; i < Num_OpClasses; ++i) { 25812065Snikos.nikoleris@arm.com queueResDist.subname(i, opClassStrings[i]); 25912065Snikos.nikoleris@arm.com } 26011308Santhony.gutierrez@amd.com*/ 26111308Santhony.gutierrez@amd.com numIssuedDist 26212065Snikos.nikoleris@arm.com .init(0,totalWidth,1) 26311308Santhony.gutierrez@amd.com .name(name() + ".issued_per_cycle") 26411308Santhony.gutierrez@amd.com .desc("Number of insts issued each cycle") 26511308Santhony.gutierrez@amd.com .flags(pdf) 26611308Santhony.gutierrez@amd.com ; 26711308Santhony.gutierrez@amd.com/* 26811308Santhony.gutierrez@amd.com dist_unissued 26911308Santhony.gutierrez@amd.com .init(Num_OpClasses+2) 27011308Santhony.gutierrez@amd.com .name(name() + ".unissued_cause") 27111308Santhony.gutierrez@amd.com .desc("Reason ready instruction not issued") 27211308Santhony.gutierrez@amd.com .flags(pdf | dist) 27311308Santhony.gutierrez@amd.com ; 27411308Santhony.gutierrez@amd.com for (int i=0; i < (Num_OpClasses + 2); ++i) { 27511308Santhony.gutierrez@amd.com dist_unissued.subname(i, unissued_names[i]); 27611308Santhony.gutierrez@amd.com } 27711308Santhony.gutierrez@amd.com*/ 27811308Santhony.gutierrez@amd.com statIssuedInstType 27911308Santhony.gutierrez@amd.com .init(numThreads,Enums::Num_OpClass) 28011308Santhony.gutierrez@amd.com .name(name() + ".FU_type") 28111308Santhony.gutierrez@amd.com .desc("Type of FU issued") 28211308Santhony.gutierrez@amd.com .flags(total | pdf | dist) 28311308Santhony.gutierrez@amd.com ; 28411308Santhony.gutierrez@amd.com statIssuedInstType.ysubnames(Enums::OpClassStrings); 28511308Santhony.gutierrez@amd.com 28611308Santhony.gutierrez@amd.com // 28711308Santhony.gutierrez@amd.com // How long did instructions for a particular FU type wait prior to issue 28811308Santhony.gutierrez@amd.com // 28911308Santhony.gutierrez@amd.com/* 29011308Santhony.gutierrez@amd.com issueDelayDist 29111308Santhony.gutierrez@amd.com .init(Num_OpClasses,0,99,2) 29211308Santhony.gutierrez@amd.com .name(name() + ".") 29311308Santhony.gutierrez@amd.com .desc("cycles from operands ready to issue") 29411308Santhony.gutierrez@amd.com .flags(pdf | cdf) 29511308Santhony.gutierrez@amd.com ; 29611308Santhony.gutierrez@amd.com 29711308Santhony.gutierrez@amd.com for (int i=0; i<Num_OpClasses; ++i) { 29811308Santhony.gutierrez@amd.com std::stringstream subname; 29911308Santhony.gutierrez@amd.com subname << opClassStrings[i] << "_delay"; 30011308Santhony.gutierrez@amd.com issueDelayDist.subname(i, subname.str()); 30111308Santhony.gutierrez@amd.com } 30211308Santhony.gutierrez@amd.com*/ 30311308Santhony.gutierrez@amd.com issueRate 30411308Santhony.gutierrez@amd.com .name(name() + ".rate") 30511308Santhony.gutierrez@amd.com .desc("Inst issue rate") 30611308Santhony.gutierrez@amd.com .flags(total) 30711308Santhony.gutierrez@amd.com ; 30811308Santhony.gutierrez@amd.com issueRate = iqInstsIssued / cpu->numCycles; 30911308Santhony.gutierrez@amd.com 31011308Santhony.gutierrez@amd.com statFuBusy 31111308Santhony.gutierrez@amd.com .init(Num_OpClasses) 31211308Santhony.gutierrez@amd.com .name(name() + ".fu_full") 31311308Santhony.gutierrez@amd.com .desc("attempts to use FU when none available") 31411308Santhony.gutierrez@amd.com .flags(pdf | dist) 31511308Santhony.gutierrez@amd.com ; 31611308Santhony.gutierrez@amd.com for (int i=0; i < Num_OpClasses; ++i) { 31711308Santhony.gutierrez@amd.com statFuBusy.subname(i, Enums::OpClassStrings[i]); 31811308Santhony.gutierrez@amd.com } 31911308Santhony.gutierrez@amd.com 32011308Santhony.gutierrez@amd.com fuBusy 32111308Santhony.gutierrez@amd.com .init(numThreads) 32211308Santhony.gutierrez@amd.com .name(name() + ".fu_busy_cnt") 32311308Santhony.gutierrez@amd.com .desc("FU busy when requested") 32411308Santhony.gutierrez@amd.com .flags(total) 32511308Santhony.gutierrez@amd.com ; 32611308Santhony.gutierrez@amd.com 32711308Santhony.gutierrez@amd.com fuBusyRate 32811308Santhony.gutierrez@amd.com .name(name() + ".fu_busy_rate") 32911308Santhony.gutierrez@amd.com .desc("FU busy rate (busy events/executed inst)") 33011308Santhony.gutierrez@amd.com .flags(total) 33111308Santhony.gutierrez@amd.com ; 33211308Santhony.gutierrez@amd.com fuBusyRate = fuBusy / iqInstsIssued; 33311308Santhony.gutierrez@amd.com 33411308Santhony.gutierrez@amd.com for (ThreadID tid = 0; tid < numThreads; tid++) { 33511308Santhony.gutierrez@amd.com // Tell mem dependence unit to reg stats as well. 33611308Santhony.gutierrez@amd.com memDepUnit[tid].regStats(); 33711308Santhony.gutierrez@amd.com } 338 339 intInstQueueReads 340 .name(name() + ".int_inst_queue_reads") 341 .desc("Number of integer instruction queue reads") 342 .flags(total); 343 344 intInstQueueWrites 345 .name(name() + ".int_inst_queue_writes") 346 .desc("Number of integer instruction queue writes") 347 .flags(total); 348 349 intInstQueueWakeupAccesses 350 .name(name() + ".int_inst_queue_wakeup_accesses") 351 .desc("Number of integer instruction queue wakeup accesses") 352 .flags(total); 353 354 fpInstQueueReads 355 .name(name() + ".fp_inst_queue_reads") 356 .desc("Number of floating instruction queue reads") 357 .flags(total); 358 359 fpInstQueueWrites 360 .name(name() + ".fp_inst_queue_writes") 361 .desc("Number of floating instruction queue writes") 362 .flags(total); 363 364 fpInstQueueWakeupQccesses 365 .name(name() + ".fp_inst_queue_wakeup_accesses") 366 .desc("Number of floating instruction queue wakeup accesses") 367 .flags(total); 368 369 intAluAccesses 370 .name(name() + ".int_alu_accesses") 371 .desc("Number of integer alu accesses") 372 .flags(total); 373 374 fpAluAccesses 375 .name(name() + ".fp_alu_accesses") 376 .desc("Number of floating point alu accesses") 377 .flags(total); 378 379} 380 381template <class Impl> 382void 383InstructionQueue<Impl>::resetState() 384{ 385 //Initialize thread IQ counts 386 for (ThreadID tid = 0; tid <numThreads; tid++) { 387 count[tid] = 0; 388 instList[tid].clear(); 389 } 390 391 // Initialize the number of free IQ entries. 392 freeEntries = numEntries; 393 394 // Note that in actuality, the registers corresponding to the logical 395 // registers start off as ready. However this doesn't matter for the 396 // IQ as the instruction should have been correctly told if those 397 // registers are ready in rename. Thus it can all be initialized as 398 // unready. 399 for (int i = 0; i < numPhysRegs; ++i) { 400 regScoreboard[i] = false; 401 } 402 403 for (ThreadID tid = 0; tid < numThreads; ++tid) { 404 squashedSeqNum[tid] = 0; 405 } 406 407 for (int i = 0; i < Num_OpClasses; ++i) { 408 while (!readyInsts[i].empty()) 409 readyInsts[i].pop(); 410 queueOnList[i] = false; 411 readyIt[i] = listOrder.end(); 412 } 413 nonSpecInsts.clear(); 414 listOrder.clear(); 415 deferredMemInsts.clear(); 416} 417 418template <class Impl> 419void 420InstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 421{ 422 activeThreads = at_ptr; 423} 424 425template <class Impl> 426void 427InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 428{ 429 issueToExecuteQueue = i2e_ptr; 430} 431 432template <class Impl> 433void 434InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 435{ 436 timeBuffer = tb_ptr; 437 438 fromCommit = timeBuffer->getWire(-commitToIEWDelay); 439} 440 441template <class Impl> 442void 443InstructionQueue<Impl>::drainSanityCheck() const 444{ 445 assert(dependGraph.empty()); 446 assert(instsToExecute.empty()); 447 for (ThreadID tid = 0; tid < numThreads; ++tid) 448 memDepUnit[tid].drainSanityCheck(); 449} 450 451template <class Impl> 452void 453InstructionQueue<Impl>::takeOverFrom() 454{ 455 resetState(); 456} 457 458template <class Impl> 459int 460InstructionQueue<Impl>::entryAmount(ThreadID num_threads) 461{ 462 if (iqPolicy == Partitioned) { 463 return numEntries / num_threads; 464 } else { 465 return 0; 466 } 467} 468 469 470template <class Impl> 471void 472InstructionQueue<Impl>::resetEntries() 473{ 474 if (iqPolicy != Dynamic || numThreads > 1) { 475 int active_threads = activeThreads->size(); 476 477 list<ThreadID>::iterator threads = activeThreads->begin(); 478 list<ThreadID>::iterator end = activeThreads->end(); 479 480 while (threads != end) { 481 ThreadID tid = *threads++; 482 483 if (iqPolicy == Partitioned) { 484 maxEntries[tid] = numEntries / active_threads; 485 } else if(iqPolicy == Threshold && active_threads == 1) { 486 maxEntries[tid] = numEntries; 487 } 488 } 489 } 490} 491 492template <class Impl> 493unsigned 494InstructionQueue<Impl>::numFreeEntries() 495{ 496 return freeEntries; 497} 498 499template <class Impl> 500unsigned 501InstructionQueue<Impl>::numFreeEntries(ThreadID tid) 502{ 503 return maxEntries[tid] - count[tid]; 504} 505 506// Might want to do something more complex if it knows how many instructions 507// will be issued this cycle. 508template <class Impl> 509bool 510InstructionQueue<Impl>::isFull() 511{ 512 if (freeEntries == 0) { 513 return(true); 514 } else { 515 return(false); 516 } 517} 518 519template <class Impl> 520bool 521InstructionQueue<Impl>::isFull(ThreadID tid) 522{ 523 if (numFreeEntries(tid) == 0) { 524 return(true); 525 } else { 526 return(false); 527 } 528} 529 530template <class Impl> 531bool 532InstructionQueue<Impl>::hasReadyInsts() 533{ 534 if (!listOrder.empty()) { 535 return true; 536 } 537 538 for (int i = 0; i < Num_OpClasses; ++i) { 539 if (!readyInsts[i].empty()) { 540 return true; 541 } 542 } 543 544 return false; 545} 546 547template <class Impl> 548void 549InstructionQueue<Impl>::insert(DynInstPtr &new_inst) 550{ 551 new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 552 // Make sure the instruction is valid 553 assert(new_inst); 554 555 DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n", 556 new_inst->seqNum, new_inst->pcState()); 557 558 assert(freeEntries != 0); 559 560 instList[new_inst->threadNumber].push_back(new_inst); 561 562 --freeEntries; 563 564 new_inst->setInIQ(); 565 566 // Look through its source registers (physical regs), and mark any 567 // dependencies. 568 addToDependents(new_inst); 569 570 // Have this instruction set itself as the producer of its destination 571 // register(s). 572 addToProducers(new_inst); 573 574 if (new_inst->isMemRef()) { 575 memDepUnit[new_inst->threadNumber].insert(new_inst); 576 } else { 577 addIfReady(new_inst); 578 } 579 580 ++iqInstsAdded; 581 582 count[new_inst->threadNumber]++; 583 584 assert(freeEntries == (numEntries - countInsts())); 585} 586 587template <class Impl> 588void 589InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) 590{ 591 // @todo: Clean up this code; can do it by setting inst as unable 592 // to issue, then calling normal insert on the inst. 593 new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 594 595 assert(new_inst); 596 597 nonSpecInsts[new_inst->seqNum] = new_inst; 598 599 DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s " 600 "to the IQ.\n", 601 new_inst->seqNum, new_inst->pcState()); 602 603 assert(freeEntries != 0); 604 605 instList[new_inst->threadNumber].push_back(new_inst); 606 607 --freeEntries; 608 609 new_inst->setInIQ(); 610 611 // Have this instruction set itself as the producer of its destination 612 // register(s). 613 addToProducers(new_inst); 614 615 // If it's a memory instruction, add it to the memory dependency 616 // unit. 617 if (new_inst->isMemRef()) { 618 memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 619 } 620 621 ++iqNonSpecInstsAdded; 622 623 count[new_inst->threadNumber]++; 624 625 assert(freeEntries == (numEntries - countInsts())); 626} 627 628template <class Impl> 629void 630InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) 631{ 632 memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 633 634 insertNonSpec(barr_inst); 635} 636 637template <class Impl> 638typename Impl::DynInstPtr 639InstructionQueue<Impl>::getInstToExecute() 640{ 641 assert(!instsToExecute.empty()); 642 DynInstPtr inst = instsToExecute.front(); 643 instsToExecute.pop_front(); 644 if (inst->isFloating()){ 645 fpInstQueueReads++; 646 } else { 647 intInstQueueReads++; 648 } 649 return inst; 650} 651 652template <class Impl> 653void 654InstructionQueue<Impl>::addToOrderList(OpClass op_class) 655{ 656 assert(!readyInsts[op_class].empty()); 657 658 ListOrderEntry queue_entry; 659 660 queue_entry.queueType = op_class; 661 662 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 663 664 ListOrderIt list_it = listOrder.begin(); 665 ListOrderIt list_end_it = listOrder.end(); 666 667 while (list_it != list_end_it) { 668 if ((*list_it).oldestInst > queue_entry.oldestInst) { 669 break; 670 } 671 672 list_it++; 673 } 674 675 readyIt[op_class] = listOrder.insert(list_it, queue_entry); 676 queueOnList[op_class] = true; 677} 678 679template <class Impl> 680void 681InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 682{ 683 // Get iterator of next item on the list 684 // Delete the original iterator 685 // Determine if the next item is either the end of the list or younger 686 // than the new instruction. If so, then add in a new iterator right here. 687 // If not, then move along. 688 ListOrderEntry queue_entry; 689 OpClass op_class = (*list_order_it).queueType; 690 ListOrderIt next_it = list_order_it; 691 692 ++next_it; 693 694 queue_entry.queueType = op_class; 695 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 696 697 while (next_it != listOrder.end() && 698 (*next_it).oldestInst < queue_entry.oldestInst) { 699 ++next_it; 700 } 701 702 readyIt[op_class] = listOrder.insert(next_it, queue_entry); 703} 704 705template <class Impl> 706void 707InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 708{ 709 DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 710 assert(!cpu->switchedOut()); 711 // The CPU could have been sleeping until this op completed (*extremely* 712 // long latency op). Wake it if it was. This may be overkill. 713 iewStage->wakeCPU(); 714 715 if (fu_idx > -1) 716 fuPool->freeUnitNextCycle(fu_idx); 717 718 // @todo: Ensure that these FU Completions happen at the beginning 719 // of a cycle, otherwise they could add too many instructions to 720 // the queue. 721 issueToExecuteQueue->access(-1)->size++; 722 instsToExecute.push_back(inst); 723} 724 725// @todo: Figure out a better way to remove the squashed items from the 726// lists. Checking the top item of each list to see if it's squashed 727// wastes time and forces jumps. 728template <class Impl> 729void 730InstructionQueue<Impl>::scheduleReadyInsts() 731{ 732 DPRINTF(IQ, "Attempting to schedule ready instructions from " 733 "the IQ.\n"); 734 735 IssueStruct *i2e_info = issueToExecuteQueue->access(0); 736 737 DynInstPtr deferred_mem_inst; 738 int total_deferred_mem_issued = 0; 739 while (total_deferred_mem_issued < totalWidth && 740 (deferred_mem_inst = getDeferredMemInstToExecute()) != 0) { 741 issueToExecuteQueue->access(0)->size++; 742 instsToExecute.push_back(deferred_mem_inst); 743 total_deferred_mem_issued++; 744 } 745 746 // Have iterator to head of the list 747 // While I haven't exceeded bandwidth or reached the end of the list, 748 // Try to get a FU that can do what this op needs. 749 // If successful, change the oldestInst to the new top of the list, put 750 // the queue in the proper place in the list. 751 // Increment the iterator. 752 // This will avoid trying to schedule a certain op class if there are no 753 // FUs that handle it. 754 ListOrderIt order_it = listOrder.begin(); 755 ListOrderIt order_end_it = listOrder.end(); 756 int total_issued = 0; 757 758 while (total_issued < (totalWidth - total_deferred_mem_issued) && 759 iewStage->canIssue() && 760 order_it != order_end_it) { 761 OpClass op_class = (*order_it).queueType; 762 763 assert(!readyInsts[op_class].empty()); 764 765 DynInstPtr issuing_inst = readyInsts[op_class].top(); 766 767 issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++; 768 769 assert(issuing_inst->seqNum == (*order_it).oldestInst); 770 771 if (issuing_inst->isSquashed()) { 772 readyInsts[op_class].pop(); 773 774 if (!readyInsts[op_class].empty()) { 775 moveToYoungerInst(order_it); 776 } else { 777 readyIt[op_class] = listOrder.end(); 778 queueOnList[op_class] = false; 779 } 780 781 listOrder.erase(order_it++); 782 783 ++iqSquashedInstsIssued; 784 785 continue; 786 } 787 788 int idx = -2; 789 Cycles op_latency = Cycles(1); 790 ThreadID tid = issuing_inst->threadNumber; 791 792 if (op_class != No_OpClass) { 793 idx = fuPool->getUnit(op_class); 794 issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++; 795 if (idx > -1) { 796 op_latency = fuPool->getOpLatency(op_class); 797 } 798 } 799 800 // If we have an instruction that doesn't require a FU, or a 801 // valid FU, then schedule for execution. 802 if (idx == -2 || idx != -1) { 803 if (op_latency == Cycles(1)) { 804 i2e_info->size++; 805 instsToExecute.push_back(issuing_inst); 806 807 // Add the FU onto the list of FU's to be freed next 808 // cycle if we used one. 809 if (idx >= 0) 810 fuPool->freeUnitNextCycle(idx); 811 } else { 812 Cycles issue_latency = fuPool->getIssueLatency(op_class); 813 // Generate completion event for the FU 814 FUCompletion *execution = new FUCompletion(issuing_inst, 815 idx, this); 816 817 cpu->schedule(execution, 818 cpu->clockEdge(Cycles(op_latency - 1))); 819 820 // @todo: Enforce that issue_latency == 1 or op_latency 821 if (issue_latency > Cycles(1)) { 822 // If FU isn't pipelined, then it must be freed 823 // upon the execution completing. 824 execution->setFreeFU(); 825 } else { 826 // Add the FU onto the list of FU's to be freed next cycle. 827 fuPool->freeUnitNextCycle(idx); 828 } 829 } 830 831 DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 832 "[sn:%lli]\n", 833 tid, issuing_inst->pcState(), 834 issuing_inst->seqNum); 835 836 readyInsts[op_class].pop(); 837 838 if (!readyInsts[op_class].empty()) { 839 moveToYoungerInst(order_it); 840 } else { 841 readyIt[op_class] = listOrder.end(); 842 queueOnList[op_class] = false; 843 } 844 845 issuing_inst->setIssued(); 846 ++total_issued; 847 848#if TRACING_ON 849 issuing_inst->issueTick = curTick() - issuing_inst->fetchTick; 850#endif 851 852 if (!issuing_inst->isMemRef()) { 853 // Memory instructions can not be freed from the IQ until they 854 // complete. 855 ++freeEntries; 856 count[tid]--; 857 issuing_inst->clearInIQ(); 858 } else { 859 memDepUnit[tid].issue(issuing_inst); 860 } 861 862 listOrder.erase(order_it++); 863 statIssuedInstType[tid][op_class]++; 864 iewStage->incrWb(issuing_inst->seqNum); 865 } else { 866 statFuBusy[op_class]++; 867 fuBusy[tid]++; 868 ++order_it; 869 } 870 } 871 872 numIssuedDist.sample(total_issued); 873 iqInstsIssued+= total_issued; 874 875 // If we issued any instructions, tell the CPU we had activity. 876 // @todo If the way deferred memory instructions are handeled due to 877 // translation changes then the deferredMemInsts condition should be removed 878 // from the code below. 879 if (total_issued || total_deferred_mem_issued || deferredMemInsts.size()) { 880 cpu->activityThisCycle(); 881 } else { 882 DPRINTF(IQ, "Not able to schedule any instructions.\n"); 883 } 884} 885 886template <class Impl> 887void 888InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 889{ 890 DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 891 "to execute.\n", inst); 892 893 NonSpecMapIt inst_it = nonSpecInsts.find(inst); 894 895 assert(inst_it != nonSpecInsts.end()); 896 897 ThreadID tid = (*inst_it).second->threadNumber; 898 899 (*inst_it).second->setAtCommit(); 900 901 (*inst_it).second->setCanIssue(); 902 903 if (!(*inst_it).second->isMemRef()) { 904 addIfReady((*inst_it).second); 905 } else { 906 memDepUnit[tid].nonSpecInstReady((*inst_it).second); 907 } 908 909 (*inst_it).second = NULL; 910 911 nonSpecInsts.erase(inst_it); 912} 913 914template <class Impl> 915void 916InstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 917{ 918 DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 919 tid,inst); 920 921 ListIt iq_it = instList[tid].begin(); 922 923 while (iq_it != instList[tid].end() && 924 (*iq_it)->seqNum <= inst) { 925 ++iq_it; 926 instList[tid].pop_front(); 927 } 928 929 assert(freeEntries == (numEntries - countInsts())); 930} 931 932template <class Impl> 933int 934InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 935{ 936 int dependents = 0; 937 938 // The instruction queue here takes care of both floating and int ops 939 if (completed_inst->isFloating()) { 940 fpInstQueueWakeupQccesses++; 941 } else { 942 intInstQueueWakeupAccesses++; 943 } 944 945 DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 946 947 assert(!completed_inst->isSquashed()); 948 949 // Tell the memory dependence unit to wake any dependents on this 950 // instruction if it is a memory instruction. Also complete the memory 951 // instruction at this point since we know it executed without issues. 952 // @todo: Might want to rename "completeMemInst" to something that 953 // indicates that it won't need to be replayed, and call this 954 // earlier. Might not be a big deal. 955 if (completed_inst->isMemRef()) { 956 memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 957 completeMemInst(completed_inst); 958 } else if (completed_inst->isMemBarrier() || 959 completed_inst->isWriteBarrier()) { 960 memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 961 } 962 963 for (int dest_reg_idx = 0; 964 dest_reg_idx < completed_inst->numDestRegs(); 965 dest_reg_idx++) 966 { 967 PhysRegIndex dest_reg = 968 completed_inst->renamedDestRegIdx(dest_reg_idx); 969 970 // Special case of uniq or control registers. They are not 971 // handled by the IQ and thus have no dependency graph entry. 972 // @todo Figure out a cleaner way to handle this. 973 if (dest_reg >= numPhysRegs) { 974 DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg, 975 numPhysRegs); 976 continue; 977 } 978 979 DPRINTF(IQ, "Waking any dependents on register %i.\n", 980 (int) dest_reg); 981 982 //Go through the dependency chain, marking the registers as 983 //ready within the waiting instructions. 984 DynInstPtr dep_inst = dependGraph.pop(dest_reg); 985 986 while (dep_inst) { 987 DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] " 988 "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 989 990 // Might want to give more information to the instruction 991 // so that it knows which of its source registers is 992 // ready. However that would mean that the dependency 993 // graph entries would need to hold the src_reg_idx. 994 dep_inst->markSrcRegReady(); 995 996 addIfReady(dep_inst); 997 998 dep_inst = dependGraph.pop(dest_reg); 999 1000 ++dependents; 1001 } 1002 1003 // Reset the head node now that all of its dependents have 1004 // been woken up. 1005 assert(dependGraph.empty(dest_reg)); 1006 dependGraph.clearInst(dest_reg); 1007 1008 // Mark the scoreboard as having that register ready. 1009 regScoreboard[dest_reg] = true; 1010 } 1011 return dependents; 1012} 1013 1014template <class Impl> 1015void 1016InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 1017{ 1018 OpClass op_class = ready_inst->opClass(); 1019 1020 readyInsts[op_class].push(ready_inst); 1021 1022 // Will need to reorder the list if either a queue is not on the list, 1023 // or it has an older instruction than last time. 1024 if (!queueOnList[op_class]) { 1025 addToOrderList(op_class); 1026 } else if (readyInsts[op_class].top()->seqNum < 1027 (*readyIt[op_class]).oldestInst) { 1028 listOrder.erase(readyIt[op_class]); 1029 addToOrderList(op_class); 1030 } 1031 1032 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 1033 "the ready list, PC %s opclass:%i [sn:%lli].\n", 1034 ready_inst->pcState(), op_class, ready_inst->seqNum); 1035} 1036 1037template <class Impl> 1038void 1039InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 1040{ 1041 DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 1042 1043 // Reset DTB translation state 1044 resched_inst->translationStarted(false); 1045 resched_inst->translationCompleted(false); 1046 1047 resched_inst->clearCanIssue(); 1048 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 1049} 1050 1051template <class Impl> 1052void 1053InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 1054{ 1055 memDepUnit[replay_inst->threadNumber].replay(replay_inst); 1056} 1057 1058template <class Impl> 1059void 1060InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 1061{ 1062 ThreadID tid = completed_inst->threadNumber; 1063 1064 DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n", 1065 completed_inst->pcState(), completed_inst->seqNum); 1066 1067 ++freeEntries; 1068 1069 completed_inst->memOpDone(true); 1070 1071 memDepUnit[tid].completed(completed_inst); 1072 count[tid]--; 1073} 1074 1075template <class Impl> 1076void 1077InstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst) 1078{ 1079 deferredMemInsts.push_back(deferred_inst); 1080} 1081 1082template <class Impl> 1083typename Impl::DynInstPtr 1084InstructionQueue<Impl>::getDeferredMemInstToExecute() 1085{ 1086 for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); 1087 ++it) { 1088 if ((*it)->translationCompleted() || (*it)->isSquashed()) { 1089 DynInstPtr ret = *it; 1090 deferredMemInsts.erase(it); 1091 return ret; 1092 } 1093 } 1094 return NULL; 1095} 1096 1097template <class Impl> 1098void 1099InstructionQueue<Impl>::violation(DynInstPtr &store, 1100 DynInstPtr &faulting_load) 1101{ 1102 intInstQueueWrites++; 1103 memDepUnit[store->threadNumber].violation(store, faulting_load); 1104} 1105 1106template <class Impl> 1107void 1108InstructionQueue<Impl>::squash(ThreadID tid) 1109{ 1110 DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 1111 "the IQ.\n", tid); 1112 1113 // Read instruction sequence number of last instruction out of the 1114 // time buffer. 1115 squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 1116 1117 // Call doSquash if there are insts in the IQ 1118 if (count[tid] > 0) { 1119 doSquash(tid); 1120 } 1121 1122 // Also tell the memory dependence unit to squash. 1123 memDepUnit[tid].squash(squashedSeqNum[tid], tid); 1124} 1125 1126template <class Impl> 1127void 1128InstructionQueue<Impl>::doSquash(ThreadID tid) 1129{ 1130 // Start at the tail. 1131 ListIt squash_it = instList[tid].end(); 1132 --squash_it; 1133 1134 DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 1135 tid, squashedSeqNum[tid]); 1136 1137 // Squash any instructions younger than the squashed sequence number 1138 // given. 1139 while (squash_it != instList[tid].end() && 1140 (*squash_it)->seqNum > squashedSeqNum[tid]) { 1141 1142 DynInstPtr squashed_inst = (*squash_it); 1143 squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 1144 1145 // Only handle the instruction if it actually is in the IQ and 1146 // hasn't already been squashed in the IQ. 1147 if (squashed_inst->threadNumber != tid || 1148 squashed_inst->isSquashedInIQ()) { 1149 --squash_it; 1150 continue; 1151 } 1152 1153 if (!squashed_inst->isIssued() || 1154 (squashed_inst->isMemRef() && 1155 !squashed_inst->memOpDone())) { 1156 1157 DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", 1158 tid, squashed_inst->seqNum, squashed_inst->pcState()); 1159 1160 // Remove the instruction from the dependency list. 1161 if (!squashed_inst->isNonSpeculative() && 1162 !squashed_inst->isStoreConditional() && 1163 !squashed_inst->isMemBarrier() && 1164 !squashed_inst->isWriteBarrier()) { 1165 1166 for (int src_reg_idx = 0; 1167 src_reg_idx < squashed_inst->numSrcRegs(); 1168 src_reg_idx++) 1169 { 1170 PhysRegIndex src_reg = 1171 squashed_inst->renamedSrcRegIdx(src_reg_idx); 1172 1173 // Only remove it from the dependency graph if it 1174 // was placed there in the first place. 1175 1176 // Instead of doing a linked list traversal, we 1177 // can just remove these squashed instructions 1178 // either at issue time, or when the register is 1179 // overwritten. The only downside to this is it 1180 // leaves more room for error. 1181 1182 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 1183 src_reg < numPhysRegs) { 1184 dependGraph.remove(src_reg, squashed_inst); 1185 } 1186 1187 1188 ++iqSquashedOperandsExamined; 1189 } 1190 } else if (!squashed_inst->isStoreConditional() || 1191 !squashed_inst->isCompleted()) { 1192 NonSpecMapIt ns_inst_it = 1193 nonSpecInsts.find(squashed_inst->seqNum); 1194 1195 if (ns_inst_it == nonSpecInsts.end()) { 1196 assert(squashed_inst->getFault() != NoFault); 1197 } else { 1198 1199 (*ns_inst_it).second = NULL; 1200 1201 nonSpecInsts.erase(ns_inst_it); 1202 1203 ++iqSquashedNonSpecRemoved; 1204 } 1205 } 1206 1207 // Might want to also clear out the head of the dependency graph. 1208 1209 // Mark it as squashed within the IQ. 1210 squashed_inst->setSquashedInIQ(); 1211 1212 // @todo: Remove this hack where several statuses are set so the 1213 // inst will flow through the rest of the pipeline. 1214 squashed_inst->setIssued(); 1215 squashed_inst->setCanCommit(); 1216 squashed_inst->clearInIQ(); 1217 1218 //Update Thread IQ Count 1219 count[squashed_inst->threadNumber]--; 1220 1221 ++freeEntries; 1222 } 1223 1224 instList[tid].erase(squash_it--); 1225 ++iqSquashedInstsExamined; 1226 } 1227} 1228 1229template <class Impl> 1230bool 1231InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 1232{ 1233 // Loop through the instruction's source registers, adding 1234 // them to the dependency list if they are not ready. 1235 int8_t total_src_regs = new_inst->numSrcRegs(); 1236 bool return_val = false; 1237 1238 for (int src_reg_idx = 0; 1239 src_reg_idx < total_src_regs; 1240 src_reg_idx++) 1241 { 1242 // Only add it to the dependency graph if it's not ready. 1243 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 1244 PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 1245 1246 // Check the IQ's scoreboard to make sure the register 1247 // hasn't become ready while the instruction was in flight 1248 // between stages. Only if it really isn't ready should 1249 // it be added to the dependency graph. 1250 if (src_reg >= numPhysRegs) { 1251 continue; 1252 } else if (regScoreboard[src_reg] == false) { 1253 DPRINTF(IQ, "Instruction PC %s has src reg %i that " 1254 "is being added to the dependency chain.\n", 1255 new_inst->pcState(), src_reg); 1256 1257 dependGraph.insert(src_reg, new_inst); 1258 1259 // Change the return value to indicate that something 1260 // was added to the dependency graph. 1261 return_val = true; 1262 } else { 1263 DPRINTF(IQ, "Instruction PC %s has src reg %i that " 1264 "became ready before it reached the IQ.\n", 1265 new_inst->pcState(), src_reg); 1266 // Mark a register ready within the instruction. 1267 new_inst->markSrcRegReady(src_reg_idx); 1268 } 1269 } 1270 } 1271 1272 return return_val; 1273} 1274 1275template <class Impl> 1276void 1277InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) 1278{ 1279 // Nothing really needs to be marked when an instruction becomes 1280 // the producer of a register's value, but for convenience a ptr 1281 // to the producing instruction will be placed in the head node of 1282 // the dependency links. 1283 int8_t total_dest_regs = new_inst->numDestRegs(); 1284 1285 for (int dest_reg_idx = 0; 1286 dest_reg_idx < total_dest_regs; 1287 dest_reg_idx++) 1288 { 1289 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 1290 1291 // Instructions that use the misc regs will have a reg number 1292 // higher than the normal physical registers. In this case these 1293 // registers are not renamed, and there is no need to track 1294 // dependencies as these instructions must be executed at commit. 1295 if (dest_reg >= numPhysRegs) { 1296 continue; 1297 } 1298 1299 if (!dependGraph.empty(dest_reg)) { 1300 dependGraph.dump(); 1301 panic("Dependency graph %i not empty!", dest_reg); 1302 } 1303 1304 dependGraph.setInst(dest_reg, new_inst); 1305 1306 // Mark the scoreboard to say it's not yet ready. 1307 regScoreboard[dest_reg] = false; 1308 } 1309} 1310 1311template <class Impl> 1312void 1313InstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 1314{ 1315 // If the instruction now has all of its source registers 1316 // available, then add it to the list of ready instructions. 1317 if (inst->readyToIssue()) { 1318 1319 //Add the instruction to the proper ready list. 1320 if (inst->isMemRef()) { 1321 1322 DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 1323 1324 // Message to the mem dependence unit that this instruction has 1325 // its registers ready. 1326 memDepUnit[inst->threadNumber].regsReady(inst); 1327 1328 return; 1329 } 1330 1331 OpClass op_class = inst->opClass(); 1332 1333 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 1334 "the ready list, PC %s opclass:%i [sn:%lli].\n", 1335 inst->pcState(), op_class, inst->seqNum); 1336 1337 readyInsts[op_class].push(inst); 1338 1339 // Will need to reorder the list if either a queue is not on the list, 1340 // or it has an older instruction than last time. 1341 if (!queueOnList[op_class]) { 1342 addToOrderList(op_class); 1343 } else if (readyInsts[op_class].top()->seqNum < 1344 (*readyIt[op_class]).oldestInst) { 1345 listOrder.erase(readyIt[op_class]); 1346 addToOrderList(op_class); 1347 } 1348 } 1349} 1350 1351template <class Impl> 1352int 1353InstructionQueue<Impl>::countInsts() 1354{ 1355#if 0 1356 //ksewell:This works but definitely could use a cleaner write 1357 //with a more intuitive way of counting. Right now it's 1358 //just brute force .... 1359 // Change the #if if you want to use this method. 1360 int total_insts = 0; 1361 1362 for (ThreadID tid = 0; tid < numThreads; ++tid) { 1363 ListIt count_it = instList[tid].begin(); 1364 1365 while (count_it != instList[tid].end()) { 1366 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 1367 if (!(*count_it)->isIssued()) { 1368 ++total_insts; 1369 } else if ((*count_it)->isMemRef() && 1370 !(*count_it)->memOpDone) { 1371 // Loads that have not been marked as executed still count 1372 // towards the total instructions. 1373 ++total_insts; 1374 } 1375 } 1376 1377 ++count_it; 1378 } 1379 } 1380 1381 return total_insts; 1382#else 1383 return numEntries - freeEntries; 1384#endif 1385} 1386 1387template <class Impl> 1388void 1389InstructionQueue<Impl>::dumpLists() 1390{ 1391 for (int i = 0; i < Num_OpClasses; ++i) { 1392 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 1393 1394 cprintf("\n"); 1395 } 1396 1397 cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 1398 1399 NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 1400 NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 1401 1402 cprintf("Non speculative list: "); 1403 1404 while (non_spec_it != non_spec_end_it) { 1405 cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(), 1406 (*non_spec_it).second->seqNum); 1407 ++non_spec_it; 1408 } 1409 1410 cprintf("\n"); 1411 1412 ListOrderIt list_order_it = listOrder.begin(); 1413 ListOrderIt list_order_end_it = listOrder.end(); 1414 int i = 1; 1415 1416 cprintf("List order: "); 1417 1418 while (list_order_it != list_order_end_it) { 1419 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 1420 (*list_order_it).oldestInst); 1421 1422 ++list_order_it; 1423 ++i; 1424 } 1425 1426 cprintf("\n"); 1427} 1428 1429 1430template <class Impl> 1431void 1432InstructionQueue<Impl>::dumpInsts() 1433{ 1434 for (ThreadID tid = 0; tid < numThreads; ++tid) { 1435 int num = 0; 1436 int valid_num = 0; 1437 ListIt inst_list_it = instList[tid].begin(); 1438 1439 while (inst_list_it != instList[tid].end()) { 1440 cprintf("Instruction:%i\n", num); 1441 if (!(*inst_list_it)->isSquashed()) { 1442 if (!(*inst_list_it)->isIssued()) { 1443 ++valid_num; 1444 cprintf("Count:%i\n", valid_num); 1445 } else if ((*inst_list_it)->isMemRef() && 1446 !(*inst_list_it)->memOpDone()) { 1447 // Loads that have not been marked as executed 1448 // still count towards the total instructions. 1449 ++valid_num; 1450 cprintf("Count:%i\n", valid_num); 1451 } 1452 } 1453 1454 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 1455 "Issued:%i\nSquashed:%i\n", 1456 (*inst_list_it)->pcState(), 1457 (*inst_list_it)->seqNum, 1458 (*inst_list_it)->threadNumber, 1459 (*inst_list_it)->isIssued(), 1460 (*inst_list_it)->isSquashed()); 1461 1462 if ((*inst_list_it)->isMemRef()) { 1463 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 1464 } 1465 1466 cprintf("\n"); 1467 1468 inst_list_it++; 1469 ++num; 1470 } 1471 } 1472 1473 cprintf("Insts to Execute list:\n"); 1474 1475 int num = 0; 1476 int valid_num = 0; 1477 ListIt inst_list_it = instsToExecute.begin(); 1478 1479 while (inst_list_it != instsToExecute.end()) 1480 { 1481 cprintf("Instruction:%i\n", 1482 num); 1483 if (!(*inst_list_it)->isSquashed()) { 1484 if (!(*inst_list_it)->isIssued()) { 1485 ++valid_num; 1486 cprintf("Count:%i\n", valid_num); 1487 } else if ((*inst_list_it)->isMemRef() && 1488 !(*inst_list_it)->memOpDone()) { 1489 // Loads that have not been marked as executed 1490 // still count towards the total instructions. 1491 ++valid_num; 1492 cprintf("Count:%i\n", valid_num); 1493 } 1494 } 1495 1496 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 1497 "Issued:%i\nSquashed:%i\n", 1498 (*inst_list_it)->pcState(), 1499 (*inst_list_it)->seqNum, 1500 (*inst_list_it)->threadNumber, 1501 (*inst_list_it)->isIssued(), 1502 (*inst_list_it)->isSquashed()); 1503 1504 if ((*inst_list_it)->isMemRef()) { 1505 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 1506 } 1507 1508 cprintf("\n"); 1509 1510 inst_list_it++; 1511 ++num; 1512 } 1513} 1514 1515#endif//__CPU_O3_INST_QUEUE_IMPL_HH__ 1516