inst_queue_impl.hh revision 9180
11689SN/A/* 27944SGiacomo.Gabrielli@arm.com * Copyright (c) 2011 ARM Limited 37944SGiacomo.Gabrielli@arm.com * All rights reserved. 47944SGiacomo.Gabrielli@arm.com * 57944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 67944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 77944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 87944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 97944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 107944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 117944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 127944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 137944SGiacomo.Gabrielli@arm.com * 142326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412831Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 442064SN/A#include <limits> 451060SN/A#include <vector> 461060SN/A 472292SN/A#include "cpu/o3/fu_pool.hh" 481717SN/A#include "cpu/o3/inst_queue.hh" 498232Snate@binkert.org#include "debug/IQ.hh" 504762Snate@binkert.org#include "enums/OpClass.hh" 516221Snate@binkert.org#include "params/DerivO3CPU.hh" 524762Snate@binkert.org#include "sim/core.hh" 531060SN/A 548737Skoansin.tan@gmail.com// clang complains about std::set being overloaded with Packet::set if 558737Skoansin.tan@gmail.com// we open up the entire namespace std 568737Skoansin.tan@gmail.comusing std::list; 575529Snate@binkert.org 581061SN/Atemplate <class Impl> 592292SN/AInstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 605606Snate@binkert.org int fu_idx, InstructionQueue<Impl> *iq_ptr) 618581Ssteve.reinhardt@amd.com : Event(Stat_Event_Pri, AutoDelete), 628581Ssteve.reinhardt@amd.com inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 631060SN/A{ 642292SN/A} 652292SN/A 662292SN/Atemplate <class Impl> 672292SN/Avoid 682292SN/AInstructionQueue<Impl>::FUCompletion::process() 692292SN/A{ 702326SN/A iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 712292SN/A inst = NULL; 722292SN/A} 732292SN/A 742292SN/A 752292SN/Atemplate <class Impl> 762292SN/Aconst char * 775336Shines@cs.fsu.eduInstructionQueue<Impl>::FUCompletion::description() const 782292SN/A{ 794873Sstever@eecs.umich.edu return "Functional unit completion"; 802292SN/A} 812292SN/A 822292SN/Atemplate <class Impl> 834329Sktlim@umich.eduInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 845529Snate@binkert.org DerivO3CPUParams *params) 854329Sktlim@umich.edu : cpu(cpu_ptr), 864329Sktlim@umich.edu iewStage(iew_ptr), 874329Sktlim@umich.edu fuPool(params->fuPool), 882292SN/A numEntries(params->numIQEntries), 892292SN/A totalWidth(params->issueWidth), 902292SN/A numPhysIntRegs(params->numPhysIntRegs), 912292SN/A numPhysFloatRegs(params->numPhysFloatRegs), 922292SN/A commitToIEWDelay(params->commitToIEWDelay) 932292SN/A{ 942292SN/A assert(fuPool); 952292SN/A 962307SN/A switchedOut = false; 972307SN/A 985529Snate@binkert.org numThreads = params->numThreads; 991060SN/A 1001060SN/A // Set the number of physical registers as the number of int + float 1011060SN/A numPhysRegs = numPhysIntRegs + numPhysFloatRegs; 1021060SN/A 1031060SN/A //Create an entry for each physical register within the 1041060SN/A //dependency graph. 1052326SN/A dependGraph.resize(numPhysRegs); 1061060SN/A 1071060SN/A // Resize the register scoreboard. 1081060SN/A regScoreboard.resize(numPhysRegs); 1091060SN/A 1102292SN/A //Initialize Mem Dependence Units 1116221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1126221Snate@binkert.org memDepUnit[tid].init(params, tid); 1136221Snate@binkert.org memDepUnit[tid].setIQ(this); 1141060SN/A } 1151060SN/A 1162307SN/A resetState(); 1172292SN/A 1182980Sgblack@eecs.umich.edu std::string policy = params->smtIQPolicy; 1192292SN/A 1202292SN/A //Convert string to lowercase 1212292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1222292SN/A (int(*)(int)) tolower); 1232292SN/A 1242292SN/A //Figure out resource sharing policy 1252292SN/A if (policy == "dynamic") { 1262292SN/A iqPolicy = Dynamic; 1272292SN/A 1282292SN/A //Set Max Entries to Total ROB Capacity 1296221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1306221Snate@binkert.org maxEntries[tid] = numEntries; 1312292SN/A } 1322292SN/A 1332292SN/A } else if (policy == "partitioned") { 1342292SN/A iqPolicy = Partitioned; 1352292SN/A 1362292SN/A //@todo:make work if part_amt doesnt divide evenly. 1372292SN/A int part_amt = numEntries / numThreads; 1382292SN/A 1392292SN/A //Divide ROB up evenly 1406221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1416221Snate@binkert.org maxEntries[tid] = part_amt; 1422292SN/A } 1432292SN/A 1442831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 1452292SN/A "%i entries per thread.\n",part_amt); 1462292SN/A } else if (policy == "threshold") { 1472292SN/A iqPolicy = Threshold; 1482292SN/A 1492292SN/A double threshold = (double)params->smtIQThreshold / 100; 1502292SN/A 1512292SN/A int thresholdIQ = (int)((double)threshold * numEntries); 1522292SN/A 1532292SN/A //Divide up by threshold amount 1546221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1556221Snate@binkert.org maxEntries[tid] = thresholdIQ; 1562292SN/A } 1572292SN/A 1582831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Threshold:" 1592292SN/A "%i entries per thread.\n",thresholdIQ); 1602292SN/A } else { 1612292SN/A assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 1622292SN/A "Partitioned, Threshold}"); 1632292SN/A } 1642292SN/A} 1652292SN/A 1662292SN/Atemplate <class Impl> 1672292SN/AInstructionQueue<Impl>::~InstructionQueue() 1682292SN/A{ 1692326SN/A dependGraph.reset(); 1702348SN/A#ifdef DEBUG 1712326SN/A cprintf("Nodes traversed: %i, removed: %i\n", 1722326SN/A dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1732348SN/A#endif 1742292SN/A} 1752292SN/A 1762292SN/Atemplate <class Impl> 1772292SN/Astd::string 1782292SN/AInstructionQueue<Impl>::name() const 1792292SN/A{ 1802292SN/A return cpu->name() + ".iq"; 1811060SN/A} 1821060SN/A 1831061SN/Atemplate <class Impl> 1841060SN/Avoid 1851062SN/AInstructionQueue<Impl>::regStats() 1861062SN/A{ 1872301SN/A using namespace Stats; 1881062SN/A iqInstsAdded 1891062SN/A .name(name() + ".iqInstsAdded") 1901062SN/A .desc("Number of instructions added to the IQ (excludes non-spec)") 1911062SN/A .prereq(iqInstsAdded); 1921062SN/A 1931062SN/A iqNonSpecInstsAdded 1941062SN/A .name(name() + ".iqNonSpecInstsAdded") 1951062SN/A .desc("Number of non-speculative instructions added to the IQ") 1961062SN/A .prereq(iqNonSpecInstsAdded); 1971062SN/A 1982301SN/A iqInstsIssued 1992301SN/A .name(name() + ".iqInstsIssued") 2002301SN/A .desc("Number of instructions issued") 2012301SN/A .prereq(iqInstsIssued); 2021062SN/A 2031062SN/A iqIntInstsIssued 2041062SN/A .name(name() + ".iqIntInstsIssued") 2051062SN/A .desc("Number of integer instructions issued") 2061062SN/A .prereq(iqIntInstsIssued); 2071062SN/A 2081062SN/A iqFloatInstsIssued 2091062SN/A .name(name() + ".iqFloatInstsIssued") 2101062SN/A .desc("Number of float instructions issued") 2111062SN/A .prereq(iqFloatInstsIssued); 2121062SN/A 2131062SN/A iqBranchInstsIssued 2141062SN/A .name(name() + ".iqBranchInstsIssued") 2151062SN/A .desc("Number of branch instructions issued") 2161062SN/A .prereq(iqBranchInstsIssued); 2171062SN/A 2181062SN/A iqMemInstsIssued 2191062SN/A .name(name() + ".iqMemInstsIssued") 2201062SN/A .desc("Number of memory instructions issued") 2211062SN/A .prereq(iqMemInstsIssued); 2221062SN/A 2231062SN/A iqMiscInstsIssued 2241062SN/A .name(name() + ".iqMiscInstsIssued") 2251062SN/A .desc("Number of miscellaneous instructions issued") 2261062SN/A .prereq(iqMiscInstsIssued); 2271062SN/A 2281062SN/A iqSquashedInstsIssued 2291062SN/A .name(name() + ".iqSquashedInstsIssued") 2301062SN/A .desc("Number of squashed instructions issued") 2311062SN/A .prereq(iqSquashedInstsIssued); 2321062SN/A 2331062SN/A iqSquashedInstsExamined 2341062SN/A .name(name() + ".iqSquashedInstsExamined") 2351062SN/A .desc("Number of squashed instructions iterated over during squash;" 2361062SN/A " mainly for profiling") 2371062SN/A .prereq(iqSquashedInstsExamined); 2381062SN/A 2391062SN/A iqSquashedOperandsExamined 2401062SN/A .name(name() + ".iqSquashedOperandsExamined") 2411062SN/A .desc("Number of squashed operands that are examined and possibly " 2421062SN/A "removed from graph") 2431062SN/A .prereq(iqSquashedOperandsExamined); 2441062SN/A 2451062SN/A iqSquashedNonSpecRemoved 2461062SN/A .name(name() + ".iqSquashedNonSpecRemoved") 2471062SN/A .desc("Number of squashed non-spec instructions that were removed") 2481062SN/A .prereq(iqSquashedNonSpecRemoved); 2492361SN/A/* 2502326SN/A queueResDist 2512301SN/A .init(Num_OpClasses, 0, 99, 2) 2522301SN/A .name(name() + ".IQ:residence:") 2532301SN/A .desc("cycles from dispatch to issue") 2542301SN/A .flags(total | pdf | cdf ) 2552301SN/A ; 2562301SN/A for (int i = 0; i < Num_OpClasses; ++i) { 2572326SN/A queueResDist.subname(i, opClassStrings[i]); 2582301SN/A } 2592361SN/A*/ 2602326SN/A numIssuedDist 2612307SN/A .init(0,totalWidth,1) 2628240Snate@binkert.org .name(name() + ".issued_per_cycle") 2632301SN/A .desc("Number of insts issued each cycle") 2642307SN/A .flags(pdf) 2652301SN/A ; 2662301SN/A/* 2672301SN/A dist_unissued 2682301SN/A .init(Num_OpClasses+2) 2698240Snate@binkert.org .name(name() + ".unissued_cause") 2702301SN/A .desc("Reason ready instruction not issued") 2712301SN/A .flags(pdf | dist) 2722301SN/A ; 2732301SN/A for (int i=0; i < (Num_OpClasses + 2); ++i) { 2742301SN/A dist_unissued.subname(i, unissued_names[i]); 2752301SN/A } 2762301SN/A*/ 2772326SN/A statIssuedInstType 2784762Snate@binkert.org .init(numThreads,Enums::Num_OpClass) 2798240Snate@binkert.org .name(name() + ".FU_type") 2802301SN/A .desc("Type of FU issued") 2812301SN/A .flags(total | pdf | dist) 2822301SN/A ; 2834762Snate@binkert.org statIssuedInstType.ysubnames(Enums::OpClassStrings); 2842301SN/A 2852301SN/A // 2862301SN/A // How long did instructions for a particular FU type wait prior to issue 2872301SN/A // 2882361SN/A/* 2892326SN/A issueDelayDist 2902301SN/A .init(Num_OpClasses,0,99,2) 2918240Snate@binkert.org .name(name() + ".") 2922301SN/A .desc("cycles from operands ready to issue") 2932301SN/A .flags(pdf | cdf) 2942301SN/A ; 2952301SN/A 2962301SN/A for (int i=0; i<Num_OpClasses; ++i) { 2972980Sgblack@eecs.umich.edu std::stringstream subname; 2982301SN/A subname << opClassStrings[i] << "_delay"; 2992326SN/A issueDelayDist.subname(i, subname.str()); 3002301SN/A } 3012361SN/A*/ 3022326SN/A issueRate 3038240Snate@binkert.org .name(name() + ".rate") 3042301SN/A .desc("Inst issue rate") 3052301SN/A .flags(total) 3062301SN/A ; 3072326SN/A issueRate = iqInstsIssued / cpu->numCycles; 3082727Sktlim@umich.edu 3092326SN/A statFuBusy 3102301SN/A .init(Num_OpClasses) 3118240Snate@binkert.org .name(name() + ".fu_full") 3122301SN/A .desc("attempts to use FU when none available") 3132301SN/A .flags(pdf | dist) 3142301SN/A ; 3152301SN/A for (int i=0; i < Num_OpClasses; ++i) { 3164762Snate@binkert.org statFuBusy.subname(i, Enums::OpClassStrings[i]); 3172301SN/A } 3182301SN/A 3192326SN/A fuBusy 3202301SN/A .init(numThreads) 3218240Snate@binkert.org .name(name() + ".fu_busy_cnt") 3222301SN/A .desc("FU busy when requested") 3232301SN/A .flags(total) 3242301SN/A ; 3252301SN/A 3262326SN/A fuBusyRate 3278240Snate@binkert.org .name(name() + ".fu_busy_rate") 3282301SN/A .desc("FU busy rate (busy events/executed inst)") 3292301SN/A .flags(total) 3302301SN/A ; 3312326SN/A fuBusyRate = fuBusy / iqInstsIssued; 3322301SN/A 3336221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3342292SN/A // Tell mem dependence unit to reg stats as well. 3356221Snate@binkert.org memDepUnit[tid].regStats(); 3362292SN/A } 3377897Shestness@cs.utexas.edu 3387897Shestness@cs.utexas.edu intInstQueueReads 3397897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_reads") 3407897Shestness@cs.utexas.edu .desc("Number of integer instruction queue reads") 3417897Shestness@cs.utexas.edu .flags(total); 3427897Shestness@cs.utexas.edu 3437897Shestness@cs.utexas.edu intInstQueueWrites 3447897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_writes") 3457897Shestness@cs.utexas.edu .desc("Number of integer instruction queue writes") 3467897Shestness@cs.utexas.edu .flags(total); 3477897Shestness@cs.utexas.edu 3487897Shestness@cs.utexas.edu intInstQueueWakeupAccesses 3497897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_wakeup_accesses") 3507897Shestness@cs.utexas.edu .desc("Number of integer instruction queue wakeup accesses") 3517897Shestness@cs.utexas.edu .flags(total); 3527897Shestness@cs.utexas.edu 3537897Shestness@cs.utexas.edu fpInstQueueReads 3547897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_reads") 3557897Shestness@cs.utexas.edu .desc("Number of floating instruction queue reads") 3567897Shestness@cs.utexas.edu .flags(total); 3577897Shestness@cs.utexas.edu 3587897Shestness@cs.utexas.edu fpInstQueueWrites 3597897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_writes") 3607897Shestness@cs.utexas.edu .desc("Number of floating instruction queue writes") 3617897Shestness@cs.utexas.edu .flags(total); 3627897Shestness@cs.utexas.edu 3637897Shestness@cs.utexas.edu fpInstQueueWakeupQccesses 3647897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_wakeup_accesses") 3657897Shestness@cs.utexas.edu .desc("Number of floating instruction queue wakeup accesses") 3667897Shestness@cs.utexas.edu .flags(total); 3677897Shestness@cs.utexas.edu 3687897Shestness@cs.utexas.edu intAluAccesses 3697897Shestness@cs.utexas.edu .name(name() + ".int_alu_accesses") 3707897Shestness@cs.utexas.edu .desc("Number of integer alu accesses") 3717897Shestness@cs.utexas.edu .flags(total); 3727897Shestness@cs.utexas.edu 3737897Shestness@cs.utexas.edu fpAluAccesses 3747897Shestness@cs.utexas.edu .name(name() + ".fp_alu_accesses") 3757897Shestness@cs.utexas.edu .desc("Number of floating point alu accesses") 3767897Shestness@cs.utexas.edu .flags(total); 3777897Shestness@cs.utexas.edu 3781062SN/A} 3791062SN/A 3801062SN/Atemplate <class Impl> 3811062SN/Avoid 3822307SN/AInstructionQueue<Impl>::resetState() 3831060SN/A{ 3842307SN/A //Initialize thread IQ counts 3856221Snate@binkert.org for (ThreadID tid = 0; tid <numThreads; tid++) { 3866221Snate@binkert.org count[tid] = 0; 3876221Snate@binkert.org instList[tid].clear(); 3882307SN/A } 3891060SN/A 3902307SN/A // Initialize the number of free IQ entries. 3912307SN/A freeEntries = numEntries; 3922307SN/A 3932307SN/A // Note that in actuality, the registers corresponding to the logical 3942307SN/A // registers start off as ready. However this doesn't matter for the 3952307SN/A // IQ as the instruction should have been correctly told if those 3962307SN/A // registers are ready in rename. Thus it can all be initialized as 3972307SN/A // unready. 3982307SN/A for (int i = 0; i < numPhysRegs; ++i) { 3992307SN/A regScoreboard[i] = false; 4002307SN/A } 4012307SN/A 4026221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 4036221Snate@binkert.org squashedSeqNum[tid] = 0; 4042307SN/A } 4052307SN/A 4062307SN/A for (int i = 0; i < Num_OpClasses; ++i) { 4072307SN/A while (!readyInsts[i].empty()) 4082307SN/A readyInsts[i].pop(); 4092307SN/A queueOnList[i] = false; 4102307SN/A readyIt[i] = listOrder.end(); 4112307SN/A } 4122307SN/A nonSpecInsts.clear(); 4132307SN/A listOrder.clear(); 4147944SGiacomo.Gabrielli@arm.com deferredMemInsts.clear(); 4151060SN/A} 4161060SN/A 4171061SN/Atemplate <class Impl> 4181060SN/Avoid 4196221Snate@binkert.orgInstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 4201060SN/A{ 4212292SN/A activeThreads = at_ptr; 4222064SN/A} 4232064SN/A 4242064SN/Atemplate <class Impl> 4252064SN/Avoid 4262292SN/AInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 4272064SN/A{ 4284318Sktlim@umich.edu issueToExecuteQueue = i2e_ptr; 4291060SN/A} 4301060SN/A 4311061SN/Atemplate <class Impl> 4321060SN/Avoid 4331060SN/AInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 4341060SN/A{ 4351060SN/A timeBuffer = tb_ptr; 4361060SN/A 4371060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 4381060SN/A} 4391060SN/A 4401684SN/Atemplate <class Impl> 4412307SN/Avoid 4422307SN/AInstructionQueue<Impl>::switchOut() 4432307SN/A{ 4442367SN/A/* 4452367SN/A if (!instList[0].empty() || (numEntries != freeEntries) || 4462367SN/A !readyInsts[0].empty() || !nonSpecInsts.empty() || !listOrder.empty()) { 4472367SN/A dumpInsts(); 4482367SN/A// assert(0); 4492367SN/A } 4502367SN/A*/ 4512307SN/A resetState(); 4522326SN/A dependGraph.reset(); 4532367SN/A instsToExecute.clear(); 4542307SN/A switchedOut = true; 4556221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 4566221Snate@binkert.org memDepUnit[tid].switchOut(); 4572307SN/A } 4582307SN/A} 4592307SN/A 4602307SN/Atemplate <class Impl> 4612307SN/Avoid 4622307SN/AInstructionQueue<Impl>::takeOverFrom() 4632307SN/A{ 4642307SN/A switchedOut = false; 4652307SN/A} 4662307SN/A 4672307SN/Atemplate <class Impl> 4682292SN/Aint 4696221Snate@binkert.orgInstructionQueue<Impl>::entryAmount(ThreadID num_threads) 4702292SN/A{ 4712292SN/A if (iqPolicy == Partitioned) { 4722292SN/A return numEntries / num_threads; 4732292SN/A } else { 4742292SN/A return 0; 4752292SN/A } 4762292SN/A} 4772292SN/A 4782292SN/A 4792292SN/Atemplate <class Impl> 4802292SN/Avoid 4812292SN/AInstructionQueue<Impl>::resetEntries() 4822292SN/A{ 4832292SN/A if (iqPolicy != Dynamic || numThreads > 1) { 4843867Sbinkertn@umich.edu int active_threads = activeThreads->size(); 4852292SN/A 4866221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4876221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4882292SN/A 4893867Sbinkertn@umich.edu while (threads != end) { 4906221Snate@binkert.org ThreadID tid = *threads++; 4913867Sbinkertn@umich.edu 4922292SN/A if (iqPolicy == Partitioned) { 4933867Sbinkertn@umich.edu maxEntries[tid] = numEntries / active_threads; 4942292SN/A } else if(iqPolicy == Threshold && active_threads == 1) { 4953867Sbinkertn@umich.edu maxEntries[tid] = numEntries; 4962292SN/A } 4972292SN/A } 4982292SN/A } 4992292SN/A} 5002292SN/A 5012292SN/Atemplate <class Impl> 5021684SN/Aunsigned 5031684SN/AInstructionQueue<Impl>::numFreeEntries() 5041684SN/A{ 5051684SN/A return freeEntries; 5061684SN/A} 5071684SN/A 5082292SN/Atemplate <class Impl> 5092292SN/Aunsigned 5106221Snate@binkert.orgInstructionQueue<Impl>::numFreeEntries(ThreadID tid) 5112292SN/A{ 5122292SN/A return maxEntries[tid] - count[tid]; 5132292SN/A} 5142292SN/A 5151060SN/A// Might want to do something more complex if it knows how many instructions 5161060SN/A// will be issued this cycle. 5171061SN/Atemplate <class Impl> 5181060SN/Abool 5191060SN/AInstructionQueue<Impl>::isFull() 5201060SN/A{ 5211060SN/A if (freeEntries == 0) { 5221060SN/A return(true); 5231060SN/A } else { 5241060SN/A return(false); 5251060SN/A } 5261060SN/A} 5271060SN/A 5281061SN/Atemplate <class Impl> 5292292SN/Abool 5306221Snate@binkert.orgInstructionQueue<Impl>::isFull(ThreadID tid) 5312292SN/A{ 5322292SN/A if (numFreeEntries(tid) == 0) { 5332292SN/A return(true); 5342292SN/A } else { 5352292SN/A return(false); 5362292SN/A } 5372292SN/A} 5382292SN/A 5392292SN/Atemplate <class Impl> 5402292SN/Abool 5412292SN/AInstructionQueue<Impl>::hasReadyInsts() 5422292SN/A{ 5432292SN/A if (!listOrder.empty()) { 5442292SN/A return true; 5452292SN/A } 5462292SN/A 5472292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 5482292SN/A if (!readyInsts[i].empty()) { 5492292SN/A return true; 5502292SN/A } 5512292SN/A } 5522292SN/A 5532292SN/A return false; 5542292SN/A} 5552292SN/A 5562292SN/Atemplate <class Impl> 5571060SN/Avoid 5581061SN/AInstructionQueue<Impl>::insert(DynInstPtr &new_inst) 5591060SN/A{ 5607897Shestness@cs.utexas.edu new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 5611060SN/A // Make sure the instruction is valid 5621060SN/A assert(new_inst); 5631060SN/A 5647720Sgblack@eecs.umich.edu DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n", 5657720Sgblack@eecs.umich.edu new_inst->seqNum, new_inst->pcState()); 5661060SN/A 5671060SN/A assert(freeEntries != 0); 5681060SN/A 5692292SN/A instList[new_inst->threadNumber].push_back(new_inst); 5701060SN/A 5712064SN/A --freeEntries; 5721060SN/A 5732292SN/A new_inst->setInIQ(); 5741060SN/A 5751060SN/A // Look through its source registers (physical regs), and mark any 5761060SN/A // dependencies. 5771060SN/A addToDependents(new_inst); 5781060SN/A 5791060SN/A // Have this instruction set itself as the producer of its destination 5801060SN/A // register(s). 5812326SN/A addToProducers(new_inst); 5821060SN/A 5831061SN/A if (new_inst->isMemRef()) { 5842292SN/A memDepUnit[new_inst->threadNumber].insert(new_inst); 5851062SN/A } else { 5861062SN/A addIfReady(new_inst); 5871061SN/A } 5881061SN/A 5891062SN/A ++iqInstsAdded; 5901060SN/A 5912292SN/A count[new_inst->threadNumber]++; 5922292SN/A 5931060SN/A assert(freeEntries == (numEntries - countInsts())); 5941060SN/A} 5951060SN/A 5961061SN/Atemplate <class Impl> 5971061SN/Avoid 5982292SN/AInstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) 5991061SN/A{ 6001061SN/A // @todo: Clean up this code; can do it by setting inst as unable 6011061SN/A // to issue, then calling normal insert on the inst. 6027897Shestness@cs.utexas.edu new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 6031061SN/A 6042292SN/A assert(new_inst); 6051061SN/A 6062292SN/A nonSpecInsts[new_inst->seqNum] = new_inst; 6071061SN/A 6087720Sgblack@eecs.umich.edu DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s " 6092326SN/A "to the IQ.\n", 6107720Sgblack@eecs.umich.edu new_inst->seqNum, new_inst->pcState()); 6112064SN/A 6121061SN/A assert(freeEntries != 0); 6131061SN/A 6142292SN/A instList[new_inst->threadNumber].push_back(new_inst); 6151061SN/A 6162064SN/A --freeEntries; 6171061SN/A 6182292SN/A new_inst->setInIQ(); 6191061SN/A 6201061SN/A // Have this instruction set itself as the producer of its destination 6211061SN/A // register(s). 6222326SN/A addToProducers(new_inst); 6231061SN/A 6241061SN/A // If it's a memory instruction, add it to the memory dependency 6251061SN/A // unit. 6262292SN/A if (new_inst->isMemRef()) { 6272292SN/A memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 6281061SN/A } 6291062SN/A 6301062SN/A ++iqNonSpecInstsAdded; 6312292SN/A 6322292SN/A count[new_inst->threadNumber]++; 6332292SN/A 6342292SN/A assert(freeEntries == (numEntries - countInsts())); 6351061SN/A} 6361061SN/A 6371061SN/Atemplate <class Impl> 6381060SN/Avoid 6392292SN/AInstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) 6401060SN/A{ 6412292SN/A memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 6421060SN/A 6432292SN/A insertNonSpec(barr_inst); 6442292SN/A} 6451060SN/A 6462064SN/Atemplate <class Impl> 6472333SN/Atypename Impl::DynInstPtr 6482333SN/AInstructionQueue<Impl>::getInstToExecute() 6492333SN/A{ 6502333SN/A assert(!instsToExecute.empty()); 6512333SN/A DynInstPtr inst = instsToExecute.front(); 6522333SN/A instsToExecute.pop_front(); 6537897Shestness@cs.utexas.edu if (inst->isFloating()){ 6547897Shestness@cs.utexas.edu fpInstQueueReads++; 6557897Shestness@cs.utexas.edu } else { 6567897Shestness@cs.utexas.edu intInstQueueReads++; 6577897Shestness@cs.utexas.edu } 6582333SN/A return inst; 6592333SN/A} 6601060SN/A 6612333SN/Atemplate <class Impl> 6622064SN/Avoid 6632292SN/AInstructionQueue<Impl>::addToOrderList(OpClass op_class) 6642292SN/A{ 6652292SN/A assert(!readyInsts[op_class].empty()); 6662292SN/A 6672292SN/A ListOrderEntry queue_entry; 6682292SN/A 6692292SN/A queue_entry.queueType = op_class; 6702292SN/A 6712292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 6722292SN/A 6732292SN/A ListOrderIt list_it = listOrder.begin(); 6742292SN/A ListOrderIt list_end_it = listOrder.end(); 6752292SN/A 6762292SN/A while (list_it != list_end_it) { 6772292SN/A if ((*list_it).oldestInst > queue_entry.oldestInst) { 6782292SN/A break; 6792292SN/A } 6802292SN/A 6812292SN/A list_it++; 6821060SN/A } 6831060SN/A 6842292SN/A readyIt[op_class] = listOrder.insert(list_it, queue_entry); 6852292SN/A queueOnList[op_class] = true; 6862292SN/A} 6871060SN/A 6882292SN/Atemplate <class Impl> 6892292SN/Avoid 6902292SN/AInstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 6912292SN/A{ 6922292SN/A // Get iterator of next item on the list 6932292SN/A // Delete the original iterator 6942292SN/A // Determine if the next item is either the end of the list or younger 6952292SN/A // than the new instruction. If so, then add in a new iterator right here. 6962292SN/A // If not, then move along. 6972292SN/A ListOrderEntry queue_entry; 6982292SN/A OpClass op_class = (*list_order_it).queueType; 6992292SN/A ListOrderIt next_it = list_order_it; 7002292SN/A 7012292SN/A ++next_it; 7022292SN/A 7032292SN/A queue_entry.queueType = op_class; 7042292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 7052292SN/A 7062292SN/A while (next_it != listOrder.end() && 7072292SN/A (*next_it).oldestInst < queue_entry.oldestInst) { 7082292SN/A ++next_it; 7091060SN/A } 7101060SN/A 7112292SN/A readyIt[op_class] = listOrder.insert(next_it, queue_entry); 7121060SN/A} 7131060SN/A 7142292SN/Atemplate <class Impl> 7152292SN/Avoid 7162292SN/AInstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 7172292SN/A{ 7182367SN/A DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 7192292SN/A // The CPU could have been sleeping until this op completed (*extremely* 7202292SN/A // long latency op). Wake it if it was. This may be overkill. 7212307SN/A if (isSwitchedOut()) { 7222367SN/A DPRINTF(IQ, "FU completion not processed, IQ is switched out [sn:%lli]\n", 7232367SN/A inst->seqNum); 7242307SN/A return; 7252307SN/A } 7262307SN/A 7272292SN/A iewStage->wakeCPU(); 7282292SN/A 7292326SN/A if (fu_idx > -1) 7302326SN/A fuPool->freeUnitNextCycle(fu_idx); 7312292SN/A 7322326SN/A // @todo: Ensure that these FU Completions happen at the beginning 7332326SN/A // of a cycle, otherwise they could add too many instructions to 7342326SN/A // the queue. 7355327Smengke97@hotmail.com issueToExecuteQueue->access(-1)->size++; 7362333SN/A instsToExecute.push_back(inst); 7372292SN/A} 7382292SN/A 7391061SN/A// @todo: Figure out a better way to remove the squashed items from the 7401061SN/A// lists. Checking the top item of each list to see if it's squashed 7411061SN/A// wastes time and forces jumps. 7421061SN/Atemplate <class Impl> 7431060SN/Avoid 7441060SN/AInstructionQueue<Impl>::scheduleReadyInsts() 7451060SN/A{ 7462292SN/A DPRINTF(IQ, "Attempting to schedule ready instructions from " 7472292SN/A "the IQ.\n"); 7481060SN/A 7491060SN/A IssueStruct *i2e_info = issueToExecuteQueue->access(0); 7501060SN/A 7517944SGiacomo.Gabrielli@arm.com DynInstPtr deferred_mem_inst; 7527944SGiacomo.Gabrielli@arm.com int total_deferred_mem_issued = 0; 7537944SGiacomo.Gabrielli@arm.com while (total_deferred_mem_issued < totalWidth && 7547962Ssaidi@eecs.umich.edu (deferred_mem_inst = getDeferredMemInstToExecute()) != 0) { 7557944SGiacomo.Gabrielli@arm.com issueToExecuteQueue->access(0)->size++; 7567944SGiacomo.Gabrielli@arm.com instsToExecute.push_back(deferred_mem_inst); 7577944SGiacomo.Gabrielli@arm.com total_deferred_mem_issued++; 7587944SGiacomo.Gabrielli@arm.com } 7597944SGiacomo.Gabrielli@arm.com 7602292SN/A // Have iterator to head of the list 7612292SN/A // While I haven't exceeded bandwidth or reached the end of the list, 7622292SN/A // Try to get a FU that can do what this op needs. 7632292SN/A // If successful, change the oldestInst to the new top of the list, put 7642292SN/A // the queue in the proper place in the list. 7652292SN/A // Increment the iterator. 7662292SN/A // This will avoid trying to schedule a certain op class if there are no 7672292SN/A // FUs that handle it. 7682292SN/A ListOrderIt order_it = listOrder.begin(); 7692292SN/A ListOrderIt order_end_it = listOrder.end(); 7702292SN/A int total_issued = 0; 7711060SN/A 7727944SGiacomo.Gabrielli@arm.com while (total_issued < (totalWidth - total_deferred_mem_issued) && 7732820Sktlim@umich.edu iewStage->canIssue() && 7742326SN/A order_it != order_end_it) { 7752292SN/A OpClass op_class = (*order_it).queueType; 7761060SN/A 7772292SN/A assert(!readyInsts[op_class].empty()); 7781060SN/A 7792292SN/A DynInstPtr issuing_inst = readyInsts[op_class].top(); 7801060SN/A 7817897Shestness@cs.utexas.edu issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++; 7827897Shestness@cs.utexas.edu 7832292SN/A assert(issuing_inst->seqNum == (*order_it).oldestInst); 7841060SN/A 7852292SN/A if (issuing_inst->isSquashed()) { 7862292SN/A readyInsts[op_class].pop(); 7871060SN/A 7882292SN/A if (!readyInsts[op_class].empty()) { 7892292SN/A moveToYoungerInst(order_it); 7902292SN/A } else { 7912292SN/A readyIt[op_class] = listOrder.end(); 7922292SN/A queueOnList[op_class] = false; 7931060SN/A } 7941060SN/A 7952292SN/A listOrder.erase(order_it++); 7961060SN/A 7972292SN/A ++iqSquashedInstsIssued; 7982292SN/A 7992292SN/A continue; 8001060SN/A } 8011060SN/A 8022326SN/A int idx = -2; 8032326SN/A int op_latency = 1; 8046221Snate@binkert.org ThreadID tid = issuing_inst->threadNumber; 8051060SN/A 8062326SN/A if (op_class != No_OpClass) { 8072326SN/A idx = fuPool->getUnit(op_class); 8087897Shestness@cs.utexas.edu issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++; 8092326SN/A if (idx > -1) { 8102326SN/A op_latency = fuPool->getOpLatency(op_class); 8111060SN/A } 8121060SN/A } 8131060SN/A 8142348SN/A // If we have an instruction that doesn't require a FU, or a 8152348SN/A // valid FU, then schedule for execution. 8162326SN/A if (idx == -2 || idx != -1) { 8172292SN/A if (op_latency == 1) { 8182292SN/A i2e_info->size++; 8192333SN/A instsToExecute.push_back(issuing_inst); 8201060SN/A 8212326SN/A // Add the FU onto the list of FU's to be freed next 8222326SN/A // cycle if we used one. 8232326SN/A if (idx >= 0) 8242326SN/A fuPool->freeUnitNextCycle(idx); 8252292SN/A } else { 8262292SN/A int issue_latency = fuPool->getIssueLatency(op_class); 8272326SN/A // Generate completion event for the FU 8282326SN/A FUCompletion *execution = new FUCompletion(issuing_inst, 8292326SN/A idx, this); 8301060SN/A 8319180Sandreas.hansson@arm.com cpu->schedule(execution, 8329180Sandreas.hansson@arm.com cpu->clockEdge(Cycles(op_latency - 1))); 8331060SN/A 8342326SN/A // @todo: Enforce that issue_latency == 1 or op_latency 8352292SN/A if (issue_latency > 1) { 8362348SN/A // If FU isn't pipelined, then it must be freed 8372348SN/A // upon the execution completing. 8382326SN/A execution->setFreeFU(); 8392292SN/A } else { 8402292SN/A // Add the FU onto the list of FU's to be freed next cycle. 8412326SN/A fuPool->freeUnitNextCycle(idx); 8422292SN/A } 8431060SN/A } 8441060SN/A 8457720Sgblack@eecs.umich.edu DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 8462292SN/A "[sn:%lli]\n", 8477720Sgblack@eecs.umich.edu tid, issuing_inst->pcState(), 8482292SN/A issuing_inst->seqNum); 8491060SN/A 8502292SN/A readyInsts[op_class].pop(); 8511061SN/A 8522292SN/A if (!readyInsts[op_class].empty()) { 8532292SN/A moveToYoungerInst(order_it); 8542292SN/A } else { 8552292SN/A readyIt[op_class] = listOrder.end(); 8562292SN/A queueOnList[op_class] = false; 8571060SN/A } 8581060SN/A 8592064SN/A issuing_inst->setIssued(); 8602292SN/A ++total_issued; 8612064SN/A 8628471SGiacomo.Gabrielli@arm.com#if TRACING_ON 8639046SAli.Saidi@ARM.com issuing_inst->issueTick = curTick() - issuing_inst->fetchTick; 8648471SGiacomo.Gabrielli@arm.com#endif 8658471SGiacomo.Gabrielli@arm.com 8662292SN/A if (!issuing_inst->isMemRef()) { 8672292SN/A // Memory instructions can not be freed from the IQ until they 8682292SN/A // complete. 8692292SN/A ++freeEntries; 8702301SN/A count[tid]--; 8712731Sktlim@umich.edu issuing_inst->clearInIQ(); 8722292SN/A } else { 8732301SN/A memDepUnit[tid].issue(issuing_inst); 8742292SN/A } 8752292SN/A 8762292SN/A listOrder.erase(order_it++); 8772326SN/A statIssuedInstType[tid][op_class]++; 8782820Sktlim@umich.edu iewStage->incrWb(issuing_inst->seqNum); 8792292SN/A } else { 8802326SN/A statFuBusy[op_class]++; 8812326SN/A fuBusy[tid]++; 8822292SN/A ++order_it; 8831060SN/A } 8841060SN/A } 8851062SN/A 8862326SN/A numIssuedDist.sample(total_issued); 8872326SN/A iqInstsIssued+= total_issued; 8882307SN/A 8892348SN/A // If we issued any instructions, tell the CPU we had activity. 8908071SAli.Saidi@ARM.com // @todo If the way deferred memory instructions are handeled due to 8918071SAli.Saidi@ARM.com // translation changes then the deferredMemInsts condition should be removed 8928071SAli.Saidi@ARM.com // from the code below. 8938071SAli.Saidi@ARM.com if (total_issued || total_deferred_mem_issued || deferredMemInsts.size()) { 8942292SN/A cpu->activityThisCycle(); 8952292SN/A } else { 8962292SN/A DPRINTF(IQ, "Not able to schedule any instructions.\n"); 8972292SN/A } 8981060SN/A} 8991060SN/A 9001061SN/Atemplate <class Impl> 9011060SN/Avoid 9021061SN/AInstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 9031060SN/A{ 9042292SN/A DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 9052292SN/A "to execute.\n", inst); 9061062SN/A 9072292SN/A NonSpecMapIt inst_it = nonSpecInsts.find(inst); 9081060SN/A 9091061SN/A assert(inst_it != nonSpecInsts.end()); 9101060SN/A 9116221Snate@binkert.org ThreadID tid = (*inst_it).second->threadNumber; 9122292SN/A 9134033Sktlim@umich.edu (*inst_it).second->setAtCommit(); 9144033Sktlim@umich.edu 9151061SN/A (*inst_it).second->setCanIssue(); 9161060SN/A 9171062SN/A if (!(*inst_it).second->isMemRef()) { 9181062SN/A addIfReady((*inst_it).second); 9191062SN/A } else { 9202292SN/A memDepUnit[tid].nonSpecInstReady((*inst_it).second); 9211062SN/A } 9221060SN/A 9232292SN/A (*inst_it).second = NULL; 9242292SN/A 9251061SN/A nonSpecInsts.erase(inst_it); 9261060SN/A} 9271060SN/A 9281061SN/Atemplate <class Impl> 9291061SN/Avoid 9306221Snate@binkert.orgInstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 9312292SN/A{ 9322292SN/A DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 9332292SN/A tid,inst); 9342292SN/A 9352292SN/A ListIt iq_it = instList[tid].begin(); 9362292SN/A 9372292SN/A while (iq_it != instList[tid].end() && 9382292SN/A (*iq_it)->seqNum <= inst) { 9392292SN/A ++iq_it; 9402292SN/A instList[tid].pop_front(); 9412292SN/A } 9422292SN/A 9432292SN/A assert(freeEntries == (numEntries - countInsts())); 9442292SN/A} 9452292SN/A 9462292SN/Atemplate <class Impl> 9472301SN/Aint 9481684SN/AInstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 9491684SN/A{ 9502301SN/A int dependents = 0; 9512301SN/A 9527897Shestness@cs.utexas.edu // The instruction queue here takes care of both floating and int ops 9537897Shestness@cs.utexas.edu if (completed_inst->isFloating()) { 9547897Shestness@cs.utexas.edu fpInstQueueWakeupQccesses++; 9557897Shestness@cs.utexas.edu } else { 9567897Shestness@cs.utexas.edu intInstQueueWakeupAccesses++; 9577897Shestness@cs.utexas.edu } 9587897Shestness@cs.utexas.edu 9592292SN/A DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 9602292SN/A 9612292SN/A assert(!completed_inst->isSquashed()); 9621684SN/A 9631684SN/A // Tell the memory dependence unit to wake any dependents on this 9642292SN/A // instruction if it is a memory instruction. Also complete the memory 9652326SN/A // instruction at this point since we know it executed without issues. 9662326SN/A // @todo: Might want to rename "completeMemInst" to something that 9672326SN/A // indicates that it won't need to be replayed, and call this 9682326SN/A // earlier. Might not be a big deal. 9691684SN/A if (completed_inst->isMemRef()) { 9702292SN/A memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 9712292SN/A completeMemInst(completed_inst); 9722292SN/A } else if (completed_inst->isMemBarrier() || 9732292SN/A completed_inst->isWriteBarrier()) { 9742292SN/A memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 9751684SN/A } 9761684SN/A 9771684SN/A for (int dest_reg_idx = 0; 9781684SN/A dest_reg_idx < completed_inst->numDestRegs(); 9791684SN/A dest_reg_idx++) 9801684SN/A { 9811684SN/A PhysRegIndex dest_reg = 9821684SN/A completed_inst->renamedDestRegIdx(dest_reg_idx); 9831684SN/A 9841684SN/A // Special case of uniq or control registers. They are not 9851684SN/A // handled by the IQ and thus have no dependency graph entry. 9861684SN/A // @todo Figure out a cleaner way to handle this. 9871684SN/A if (dest_reg >= numPhysRegs) { 9887599Sminkyu.jeong@arm.com DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg, 9897599Sminkyu.jeong@arm.com numPhysRegs); 9901684SN/A continue; 9911684SN/A } 9921684SN/A 9932292SN/A DPRINTF(IQ, "Waking any dependents on register %i.\n", 9941684SN/A (int) dest_reg); 9951684SN/A 9962326SN/A //Go through the dependency chain, marking the registers as 9972326SN/A //ready within the waiting instructions. 9982326SN/A DynInstPtr dep_inst = dependGraph.pop(dest_reg); 9991684SN/A 10002326SN/A while (dep_inst) { 10017599Sminkyu.jeong@arm.com DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] " 10027720Sgblack@eecs.umich.edu "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 10031684SN/A 10041684SN/A // Might want to give more information to the instruction 10052326SN/A // so that it knows which of its source registers is 10062326SN/A // ready. However that would mean that the dependency 10072326SN/A // graph entries would need to hold the src_reg_idx. 10082326SN/A dep_inst->markSrcRegReady(); 10091684SN/A 10102326SN/A addIfReady(dep_inst); 10111684SN/A 10122326SN/A dep_inst = dependGraph.pop(dest_reg); 10131684SN/A 10142301SN/A ++dependents; 10151684SN/A } 10161684SN/A 10172326SN/A // Reset the head node now that all of its dependents have 10182326SN/A // been woken up. 10192326SN/A assert(dependGraph.empty(dest_reg)); 10202326SN/A dependGraph.clearInst(dest_reg); 10211684SN/A 10221684SN/A // Mark the scoreboard as having that register ready. 10231684SN/A regScoreboard[dest_reg] = true; 10241684SN/A } 10252301SN/A return dependents; 10262064SN/A} 10272064SN/A 10282064SN/Atemplate <class Impl> 10292064SN/Avoid 10302292SN/AInstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 10312064SN/A{ 10322292SN/A OpClass op_class = ready_inst->opClass(); 10332292SN/A 10342292SN/A readyInsts[op_class].push(ready_inst); 10352292SN/A 10362326SN/A // Will need to reorder the list if either a queue is not on the list, 10372326SN/A // or it has an older instruction than last time. 10382326SN/A if (!queueOnList[op_class]) { 10392326SN/A addToOrderList(op_class); 10402326SN/A } else if (readyInsts[op_class].top()->seqNum < 10412326SN/A (*readyIt[op_class]).oldestInst) { 10422326SN/A listOrder.erase(readyIt[op_class]); 10432326SN/A addToOrderList(op_class); 10442326SN/A } 10452326SN/A 10462292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 10477720Sgblack@eecs.umich.edu "the ready list, PC %s opclass:%i [sn:%lli].\n", 10487720Sgblack@eecs.umich.edu ready_inst->pcState(), op_class, ready_inst->seqNum); 10492064SN/A} 10502064SN/A 10512064SN/Atemplate <class Impl> 10522064SN/Avoid 10532292SN/AInstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 10542064SN/A{ 10554033Sktlim@umich.edu DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 10567944SGiacomo.Gabrielli@arm.com 10577944SGiacomo.Gabrielli@arm.com // Reset DTB translation state 10589046SAli.Saidi@ARM.com resched_inst->translationStarted(false); 10599046SAli.Saidi@ARM.com resched_inst->translationCompleted(false); 10607944SGiacomo.Gabrielli@arm.com 10614033Sktlim@umich.edu resched_inst->clearCanIssue(); 10622292SN/A memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 10632064SN/A} 10642064SN/A 10652064SN/Atemplate <class Impl> 10662064SN/Avoid 10672292SN/AInstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 10682064SN/A{ 10692292SN/A memDepUnit[replay_inst->threadNumber].replay(replay_inst); 10702292SN/A} 10712292SN/A 10722292SN/Atemplate <class Impl> 10732292SN/Avoid 10742292SN/AInstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 10752292SN/A{ 10766221Snate@binkert.org ThreadID tid = completed_inst->threadNumber; 10772292SN/A 10787720Sgblack@eecs.umich.edu DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n", 10797720Sgblack@eecs.umich.edu completed_inst->pcState(), completed_inst->seqNum); 10802292SN/A 10812292SN/A ++freeEntries; 10822292SN/A 10839046SAli.Saidi@ARM.com completed_inst->memOpDone(true); 10842292SN/A 10852292SN/A memDepUnit[tid].completed(completed_inst); 10862292SN/A count[tid]--; 10871684SN/A} 10881684SN/A 10891684SN/Atemplate <class Impl> 10901684SN/Avoid 10917944SGiacomo.Gabrielli@arm.comInstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst) 10927944SGiacomo.Gabrielli@arm.com{ 10937944SGiacomo.Gabrielli@arm.com deferredMemInsts.push_back(deferred_inst); 10947944SGiacomo.Gabrielli@arm.com} 10957944SGiacomo.Gabrielli@arm.com 10967944SGiacomo.Gabrielli@arm.comtemplate <class Impl> 10977944SGiacomo.Gabrielli@arm.comtypename Impl::DynInstPtr 10987944SGiacomo.Gabrielli@arm.comInstructionQueue<Impl>::getDeferredMemInstToExecute() 10997944SGiacomo.Gabrielli@arm.com{ 11007944SGiacomo.Gabrielli@arm.com for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); 11017944SGiacomo.Gabrielli@arm.com ++it) { 11029046SAli.Saidi@ARM.com if ((*it)->translationCompleted() || (*it)->isSquashed()) { 11037944SGiacomo.Gabrielli@arm.com DynInstPtr ret = *it; 11047944SGiacomo.Gabrielli@arm.com deferredMemInsts.erase(it); 11057944SGiacomo.Gabrielli@arm.com return ret; 11067944SGiacomo.Gabrielli@arm.com } 11077944SGiacomo.Gabrielli@arm.com } 11087944SGiacomo.Gabrielli@arm.com return NULL; 11097944SGiacomo.Gabrielli@arm.com} 11107944SGiacomo.Gabrielli@arm.com 11117944SGiacomo.Gabrielli@arm.comtemplate <class Impl> 11127944SGiacomo.Gabrielli@arm.comvoid 11131061SN/AInstructionQueue<Impl>::violation(DynInstPtr &store, 11141061SN/A DynInstPtr &faulting_load) 11151061SN/A{ 11167897Shestness@cs.utexas.edu intInstQueueWrites++; 11172292SN/A memDepUnit[store->threadNumber].violation(store, faulting_load); 11181061SN/A} 11191061SN/A 11201061SN/Atemplate <class Impl> 11211060SN/Avoid 11226221Snate@binkert.orgInstructionQueue<Impl>::squash(ThreadID tid) 11231060SN/A{ 11242292SN/A DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 11252292SN/A "the IQ.\n", tid); 11261060SN/A 11271060SN/A // Read instruction sequence number of last instruction out of the 11281060SN/A // time buffer. 11292292SN/A squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 11301060SN/A 11311681SN/A // Call doSquash if there are insts in the IQ 11322292SN/A if (count[tid] > 0) { 11332292SN/A doSquash(tid); 11341681SN/A } 11351061SN/A 11361061SN/A // Also tell the memory dependence unit to squash. 11372292SN/A memDepUnit[tid].squash(squashedSeqNum[tid], tid); 11381060SN/A} 11391060SN/A 11401061SN/Atemplate <class Impl> 11411061SN/Avoid 11426221Snate@binkert.orgInstructionQueue<Impl>::doSquash(ThreadID tid) 11431061SN/A{ 11442326SN/A // Start at the tail. 11452326SN/A ListIt squash_it = instList[tid].end(); 11462326SN/A --squash_it; 11471061SN/A 11482292SN/A DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 11492292SN/A tid, squashedSeqNum[tid]); 11501061SN/A 11511061SN/A // Squash any instructions younger than the squashed sequence number 11521061SN/A // given. 11532326SN/A while (squash_it != instList[tid].end() && 11542326SN/A (*squash_it)->seqNum > squashedSeqNum[tid]) { 11552292SN/A 11562326SN/A DynInstPtr squashed_inst = (*squash_it); 11577897Shestness@cs.utexas.edu squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 11581061SN/A 11591061SN/A // Only handle the instruction if it actually is in the IQ and 11601061SN/A // hasn't already been squashed in the IQ. 11612292SN/A if (squashed_inst->threadNumber != tid || 11622292SN/A squashed_inst->isSquashedInIQ()) { 11632326SN/A --squash_it; 11642292SN/A continue; 11652292SN/A } 11662292SN/A 11672292SN/A if (!squashed_inst->isIssued() || 11682292SN/A (squashed_inst->isMemRef() && 11699046SAli.Saidi@ARM.com !squashed_inst->memOpDone())) { 11701062SN/A 11717720Sgblack@eecs.umich.edu DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", 11727720Sgblack@eecs.umich.edu tid, squashed_inst->seqNum, squashed_inst->pcState()); 11732367SN/A 11741061SN/A // Remove the instruction from the dependency list. 11752292SN/A if (!squashed_inst->isNonSpeculative() && 11762336SN/A !squashed_inst->isStoreConditional() && 11772292SN/A !squashed_inst->isMemBarrier() && 11782292SN/A !squashed_inst->isWriteBarrier()) { 11791061SN/A 11801061SN/A for (int src_reg_idx = 0; 11811681SN/A src_reg_idx < squashed_inst->numSrcRegs(); 11821061SN/A src_reg_idx++) 11831061SN/A { 11841061SN/A PhysRegIndex src_reg = 11851061SN/A squashed_inst->renamedSrcRegIdx(src_reg_idx); 11861061SN/A 11872326SN/A // Only remove it from the dependency graph if it 11882326SN/A // was placed there in the first place. 11892326SN/A 11902326SN/A // Instead of doing a linked list traversal, we 11912326SN/A // can just remove these squashed instructions 11922326SN/A // either at issue time, or when the register is 11932326SN/A // overwritten. The only downside to this is it 11942326SN/A // leaves more room for error. 11952292SN/A 11961061SN/A if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 11971061SN/A src_reg < numPhysRegs) { 11982326SN/A dependGraph.remove(src_reg, squashed_inst); 11991061SN/A } 12001062SN/A 12012292SN/A 12021062SN/A ++iqSquashedOperandsExamined; 12031061SN/A } 12044033Sktlim@umich.edu } else if (!squashed_inst->isStoreConditional() || 12054033Sktlim@umich.edu !squashed_inst->isCompleted()) { 12062292SN/A NonSpecMapIt ns_inst_it = 12072292SN/A nonSpecInsts.find(squashed_inst->seqNum); 12088275SAli.Saidi@ARM.com 12094033Sktlim@umich.edu if (ns_inst_it == nonSpecInsts.end()) { 12104033Sktlim@umich.edu assert(squashed_inst->getFault() != NoFault); 12114033Sktlim@umich.edu } else { 12121062SN/A 12134033Sktlim@umich.edu (*ns_inst_it).second = NULL; 12141681SN/A 12154033Sktlim@umich.edu nonSpecInsts.erase(ns_inst_it); 12161062SN/A 12174033Sktlim@umich.edu ++iqSquashedNonSpecRemoved; 12184033Sktlim@umich.edu } 12191061SN/A } 12201061SN/A 12211061SN/A // Might want to also clear out the head of the dependency graph. 12221061SN/A 12231061SN/A // Mark it as squashed within the IQ. 12241061SN/A squashed_inst->setSquashedInIQ(); 12251061SN/A 12262292SN/A // @todo: Remove this hack where several statuses are set so the 12272292SN/A // inst will flow through the rest of the pipeline. 12281681SN/A squashed_inst->setIssued(); 12291681SN/A squashed_inst->setCanCommit(); 12302731Sktlim@umich.edu squashed_inst->clearInIQ(); 12312292SN/A 12322292SN/A //Update Thread IQ Count 12332292SN/A count[squashed_inst->threadNumber]--; 12341681SN/A 12351681SN/A ++freeEntries; 12361061SN/A } 12371061SN/A 12382326SN/A instList[tid].erase(squash_it--); 12391062SN/A ++iqSquashedInstsExamined; 12401061SN/A } 12411060SN/A} 12421060SN/A 12431061SN/Atemplate <class Impl> 12441060SN/Abool 12451061SN/AInstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 12461060SN/A{ 12471060SN/A // Loop through the instruction's source registers, adding 12481060SN/A // them to the dependency list if they are not ready. 12491060SN/A int8_t total_src_regs = new_inst->numSrcRegs(); 12501060SN/A bool return_val = false; 12511060SN/A 12521060SN/A for (int src_reg_idx = 0; 12531060SN/A src_reg_idx < total_src_regs; 12541060SN/A src_reg_idx++) 12551060SN/A { 12561060SN/A // Only add it to the dependency graph if it's not ready. 12571060SN/A if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 12581060SN/A PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 12591060SN/A 12601060SN/A // Check the IQ's scoreboard to make sure the register 12611060SN/A // hasn't become ready while the instruction was in flight 12621060SN/A // between stages. Only if it really isn't ready should 12631060SN/A // it be added to the dependency graph. 12641061SN/A if (src_reg >= numPhysRegs) { 12651061SN/A continue; 12661061SN/A } else if (regScoreboard[src_reg] == false) { 12677720Sgblack@eecs.umich.edu DPRINTF(IQ, "Instruction PC %s has src reg %i that " 12681060SN/A "is being added to the dependency chain.\n", 12697720Sgblack@eecs.umich.edu new_inst->pcState(), src_reg); 12701060SN/A 12712326SN/A dependGraph.insert(src_reg, new_inst); 12721060SN/A 12731060SN/A // Change the return value to indicate that something 12741060SN/A // was added to the dependency graph. 12751060SN/A return_val = true; 12761060SN/A } else { 12777720Sgblack@eecs.umich.edu DPRINTF(IQ, "Instruction PC %s has src reg %i that " 12781060SN/A "became ready before it reached the IQ.\n", 12797720Sgblack@eecs.umich.edu new_inst->pcState(), src_reg); 12801060SN/A // Mark a register ready within the instruction. 12812326SN/A new_inst->markSrcRegReady(src_reg_idx); 12821060SN/A } 12831060SN/A } 12841060SN/A } 12851060SN/A 12861060SN/A return return_val; 12871060SN/A} 12881060SN/A 12891061SN/Atemplate <class Impl> 12901060SN/Avoid 12912326SN/AInstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) 12921060SN/A{ 12932326SN/A // Nothing really needs to be marked when an instruction becomes 12942326SN/A // the producer of a register's value, but for convenience a ptr 12952326SN/A // to the producing instruction will be placed in the head node of 12962326SN/A // the dependency links. 12971060SN/A int8_t total_dest_regs = new_inst->numDestRegs(); 12981060SN/A 12991060SN/A for (int dest_reg_idx = 0; 13001060SN/A dest_reg_idx < total_dest_regs; 13011060SN/A dest_reg_idx++) 13021060SN/A { 13031061SN/A PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 13041061SN/A 13051061SN/A // Instructions that use the misc regs will have a reg number 13061061SN/A // higher than the normal physical registers. In this case these 13071061SN/A // registers are not renamed, and there is no need to track 13081061SN/A // dependencies as these instructions must be executed at commit. 13091061SN/A if (dest_reg >= numPhysRegs) { 13101061SN/A continue; 13111060SN/A } 13121060SN/A 13132326SN/A if (!dependGraph.empty(dest_reg)) { 13142326SN/A dependGraph.dump(); 13152292SN/A panic("Dependency graph %i not empty!", dest_reg); 13162064SN/A } 13171062SN/A 13182326SN/A dependGraph.setInst(dest_reg, new_inst); 13191062SN/A 13201060SN/A // Mark the scoreboard to say it's not yet ready. 13211060SN/A regScoreboard[dest_reg] = false; 13221060SN/A } 13231060SN/A} 13241060SN/A 13251061SN/Atemplate <class Impl> 13261060SN/Avoid 13271061SN/AInstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 13281060SN/A{ 13292326SN/A // If the instruction now has all of its source registers 13301060SN/A // available, then add it to the list of ready instructions. 13311060SN/A if (inst->readyToIssue()) { 13321061SN/A 13331060SN/A //Add the instruction to the proper ready list. 13342292SN/A if (inst->isMemRef()) { 13351061SN/A 13362292SN/A DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 13371061SN/A 13381062SN/A // Message to the mem dependence unit that this instruction has 13391062SN/A // its registers ready. 13402292SN/A memDepUnit[inst->threadNumber].regsReady(inst); 13411062SN/A 13422292SN/A return; 13432292SN/A } 13441062SN/A 13452292SN/A OpClass op_class = inst->opClass(); 13461061SN/A 13472292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 13487720Sgblack@eecs.umich.edu "the ready list, PC %s opclass:%i [sn:%lli].\n", 13497720Sgblack@eecs.umich.edu inst->pcState(), op_class, inst->seqNum); 13501061SN/A 13512292SN/A readyInsts[op_class].push(inst); 13521061SN/A 13532326SN/A // Will need to reorder the list if either a queue is not on the list, 13542326SN/A // or it has an older instruction than last time. 13552326SN/A if (!queueOnList[op_class]) { 13562326SN/A addToOrderList(op_class); 13572326SN/A } else if (readyInsts[op_class].top()->seqNum < 13582326SN/A (*readyIt[op_class]).oldestInst) { 13592326SN/A listOrder.erase(readyIt[op_class]); 13602326SN/A addToOrderList(op_class); 13611060SN/A } 13621060SN/A } 13631060SN/A} 13641060SN/A 13651061SN/Atemplate <class Impl> 13661061SN/Aint 13671061SN/AInstructionQueue<Impl>::countInsts() 13681061SN/A{ 13692698Sktlim@umich.edu#if 0 13702292SN/A //ksewell:This works but definitely could use a cleaner write 13712292SN/A //with a more intuitive way of counting. Right now it's 13722292SN/A //just brute force .... 13732698Sktlim@umich.edu // Change the #if if you want to use this method. 13741061SN/A int total_insts = 0; 13751061SN/A 13766221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 13776221Snate@binkert.org ListIt count_it = instList[tid].begin(); 13781681SN/A 13796221Snate@binkert.org while (count_it != instList[tid].end()) { 13802292SN/A if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 13812292SN/A if (!(*count_it)->isIssued()) { 13822292SN/A ++total_insts; 13832292SN/A } else if ((*count_it)->isMemRef() && 13842292SN/A !(*count_it)->memOpDone) { 13852292SN/A // Loads that have not been marked as executed still count 13862292SN/A // towards the total instructions. 13872292SN/A ++total_insts; 13882292SN/A } 13892292SN/A } 13902292SN/A 13912292SN/A ++count_it; 13921061SN/A } 13931061SN/A } 13941061SN/A 13951061SN/A return total_insts; 13962292SN/A#else 13972292SN/A return numEntries - freeEntries; 13982292SN/A#endif 13991681SN/A} 14001681SN/A 14011681SN/Atemplate <class Impl> 14021681SN/Avoid 14031061SN/AInstructionQueue<Impl>::dumpLists() 14041061SN/A{ 14052292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 14062292SN/A cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 14071061SN/A 14082292SN/A cprintf("\n"); 14092292SN/A } 14101061SN/A 14111061SN/A cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 14121061SN/A 14132292SN/A NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 14142292SN/A NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 14151061SN/A 14161061SN/A cprintf("Non speculative list: "); 14171061SN/A 14182292SN/A while (non_spec_it != non_spec_end_it) { 14197720Sgblack@eecs.umich.edu cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(), 14202292SN/A (*non_spec_it).second->seqNum); 14211061SN/A ++non_spec_it; 14221061SN/A } 14231061SN/A 14241061SN/A cprintf("\n"); 14251061SN/A 14262292SN/A ListOrderIt list_order_it = listOrder.begin(); 14272292SN/A ListOrderIt list_order_end_it = listOrder.end(); 14282292SN/A int i = 1; 14292292SN/A 14302292SN/A cprintf("List order: "); 14312292SN/A 14322292SN/A while (list_order_it != list_order_end_it) { 14332292SN/A cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 14342292SN/A (*list_order_it).oldestInst); 14352292SN/A 14362292SN/A ++list_order_it; 14372292SN/A ++i; 14382292SN/A } 14392292SN/A 14402292SN/A cprintf("\n"); 14411061SN/A} 14422292SN/A 14432292SN/A 14442292SN/Atemplate <class Impl> 14452292SN/Avoid 14462292SN/AInstructionQueue<Impl>::dumpInsts() 14472292SN/A{ 14486221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 14492292SN/A int num = 0; 14502292SN/A int valid_num = 0; 14516221Snate@binkert.org ListIt inst_list_it = instList[tid].begin(); 14522292SN/A 14536221Snate@binkert.org while (inst_list_it != instList[tid].end()) { 14546221Snate@binkert.org cprintf("Instruction:%i\n", num); 14552292SN/A if (!(*inst_list_it)->isSquashed()) { 14562292SN/A if (!(*inst_list_it)->isIssued()) { 14572292SN/A ++valid_num; 14582292SN/A cprintf("Count:%i\n", valid_num); 14592292SN/A } else if ((*inst_list_it)->isMemRef() && 14609046SAli.Saidi@ARM.com !(*inst_list_it)->memOpDone()) { 14612326SN/A // Loads that have not been marked as executed 14622326SN/A // still count towards the total instructions. 14632292SN/A ++valid_num; 14642292SN/A cprintf("Count:%i\n", valid_num); 14652292SN/A } 14662292SN/A } 14672292SN/A 14687720Sgblack@eecs.umich.edu cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 14692292SN/A "Issued:%i\nSquashed:%i\n", 14707720Sgblack@eecs.umich.edu (*inst_list_it)->pcState(), 14712292SN/A (*inst_list_it)->seqNum, 14722292SN/A (*inst_list_it)->threadNumber, 14732292SN/A (*inst_list_it)->isIssued(), 14742292SN/A (*inst_list_it)->isSquashed()); 14752292SN/A 14762292SN/A if ((*inst_list_it)->isMemRef()) { 14779046SAli.Saidi@ARM.com cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 14782292SN/A } 14792292SN/A 14802292SN/A cprintf("\n"); 14812292SN/A 14822292SN/A inst_list_it++; 14832292SN/A ++num; 14842292SN/A } 14852292SN/A } 14862348SN/A 14872348SN/A cprintf("Insts to Execute list:\n"); 14882348SN/A 14892348SN/A int num = 0; 14902348SN/A int valid_num = 0; 14912348SN/A ListIt inst_list_it = instsToExecute.begin(); 14922348SN/A 14932348SN/A while (inst_list_it != instsToExecute.end()) 14942348SN/A { 14952348SN/A cprintf("Instruction:%i\n", 14962348SN/A num); 14972348SN/A if (!(*inst_list_it)->isSquashed()) { 14982348SN/A if (!(*inst_list_it)->isIssued()) { 14992348SN/A ++valid_num; 15002348SN/A cprintf("Count:%i\n", valid_num); 15012348SN/A } else if ((*inst_list_it)->isMemRef() && 15029046SAli.Saidi@ARM.com !(*inst_list_it)->memOpDone()) { 15032348SN/A // Loads that have not been marked as executed 15042348SN/A // still count towards the total instructions. 15052348SN/A ++valid_num; 15062348SN/A cprintf("Count:%i\n", valid_num); 15072348SN/A } 15082348SN/A } 15092348SN/A 15107720Sgblack@eecs.umich.edu cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 15112348SN/A "Issued:%i\nSquashed:%i\n", 15127720Sgblack@eecs.umich.edu (*inst_list_it)->pcState(), 15132348SN/A (*inst_list_it)->seqNum, 15142348SN/A (*inst_list_it)->threadNumber, 15152348SN/A (*inst_list_it)->isIssued(), 15162348SN/A (*inst_list_it)->isSquashed()); 15172348SN/A 15182348SN/A if ((*inst_list_it)->isMemRef()) { 15199046SAli.Saidi@ARM.com cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 15202348SN/A } 15212348SN/A 15222348SN/A cprintf("\n"); 15232348SN/A 15242348SN/A inst_list_it++; 15252348SN/A ++num; 15262348SN/A } 15272292SN/A} 1528