inst_queue_impl.hh revision 8737
111986Sandreas.sandberg@arm.com/* 211986Sandreas.sandberg@arm.com * Copyright (c) 2011 ARM Limited 311986Sandreas.sandberg@arm.com * All rights reserved. 411986Sandreas.sandberg@arm.com * 511986Sandreas.sandberg@arm.com * The license below extends only to copyright in the software and shall 611986Sandreas.sandberg@arm.com * not be construed as granting a license to any other intellectual 711986Sandreas.sandberg@arm.com * property including but not limited to intellectual property relating 811986Sandreas.sandberg@arm.com * to a hardware implementation of the functionality of the software 911986Sandreas.sandberg@arm.com * licensed hereunder. You may use the software subject to the license 1011986Sandreas.sandberg@arm.com * terms below provided that you ensure that this notice is replicated 1111986Sandreas.sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 1211986Sandreas.sandberg@arm.com * modified or unmodified, in source code or in binary form. 1311986Sandreas.sandberg@arm.com * 1411986Sandreas.sandberg@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 1511986Sandreas.sandberg@arm.com * All rights reserved. 1611986Sandreas.sandberg@arm.com * 1711986Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 1811986Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 1912037Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 2011986Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 2111986Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 2211986Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 2311986Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 2411986Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 2511986Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 2611986Sandreas.sandberg@arm.com * this software without specific prior written permission. 2711986Sandreas.sandberg@arm.com * 2811986Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2911986Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3011986Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3112391Sjason@lowepower.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3211986Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3311986Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3411986Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3511986Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3611986Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3711986Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3812391Sjason@lowepower.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3911986Sandreas.sandberg@arm.com * 4011986Sandreas.sandberg@arm.com * Authors: Kevin Lim 4111986Sandreas.sandberg@arm.com * Korey Sewell 4211986Sandreas.sandberg@arm.com */ 4312391Sjason@lowepower.com 4412391Sjason@lowepower.com#include <limits> 4512391Sjason@lowepower.com#include <vector> 4612391Sjason@lowepower.com 4712391Sjason@lowepower.com#include "cpu/o3/fu_pool.hh" 4811986Sandreas.sandberg@arm.com#include "cpu/o3/inst_queue.hh" 4911986Sandreas.sandberg@arm.com#include "debug/IQ.hh" 5011986Sandreas.sandberg@arm.com#include "enums/OpClass.hh" 5111986Sandreas.sandberg@arm.com#include "params/DerivO3CPU.hh" 5211986Sandreas.sandberg@arm.com#include "sim/core.hh" 5311986Sandreas.sandberg@arm.com 5411986Sandreas.sandberg@arm.com// clang complains about std::set being overloaded with Packet::set if 5511986Sandreas.sandberg@arm.com// we open up the entire namespace std 5612037Sandreas.sandberg@arm.comusing std::list; 5712037Sandreas.sandberg@arm.com 5812037Sandreas.sandberg@arm.comtemplate <class Impl> 5912037Sandreas.sandberg@arm.comInstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 6012037Sandreas.sandberg@arm.com int fu_idx, InstructionQueue<Impl> *iq_ptr) 6112037Sandreas.sandberg@arm.com : Event(Stat_Event_Pri, AutoDelete), 6212037Sandreas.sandberg@arm.com inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 6312037Sandreas.sandberg@arm.com{ 6412037Sandreas.sandberg@arm.com} 6512037Sandreas.sandberg@arm.com 6612037Sandreas.sandberg@arm.comtemplate <class Impl> 6712037Sandreas.sandberg@arm.comvoid 6812037Sandreas.sandberg@arm.comInstructionQueue<Impl>::FUCompletion::process() 6912037Sandreas.sandberg@arm.com{ 7012037Sandreas.sandberg@arm.com iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 7112391Sjason@lowepower.com inst = NULL; 7212391Sjason@lowepower.com} 7312391Sjason@lowepower.com 7411986Sandreas.sandberg@arm.com 7512391Sjason@lowepower.comtemplate <class Impl> 7611986Sandreas.sandberg@arm.comconst char * 7711986Sandreas.sandberg@arm.comInstructionQueue<Impl>::FUCompletion::description() const 7812391Sjason@lowepower.com{ 7911986Sandreas.sandberg@arm.com return "Functional unit completion"; 8012391Sjason@lowepower.com} 8111986Sandreas.sandberg@arm.com 8211986Sandreas.sandberg@arm.comtemplate <class Impl> 8311986Sandreas.sandberg@arm.comInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 8411986Sandreas.sandberg@arm.com DerivO3CPUParams *params) 8511986Sandreas.sandberg@arm.com : cpu(cpu_ptr), 8611986Sandreas.sandberg@arm.com iewStage(iew_ptr), 8712391Sjason@lowepower.com fuPool(params->fuPool), 8811986Sandreas.sandberg@arm.com numEntries(params->numIQEntries), 8911986Sandreas.sandberg@arm.com totalWidth(params->issueWidth), 9011986Sandreas.sandberg@arm.com numPhysIntRegs(params->numPhysIntRegs), 9111986Sandreas.sandberg@arm.com numPhysFloatRegs(params->numPhysFloatRegs), 9212391Sjason@lowepower.com commitToIEWDelay(params->commitToIEWDelay) 9312391Sjason@lowepower.com{ 9412391Sjason@lowepower.com assert(fuPool); 9512391Sjason@lowepower.com 9611986Sandreas.sandberg@arm.com switchedOut = false; 9711986Sandreas.sandberg@arm.com 9811986Sandreas.sandberg@arm.com numThreads = params->numThreads; 9911986Sandreas.sandberg@arm.com 10011986Sandreas.sandberg@arm.com // Set the number of physical registers as the number of int + float 10112391Sjason@lowepower.com numPhysRegs = numPhysIntRegs + numPhysFloatRegs; 10212391Sjason@lowepower.com 10312391Sjason@lowepower.com //Create an entry for each physical register within the 10411986Sandreas.sandberg@arm.com //dependency graph. 10512391Sjason@lowepower.com dependGraph.resize(numPhysRegs); 10611986Sandreas.sandberg@arm.com 10711986Sandreas.sandberg@arm.com // Resize the register scoreboard. 10811986Sandreas.sandberg@arm.com regScoreboard.resize(numPhysRegs); 10912391Sjason@lowepower.com 11012391Sjason@lowepower.com //Initialize Mem Dependence Units 11111986Sandreas.sandberg@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 11211986Sandreas.sandberg@arm.com memDepUnit[tid].init(params, tid); 11311986Sandreas.sandberg@arm.com memDepUnit[tid].setIQ(this); 11411986Sandreas.sandberg@arm.com } 11511986Sandreas.sandberg@arm.com 11612391Sjason@lowepower.com resetState(); 11711986Sandreas.sandberg@arm.com 11811986Sandreas.sandberg@arm.com std::string policy = params->smtIQPolicy; 11911986Sandreas.sandberg@arm.com 12011986Sandreas.sandberg@arm.com //Convert string to lowercase 12111986Sandreas.sandberg@arm.com std::transform(policy.begin(), policy.end(), policy.begin(), 12211986Sandreas.sandberg@arm.com (int(*)(int)) tolower); 12311986Sandreas.sandberg@arm.com 12411986Sandreas.sandberg@arm.com //Figure out resource sharing policy 12511986Sandreas.sandberg@arm.com if (policy == "dynamic") { 12611986Sandreas.sandberg@arm.com iqPolicy = Dynamic; 12711986Sandreas.sandberg@arm.com 12811986Sandreas.sandberg@arm.com //Set Max Entries to Total ROB Capacity 12911986Sandreas.sandberg@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 13011986Sandreas.sandberg@arm.com maxEntries[tid] = numEntries; 13112391Sjason@lowepower.com } 13211986Sandreas.sandberg@arm.com 13311986Sandreas.sandberg@arm.com } else if (policy == "partitioned") { 13412391Sjason@lowepower.com iqPolicy = Partitioned; 13511986Sandreas.sandberg@arm.com 13611986Sandreas.sandberg@arm.com //@todo:make work if part_amt doesnt divide evenly. 13711986Sandreas.sandberg@arm.com int part_amt = numEntries / numThreads; 13811986Sandreas.sandberg@arm.com 13911986Sandreas.sandberg@arm.com //Divide ROB up evenly 14011986Sandreas.sandberg@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 14111986Sandreas.sandberg@arm.com maxEntries[tid] = part_amt; 14212391Sjason@lowepower.com } 14311986Sandreas.sandberg@arm.com 14411986Sandreas.sandberg@arm.com DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 14511986Sandreas.sandberg@arm.com "%i entries per thread.\n",part_amt); 14611986Sandreas.sandberg@arm.com } else if (policy == "threshold") { 14711986Sandreas.sandberg@arm.com iqPolicy = Threshold; 14811986Sandreas.sandberg@arm.com 14911986Sandreas.sandberg@arm.com double threshold = (double)params->smtIQThreshold / 100; 15011986Sandreas.sandberg@arm.com 15111986Sandreas.sandberg@arm.com int thresholdIQ = (int)((double)threshold * numEntries); 15211986Sandreas.sandberg@arm.com 15311986Sandreas.sandberg@arm.com //Divide up by threshold amount 15411986Sandreas.sandberg@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 15511986Sandreas.sandberg@arm.com maxEntries[tid] = thresholdIQ; 15611986Sandreas.sandberg@arm.com } 15712037Sandreas.sandberg@arm.com 15812391Sjason@lowepower.com DPRINTF(IQ, "IQ sharing policy set to Threshold:" 15912037Sandreas.sandberg@arm.com "%i entries per thread.\n",thresholdIQ); 16012037Sandreas.sandberg@arm.com } else { 16112037Sandreas.sandberg@arm.com assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 16212037Sandreas.sandberg@arm.com "Partitioned, Threshold}"); 16312037Sandreas.sandberg@arm.com } 16412037Sandreas.sandberg@arm.com} 16512037Sandreas.sandberg@arm.com 16612037Sandreas.sandberg@arm.comtemplate <class Impl> 16712037Sandreas.sandberg@arm.comInstructionQueue<Impl>::~InstructionQueue() 16812037Sandreas.sandberg@arm.com{ 16912037Sandreas.sandberg@arm.com dependGraph.reset(); 17012037Sandreas.sandberg@arm.com#ifdef DEBUG 17112037Sandreas.sandberg@arm.com cprintf("Nodes traversed: %i, removed: %i\n", 17212037Sandreas.sandberg@arm.com dependGraph.nodesTraversed, dependGraph.nodesRemoved); 17312037Sandreas.sandberg@arm.com#endif 17412037Sandreas.sandberg@arm.com} 17512037Sandreas.sandberg@arm.com 17612037Sandreas.sandberg@arm.comtemplate <class Impl> 17712037Sandreas.sandberg@arm.comstd::string 17812037Sandreas.sandberg@arm.comInstructionQueue<Impl>::name() const 17912037Sandreas.sandberg@arm.com{ 18012037Sandreas.sandberg@arm.com return cpu->name() + ".iq"; 18112037Sandreas.sandberg@arm.com} 18212037Sandreas.sandberg@arm.com 18312037Sandreas.sandberg@arm.comtemplate <class Impl> 18412037Sandreas.sandberg@arm.comvoid 18512037Sandreas.sandberg@arm.comInstructionQueue<Impl>::regStats() 18612391Sjason@lowepower.com{ 18712037Sandreas.sandberg@arm.com using namespace Stats; 18812037Sandreas.sandberg@arm.com iqInstsAdded 18912037Sandreas.sandberg@arm.com .name(name() + ".iqInstsAdded") 19012037Sandreas.sandberg@arm.com .desc("Number of instructions added to the IQ (excludes non-spec)") 19112037Sandreas.sandberg@arm.com .prereq(iqInstsAdded); 19212391Sjason@lowepower.com 19312037Sandreas.sandberg@arm.com iqNonSpecInstsAdded 19412037Sandreas.sandberg@arm.com .name(name() + ".iqNonSpecInstsAdded") 19512391Sjason@lowepower.com .desc("Number of non-speculative instructions added to the IQ") 19612391Sjason@lowepower.com .prereq(iqNonSpecInstsAdded); 19712037Sandreas.sandberg@arm.com 19812037Sandreas.sandberg@arm.com iqInstsIssued 19912037Sandreas.sandberg@arm.com .name(name() + ".iqInstsIssued") 20012037Sandreas.sandberg@arm.com .desc("Number of instructions issued") 20112037Sandreas.sandberg@arm.com .prereq(iqInstsIssued); 20212037Sandreas.sandberg@arm.com 20312391Sjason@lowepower.com iqIntInstsIssued 20412391Sjason@lowepower.com .name(name() + ".iqIntInstsIssued") 20512391Sjason@lowepower.com .desc("Number of integer instructions issued") 20612037Sandreas.sandberg@arm.com .prereq(iqIntInstsIssued); 20712037Sandreas.sandberg@arm.com 20812037Sandreas.sandberg@arm.com iqFloatInstsIssued 20912037Sandreas.sandberg@arm.com .name(name() + ".iqFloatInstsIssued") 21012037Sandreas.sandberg@arm.com .desc("Number of float instructions issued") 21112037Sandreas.sandberg@arm.com .prereq(iqFloatInstsIssued); 21212391Sjason@lowepower.com 21312391Sjason@lowepower.com iqBranchInstsIssued 21412391Sjason@lowepower.com .name(name() + ".iqBranchInstsIssued") 21512037Sandreas.sandberg@arm.com .desc("Number of branch instructions issued") 21612037Sandreas.sandberg@arm.com .prereq(iqBranchInstsIssued); 21712037Sandreas.sandberg@arm.com 21812037Sandreas.sandberg@arm.com iqMemInstsIssued 21912037Sandreas.sandberg@arm.com .name(name() + ".iqMemInstsIssued") 22012037Sandreas.sandberg@arm.com .desc("Number of memory instructions issued") 22112391Sjason@lowepower.com .prereq(iqMemInstsIssued); 22212037Sandreas.sandberg@arm.com 22312037Sandreas.sandberg@arm.com iqMiscInstsIssued 22412037Sandreas.sandberg@arm.com .name(name() + ".iqMiscInstsIssued") 22512037Sandreas.sandberg@arm.com .desc("Number of miscellaneous instructions issued") 22612037Sandreas.sandberg@arm.com .prereq(iqMiscInstsIssued); 22712037Sandreas.sandberg@arm.com 22812037Sandreas.sandberg@arm.com iqSquashedInstsIssued 22912037Sandreas.sandberg@arm.com .name(name() + ".iqSquashedInstsIssued") 23012037Sandreas.sandberg@arm.com .desc("Number of squashed instructions issued") 23112037Sandreas.sandberg@arm.com .prereq(iqSquashedInstsIssued); 23212391Sjason@lowepower.com 23312037Sandreas.sandberg@arm.com iqSquashedInstsExamined 23412037Sandreas.sandberg@arm.com .name(name() + ".iqSquashedInstsExamined") 23512037Sandreas.sandberg@arm.com .desc("Number of squashed instructions iterated over during squash;" 23612037Sandreas.sandberg@arm.com " mainly for profiling") 23712391Sjason@lowepower.com .prereq(iqSquashedInstsExamined); 23812391Sjason@lowepower.com 23912037Sandreas.sandberg@arm.com iqSquashedOperandsExamined 24012037Sandreas.sandberg@arm.com .name(name() + ".iqSquashedOperandsExamined") 24112037Sandreas.sandberg@arm.com .desc("Number of squashed operands that are examined and possibly " 24212037Sandreas.sandberg@arm.com "removed from graph") 24312037Sandreas.sandberg@arm.com .prereq(iqSquashedOperandsExamined); 24412037Sandreas.sandberg@arm.com 24512391Sjason@lowepower.com iqSquashedNonSpecRemoved 24612391Sjason@lowepower.com .name(name() + ".iqSquashedNonSpecRemoved") 24712391Sjason@lowepower.com .desc("Number of squashed non-spec instructions that were removed") 24812037Sandreas.sandberg@arm.com .prereq(iqSquashedNonSpecRemoved); 24912037Sandreas.sandberg@arm.com/* 25012037Sandreas.sandberg@arm.com queueResDist 25112037Sandreas.sandberg@arm.com .init(Num_OpClasses, 0, 99, 2) 25212037Sandreas.sandberg@arm.com .name(name() + ".IQ:residence:") 25312037Sandreas.sandberg@arm.com .desc("cycles from dispatch to issue") 25412037Sandreas.sandberg@arm.com .flags(total | pdf | cdf ) 25512037Sandreas.sandberg@arm.com ; 25612037Sandreas.sandberg@arm.com for (int i = 0; i < Num_OpClasses; ++i) { 25712037Sandreas.sandberg@arm.com queueResDist.subname(i, opClassStrings[i]); 25812391Sjason@lowepower.com } 25912391Sjason@lowepower.com*/ 26012391Sjason@lowepower.com numIssuedDist 26112391Sjason@lowepower.com .init(0,totalWidth,1) 26212391Sjason@lowepower.com .name(name() + ".issued_per_cycle") 26312391Sjason@lowepower.com .desc("Number of insts issued each cycle") 26412391Sjason@lowepower.com .flags(pdf) 26512391Sjason@lowepower.com ; 26612391Sjason@lowepower.com/* 26712391Sjason@lowepower.com dist_unissued 26812391Sjason@lowepower.com .init(Num_OpClasses+2) 26912391Sjason@lowepower.com .name(name() + ".unissued_cause") 27012391Sjason@lowepower.com .desc("Reason ready instruction not issued") 27112391Sjason@lowepower.com .flags(pdf | dist) 27212391Sjason@lowepower.com ; 27312391Sjason@lowepower.com for (int i=0; i < (Num_OpClasses + 2); ++i) { 27412391Sjason@lowepower.com dist_unissued.subname(i, unissued_names[i]); 27512391Sjason@lowepower.com } 27612391Sjason@lowepower.com*/ 27712391Sjason@lowepower.com statIssuedInstType 27812391Sjason@lowepower.com .init(numThreads,Enums::Num_OpClass) 27912391Sjason@lowepower.com .name(name() + ".FU_type") 28012391Sjason@lowepower.com .desc("Type of FU issued") 28112391Sjason@lowepower.com .flags(total | pdf | dist) 28212391Sjason@lowepower.com ; 28312391Sjason@lowepower.com statIssuedInstType.ysubnames(Enums::OpClassStrings); 28412391Sjason@lowepower.com 28512391Sjason@lowepower.com // 28612391Sjason@lowepower.com // How long did instructions for a particular FU type wait prior to issue 28712391Sjason@lowepower.com // 28812391Sjason@lowepower.com/* 28912391Sjason@lowepower.com issueDelayDist 29012391Sjason@lowepower.com .init(Num_OpClasses,0,99,2) 29112391Sjason@lowepower.com .name(name() + ".") 29212391Sjason@lowepower.com .desc("cycles from operands ready to issue") 29312391Sjason@lowepower.com .flags(pdf | cdf) 29412391Sjason@lowepower.com ; 29512391Sjason@lowepower.com 296 for (int i=0; i<Num_OpClasses; ++i) { 297 std::stringstream subname; 298 subname << opClassStrings[i] << "_delay"; 299 issueDelayDist.subname(i, subname.str()); 300 } 301*/ 302 issueRate 303 .name(name() + ".rate") 304 .desc("Inst issue rate") 305 .flags(total) 306 ; 307 issueRate = iqInstsIssued / cpu->numCycles; 308 309 statFuBusy 310 .init(Num_OpClasses) 311 .name(name() + ".fu_full") 312 .desc("attempts to use FU when none available") 313 .flags(pdf | dist) 314 ; 315 for (int i=0; i < Num_OpClasses; ++i) { 316 statFuBusy.subname(i, Enums::OpClassStrings[i]); 317 } 318 319 fuBusy 320 .init(numThreads) 321 .name(name() + ".fu_busy_cnt") 322 .desc("FU busy when requested") 323 .flags(total) 324 ; 325 326 fuBusyRate 327 .name(name() + ".fu_busy_rate") 328 .desc("FU busy rate (busy events/executed inst)") 329 .flags(total) 330 ; 331 fuBusyRate = fuBusy / iqInstsIssued; 332 333 for (ThreadID tid = 0; tid < numThreads; tid++) { 334 // Tell mem dependence unit to reg stats as well. 335 memDepUnit[tid].regStats(); 336 } 337 338 intInstQueueReads 339 .name(name() + ".int_inst_queue_reads") 340 .desc("Number of integer instruction queue reads") 341 .flags(total); 342 343 intInstQueueWrites 344 .name(name() + ".int_inst_queue_writes") 345 .desc("Number of integer instruction queue writes") 346 .flags(total); 347 348 intInstQueueWakeupAccesses 349 .name(name() + ".int_inst_queue_wakeup_accesses") 350 .desc("Number of integer instruction queue wakeup accesses") 351 .flags(total); 352 353 fpInstQueueReads 354 .name(name() + ".fp_inst_queue_reads") 355 .desc("Number of floating instruction queue reads") 356 .flags(total); 357 358 fpInstQueueWrites 359 .name(name() + ".fp_inst_queue_writes") 360 .desc("Number of floating instruction queue writes") 361 .flags(total); 362 363 fpInstQueueWakeupQccesses 364 .name(name() + ".fp_inst_queue_wakeup_accesses") 365 .desc("Number of floating instruction queue wakeup accesses") 366 .flags(total); 367 368 intAluAccesses 369 .name(name() + ".int_alu_accesses") 370 .desc("Number of integer alu accesses") 371 .flags(total); 372 373 fpAluAccesses 374 .name(name() + ".fp_alu_accesses") 375 .desc("Number of floating point alu accesses") 376 .flags(total); 377 378} 379 380template <class Impl> 381void 382InstructionQueue<Impl>::resetState() 383{ 384 //Initialize thread IQ counts 385 for (ThreadID tid = 0; tid <numThreads; tid++) { 386 count[tid] = 0; 387 instList[tid].clear(); 388 } 389 390 // Initialize the number of free IQ entries. 391 freeEntries = numEntries; 392 393 // Note that in actuality, the registers corresponding to the logical 394 // registers start off as ready. However this doesn't matter for the 395 // IQ as the instruction should have been correctly told if those 396 // registers are ready in rename. Thus it can all be initialized as 397 // unready. 398 for (int i = 0; i < numPhysRegs; ++i) { 399 regScoreboard[i] = false; 400 } 401 402 for (ThreadID tid = 0; tid < numThreads; ++tid) { 403 squashedSeqNum[tid] = 0; 404 } 405 406 for (int i = 0; i < Num_OpClasses; ++i) { 407 while (!readyInsts[i].empty()) 408 readyInsts[i].pop(); 409 queueOnList[i] = false; 410 readyIt[i] = listOrder.end(); 411 } 412 nonSpecInsts.clear(); 413 listOrder.clear(); 414 deferredMemInsts.clear(); 415} 416 417template <class Impl> 418void 419InstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 420{ 421 activeThreads = at_ptr; 422} 423 424template <class Impl> 425void 426InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 427{ 428 issueToExecuteQueue = i2e_ptr; 429} 430 431template <class Impl> 432void 433InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 434{ 435 timeBuffer = tb_ptr; 436 437 fromCommit = timeBuffer->getWire(-commitToIEWDelay); 438} 439 440template <class Impl> 441void 442InstructionQueue<Impl>::switchOut() 443{ 444/* 445 if (!instList[0].empty() || (numEntries != freeEntries) || 446 !readyInsts[0].empty() || !nonSpecInsts.empty() || !listOrder.empty()) { 447 dumpInsts(); 448// assert(0); 449 } 450*/ 451 resetState(); 452 dependGraph.reset(); 453 instsToExecute.clear(); 454 switchedOut = true; 455 for (ThreadID tid = 0; tid < numThreads; ++tid) { 456 memDepUnit[tid].switchOut(); 457 } 458} 459 460template <class Impl> 461void 462InstructionQueue<Impl>::takeOverFrom() 463{ 464 switchedOut = false; 465} 466 467template <class Impl> 468int 469InstructionQueue<Impl>::entryAmount(ThreadID num_threads) 470{ 471 if (iqPolicy == Partitioned) { 472 return numEntries / num_threads; 473 } else { 474 return 0; 475 } 476} 477 478 479template <class Impl> 480void 481InstructionQueue<Impl>::resetEntries() 482{ 483 if (iqPolicy != Dynamic || numThreads > 1) { 484 int active_threads = activeThreads->size(); 485 486 list<ThreadID>::iterator threads = activeThreads->begin(); 487 list<ThreadID>::iterator end = activeThreads->end(); 488 489 while (threads != end) { 490 ThreadID tid = *threads++; 491 492 if (iqPolicy == Partitioned) { 493 maxEntries[tid] = numEntries / active_threads; 494 } else if(iqPolicy == Threshold && active_threads == 1) { 495 maxEntries[tid] = numEntries; 496 } 497 } 498 } 499} 500 501template <class Impl> 502unsigned 503InstructionQueue<Impl>::numFreeEntries() 504{ 505 return freeEntries; 506} 507 508template <class Impl> 509unsigned 510InstructionQueue<Impl>::numFreeEntries(ThreadID tid) 511{ 512 return maxEntries[tid] - count[tid]; 513} 514 515// Might want to do something more complex if it knows how many instructions 516// will be issued this cycle. 517template <class Impl> 518bool 519InstructionQueue<Impl>::isFull() 520{ 521 if (freeEntries == 0) { 522 return(true); 523 } else { 524 return(false); 525 } 526} 527 528template <class Impl> 529bool 530InstructionQueue<Impl>::isFull(ThreadID tid) 531{ 532 if (numFreeEntries(tid) == 0) { 533 return(true); 534 } else { 535 return(false); 536 } 537} 538 539template <class Impl> 540bool 541InstructionQueue<Impl>::hasReadyInsts() 542{ 543 if (!listOrder.empty()) { 544 return true; 545 } 546 547 for (int i = 0; i < Num_OpClasses; ++i) { 548 if (!readyInsts[i].empty()) { 549 return true; 550 } 551 } 552 553 return false; 554} 555 556template <class Impl> 557void 558InstructionQueue<Impl>::insert(DynInstPtr &new_inst) 559{ 560 new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 561 // Make sure the instruction is valid 562 assert(new_inst); 563 564 DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n", 565 new_inst->seqNum, new_inst->pcState()); 566 567 assert(freeEntries != 0); 568 569 instList[new_inst->threadNumber].push_back(new_inst); 570 571 --freeEntries; 572 573 new_inst->setInIQ(); 574 575 // Look through its source registers (physical regs), and mark any 576 // dependencies. 577 addToDependents(new_inst); 578 579 // Have this instruction set itself as the producer of its destination 580 // register(s). 581 addToProducers(new_inst); 582 583 if (new_inst->isMemRef()) { 584 memDepUnit[new_inst->threadNumber].insert(new_inst); 585 } else { 586 addIfReady(new_inst); 587 } 588 589 ++iqInstsAdded; 590 591 count[new_inst->threadNumber]++; 592 593 assert(freeEntries == (numEntries - countInsts())); 594} 595 596template <class Impl> 597void 598InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) 599{ 600 // @todo: Clean up this code; can do it by setting inst as unable 601 // to issue, then calling normal insert on the inst. 602 new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 603 604 assert(new_inst); 605 606 nonSpecInsts[new_inst->seqNum] = new_inst; 607 608 DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s " 609 "to the IQ.\n", 610 new_inst->seqNum, new_inst->pcState()); 611 612 assert(freeEntries != 0); 613 614 instList[new_inst->threadNumber].push_back(new_inst); 615 616 --freeEntries; 617 618 new_inst->setInIQ(); 619 620 // Have this instruction set itself as the producer of its destination 621 // register(s). 622 addToProducers(new_inst); 623 624 // If it's a memory instruction, add it to the memory dependency 625 // unit. 626 if (new_inst->isMemRef()) { 627 memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 628 } 629 630 ++iqNonSpecInstsAdded; 631 632 count[new_inst->threadNumber]++; 633 634 assert(freeEntries == (numEntries - countInsts())); 635} 636 637template <class Impl> 638void 639InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) 640{ 641 memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 642 643 insertNonSpec(barr_inst); 644} 645 646template <class Impl> 647typename Impl::DynInstPtr 648InstructionQueue<Impl>::getInstToExecute() 649{ 650 assert(!instsToExecute.empty()); 651 DynInstPtr inst = instsToExecute.front(); 652 instsToExecute.pop_front(); 653 if (inst->isFloating()){ 654 fpInstQueueReads++; 655 } else { 656 intInstQueueReads++; 657 } 658 return inst; 659} 660 661template <class Impl> 662void 663InstructionQueue<Impl>::addToOrderList(OpClass op_class) 664{ 665 assert(!readyInsts[op_class].empty()); 666 667 ListOrderEntry queue_entry; 668 669 queue_entry.queueType = op_class; 670 671 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 672 673 ListOrderIt list_it = listOrder.begin(); 674 ListOrderIt list_end_it = listOrder.end(); 675 676 while (list_it != list_end_it) { 677 if ((*list_it).oldestInst > queue_entry.oldestInst) { 678 break; 679 } 680 681 list_it++; 682 } 683 684 readyIt[op_class] = listOrder.insert(list_it, queue_entry); 685 queueOnList[op_class] = true; 686} 687 688template <class Impl> 689void 690InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 691{ 692 // Get iterator of next item on the list 693 // Delete the original iterator 694 // Determine if the next item is either the end of the list or younger 695 // than the new instruction. If so, then add in a new iterator right here. 696 // If not, then move along. 697 ListOrderEntry queue_entry; 698 OpClass op_class = (*list_order_it).queueType; 699 ListOrderIt next_it = list_order_it; 700 701 ++next_it; 702 703 queue_entry.queueType = op_class; 704 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 705 706 while (next_it != listOrder.end() && 707 (*next_it).oldestInst < queue_entry.oldestInst) { 708 ++next_it; 709 } 710 711 readyIt[op_class] = listOrder.insert(next_it, queue_entry); 712} 713 714template <class Impl> 715void 716InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 717{ 718 DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 719 // The CPU could have been sleeping until this op completed (*extremely* 720 // long latency op). Wake it if it was. This may be overkill. 721 if (isSwitchedOut()) { 722 DPRINTF(IQ, "FU completion not processed, IQ is switched out [sn:%lli]\n", 723 inst->seqNum); 724 return; 725 } 726 727 iewStage->wakeCPU(); 728 729 if (fu_idx > -1) 730 fuPool->freeUnitNextCycle(fu_idx); 731 732 // @todo: Ensure that these FU Completions happen at the beginning 733 // of a cycle, otherwise they could add too many instructions to 734 // the queue. 735 issueToExecuteQueue->access(-1)->size++; 736 instsToExecute.push_back(inst); 737} 738 739// @todo: Figure out a better way to remove the squashed items from the 740// lists. Checking the top item of each list to see if it's squashed 741// wastes time and forces jumps. 742template <class Impl> 743void 744InstructionQueue<Impl>::scheduleReadyInsts() 745{ 746 DPRINTF(IQ, "Attempting to schedule ready instructions from " 747 "the IQ.\n"); 748 749 IssueStruct *i2e_info = issueToExecuteQueue->access(0); 750 751 DynInstPtr deferred_mem_inst; 752 int total_deferred_mem_issued = 0; 753 while (total_deferred_mem_issued < totalWidth && 754 (deferred_mem_inst = getDeferredMemInstToExecute()) != 0) { 755 issueToExecuteQueue->access(0)->size++; 756 instsToExecute.push_back(deferred_mem_inst); 757 total_deferred_mem_issued++; 758 } 759 760 // Have iterator to head of the list 761 // While I haven't exceeded bandwidth or reached the end of the list, 762 // Try to get a FU that can do what this op needs. 763 // If successful, change the oldestInst to the new top of the list, put 764 // the queue in the proper place in the list. 765 // Increment the iterator. 766 // This will avoid trying to schedule a certain op class if there are no 767 // FUs that handle it. 768 ListOrderIt order_it = listOrder.begin(); 769 ListOrderIt order_end_it = listOrder.end(); 770 int total_issued = 0; 771 772 while (total_issued < (totalWidth - total_deferred_mem_issued) && 773 iewStage->canIssue() && 774 order_it != order_end_it) { 775 OpClass op_class = (*order_it).queueType; 776 777 assert(!readyInsts[op_class].empty()); 778 779 DynInstPtr issuing_inst = readyInsts[op_class].top(); 780 781 issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++; 782 783 assert(issuing_inst->seqNum == (*order_it).oldestInst); 784 785 if (issuing_inst->isSquashed()) { 786 readyInsts[op_class].pop(); 787 788 if (!readyInsts[op_class].empty()) { 789 moveToYoungerInst(order_it); 790 } else { 791 readyIt[op_class] = listOrder.end(); 792 queueOnList[op_class] = false; 793 } 794 795 listOrder.erase(order_it++); 796 797 ++iqSquashedInstsIssued; 798 799 continue; 800 } 801 802 int idx = -2; 803 int op_latency = 1; 804 ThreadID tid = issuing_inst->threadNumber; 805 806 if (op_class != No_OpClass) { 807 idx = fuPool->getUnit(op_class); 808 issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++; 809 if (idx > -1) { 810 op_latency = fuPool->getOpLatency(op_class); 811 } 812 } 813 814 // If we have an instruction that doesn't require a FU, or a 815 // valid FU, then schedule for execution. 816 if (idx == -2 || idx != -1) { 817 if (op_latency == 1) { 818 i2e_info->size++; 819 instsToExecute.push_back(issuing_inst); 820 821 // Add the FU onto the list of FU's to be freed next 822 // cycle if we used one. 823 if (idx >= 0) 824 fuPool->freeUnitNextCycle(idx); 825 } else { 826 int issue_latency = fuPool->getIssueLatency(op_class); 827 // Generate completion event for the FU 828 FUCompletion *execution = new FUCompletion(issuing_inst, 829 idx, this); 830 831 cpu->schedule(execution, curTick() + cpu->ticks(op_latency - 1)); 832 833 // @todo: Enforce that issue_latency == 1 or op_latency 834 if (issue_latency > 1) { 835 // If FU isn't pipelined, then it must be freed 836 // upon the execution completing. 837 execution->setFreeFU(); 838 } else { 839 // Add the FU onto the list of FU's to be freed next cycle. 840 fuPool->freeUnitNextCycle(idx); 841 } 842 } 843 844 DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 845 "[sn:%lli]\n", 846 tid, issuing_inst->pcState(), 847 issuing_inst->seqNum); 848 849 readyInsts[op_class].pop(); 850 851 if (!readyInsts[op_class].empty()) { 852 moveToYoungerInst(order_it); 853 } else { 854 readyIt[op_class] = listOrder.end(); 855 queueOnList[op_class] = false; 856 } 857 858 issuing_inst->setIssued(); 859 ++total_issued; 860 861#if TRACING_ON 862 issuing_inst->issueTick = curTick(); 863#endif 864 865 if (!issuing_inst->isMemRef()) { 866 // Memory instructions can not be freed from the IQ until they 867 // complete. 868 ++freeEntries; 869 count[tid]--; 870 issuing_inst->clearInIQ(); 871 } else { 872 memDepUnit[tid].issue(issuing_inst); 873 } 874 875 listOrder.erase(order_it++); 876 statIssuedInstType[tid][op_class]++; 877 iewStage->incrWb(issuing_inst->seqNum); 878 } else { 879 statFuBusy[op_class]++; 880 fuBusy[tid]++; 881 ++order_it; 882 } 883 } 884 885 numIssuedDist.sample(total_issued); 886 iqInstsIssued+= total_issued; 887 888 // If we issued any instructions, tell the CPU we had activity. 889 // @todo If the way deferred memory instructions are handeled due to 890 // translation changes then the deferredMemInsts condition should be removed 891 // from the code below. 892 if (total_issued || total_deferred_mem_issued || deferredMemInsts.size()) { 893 cpu->activityThisCycle(); 894 } else { 895 DPRINTF(IQ, "Not able to schedule any instructions.\n"); 896 } 897} 898 899template <class Impl> 900void 901InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 902{ 903 DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 904 "to execute.\n", inst); 905 906 NonSpecMapIt inst_it = nonSpecInsts.find(inst); 907 908 assert(inst_it != nonSpecInsts.end()); 909 910 ThreadID tid = (*inst_it).second->threadNumber; 911 912 (*inst_it).second->setAtCommit(); 913 914 (*inst_it).second->setCanIssue(); 915 916 if (!(*inst_it).second->isMemRef()) { 917 addIfReady((*inst_it).second); 918 } else { 919 memDepUnit[tid].nonSpecInstReady((*inst_it).second); 920 } 921 922 (*inst_it).second = NULL; 923 924 nonSpecInsts.erase(inst_it); 925} 926 927template <class Impl> 928void 929InstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 930{ 931 DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 932 tid,inst); 933 934 ListIt iq_it = instList[tid].begin(); 935 936 while (iq_it != instList[tid].end() && 937 (*iq_it)->seqNum <= inst) { 938 ++iq_it; 939 instList[tid].pop_front(); 940 } 941 942 assert(freeEntries == (numEntries - countInsts())); 943} 944 945template <class Impl> 946int 947InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 948{ 949 int dependents = 0; 950 951 // The instruction queue here takes care of both floating and int ops 952 if (completed_inst->isFloating()) { 953 fpInstQueueWakeupQccesses++; 954 } else { 955 intInstQueueWakeupAccesses++; 956 } 957 958 DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 959 960 assert(!completed_inst->isSquashed()); 961 962 // Tell the memory dependence unit to wake any dependents on this 963 // instruction if it is a memory instruction. Also complete the memory 964 // instruction at this point since we know it executed without issues. 965 // @todo: Might want to rename "completeMemInst" to something that 966 // indicates that it won't need to be replayed, and call this 967 // earlier. Might not be a big deal. 968 if (completed_inst->isMemRef()) { 969 memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 970 completeMemInst(completed_inst); 971 } else if (completed_inst->isMemBarrier() || 972 completed_inst->isWriteBarrier()) { 973 memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 974 } 975 976 for (int dest_reg_idx = 0; 977 dest_reg_idx < completed_inst->numDestRegs(); 978 dest_reg_idx++) 979 { 980 PhysRegIndex dest_reg = 981 completed_inst->renamedDestRegIdx(dest_reg_idx); 982 983 // Special case of uniq or control registers. They are not 984 // handled by the IQ and thus have no dependency graph entry. 985 // @todo Figure out a cleaner way to handle this. 986 if (dest_reg >= numPhysRegs) { 987 DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg, 988 numPhysRegs); 989 continue; 990 } 991 992 DPRINTF(IQ, "Waking any dependents on register %i.\n", 993 (int) dest_reg); 994 995 //Go through the dependency chain, marking the registers as 996 //ready within the waiting instructions. 997 DynInstPtr dep_inst = dependGraph.pop(dest_reg); 998 999 while (dep_inst) { 1000 DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] " 1001 "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 1002 1003 // Might want to give more information to the instruction 1004 // so that it knows which of its source registers is 1005 // ready. However that would mean that the dependency 1006 // graph entries would need to hold the src_reg_idx. 1007 dep_inst->markSrcRegReady(); 1008 1009 addIfReady(dep_inst); 1010 1011 dep_inst = dependGraph.pop(dest_reg); 1012 1013 ++dependents; 1014 } 1015 1016 // Reset the head node now that all of its dependents have 1017 // been woken up. 1018 assert(dependGraph.empty(dest_reg)); 1019 dependGraph.clearInst(dest_reg); 1020 1021 // Mark the scoreboard as having that register ready. 1022 regScoreboard[dest_reg] = true; 1023 } 1024 return dependents; 1025} 1026 1027template <class Impl> 1028void 1029InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 1030{ 1031 OpClass op_class = ready_inst->opClass(); 1032 1033 readyInsts[op_class].push(ready_inst); 1034 1035 // Will need to reorder the list if either a queue is not on the list, 1036 // or it has an older instruction than last time. 1037 if (!queueOnList[op_class]) { 1038 addToOrderList(op_class); 1039 } else if (readyInsts[op_class].top()->seqNum < 1040 (*readyIt[op_class]).oldestInst) { 1041 listOrder.erase(readyIt[op_class]); 1042 addToOrderList(op_class); 1043 } 1044 1045 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 1046 "the ready list, PC %s opclass:%i [sn:%lli].\n", 1047 ready_inst->pcState(), op_class, ready_inst->seqNum); 1048} 1049 1050template <class Impl> 1051void 1052InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 1053{ 1054 DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 1055 1056 // Reset DTB translation state 1057 resched_inst->translationStarted = false; 1058 resched_inst->translationCompleted = false; 1059 1060 resched_inst->clearCanIssue(); 1061 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 1062} 1063 1064template <class Impl> 1065void 1066InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 1067{ 1068 memDepUnit[replay_inst->threadNumber].replay(replay_inst); 1069} 1070 1071template <class Impl> 1072void 1073InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 1074{ 1075 ThreadID tid = completed_inst->threadNumber; 1076 1077 DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n", 1078 completed_inst->pcState(), completed_inst->seqNum); 1079 1080 ++freeEntries; 1081 1082 completed_inst->memOpDone = true; 1083 1084 memDepUnit[tid].completed(completed_inst); 1085 count[tid]--; 1086} 1087 1088template <class Impl> 1089void 1090InstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst) 1091{ 1092 deferredMemInsts.push_back(deferred_inst); 1093} 1094 1095template <class Impl> 1096typename Impl::DynInstPtr 1097InstructionQueue<Impl>::getDeferredMemInstToExecute() 1098{ 1099 for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); 1100 ++it) { 1101 if ((*it)->translationCompleted || (*it)->isSquashed()) { 1102 DynInstPtr ret = *it; 1103 deferredMemInsts.erase(it); 1104 return ret; 1105 } 1106 } 1107 return NULL; 1108} 1109 1110template <class Impl> 1111void 1112InstructionQueue<Impl>::violation(DynInstPtr &store, 1113 DynInstPtr &faulting_load) 1114{ 1115 intInstQueueWrites++; 1116 memDepUnit[store->threadNumber].violation(store, faulting_load); 1117} 1118 1119template <class Impl> 1120void 1121InstructionQueue<Impl>::squash(ThreadID tid) 1122{ 1123 DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 1124 "the IQ.\n", tid); 1125 1126 // Read instruction sequence number of last instruction out of the 1127 // time buffer. 1128 squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 1129 1130 // Call doSquash if there are insts in the IQ 1131 if (count[tid] > 0) { 1132 doSquash(tid); 1133 } 1134 1135 // Also tell the memory dependence unit to squash. 1136 memDepUnit[tid].squash(squashedSeqNum[tid], tid); 1137} 1138 1139template <class Impl> 1140void 1141InstructionQueue<Impl>::doSquash(ThreadID tid) 1142{ 1143 // Start at the tail. 1144 ListIt squash_it = instList[tid].end(); 1145 --squash_it; 1146 1147 DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 1148 tid, squashedSeqNum[tid]); 1149 1150 // Squash any instructions younger than the squashed sequence number 1151 // given. 1152 while (squash_it != instList[tid].end() && 1153 (*squash_it)->seqNum > squashedSeqNum[tid]) { 1154 1155 DynInstPtr squashed_inst = (*squash_it); 1156 squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 1157 1158 // Only handle the instruction if it actually is in the IQ and 1159 // hasn't already been squashed in the IQ. 1160 if (squashed_inst->threadNumber != tid || 1161 squashed_inst->isSquashedInIQ()) { 1162 --squash_it; 1163 continue; 1164 } 1165 1166 if (!squashed_inst->isIssued() || 1167 (squashed_inst->isMemRef() && 1168 !squashed_inst->memOpDone)) { 1169 1170 DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", 1171 tid, squashed_inst->seqNum, squashed_inst->pcState()); 1172 1173 // Remove the instruction from the dependency list. 1174 if (!squashed_inst->isNonSpeculative() && 1175 !squashed_inst->isStoreConditional() && 1176 !squashed_inst->isMemBarrier() && 1177 !squashed_inst->isWriteBarrier()) { 1178 1179 for (int src_reg_idx = 0; 1180 src_reg_idx < squashed_inst->numSrcRegs(); 1181 src_reg_idx++) 1182 { 1183 PhysRegIndex src_reg = 1184 squashed_inst->renamedSrcRegIdx(src_reg_idx); 1185 1186 // Only remove it from the dependency graph if it 1187 // was placed there in the first place. 1188 1189 // Instead of doing a linked list traversal, we 1190 // can just remove these squashed instructions 1191 // either at issue time, or when the register is 1192 // overwritten. The only downside to this is it 1193 // leaves more room for error. 1194 1195 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 1196 src_reg < numPhysRegs) { 1197 dependGraph.remove(src_reg, squashed_inst); 1198 } 1199 1200 1201 ++iqSquashedOperandsExamined; 1202 } 1203 } else if (!squashed_inst->isStoreConditional() || 1204 !squashed_inst->isCompleted()) { 1205 NonSpecMapIt ns_inst_it = 1206 nonSpecInsts.find(squashed_inst->seqNum); 1207 1208 if (ns_inst_it == nonSpecInsts.end()) { 1209 assert(squashed_inst->getFault() != NoFault); 1210 } else { 1211 1212 (*ns_inst_it).second = NULL; 1213 1214 nonSpecInsts.erase(ns_inst_it); 1215 1216 ++iqSquashedNonSpecRemoved; 1217 } 1218 } 1219 1220 // Might want to also clear out the head of the dependency graph. 1221 1222 // Mark it as squashed within the IQ. 1223 squashed_inst->setSquashedInIQ(); 1224 1225 // @todo: Remove this hack where several statuses are set so the 1226 // inst will flow through the rest of the pipeline. 1227 squashed_inst->setIssued(); 1228 squashed_inst->setCanCommit(); 1229 squashed_inst->clearInIQ(); 1230 1231 //Update Thread IQ Count 1232 count[squashed_inst->threadNumber]--; 1233 1234 ++freeEntries; 1235 } 1236 1237 instList[tid].erase(squash_it--); 1238 ++iqSquashedInstsExamined; 1239 } 1240} 1241 1242template <class Impl> 1243bool 1244InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 1245{ 1246 // Loop through the instruction's source registers, adding 1247 // them to the dependency list if they are not ready. 1248 int8_t total_src_regs = new_inst->numSrcRegs(); 1249 bool return_val = false; 1250 1251 for (int src_reg_idx = 0; 1252 src_reg_idx < total_src_regs; 1253 src_reg_idx++) 1254 { 1255 // Only add it to the dependency graph if it's not ready. 1256 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 1257 PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 1258 1259 // Check the IQ's scoreboard to make sure the register 1260 // hasn't become ready while the instruction was in flight 1261 // between stages. Only if it really isn't ready should 1262 // it be added to the dependency graph. 1263 if (src_reg >= numPhysRegs) { 1264 continue; 1265 } else if (regScoreboard[src_reg] == false) { 1266 DPRINTF(IQ, "Instruction PC %s has src reg %i that " 1267 "is being added to the dependency chain.\n", 1268 new_inst->pcState(), src_reg); 1269 1270 dependGraph.insert(src_reg, new_inst); 1271 1272 // Change the return value to indicate that something 1273 // was added to the dependency graph. 1274 return_val = true; 1275 } else { 1276 DPRINTF(IQ, "Instruction PC %s has src reg %i that " 1277 "became ready before it reached the IQ.\n", 1278 new_inst->pcState(), src_reg); 1279 // Mark a register ready within the instruction. 1280 new_inst->markSrcRegReady(src_reg_idx); 1281 } 1282 } 1283 } 1284 1285 return return_val; 1286} 1287 1288template <class Impl> 1289void 1290InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) 1291{ 1292 // Nothing really needs to be marked when an instruction becomes 1293 // the producer of a register's value, but for convenience a ptr 1294 // to the producing instruction will be placed in the head node of 1295 // the dependency links. 1296 int8_t total_dest_regs = new_inst->numDestRegs(); 1297 1298 for (int dest_reg_idx = 0; 1299 dest_reg_idx < total_dest_regs; 1300 dest_reg_idx++) 1301 { 1302 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 1303 1304 // Instructions that use the misc regs will have a reg number 1305 // higher than the normal physical registers. In this case these 1306 // registers are not renamed, and there is no need to track 1307 // dependencies as these instructions must be executed at commit. 1308 if (dest_reg >= numPhysRegs) { 1309 continue; 1310 } 1311 1312 if (!dependGraph.empty(dest_reg)) { 1313 dependGraph.dump(); 1314 panic("Dependency graph %i not empty!", dest_reg); 1315 } 1316 1317 dependGraph.setInst(dest_reg, new_inst); 1318 1319 // Mark the scoreboard to say it's not yet ready. 1320 regScoreboard[dest_reg] = false; 1321 } 1322} 1323 1324template <class Impl> 1325void 1326InstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 1327{ 1328 // If the instruction now has all of its source registers 1329 // available, then add it to the list of ready instructions. 1330 if (inst->readyToIssue()) { 1331 1332 //Add the instruction to the proper ready list. 1333 if (inst->isMemRef()) { 1334 1335 DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 1336 1337 // Message to the mem dependence unit that this instruction has 1338 // its registers ready. 1339 memDepUnit[inst->threadNumber].regsReady(inst); 1340 1341 return; 1342 } 1343 1344 OpClass op_class = inst->opClass(); 1345 1346 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 1347 "the ready list, PC %s opclass:%i [sn:%lli].\n", 1348 inst->pcState(), op_class, inst->seqNum); 1349 1350 readyInsts[op_class].push(inst); 1351 1352 // Will need to reorder the list if either a queue is not on the list, 1353 // or it has an older instruction than last time. 1354 if (!queueOnList[op_class]) { 1355 addToOrderList(op_class); 1356 } else if (readyInsts[op_class].top()->seqNum < 1357 (*readyIt[op_class]).oldestInst) { 1358 listOrder.erase(readyIt[op_class]); 1359 addToOrderList(op_class); 1360 } 1361 } 1362} 1363 1364template <class Impl> 1365int 1366InstructionQueue<Impl>::countInsts() 1367{ 1368#if 0 1369 //ksewell:This works but definitely could use a cleaner write 1370 //with a more intuitive way of counting. Right now it's 1371 //just brute force .... 1372 // Change the #if if you want to use this method. 1373 int total_insts = 0; 1374 1375 for (ThreadID tid = 0; tid < numThreads; ++tid) { 1376 ListIt count_it = instList[tid].begin(); 1377 1378 while (count_it != instList[tid].end()) { 1379 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 1380 if (!(*count_it)->isIssued()) { 1381 ++total_insts; 1382 } else if ((*count_it)->isMemRef() && 1383 !(*count_it)->memOpDone) { 1384 // Loads that have not been marked as executed still count 1385 // towards the total instructions. 1386 ++total_insts; 1387 } 1388 } 1389 1390 ++count_it; 1391 } 1392 } 1393 1394 return total_insts; 1395#else 1396 return numEntries - freeEntries; 1397#endif 1398} 1399 1400template <class Impl> 1401void 1402InstructionQueue<Impl>::dumpLists() 1403{ 1404 for (int i = 0; i < Num_OpClasses; ++i) { 1405 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 1406 1407 cprintf("\n"); 1408 } 1409 1410 cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 1411 1412 NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 1413 NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 1414 1415 cprintf("Non speculative list: "); 1416 1417 while (non_spec_it != non_spec_end_it) { 1418 cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(), 1419 (*non_spec_it).second->seqNum); 1420 ++non_spec_it; 1421 } 1422 1423 cprintf("\n"); 1424 1425 ListOrderIt list_order_it = listOrder.begin(); 1426 ListOrderIt list_order_end_it = listOrder.end(); 1427 int i = 1; 1428 1429 cprintf("List order: "); 1430 1431 while (list_order_it != list_order_end_it) { 1432 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 1433 (*list_order_it).oldestInst); 1434 1435 ++list_order_it; 1436 ++i; 1437 } 1438 1439 cprintf("\n"); 1440} 1441 1442 1443template <class Impl> 1444void 1445InstructionQueue<Impl>::dumpInsts() 1446{ 1447 for (ThreadID tid = 0; tid < numThreads; ++tid) { 1448 int num = 0; 1449 int valid_num = 0; 1450 ListIt inst_list_it = instList[tid].begin(); 1451 1452 while (inst_list_it != instList[tid].end()) { 1453 cprintf("Instruction:%i\n", num); 1454 if (!(*inst_list_it)->isSquashed()) { 1455 if (!(*inst_list_it)->isIssued()) { 1456 ++valid_num; 1457 cprintf("Count:%i\n", valid_num); 1458 } else if ((*inst_list_it)->isMemRef() && 1459 !(*inst_list_it)->memOpDone) { 1460 // Loads that have not been marked as executed 1461 // still count towards the total instructions. 1462 ++valid_num; 1463 cprintf("Count:%i\n", valid_num); 1464 } 1465 } 1466 1467 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 1468 "Issued:%i\nSquashed:%i\n", 1469 (*inst_list_it)->pcState(), 1470 (*inst_list_it)->seqNum, 1471 (*inst_list_it)->threadNumber, 1472 (*inst_list_it)->isIssued(), 1473 (*inst_list_it)->isSquashed()); 1474 1475 if ((*inst_list_it)->isMemRef()) { 1476 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 1477 } 1478 1479 cprintf("\n"); 1480 1481 inst_list_it++; 1482 ++num; 1483 } 1484 } 1485 1486 cprintf("Insts to Execute list:\n"); 1487 1488 int num = 0; 1489 int valid_num = 0; 1490 ListIt inst_list_it = instsToExecute.begin(); 1491 1492 while (inst_list_it != instsToExecute.end()) 1493 { 1494 cprintf("Instruction:%i\n", 1495 num); 1496 if (!(*inst_list_it)->isSquashed()) { 1497 if (!(*inst_list_it)->isIssued()) { 1498 ++valid_num; 1499 cprintf("Count:%i\n", valid_num); 1500 } else if ((*inst_list_it)->isMemRef() && 1501 !(*inst_list_it)->memOpDone) { 1502 // Loads that have not been marked as executed 1503 // still count towards the total instructions. 1504 ++valid_num; 1505 cprintf("Count:%i\n", valid_num); 1506 } 1507 } 1508 1509 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 1510 "Issued:%i\nSquashed:%i\n", 1511 (*inst_list_it)->pcState(), 1512 (*inst_list_it)->seqNum, 1513 (*inst_list_it)->threadNumber, 1514 (*inst_list_it)->isIssued(), 1515 (*inst_list_it)->isSquashed()); 1516 1517 if ((*inst_list_it)->isMemRef()) { 1518 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 1519 } 1520 1521 cprintf("\n"); 1522 1523 inst_list_it++; 1524 ++num; 1525 } 1526} 1527