inst_queue_impl.hh revision 8471
12686Sksewell@umich.edu/* 22100SN/A * Copyright (c) 2011 ARM Limited 32022SN/A * All rights reserved. 42022SN/A * 52043SN/A * The license below extends only to copyright in the software and shall 62024SN/A * not be construed as granting a license to any other intellectual 72024SN/A * property including but not limited to intellectual property relating 82043SN/A * to a hardware implementation of the functionality of the software 92686Sksewell@umich.edu * licensed hereunder. You may use the software subject to the license 102024SN/A * terms below provided that you ensure that this notice is replicated 112022SN/A * unmodified and in its entirety in all distributions of the software, 122083SN/A * modified or unmodified, in source code or in binary form. 132686Sksewell@umich.edu * 142101SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 152043SN/A * All rights reserved. 162043SN/A * 172101SN/A * Redistribution and use in source and binary forms, with or without 182101SN/A * modification, are permitted provided that the following conditions are 192686Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 202686Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 212101SN/A * redistributions in binary form must reproduce the above copyright 222101SN/A * notice, this list of conditions and the following disclaimer in the 232101SN/A * documentation and/or other materials provided with the distribution; 242046SN/A * neither the name of the copyright holders nor the names of its 252686Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 262686Sksewell@umich.edu * this software without specific prior written permission. 272686Sksewell@umich.edu * 282470SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292686Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302686Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312686Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322686Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332686Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342686Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352470SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362241SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372101SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382495SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392495SN/A * 402495SN/A * Authors: Kevin Lim 412101SN/A * Korey Sewell 422495SN/A */ 432495SN/A 442495SN/A#include <limits> 452101SN/A#include <vector> 462101SN/A 472495SN/A#include "cpu/o3/fu_pool.hh" 482495SN/A#include "cpu/o3/inst_queue.hh" 492495SN/A#include "debug/IQ.hh" 502495SN/A#include "enums/OpClass.hh" 512495SN/A#include "params/DerivO3CPU.hh" 522495SN/A#include "sim/core.hh" 532495SN/A 542495SN/Ausing namespace std; 552495SN/A 562495SN/Atemplate <class Impl> 572495SN/AInstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 582495SN/A int fu_idx, InstructionQueue<Impl> *iq_ptr) 592495SN/A : Event(Stat_Event_Pri), inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), 602101SN/A freeFU(false) 612101SN/A{ 622101SN/A this->setFlags(Event::AutoDelete); 632101SN/A} 642101SN/A 652101SN/Atemplate <class Impl> 662101SN/Avoid 672101SN/AInstructionQueue<Impl>::FUCompletion::process() 682101SN/A{ 692101SN/A iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 702495SN/A inst = NULL; 712495SN/A} 722495SN/A 732495SN/A 742495SN/Atemplate <class Impl> 752495SN/Aconst char * 762495SN/AInstructionQueue<Impl>::FUCompletion::description() const 772495SN/A{ 782495SN/A return "Functional unit completion"; 792495SN/A} 802495SN/A 812495SN/Atemplate <class Impl> 822495SN/AInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 832495SN/A DerivO3CPUParams *params) 842495SN/A : cpu(cpu_ptr), 852043SN/A iewStage(iew_ptr), 862043SN/A fuPool(params->fuPool), 872025SN/A numEntries(params->numIQEntries), 882043SN/A totalWidth(params->issueWidth), 892686Sksewell@umich.edu numPhysIntRegs(params->numPhysIntRegs), 902686Sksewell@umich.edu numPhysFloatRegs(params->numPhysFloatRegs), 912123SN/A commitToIEWDelay(params->commitToIEWDelay) 922101SN/A{ 932686Sksewell@umich.edu assert(fuPool); 942686Sksewell@umich.edu 952101SN/A switchedOut = false; 962042SN/A 972101SN/A numThreads = params->numThreads; 982686Sksewell@umich.edu 992686Sksewell@umich.edu // Set the number of physical registers as the number of int + float 1002686Sksewell@umich.edu numPhysRegs = numPhysIntRegs + numPhysFloatRegs; 1012686Sksewell@umich.edu 1022101SN/A //Create an entry for each physical register within the 1032101SN/A //dependency graph. 1042042SN/A dependGraph.resize(numPhysRegs); 1052101SN/A 1062686Sksewell@umich.edu // Resize the register scoreboard. 1072686Sksewell@umich.edu regScoreboard.resize(numPhysRegs); 1082686Sksewell@umich.edu 1092686Sksewell@umich.edu //Initialize Mem Dependence Units 1102101SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1112083SN/A memDepUnit[tid].init(params, tid); 1122686Sksewell@umich.edu memDepUnit[tid].setIQ(this); 1132686Sksewell@umich.edu } 1142101SN/A 1152043SN/A resetState(); 1162025SN/A 1172043SN/A std::string policy = params->smtIQPolicy; 1182686Sksewell@umich.edu 1192616SN/A //Convert string to lowercase 1202616SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1212616SN/A (int(*)(int)) tolower); 1222616SN/A 1232101SN/A //Figure out resource sharing policy 1242083SN/A if (policy == "dynamic") { 1252025SN/A iqPolicy = Dynamic; 1262043SN/A 1272686Sksewell@umich.edu //Set Max Entries to Total ROB Capacity 1282686Sksewell@umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 1292686Sksewell@umich.edu maxEntries[tid] = numEntries; 1302686Sksewell@umich.edu } 1312025SN/A 1322686Sksewell@umich.edu } else if (policy == "partitioned") { 1332101SN/A iqPolicy = Partitioned; 1342616SN/A 1352616SN/A //@todo:make work if part_amt doesnt divide evenly. 1362101SN/A int part_amt = numEntries / numThreads; 1372101SN/A 1382616SN/A //Divide ROB up evenly 1392616SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1402101SN/A maxEntries[tid] = part_amt; 1412101SN/A } 1422084SN/A 1432025SN/A DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 1442495SN/A "%i entries per thread.\n",part_amt); 1452495SN/A } else if (policy == "threshold") { 1462495SN/A iqPolicy = Threshold; 1472616SN/A 1482495SN/A double threshold = (double)params->smtIQThreshold / 100; 1492616SN/A 1502495SN/A int thresholdIQ = (int)((double)threshold * numEntries); 1512495SN/A 1522495SN/A //Divide up by threshold amount 1532495SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1542495SN/A maxEntries[tid] = thresholdIQ; 1552495SN/A } 1562101SN/A 1572043SN/A DPRINTF(IQ, "IQ sharing policy set to Threshold:" 1582025SN/A "%i entries per thread.\n",thresholdIQ); 1592495SN/A } else { 1602495SN/A assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 1612495SN/A "Partitioned, Threshold}"); 1622495SN/A } 1632495SN/A} 1642495SN/A 1652101SN/Atemplate <class Impl> 1662084SN/AInstructionQueue<Impl>::~InstructionQueue() 1672024SN/A{ 1682043SN/A dependGraph.reset(); 1692239SN/A#ifdef DEBUG 1702239SN/A cprintf("Nodes traversed: %i, removed: %i\n", 1712101SN/A dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1722101SN/A#endif 1732101SN/A} 1742101SN/A 1752101SN/Atemplate <class Impl> 1762101SN/Astd::string 1772043SN/AInstructionQueue<Impl>::name() const 1782043SN/A{ 1792025SN/A return cpu->name() + ".iq"; 1802043SN/A} 1812043SN/A 1822101SN/Atemplate <class Impl> 1832101SN/Avoid 1842101SN/AInstructionQueue<Impl>::regStats() 1852686Sksewell@umich.edu{ 1862686Sksewell@umich.edu using namespace Stats; 1872101SN/A iqInstsAdded 1882043SN/A .name(name() + ".iqInstsAdded") 1892025SN/A .desc("Number of instructions added to the IQ (excludes non-spec)") 1902043SN/A .prereq(iqInstsAdded); 1912239SN/A 1922101SN/A iqNonSpecInstsAdded 1932104SN/A .name(name() + ".iqNonSpecInstsAdded") 1942101SN/A .desc("Number of non-speculative instructions added to the IQ") 1952101SN/A .prereq(iqNonSpecInstsAdded); 1962101SN/A 1972101SN/A iqInstsIssued 1982101SN/A .name(name() + ".iqInstsIssued") 1992043SN/A .desc("Number of instructions issued") 2002043SN/A .prereq(iqInstsIssued); 2012043SN/A 2022101SN/A iqIntInstsIssued 2032686Sksewell@umich.edu .name(name() + ".iqIntInstsIssued") 2042686Sksewell@umich.edu .desc("Number of integer instructions issued") 2052686Sksewell@umich.edu .prereq(iqIntInstsIssued); 2062686Sksewell@umich.edu 2072686Sksewell@umich.edu iqFloatInstsIssued 2082686Sksewell@umich.edu .name(name() + ".iqFloatInstsIssued") 2092686Sksewell@umich.edu .desc("Number of float instructions issued") 2102101SN/A .prereq(iqFloatInstsIssued); 2112043SN/A 2122043SN/A iqBranchInstsIssued 2132043SN/A .name(name() + ".iqBranchInstsIssued") 2142101SN/A .desc("Number of branch instructions issued") 2152101SN/A .prereq(iqBranchInstsIssued); 2162101SN/A 2172043SN/A iqMemInstsIssued 2182043SN/A .name(name() + ".iqMemInstsIssued") 2192043SN/A .desc("Number of memory instructions issued") 2202123SN/A .prereq(iqMemInstsIssued); 2212239SN/A 2222686Sksewell@umich.edu iqMiscInstsIssued 2232686Sksewell@umich.edu .name(name() + ".iqMiscInstsIssued") 2242043SN/A .desc("Number of miscellaneous instructions issued") 2252043SN/A .prereq(iqMiscInstsIssued); 2262100SN/A 2272686Sksewell@umich.edu iqSquashedInstsIssued 2282686Sksewell@umich.edu .name(name() + ".iqSquashedInstsIssued") 2292686Sksewell@umich.edu .desc("Number of squashed instructions issued") 2302686Sksewell@umich.edu .prereq(iqSquashedInstsIssued); 2312239SN/A 2322686Sksewell@umich.edu iqSquashedInstsExamined 2332686Sksewell@umich.edu .name(name() + ".iqSquashedInstsExamined") 2342043SN/A .desc("Number of squashed instructions iterated over during squash;" 2352084SN/A " mainly for profiling") 2362024SN/A .prereq(iqSquashedInstsExamined); 2372101SN/A 2382686Sksewell@umich.edu iqSquashedOperandsExamined 2392239SN/A .name(name() + ".iqSquashedOperandsExamined") 2402239SN/A .desc("Number of squashed operands that are examined and possibly " 2412239SN/A "removed from graph") 2422495SN/A .prereq(iqSquashedOperandsExamined); 2432495SN/A 2442495SN/A iqSquashedNonSpecRemoved 2452495SN/A .name(name() + ".iqSquashedNonSpecRemoved") 2462495SN/A .desc("Number of squashed non-spec instructions that were removed") 2472495SN/A .prereq(iqSquashedNonSpecRemoved); 2482495SN/A/* 2492495SN/A queueResDist 2502084SN/A .init(Num_OpClasses, 0, 99, 2) 2512084SN/A .name(name() + ".IQ:residence:") 2522024SN/A .desc("cycles from dispatch to issue") 2532101SN/A .flags(total | pdf | cdf ) 2542101SN/A ; 2552101SN/A for (int i = 0; i < Num_OpClasses; ++i) { 2562101SN/A queueResDist.subname(i, opClassStrings[i]); 2572686Sksewell@umich.edu } 2582686Sksewell@umich.edu*/ 2592686Sksewell@umich.edu numIssuedDist 2602686Sksewell@umich.edu .init(0,totalWidth,1) 2612052SN/A .name(name() + ".issued_per_cycle") 2622686Sksewell@umich.edu .desc("Number of insts issued each cycle") 2632686Sksewell@umich.edu .flags(pdf) 2642686Sksewell@umich.edu ; 2652101SN/A/* 2662101SN/A dist_unissued 2672686Sksewell@umich.edu .init(Num_OpClasses+2) 2682686Sksewell@umich.edu .name(name() + ".unissued_cause") 2692101SN/A .desc("Reason ready instruction not issued") 2702101SN/A .flags(pdf | dist) 2712686Sksewell@umich.edu ; 2722686Sksewell@umich.edu for (int i=0; i < (Num_OpClasses + 2); ++i) { 2732686Sksewell@umich.edu dist_unissued.subname(i, unissued_names[i]); 2742686Sksewell@umich.edu } 2752686Sksewell@umich.edu*/ 2762686Sksewell@umich.edu statIssuedInstType 2772101SN/A .init(numThreads,Enums::Num_OpClass) 2782101SN/A .name(name() + ".FU_type") 2792686Sksewell@umich.edu .desc("Type of FU issued") 2802027SN/A .flags(total | pdf | dist) 2812686Sksewell@umich.edu ; 2822686Sksewell@umich.edu statIssuedInstType.ysubnames(Enums::OpClassStrings); 2832686Sksewell@umich.edu 2842101SN/A // 2852101SN/A // How long did instructions for a particular FU type wait prior to issue 2862101SN/A // 2872101SN/A/* 2882101SN/A issueDelayDist 2892686Sksewell@umich.edu .init(Num_OpClasses,0,99,2) 2902686Sksewell@umich.edu .name(name() + ".") 2912686Sksewell@umich.edu .desc("cycles from operands ready to issue") 2922686Sksewell@umich.edu .flags(pdf | cdf) 2932686Sksewell@umich.edu ; 2942101SN/A 2952101SN/A for (int i=0; i<Num_OpClasses; ++i) { 2962101SN/A std::stringstream subname; 2972101SN/A subname << opClassStrings[i] << "_delay"; 2982101SN/A issueDelayDist.subname(i, subname.str()); 2992101SN/A } 3002043SN/A*/ 3012027SN/A issueRate 3022101SN/A .name(name() + ".rate") 3032101SN/A .desc("Inst issue rate") 3042041SN/A .flags(total) 3052101SN/A ; 3062101SN/A issueRate = iqInstsIssued / cpu->numCycles; 3072686Sksewell@umich.edu 3082573SN/A statFuBusy 3092495SN/A .init(Num_OpClasses) 3102495SN/A .name(name() + ".fu_full") 3112573SN/A .desc("attempts to use FU when none available") 3122573SN/A .flags(pdf | dist) 3132573SN/A ; 3142616SN/A for (int i=0; i < Num_OpClasses; ++i) { 3152573SN/A statFuBusy.subname(i, Enums::OpClassStrings[i]); 3162573SN/A } 3172616SN/A 3182573SN/A fuBusy 3192573SN/A .init(numThreads) 3202616SN/A .name(name() + ".fu_busy_cnt") 3212573SN/A .desc("FU busy when requested") 3222573SN/A .flags(total) 3232616SN/A ; 3242573SN/A 3252573SN/A fuBusyRate 3262616SN/A .name(name() + ".fu_busy_rate") 3272573SN/A .desc("FU busy rate (busy events/executed inst)") 3282573SN/A .flags(total) 3292686Sksewell@umich.edu ; 3302573SN/A fuBusyRate = fuBusy / iqInstsIssued; 3312573SN/A 3322573SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 3332686Sksewell@umich.edu // Tell mem dependence unit to reg stats as well. 3342686Sksewell@umich.edu memDepUnit[tid].regStats(); 3352686Sksewell@umich.edu } 3362686Sksewell@umich.edu 3372573SN/A intInstQueueReads 3382573SN/A .name(name() + ".int_inst_queue_reads") 3392573SN/A .desc("Number of integer instruction queue reads") 3402573SN/A .flags(total); 3412616SN/A 3422616SN/A intInstQueueWrites 3432616SN/A .name(name() + ".int_inst_queue_writes") 3442573SN/A .desc("Number of integer instruction queue writes") 3452573SN/A .flags(total); 3462573SN/A 3472616SN/A intInstQueueWakeupAccesses 3482573SN/A .name(name() + ".int_inst_queue_wakeup_accesses") 3492616SN/A .desc("Number of integer instruction queue wakeup accesses") 3502573SN/A .flags(total); 3512616SN/A 3522573SN/A fpInstQueueReads 3532573SN/A .name(name() + ".fp_inst_queue_reads") 3542573SN/A .desc("Number of floating instruction queue reads") 3552616SN/A .flags(total); 3562573SN/A 3572616SN/A fpInstQueueWrites 3582573SN/A .name(name() + ".fp_inst_queue_writes") 3592616SN/A .desc("Number of floating instruction queue writes") 3602573SN/A .flags(total); 3612573SN/A 3622573SN/A fpInstQueueWakeupQccesses 3632573SN/A .name(name() + ".fp_inst_queue_wakeup_accesses") 3642616SN/A .desc("Number of floating instruction queue wakeup accesses") 3652573SN/A .flags(total); 3662573SN/A 3672573SN/A intAluAccesses 3682495SN/A .name(name() + ".int_alu_accesses") 3692616SN/A .desc("Number of integer alu accesses") 3702495SN/A .flags(total); 3712495SN/A 3722686Sksewell@umich.edu fpAluAccesses 3732686Sksewell@umich.edu .name(name() + ".fp_alu_accesses") 3742686Sksewell@umich.edu .desc("Number of floating point alu accesses") 3752686Sksewell@umich.edu .flags(total); 3762686Sksewell@umich.edu 3772686Sksewell@umich.edu} 3782686Sksewell@umich.edu 3792101SN/Atemplate <class Impl> 3802101SN/Avoid 3812025SN/AInstructionQueue<Impl>::resetState() 3822101SN/A{ 3832686Sksewell@umich.edu //Initialize thread IQ counts 3842686Sksewell@umich.edu for (ThreadID tid = 0; tid <numThreads; tid++) { 3852686Sksewell@umich.edu count[tid] = 0; 3862686Sksewell@umich.edu instList[tid].clear(); 3872686Sksewell@umich.edu } 3882686Sksewell@umich.edu 3892101SN/A // Initialize the number of free IQ entries. 3902686Sksewell@umich.edu freeEntries = numEntries; 3912686Sksewell@umich.edu 3922686Sksewell@umich.edu // Note that in actuality, the registers corresponding to the logical 3932686Sksewell@umich.edu // registers start off as ready. However this doesn't matter for the 3942686Sksewell@umich.edu // IQ as the instruction should have been correctly told if those 3952101SN/A // registers are ready in rename. Thus it can all be initialized as 3962101SN/A // unready. 3972101SN/A for (int i = 0; i < numPhysRegs; ++i) { 3982043SN/A regScoreboard[i] = false; 3992027SN/A } 4002101SN/A 4012101SN/A for (ThreadID tid = 0; tid < numThreads; ++tid) { 4022101SN/A squashedSeqNum[tid] = 0; 4032686Sksewell@umich.edu } 4042572SN/A 4052572SN/A for (int i = 0; i < Num_OpClasses; ++i) { 4062101SN/A while (!readyInsts[i].empty()) 4072601SN/A readyInsts[i].pop(); 4082601SN/A queueOnList[i] = false; 4092601SN/A readyIt[i] = listOrder.end(); 4102601SN/A } 4112601SN/A nonSpecInsts.clear(); 4122601SN/A listOrder.clear(); 4132601SN/A deferredMemInsts.clear(); 4142686Sksewell@umich.edu} 4152101SN/A 4162101SN/Atemplate <class Impl> 4172027SN/Avoid 4182572SN/AInstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 4192686Sksewell@umich.edu{ 4202686Sksewell@umich.edu activeThreads = at_ptr; 4212686Sksewell@umich.edu} 4222686Sksewell@umich.edu 4232686Sksewell@umich.edutemplate <class Impl> 4242686Sksewell@umich.eduvoid 4252686Sksewell@umich.eduInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 4262686Sksewell@umich.edu{ 4272686Sksewell@umich.edu issueToExecuteQueue = i2e_ptr; 4282686Sksewell@umich.edu} 4292686Sksewell@umich.edu 4302686Sksewell@umich.edutemplate <class Impl> 4312686Sksewell@umich.eduvoid 4322686Sksewell@umich.eduInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 4332686Sksewell@umich.edu{ 4342686Sksewell@umich.edu timeBuffer = tb_ptr; 4352686Sksewell@umich.edu 4362101SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 4372101SN/A} 4382027SN/A 4392572SN/Atemplate <class Impl> 4402101SN/Avoid 4412686Sksewell@umich.eduInstructionQueue<Impl>::switchOut() 4422686Sksewell@umich.edu{ 4432686Sksewell@umich.edu/* 4442101SN/A if (!instList[0].empty() || (numEntries != freeEntries) || 4452101SN/A !readyInsts[0].empty() || !nonSpecInsts.empty() || !listOrder.empty()) { 4462027SN/A dumpInsts(); 4472686Sksewell@umich.edu// assert(0); 4482686Sksewell@umich.edu } 4492686Sksewell@umich.edu*/ 4502686Sksewell@umich.edu resetState(); 4512686Sksewell@umich.edu dependGraph.reset(); 4522602SN/A instsToExecute.clear(); 4532602SN/A switchedOut = true; 4542602SN/A for (ThreadID tid = 0; tid < numThreads; ++tid) { 4552101SN/A memDepUnit[tid].switchOut(); 4562101SN/A } 4572027SN/A} 4582572SN/A 4592603SN/Atemplate <class Impl> 4602686Sksewell@umich.eduvoid 4612686Sksewell@umich.eduInstructionQueue<Impl>::takeOverFrom() 4622686Sksewell@umich.edu{ 4632101SN/A switchedOut = false; 4642055SN/A} 4652686Sksewell@umich.edu 4662686Sksewell@umich.edutemplate <class Impl> 4672686Sksewell@umich.eduint 4682101SN/AInstructionQueue<Impl>::entryAmount(ThreadID num_threads) 4692101SN/A{ 4702602SN/A if (iqPolicy == Partitioned) { 4712602SN/A return numEntries / num_threads; 4722603SN/A } else { 4732686Sksewell@umich.edu return 0; 4742686Sksewell@umich.edu } 4752686Sksewell@umich.edu} 4762686Sksewell@umich.edu 4772686Sksewell@umich.edu 4782686Sksewell@umich.edutemplate <class Impl> 4792686Sksewell@umich.eduvoid 4802686Sksewell@umich.eduInstructionQueue<Impl>::resetEntries() 4812686Sksewell@umich.edu{ 4822686Sksewell@umich.edu if (iqPolicy != Dynamic || numThreads > 1) { 4832686Sksewell@umich.edu int active_threads = activeThreads->size(); 4842686Sksewell@umich.edu 4852686Sksewell@umich.edu list<ThreadID>::iterator threads = activeThreads->begin(); 4862686Sksewell@umich.edu list<ThreadID>::iterator end = activeThreads->end(); 4872686Sksewell@umich.edu 4882686Sksewell@umich.edu while (threads != end) { 4892602SN/A ThreadID tid = *threads++; 4902602SN/A 4912602SN/A if (iqPolicy == Partitioned) { 4922602SN/A maxEntries[tid] = numEntries / active_threads; 4932686Sksewell@umich.edu } else if(iqPolicy == Threshold && active_threads == 1) { 4942686Sksewell@umich.edu maxEntries[tid] = numEntries; 4952686Sksewell@umich.edu } 4962686Sksewell@umich.edu } 4972686Sksewell@umich.edu } 4982686Sksewell@umich.edu} 4992686Sksewell@umich.edu 5002686Sksewell@umich.edutemplate <class Impl> 5012686Sksewell@umich.eduunsigned 5022686Sksewell@umich.eduInstructionQueue<Impl>::numFreeEntries() 5032686Sksewell@umich.edu{ 5042686Sksewell@umich.edu return freeEntries; 5052686Sksewell@umich.edu} 5062686Sksewell@umich.edu 5072686Sksewell@umich.edutemplate <class Impl> 5082686Sksewell@umich.eduunsigned 5092686Sksewell@umich.eduInstructionQueue<Impl>::numFreeEntries(ThreadID tid) 5102602SN/A{ 5112602SN/A return maxEntries[tid] - count[tid]; 5122101SN/A} 5132055SN/A 5142101SN/A// Might want to do something more complex if it knows how many instructions 5152572SN/A// will be issued this cycle. 5162572SN/Atemplate <class Impl> 5172101SN/Abool 5182686Sksewell@umich.eduInstructionQueue<Impl>::isFull() 5192686Sksewell@umich.edu{ 5202686Sksewell@umich.edu if (freeEntries == 0) { 5212686Sksewell@umich.edu return(true); 5222686Sksewell@umich.edu } else { 5232686Sksewell@umich.edu return(false); 5242686Sksewell@umich.edu } 5252686Sksewell@umich.edu} 5262101SN/A 5272101SN/Atemplate <class Impl> 5282027SN/Abool 5292572SN/AInstructionQueue<Impl>::isFull(ThreadID tid) 5302686Sksewell@umich.edu{ 5312686Sksewell@umich.edu if (numFreeEntries(tid) == 0) { 5322686Sksewell@umich.edu return(true); 5332686Sksewell@umich.edu } else { 5342686Sksewell@umich.edu return(false); 5352686Sksewell@umich.edu } 5362686Sksewell@umich.edu} 5372686Sksewell@umich.edu 5382686Sksewell@umich.edutemplate <class Impl> 5392686Sksewell@umich.edubool 5402686Sksewell@umich.eduInstructionQueue<Impl>::hasReadyInsts() 5412686Sksewell@umich.edu{ 5422686Sksewell@umich.edu if (!listOrder.empty()) { 5432686Sksewell@umich.edu return true; 5442686Sksewell@umich.edu } 5452686Sksewell@umich.edu 5462686Sksewell@umich.edu for (int i = 0; i < Num_OpClasses; ++i) { 5472101SN/A if (!readyInsts[i].empty()) { 5482101SN/A return true; 5492027SN/A } 5502572SN/A } 5512101SN/A 5522686Sksewell@umich.edu return false; 5532686Sksewell@umich.edu} 5542686Sksewell@umich.edu 5552686Sksewell@umich.edutemplate <class Impl> 5562686Sksewell@umich.eduvoid 5572686Sksewell@umich.eduInstructionQueue<Impl>::insert(DynInstPtr &new_inst) 5582686Sksewell@umich.edu{ 5592101SN/A new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 5602101SN/A // Make sure the instruction is valid 5612027SN/A assert(new_inst); 5622101SN/A 5632686Sksewell@umich.edu DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n", 5642686Sksewell@umich.edu new_inst->seqNum, new_inst->pcState()); 5652101SN/A 5662027SN/A assert(freeEntries != 0); 5672605SN/A 5682686Sksewell@umich.edu instList[new_inst->threadNumber].push_back(new_inst); 5692605SN/A 5702101SN/A --freeEntries; 5712101SN/A 5722027SN/A new_inst->setInIQ(); 5732572SN/A 5742686Sksewell@umich.edu // Look through its source registers (physical regs), and mark any 5752686Sksewell@umich.edu // dependencies. 5762686Sksewell@umich.edu addToDependents(new_inst); 5772686Sksewell@umich.edu 5782101SN/A // Have this instruction set itself as the producer of its destination 5792101SN/A // register(s). 5802602SN/A addToProducers(new_inst); 5812602SN/A 5822604SN/A if (new_inst->isMemRef()) { 5832686Sksewell@umich.edu memDepUnit[new_inst->threadNumber].insert(new_inst); 5842686Sksewell@umich.edu } else { 5852686Sksewell@umich.edu addIfReady(new_inst); 5862686Sksewell@umich.edu } 5872686Sksewell@umich.edu 5882686Sksewell@umich.edu ++iqInstsAdded; 5892686Sksewell@umich.edu 5902686Sksewell@umich.edu count[new_inst->threadNumber]++; 5912686Sksewell@umich.edu 5922686Sksewell@umich.edu assert(freeEntries == (numEntries - countInsts())); 5932686Sksewell@umich.edu} 5942686Sksewell@umich.edu 5952686Sksewell@umich.edutemplate <class Impl> 5962686Sksewell@umich.eduvoid 5972686Sksewell@umich.eduInstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) 5982686Sksewell@umich.edu{ 5992602SN/A // @todo: Clean up this code; can do it by setting inst as unable 6002602SN/A // to issue, then calling normal insert on the inst. 6012602SN/A new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 6022602SN/A 6032686Sksewell@umich.edu assert(new_inst); 6042686Sksewell@umich.edu 6052686Sksewell@umich.edu nonSpecInsts[new_inst->seqNum] = new_inst; 6062686Sksewell@umich.edu 6072686Sksewell@umich.edu DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s " 6082686Sksewell@umich.edu "to the IQ.\n", 6092686Sksewell@umich.edu new_inst->seqNum, new_inst->pcState()); 6102686Sksewell@umich.edu 6112686Sksewell@umich.edu assert(freeEntries != 0); 6122686Sksewell@umich.edu 6132686Sksewell@umich.edu instList[new_inst->threadNumber].push_back(new_inst); 6142686Sksewell@umich.edu 6152686Sksewell@umich.edu --freeEntries; 6162686Sksewell@umich.edu 6172686Sksewell@umich.edu new_inst->setInIQ(); 6182686Sksewell@umich.edu 6192686Sksewell@umich.edu // Have this instruction set itself as the producer of its destination 6202602SN/A // register(s). 6212602SN/A addToProducers(new_inst); 6222101SN/A 6232027SN/A // If it's a memory instruction, add it to the memory dependency 6242101SN/A // unit. 6252101SN/A if (new_inst->isMemRef()) { 6262605SN/A memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 6272686Sksewell@umich.edu } 6282686Sksewell@umich.edu 6292686Sksewell@umich.edu ++iqNonSpecInstsAdded; 6302101SN/A 6312101SN/A count[new_inst->threadNumber]++; 6322027SN/A 6332101SN/A assert(freeEntries == (numEntries - countInsts())); 6342101SN/A} 6352101SN/A 6362101SN/Atemplate <class Impl> 6372686Sksewell@umich.eduvoid 6382686Sksewell@umich.eduInstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) 6392686Sksewell@umich.edu{ 6402686Sksewell@umich.edu memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 6412101SN/A 6422101SN/A insertNonSpec(barr_inst); 6432101SN/A} 6442101SN/A 6452101SN/Atemplate <class Impl> 6462101SN/Atypename Impl::DynInstPtr 6472572SN/AInstructionQueue<Impl>::getInstToExecute() 6482572SN/A{ 6492101SN/A assert(!instsToExecute.empty()); 6502605SN/A DynInstPtr inst = instsToExecute.front(); 6512607SN/A instsToExecute.pop_front(); 6522607SN/A if (inst->isFloating()){ 6532101SN/A fpInstQueueReads++; 6542605SN/A } else { 6552607SN/A intInstQueueReads++; 6562607SN/A } 6572101SN/A return inst; 6582605SN/A} 6592607SN/A 6602607SN/Atemplate <class Impl> 6612101SN/Avoid 6622605SN/AInstructionQueue<Impl>::addToOrderList(OpClass op_class) 6632607SN/A{ 6642607SN/A assert(!readyInsts[op_class].empty()); 6652101SN/A 6662605SN/A ListOrderEntry queue_entry; 6672607SN/A 6682607SN/A queue_entry.queueType = op_class; 6692101SN/A 6702605SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 6712686Sksewell@umich.edu 6722686Sksewell@umich.edu ListOrderIt list_it = listOrder.begin(); 6732101SN/A ListOrderIt list_end_it = listOrder.end(); 6742101SN/A 6752101SN/A while (list_it != list_end_it) { 6762101SN/A if ((*list_it).oldestInst > queue_entry.oldestInst) { 6772572SN/A break; 6782101SN/A } 6792101SN/A 6802607SN/A list_it++; 6812686Sksewell@umich.edu } 6822686Sksewell@umich.edu 6832686Sksewell@umich.edu readyIt[op_class] = listOrder.insert(list_it, queue_entry); 6842686Sksewell@umich.edu queueOnList[op_class] = true; 6852607SN/A} 6862607SN/A 6872686Sksewell@umich.edutemplate <class Impl> 6882686Sksewell@umich.eduvoid 6892686Sksewell@umich.eduInstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 6902686Sksewell@umich.edu{ 6912607SN/A // Get iterator of next item on the list 6922101SN/A // Delete the original iterator 6932101SN/A // Determine if the next item is either the end of the list or younger 6942101SN/A // than the new instruction. If so, then add in a new iterator right here. 6952605SN/A // If not, then move along. 6962607SN/A ListOrderEntry queue_entry; 6972686Sksewell@umich.edu OpClass op_class = (*list_order_it).queueType; 6982686Sksewell@umich.edu ListOrderIt next_it = list_order_it; 6992686Sksewell@umich.edu 7002686Sksewell@umich.edu ++next_it; 7012607SN/A 7022607SN/A queue_entry.queueType = op_class; 7032686Sksewell@umich.edu queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 7042686Sksewell@umich.edu 7052686Sksewell@umich.edu while (next_it != listOrder.end() && 7062686Sksewell@umich.edu (*next_it).oldestInst < queue_entry.oldestInst) { 7072607SN/A ++next_it; 7082135SN/A } 7092135SN/A 7102101SN/A readyIt[op_class] = listOrder.insert(next_it, queue_entry); 7112101SN/A} 7122572SN/A 7132686Sksewell@umich.edutemplate <class Impl> 7142101SN/Avoid 7152101SN/AInstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 7162572SN/A{ 7172686Sksewell@umich.edu DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 7182686Sksewell@umich.edu // The CPU could have been sleeping until this op completed (*extremely* 7192101SN/A // long latency op). Wake it if it was. This may be overkill. 7202686Sksewell@umich.edu if (isSwitchedOut()) { 7212686Sksewell@umich.edu DPRINTF(IQ, "FU completion not processed, IQ is switched out [sn:%lli]\n", 7222686Sksewell@umich.edu inst->seqNum); 7232686Sksewell@umich.edu return; 7242686Sksewell@umich.edu } 7252686Sksewell@umich.edu 7262686Sksewell@umich.edu iewStage->wakeCPU(); 7272686Sksewell@umich.edu 7282686Sksewell@umich.edu if (fu_idx > -1) 7292686Sksewell@umich.edu fuPool->freeUnitNextCycle(fu_idx); 7302686Sksewell@umich.edu 7312686Sksewell@umich.edu // @todo: Ensure that these FU Completions happen at the beginning 7322101SN/A // of a cycle, otherwise they could add too many instructions to 7332101SN/A // the queue. 7342602SN/A issueToExecuteQueue->access(-1)->size++; 7352602SN/A instsToExecute.push_back(inst); 7362608SN/A} 7372686Sksewell@umich.edu 7382686Sksewell@umich.edu// @todo: Figure out a better way to remove the squashed items from the 7392686Sksewell@umich.edu// lists. Checking the top item of each list to see if it's squashed 7402686Sksewell@umich.edu// wastes time and forces jumps. 7412686Sksewell@umich.edutemplate <class Impl> 7422686Sksewell@umich.eduvoid 7432686Sksewell@umich.eduInstructionQueue<Impl>::scheduleReadyInsts() 7442686Sksewell@umich.edu{ 7452686Sksewell@umich.edu DPRINTF(IQ, "Attempting to schedule ready instructions from " 7462686Sksewell@umich.edu "the IQ.\n"); 7472686Sksewell@umich.edu 7482686Sksewell@umich.edu IssueStruct *i2e_info = issueToExecuteQueue->access(0); 7492686Sksewell@umich.edu 7502686Sksewell@umich.edu DynInstPtr deferred_mem_inst; 7512686Sksewell@umich.edu int total_deferred_mem_issued = 0; 7522686Sksewell@umich.edu while (total_deferred_mem_issued < totalWidth && 7532686Sksewell@umich.edu (deferred_mem_inst = getDeferredMemInstToExecute()) != 0) { 7542686Sksewell@umich.edu issueToExecuteQueue->access(0)->size++; 7552686Sksewell@umich.edu instsToExecute.push_back(deferred_mem_inst); 7562686Sksewell@umich.edu total_deferred_mem_issued++; 7572686Sksewell@umich.edu } 7582686Sksewell@umich.edu 7592602SN/A // Have iterator to head of the list 7602602SN/A // While I haven't exceeded bandwidth or reached the end of the list, 7612602SN/A // Try to get a FU that can do what this op needs. 7622602SN/A // If successful, change the oldestInst to the new top of the list, put 7632686Sksewell@umich.edu // the queue in the proper place in the list. 7642686Sksewell@umich.edu // Increment the iterator. 7652686Sksewell@umich.edu // This will avoid trying to schedule a certain op class if there are no 7662686Sksewell@umich.edu // FUs that handle it. 7672686Sksewell@umich.edu ListOrderIt order_it = listOrder.begin(); 7682686Sksewell@umich.edu ListOrderIt order_end_it = listOrder.end(); 7692686Sksewell@umich.edu int total_issued = 0; 7702686Sksewell@umich.edu 7712686Sksewell@umich.edu while (total_issued < (totalWidth - total_deferred_mem_issued) && 7722686Sksewell@umich.edu iewStage->canIssue() && 7732686Sksewell@umich.edu order_it != order_end_it) { 7742686Sksewell@umich.edu OpClass op_class = (*order_it).queueType; 7752686Sksewell@umich.edu 7762686Sksewell@umich.edu assert(!readyInsts[op_class].empty()); 7772686Sksewell@umich.edu 7782686Sksewell@umich.edu DynInstPtr issuing_inst = readyInsts[op_class].top(); 7792686Sksewell@umich.edu 7802686Sksewell@umich.edu issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++; 7812686Sksewell@umich.edu 7822686Sksewell@umich.edu assert(issuing_inst->seqNum == (*order_it).oldestInst); 7832686Sksewell@umich.edu 7842686Sksewell@umich.edu if (issuing_inst->isSquashed()) { 7852686Sksewell@umich.edu readyInsts[op_class].pop(); 7862686Sksewell@umich.edu 7872602SN/A if (!readyInsts[op_class].empty()) { 7882602SN/A moveToYoungerInst(order_it); 7892101SN/A } else { 7902101SN/A readyIt[op_class] = listOrder.end(); 7912101SN/A queueOnList[op_class] = false; 7922101SN/A } 7932101SN/A 7942101SN/A listOrder.erase(order_it++); 7952101SN/A 7962686Sksewell@umich.edu ++iqSquashedInstsIssued; 7972686Sksewell@umich.edu 7982686Sksewell@umich.edu continue; 7992101SN/A } 8002101SN/A 8012101SN/A int idx = -2; 8022101SN/A int op_latency = 1; 8032101SN/A ThreadID tid = issuing_inst->threadNumber; 8042101SN/A 8052101SN/A if (op_class != No_OpClass) { 8062101SN/A idx = fuPool->getUnit(op_class); 8072686Sksewell@umich.edu issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++; 8082686Sksewell@umich.edu if (idx > -1) { 8092101SN/A op_latency = fuPool->getOpLatency(op_class); 8102101SN/A } 8112101SN/A } 8122101SN/A 8132686Sksewell@umich.edu // If we have an instruction that doesn't require a FU, or a 8142101SN/A // valid FU, then schedule for execution. 8152101SN/A if (idx == -2 || idx != -1) { 8162101SN/A if (op_latency == 1) { 8172101SN/A i2e_info->size++; 8182101SN/A instsToExecute.push_back(issuing_inst); 8192101SN/A 8202101SN/A // Add the FU onto the list of FU's to be freed next 8212101SN/A // cycle if we used one. 8222101SN/A if (idx >= 0) 8232101SN/A fuPool->freeUnitNextCycle(idx); 8242101SN/A } else { 8252101SN/A int issue_latency = fuPool->getIssueLatency(op_class); 8262101SN/A // Generate completion event for the FU 8272686Sksewell@umich.edu FUCompletion *execution = new FUCompletion(issuing_inst, 8282686Sksewell@umich.edu idx, this); 8292686Sksewell@umich.edu 8302686Sksewell@umich.edu cpu->schedule(execution, curTick() + cpu->ticks(op_latency - 1)); 8312101SN/A 8322043SN/A // @todo: Enforce that issue_latency == 1 or op_latency 8332027SN/A if (issue_latency > 1) { 8342101SN/A // If FU isn't pipelined, then it must be freed 8352686Sksewell@umich.edu // upon the execution completing. 8362686Sksewell@umich.edu execution->setFreeFU(); 8372686Sksewell@umich.edu } else { 8382686Sksewell@umich.edu // Add the FU onto the list of FU's to be freed next cycle. 8392046SN/A fuPool->freeUnitNextCycle(idx); 8402084SN/A } 8412686Sksewell@umich.edu } 8422101SN/A 8432027SN/A DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 8442686Sksewell@umich.edu "[sn:%lli]\n", 8452686Sksewell@umich.edu tid, issuing_inst->pcState(), 8462686Sksewell@umich.edu issuing_inst->seqNum); 8472686Sksewell@umich.edu 8482686Sksewell@umich.edu readyInsts[op_class].pop(); 8492686Sksewell@umich.edu 8502686Sksewell@umich.edu if (!readyInsts[op_class].empty()) { 8512686Sksewell@umich.edu moveToYoungerInst(order_it); 8522686Sksewell@umich.edu } else { 8532686Sksewell@umich.edu readyIt[op_class] = listOrder.end(); 8542686Sksewell@umich.edu queueOnList[op_class] = false; 8552686Sksewell@umich.edu } 8562686Sksewell@umich.edu 8572686Sksewell@umich.edu issuing_inst->setIssued(); 8582686Sksewell@umich.edu ++total_issued; 8592686Sksewell@umich.edu 8602027SN/A#if TRACING_ON 8612686Sksewell@umich.edu issuing_inst->issueTick = curTick(); 8622686Sksewell@umich.edu#endif 8632686Sksewell@umich.edu 8642686Sksewell@umich.edu if (!issuing_inst->isMemRef()) { 8652686Sksewell@umich.edu // Memory instructions can not be freed from the IQ until they 8662686Sksewell@umich.edu // complete. 8672686Sksewell@umich.edu ++freeEntries; 8682686Sksewell@umich.edu count[tid]--; 8692686Sksewell@umich.edu issuing_inst->clearInIQ(); 8702027SN/A } else { 8712686Sksewell@umich.edu memDepUnit[tid].issue(issuing_inst); 8722686Sksewell@umich.edu } 8732686Sksewell@umich.edu 8742686Sksewell@umich.edu listOrder.erase(order_it++); 8752686Sksewell@umich.edu statIssuedInstType[tid][op_class]++; 8762686Sksewell@umich.edu iewStage->incrWb(issuing_inst->seqNum); 8772686Sksewell@umich.edu } else { 8782686Sksewell@umich.edu statFuBusy[op_class]++; 8792027SN/A fuBusy[tid]++; 8802686Sksewell@umich.edu ++order_it; 8812686Sksewell@umich.edu } 8822686Sksewell@umich.edu } 8832686Sksewell@umich.edu 8842686Sksewell@umich.edu numIssuedDist.sample(total_issued); 8852686Sksewell@umich.edu iqInstsIssued+= total_issued; 8862686Sksewell@umich.edu 8872686Sksewell@umich.edu // If we issued any instructions, tell the CPU we had activity. 8882027SN/A // @todo If the way deferred memory instructions are handeled due to 8892686Sksewell@umich.edu // translation changes then the deferredMemInsts condition should be removed 8902686Sksewell@umich.edu // from the code below. 8912686Sksewell@umich.edu if (total_issued || total_deferred_mem_issued || deferredMemInsts.size()) { 8922686Sksewell@umich.edu cpu->activityThisCycle(); 8932686Sksewell@umich.edu } else { 8942686Sksewell@umich.edu DPRINTF(IQ, "Not able to schedule any instructions.\n"); 8952686Sksewell@umich.edu } 8962046SN/A} 8972686Sksewell@umich.edu 8982101SN/Atemplate <class Impl> 8992043SN/Avoid 9002025SN/AInstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 9012686Sksewell@umich.edu{ 9022686Sksewell@umich.edu DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 9032686Sksewell@umich.edu "to execute.\n", inst); 9042686Sksewell@umich.edu 9052686Sksewell@umich.edu NonSpecMapIt inst_it = nonSpecInsts.find(inst); 9062046SN/A 9072084SN/A assert(inst_it != nonSpecInsts.end()); 9082024SN/A 9092686Sksewell@umich.edu ThreadID tid = (*inst_it).second->threadNumber; 9102043SN/A 9112043SN/A (*inst_it).second->setAtCommit(); 9122686Sksewell@umich.edu 9132686Sksewell@umich.edu (*inst_it).second->setCanIssue(); 9142686Sksewell@umich.edu 9152686Sksewell@umich.edu if (!(*inst_it).second->isMemRef()) { 9162027SN/A addIfReady((*inst_it).second); 9172686Sksewell@umich.edu } else { 9182686Sksewell@umich.edu memDepUnit[tid].nonSpecInstReady((*inst_it).second); 9192686Sksewell@umich.edu } 9202686Sksewell@umich.edu 9212686Sksewell@umich.edu (*inst_it).second = NULL; 9222686Sksewell@umich.edu 9232686Sksewell@umich.edu nonSpecInsts.erase(inst_it); 9242686Sksewell@umich.edu} 9252686Sksewell@umich.edu 9262686Sksewell@umich.edutemplate <class Impl> 9272686Sksewell@umich.eduvoid 9282686Sksewell@umich.eduInstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 9292686Sksewell@umich.edu{ 9302043SN/A DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 9312043SN/A tid,inst); 9322027SN/A 9332043SN/A ListIt iq_it = instList[tid].begin(); 9342101SN/A 9352686Sksewell@umich.edu while (iq_it != instList[tid].end() && 9362686Sksewell@umich.edu (*iq_it)->seqNum <= inst) { 9372686Sksewell@umich.edu ++iq_it; 9382686Sksewell@umich.edu instList[tid].pop_front(); 9392686Sksewell@umich.edu } 9402686Sksewell@umich.edu 9412686Sksewell@umich.edu assert(freeEntries == (numEntries - countInsts())); 9422686Sksewell@umich.edu} 9432686Sksewell@umich.edu 9442686Sksewell@umich.edutemplate <class Impl> 9452686Sksewell@umich.eduint 9462686Sksewell@umich.eduInstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 9472686Sksewell@umich.edu{ 9482686Sksewell@umich.edu int dependents = 0; 9492686Sksewell@umich.edu 9502686Sksewell@umich.edu // The instruction queue here takes care of both floating and int ops 9512686Sksewell@umich.edu if (completed_inst->isFloating()) { 9522686Sksewell@umich.edu fpInstQueueWakeupQccesses++; 9532101SN/A } else { 9542043SN/A intInstQueueWakeupAccesses++; 9552027SN/A } 9562043SN/A 9572686Sksewell@umich.edu DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 9582043SN/A 9592043SN/A assert(!completed_inst->isSquashed()); 9602024SN/A 9612686Sksewell@umich.edu // Tell the memory dependence unit to wake any dependents on this 9622686Sksewell@umich.edu // instruction if it is a memory instruction. Also complete the memory 9632043SN/A // instruction at this point since we know it executed without issues. 9642101SN/A // @todo: Might want to rename "completeMemInst" to something that 9652686Sksewell@umich.edu // indicates that it won't need to be replayed, and call this 9662686Sksewell@umich.edu // earlier. Might not be a big deal. 9672686Sksewell@umich.edu if (completed_inst->isMemRef()) { 9682686Sksewell@umich.edu memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 9692686Sksewell@umich.edu completeMemInst(completed_inst); 9702686Sksewell@umich.edu } else if (completed_inst->isMemBarrier() || 9712046SN/A completed_inst->isWriteBarrier()) { 9722101SN/A memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 9732026SN/A } 9742101SN/A 9752686Sksewell@umich.edu for (int dest_reg_idx = 0; 9762084SN/A dest_reg_idx < completed_inst->numDestRegs(); 9772084SN/A dest_reg_idx++) 9782061SN/A { 9792101SN/A PhysRegIndex dest_reg = 9802061SN/A completed_inst->renamedDestRegIdx(dest_reg_idx); 9812101SN/A 9822101SN/A // Special case of uniq or control registers. They are not 9832046SN/A // handled by the IQ and thus have no dependency graph entry. 9842686Sksewell@umich.edu // @todo Figure out a cleaner way to handle this. 9852686Sksewell@umich.edu if (dest_reg >= numPhysRegs) { 9862686Sksewell@umich.edu DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg, 9872686Sksewell@umich.edu numPhysRegs); 9882686Sksewell@umich.edu continue; 9892616SN/A } 9902616SN/A 9912046SN/A DPRINTF(IQ, "Waking any dependents on register %i.\n", 9922101SN/A (int) dest_reg); 9932043SN/A 9942101SN/A //Go through the dependency chain, marking the registers as 9952686Sksewell@umich.edu //ready within the waiting instructions. 9962101SN/A DynInstPtr dep_inst = dependGraph.pop(dest_reg); 9972043SN/A 9982084SN/A while (dep_inst) { 9992024SN/A DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] " 10002686Sksewell@umich.edu "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 10012124SN/A 10022239SN/A // Might want to give more information to the instruction 10032239SN/A // so that it knows which of its source registers is 10042479SN/A // ready. However that would mean that the dependency 10052239SN/A // graph entries would need to hold the src_reg_idx. 10062239SN/A dep_inst->markSrcRegReady(); 10072686Sksewell@umich.edu 10082495SN/A addIfReady(dep_inst); 10092686Sksewell@umich.edu 10102686Sksewell@umich.edu dep_inst = dependGraph.pop(dest_reg); 10112686Sksewell@umich.edu 10122686Sksewell@umich.edu ++dependents; 10132686Sksewell@umich.edu } 10142686Sksewell@umich.edu 10152686Sksewell@umich.edu // Reset the head node now that all of its dependents have 10162686Sksewell@umich.edu // been woken up. 10172686Sksewell@umich.edu assert(dependGraph.empty(dest_reg)); 10182084SN/A dependGraph.clearInst(dest_reg); 10192084SN/A 10202024SN/A // Mark the scoreboard as having that register ready. 10212686Sksewell@umich.edu regScoreboard[dest_reg] = true; 10222124SN/A } 10232124SN/A return dependents; 10242124SN/A} 10252479SN/A 10262084SN/Atemplate <class Impl> 10272024SN/Avoid 10282686Sksewell@umich.eduInstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 10292686Sksewell@umich.edu{ 10302686Sksewell@umich.edu OpClass op_class = ready_inst->opClass(); 10312686Sksewell@umich.edu 10322686Sksewell@umich.edu readyInsts[op_class].push(ready_inst); 10332686Sksewell@umich.edu 10342686Sksewell@umich.edu // Will need to reorder the list if either a queue is not on the list, 10352686Sksewell@umich.edu // or it has an older instruction than last time. 10362686Sksewell@umich.edu if (!queueOnList[op_class]) { 10372686Sksewell@umich.edu addToOrderList(op_class); 10382084SN/A } else if (readyInsts[op_class].top()->seqNum < 10392024SN/A (*readyIt[op_class]).oldestInst) { 10402686Sksewell@umich.edu listOrder.erase(readyIt[op_class]); 10412084SN/A addToOrderList(op_class); 10422024SN/A } 10432686Sksewell@umich.edu 10442686Sksewell@umich.edu DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 10452686Sksewell@umich.edu "the ready list, PC %s opclass:%i [sn:%lli].\n", 10462686Sksewell@umich.edu ready_inst->pcState(), op_class, ready_inst->seqNum); 10472573SN/A} 10482084SN/A 10492686Sksewell@umich.edutemplate <class Impl> 10502686Sksewell@umich.eduvoid 10512084SN/AInstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 10522024SN/A{ 10532239SN/A DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 10542686Sksewell@umich.edu 10552686Sksewell@umich.edu // Reset DTB translation state 10562686Sksewell@umich.edu resched_inst->translationStarted = false; 10572686Sksewell@umich.edu resched_inst->translationCompleted = false; 10582686Sksewell@umich.edu 10592055SN/A resched_inst->clearCanIssue(); 10602686Sksewell@umich.edu memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 10612573SN/A} 10622573SN/A 10632084SN/Atemplate <class Impl> 10642027SN/Avoid 10652024SN/AInstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 10662022SN/A{ 10672027SN/A memDepUnit[replay_inst->threadNumber].replay(replay_inst); 1068} 1069 1070template <class Impl> 1071void 1072InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 1073{ 1074 ThreadID tid = completed_inst->threadNumber; 1075 1076 DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n", 1077 completed_inst->pcState(), completed_inst->seqNum); 1078 1079 ++freeEntries; 1080 1081 completed_inst->memOpDone = true; 1082 1083 memDepUnit[tid].completed(completed_inst); 1084 count[tid]--; 1085} 1086 1087template <class Impl> 1088void 1089InstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst) 1090{ 1091 deferredMemInsts.push_back(deferred_inst); 1092} 1093 1094template <class Impl> 1095typename Impl::DynInstPtr 1096InstructionQueue<Impl>::getDeferredMemInstToExecute() 1097{ 1098 for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); 1099 ++it) { 1100 if ((*it)->translationCompleted) { 1101 DynInstPtr ret = *it; 1102 deferredMemInsts.erase(it); 1103 return ret; 1104 } 1105 } 1106 return NULL; 1107} 1108 1109template <class Impl> 1110void 1111InstructionQueue<Impl>::violation(DynInstPtr &store, 1112 DynInstPtr &faulting_load) 1113{ 1114 intInstQueueWrites++; 1115 memDepUnit[store->threadNumber].violation(store, faulting_load); 1116} 1117 1118template <class Impl> 1119void 1120InstructionQueue<Impl>::squash(ThreadID tid) 1121{ 1122 DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 1123 "the IQ.\n", tid); 1124 1125 // Read instruction sequence number of last instruction out of the 1126 // time buffer. 1127 squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 1128 1129 // Call doSquash if there are insts in the IQ 1130 if (count[tid] > 0) { 1131 doSquash(tid); 1132 } 1133 1134 // Also tell the memory dependence unit to squash. 1135 memDepUnit[tid].squash(squashedSeqNum[tid], tid); 1136} 1137 1138template <class Impl> 1139void 1140InstructionQueue<Impl>::doSquash(ThreadID tid) 1141{ 1142 // Start at the tail. 1143 ListIt squash_it = instList[tid].end(); 1144 --squash_it; 1145 1146 DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 1147 tid, squashedSeqNum[tid]); 1148 1149 // Squash any instructions younger than the squashed sequence number 1150 // given. 1151 while (squash_it != instList[tid].end() && 1152 (*squash_it)->seqNum > squashedSeqNum[tid]) { 1153 1154 DynInstPtr squashed_inst = (*squash_it); 1155 squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 1156 1157 // Only handle the instruction if it actually is in the IQ and 1158 // hasn't already been squashed in the IQ. 1159 if (squashed_inst->threadNumber != tid || 1160 squashed_inst->isSquashedInIQ()) { 1161 --squash_it; 1162 continue; 1163 } 1164 1165 if (!squashed_inst->isIssued() || 1166 (squashed_inst->isMemRef() && 1167 !squashed_inst->memOpDone)) { 1168 1169 DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", 1170 tid, squashed_inst->seqNum, squashed_inst->pcState()); 1171 1172 // Remove the instruction from the dependency list. 1173 if (!squashed_inst->isNonSpeculative() && 1174 !squashed_inst->isStoreConditional() && 1175 !squashed_inst->isMemBarrier() && 1176 !squashed_inst->isWriteBarrier()) { 1177 1178 for (int src_reg_idx = 0; 1179 src_reg_idx < squashed_inst->numSrcRegs(); 1180 src_reg_idx++) 1181 { 1182 PhysRegIndex src_reg = 1183 squashed_inst->renamedSrcRegIdx(src_reg_idx); 1184 1185 // Only remove it from the dependency graph if it 1186 // was placed there in the first place. 1187 1188 // Instead of doing a linked list traversal, we 1189 // can just remove these squashed instructions 1190 // either at issue time, or when the register is 1191 // overwritten. The only downside to this is it 1192 // leaves more room for error. 1193 1194 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 1195 src_reg < numPhysRegs) { 1196 dependGraph.remove(src_reg, squashed_inst); 1197 } 1198 1199 1200 ++iqSquashedOperandsExamined; 1201 } 1202 } else if (!squashed_inst->isStoreConditional() || 1203 !squashed_inst->isCompleted()) { 1204 NonSpecMapIt ns_inst_it = 1205 nonSpecInsts.find(squashed_inst->seqNum); 1206 1207 if (ns_inst_it == nonSpecInsts.end()) { 1208 assert(squashed_inst->getFault() != NoFault); 1209 } else { 1210 1211 (*ns_inst_it).second = NULL; 1212 1213 nonSpecInsts.erase(ns_inst_it); 1214 1215 ++iqSquashedNonSpecRemoved; 1216 } 1217 } 1218 1219 // Might want to also clear out the head of the dependency graph. 1220 1221 // Mark it as squashed within the IQ. 1222 squashed_inst->setSquashedInIQ(); 1223 1224 // @todo: Remove this hack where several statuses are set so the 1225 // inst will flow through the rest of the pipeline. 1226 squashed_inst->setIssued(); 1227 squashed_inst->setCanCommit(); 1228 squashed_inst->clearInIQ(); 1229 1230 //Update Thread IQ Count 1231 count[squashed_inst->threadNumber]--; 1232 1233 ++freeEntries; 1234 } 1235 1236 instList[tid].erase(squash_it--); 1237 ++iqSquashedInstsExamined; 1238 } 1239} 1240 1241template <class Impl> 1242bool 1243InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 1244{ 1245 // Loop through the instruction's source registers, adding 1246 // them to the dependency list if they are not ready. 1247 int8_t total_src_regs = new_inst->numSrcRegs(); 1248 bool return_val = false; 1249 1250 for (int src_reg_idx = 0; 1251 src_reg_idx < total_src_regs; 1252 src_reg_idx++) 1253 { 1254 // Only add it to the dependency graph if it's not ready. 1255 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 1256 PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 1257 1258 // Check the IQ's scoreboard to make sure the register 1259 // hasn't become ready while the instruction was in flight 1260 // between stages. Only if it really isn't ready should 1261 // it be added to the dependency graph. 1262 if (src_reg >= numPhysRegs) { 1263 continue; 1264 } else if (regScoreboard[src_reg] == false) { 1265 DPRINTF(IQ, "Instruction PC %s has src reg %i that " 1266 "is being added to the dependency chain.\n", 1267 new_inst->pcState(), src_reg); 1268 1269 dependGraph.insert(src_reg, new_inst); 1270 1271 // Change the return value to indicate that something 1272 // was added to the dependency graph. 1273 return_val = true; 1274 } else { 1275 DPRINTF(IQ, "Instruction PC %s has src reg %i that " 1276 "became ready before it reached the IQ.\n", 1277 new_inst->pcState(), src_reg); 1278 // Mark a register ready within the instruction. 1279 new_inst->markSrcRegReady(src_reg_idx); 1280 } 1281 } 1282 } 1283 1284 return return_val; 1285} 1286 1287template <class Impl> 1288void 1289InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) 1290{ 1291 // Nothing really needs to be marked when an instruction becomes 1292 // the producer of a register's value, but for convenience a ptr 1293 // to the producing instruction will be placed in the head node of 1294 // the dependency links. 1295 int8_t total_dest_regs = new_inst->numDestRegs(); 1296 1297 for (int dest_reg_idx = 0; 1298 dest_reg_idx < total_dest_regs; 1299 dest_reg_idx++) 1300 { 1301 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 1302 1303 // Instructions that use the misc regs will have a reg number 1304 // higher than the normal physical registers. In this case these 1305 // registers are not renamed, and there is no need to track 1306 // dependencies as these instructions must be executed at commit. 1307 if (dest_reg >= numPhysRegs) { 1308 continue; 1309 } 1310 1311 if (!dependGraph.empty(dest_reg)) { 1312 dependGraph.dump(); 1313 panic("Dependency graph %i not empty!", dest_reg); 1314 } 1315 1316 dependGraph.setInst(dest_reg, new_inst); 1317 1318 // Mark the scoreboard to say it's not yet ready. 1319 regScoreboard[dest_reg] = false; 1320 } 1321} 1322 1323template <class Impl> 1324void 1325InstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 1326{ 1327 // If the instruction now has all of its source registers 1328 // available, then add it to the list of ready instructions. 1329 if (inst->readyToIssue()) { 1330 1331 //Add the instruction to the proper ready list. 1332 if (inst->isMemRef()) { 1333 1334 DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 1335 1336 // Message to the mem dependence unit that this instruction has 1337 // its registers ready. 1338 memDepUnit[inst->threadNumber].regsReady(inst); 1339 1340 return; 1341 } 1342 1343 OpClass op_class = inst->opClass(); 1344 1345 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 1346 "the ready list, PC %s opclass:%i [sn:%lli].\n", 1347 inst->pcState(), op_class, inst->seqNum); 1348 1349 readyInsts[op_class].push(inst); 1350 1351 // Will need to reorder the list if either a queue is not on the list, 1352 // or it has an older instruction than last time. 1353 if (!queueOnList[op_class]) { 1354 addToOrderList(op_class); 1355 } else if (readyInsts[op_class].top()->seqNum < 1356 (*readyIt[op_class]).oldestInst) { 1357 listOrder.erase(readyIt[op_class]); 1358 addToOrderList(op_class); 1359 } 1360 } 1361} 1362 1363template <class Impl> 1364int 1365InstructionQueue<Impl>::countInsts() 1366{ 1367#if 0 1368 //ksewell:This works but definitely could use a cleaner write 1369 //with a more intuitive way of counting. Right now it's 1370 //just brute force .... 1371 // Change the #if if you want to use this method. 1372 int total_insts = 0; 1373 1374 for (ThreadID tid = 0; tid < numThreads; ++tid) { 1375 ListIt count_it = instList[tid].begin(); 1376 1377 while (count_it != instList[tid].end()) { 1378 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 1379 if (!(*count_it)->isIssued()) { 1380 ++total_insts; 1381 } else if ((*count_it)->isMemRef() && 1382 !(*count_it)->memOpDone) { 1383 // Loads that have not been marked as executed still count 1384 // towards the total instructions. 1385 ++total_insts; 1386 } 1387 } 1388 1389 ++count_it; 1390 } 1391 } 1392 1393 return total_insts; 1394#else 1395 return numEntries - freeEntries; 1396#endif 1397} 1398 1399template <class Impl> 1400void 1401InstructionQueue<Impl>::dumpLists() 1402{ 1403 for (int i = 0; i < Num_OpClasses; ++i) { 1404 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 1405 1406 cprintf("\n"); 1407 } 1408 1409 cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 1410 1411 NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 1412 NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 1413 1414 cprintf("Non speculative list: "); 1415 1416 while (non_spec_it != non_spec_end_it) { 1417 cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(), 1418 (*non_spec_it).second->seqNum); 1419 ++non_spec_it; 1420 } 1421 1422 cprintf("\n"); 1423 1424 ListOrderIt list_order_it = listOrder.begin(); 1425 ListOrderIt list_order_end_it = listOrder.end(); 1426 int i = 1; 1427 1428 cprintf("List order: "); 1429 1430 while (list_order_it != list_order_end_it) { 1431 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 1432 (*list_order_it).oldestInst); 1433 1434 ++list_order_it; 1435 ++i; 1436 } 1437 1438 cprintf("\n"); 1439} 1440 1441 1442template <class Impl> 1443void 1444InstructionQueue<Impl>::dumpInsts() 1445{ 1446 for (ThreadID tid = 0; tid < numThreads; ++tid) { 1447 int num = 0; 1448 int valid_num = 0; 1449 ListIt inst_list_it = instList[tid].begin(); 1450 1451 while (inst_list_it != instList[tid].end()) { 1452 cprintf("Instruction:%i\n", num); 1453 if (!(*inst_list_it)->isSquashed()) { 1454 if (!(*inst_list_it)->isIssued()) { 1455 ++valid_num; 1456 cprintf("Count:%i\n", valid_num); 1457 } else if ((*inst_list_it)->isMemRef() && 1458 !(*inst_list_it)->memOpDone) { 1459 // Loads that have not been marked as executed 1460 // still count towards the total instructions. 1461 ++valid_num; 1462 cprintf("Count:%i\n", valid_num); 1463 } 1464 } 1465 1466 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 1467 "Issued:%i\nSquashed:%i\n", 1468 (*inst_list_it)->pcState(), 1469 (*inst_list_it)->seqNum, 1470 (*inst_list_it)->threadNumber, 1471 (*inst_list_it)->isIssued(), 1472 (*inst_list_it)->isSquashed()); 1473 1474 if ((*inst_list_it)->isMemRef()) { 1475 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 1476 } 1477 1478 cprintf("\n"); 1479 1480 inst_list_it++; 1481 ++num; 1482 } 1483 } 1484 1485 cprintf("Insts to Execute list:\n"); 1486 1487 int num = 0; 1488 int valid_num = 0; 1489 ListIt inst_list_it = instsToExecute.begin(); 1490 1491 while (inst_list_it != instsToExecute.end()) 1492 { 1493 cprintf("Instruction:%i\n", 1494 num); 1495 if (!(*inst_list_it)->isSquashed()) { 1496 if (!(*inst_list_it)->isIssued()) { 1497 ++valid_num; 1498 cprintf("Count:%i\n", valid_num); 1499 } else if ((*inst_list_it)->isMemRef() && 1500 !(*inst_list_it)->memOpDone) { 1501 // Loads that have not been marked as executed 1502 // still count towards the total instructions. 1503 ++valid_num; 1504 cprintf("Count:%i\n", valid_num); 1505 } 1506 } 1507 1508 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 1509 "Issued:%i\nSquashed:%i\n", 1510 (*inst_list_it)->pcState(), 1511 (*inst_list_it)->seqNum, 1512 (*inst_list_it)->threadNumber, 1513 (*inst_list_it)->isIssued(), 1514 (*inst_list_it)->isSquashed()); 1515 1516 if ((*inst_list_it)->isMemRef()) { 1517 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 1518 } 1519 1520 cprintf("\n"); 1521 1522 inst_list_it++; 1523 ++num; 1524 } 1525} 1526