inst_queue_impl.hh revision 8275
11689SN/A/* 22326SN/A * Copyright (c) 2011 ARM Limited 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * The license below extends only to copyright in the software and shall 61689SN/A * not be construed as granting a license to any other intellectual 71689SN/A * property including but not limited to intellectual property relating 81689SN/A * to a hardware implementation of the functionality of the software 91689SN/A * licensed hereunder. You may use the software subject to the license 101689SN/A * terms below provided that you ensure that this notice is replicated 111689SN/A * unmodified and in its entirety in all distributions of the software, 121689SN/A * modified or unmodified, in source code or in binary form. 131689SN/A * 141689SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312064SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341696SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371717SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392292SN/A * 401060SN/A * Authors: Kevin Lim 411061SN/A * Korey Sewell 422292SN/A */ 432292SN/A 442292SN/A#include <limits> 452292SN/A#include <vector> 462326SN/A 471060SN/A#include "cpu/o3/fu_pool.hh" 482292SN/A#include "cpu/o3/inst_queue.hh" 492292SN/A#include "debug/IQ.hh" 502292SN/A#include "enums/OpClass.hh" 512292SN/A#include "params/DerivO3CPU.hh" 522292SN/A#include "sim/core.hh" 532292SN/A 542292SN/Ausing namespace std; 552326SN/A 562292SN/Atemplate <class Impl> 572292SN/AInstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 582292SN/A int fu_idx, InstructionQueue<Impl> *iq_ptr) 592292SN/A : Event(Stat_Event_Pri), inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), 602292SN/A freeFU(false) 612292SN/A{ 622292SN/A this->setFlags(Event::AutoDelete); 632292SN/A} 642292SN/A 652292SN/Atemplate <class Impl> 662292SN/Avoid 672292SN/AInstructionQueue<Impl>::FUCompletion::process() 682292SN/A{ 692669Sktlim@umich.edu iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 702292SN/A inst = NULL; 712292SN/A} 722292SN/A 732292SN/A 742292SN/Atemplate <class Impl> 752292SN/Aconst char * 762292SN/AInstructionQueue<Impl>::FUCompletion::description() const 772292SN/A{ 782307SN/A return "Functional unit completion"; 792307SN/A} 802292SN/A 811060SN/Atemplate <class Impl> 821060SN/AInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 831060SN/A DerivO3CPUParams *params) 841060SN/A : cpu(cpu_ptr), 852292SN/A iewStage(iew_ptr), 861060SN/A fuPool(params->fuPool), 871060SN/A numEntries(params->numIQEntries), 881060SN/A totalWidth(params->issueWidth), 892326SN/A numPhysIntRegs(params->numPhysIntRegs), 901060SN/A numPhysFloatRegs(params->numPhysFloatRegs), 911060SN/A commitToIEWDelay(params->commitToIEWDelay) 921060SN/A{ 931060SN/A assert(fuPool); 942292SN/A 952292SN/A switchedOut = false; 962292SN/A 972292SN/A numThreads = params->numThreads; 981060SN/A 991060SN/A // Set the number of physical registers as the number of int + float 1002307SN/A numPhysRegs = numPhysIntRegs + numPhysFloatRegs; 1012292SN/A 1022292SN/A //Create an entry for each physical register within the 1032292SN/A //dependency graph. 1042292SN/A dependGraph.resize(numPhysRegs); 1052292SN/A 1062292SN/A // Resize the register scoreboard. 1072292SN/A regScoreboard.resize(numPhysRegs); 1082292SN/A 1092292SN/A //Initialize Mem Dependence Units 1102292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1112292SN/A memDepUnit[tid].init(params, tid); 1122292SN/A memDepUnit[tid].setIQ(this); 1132292SN/A } 1142292SN/A 1152292SN/A resetState(); 1162292SN/A 1172292SN/A std::string policy = params->smtIQPolicy; 1182292SN/A 1192292SN/A //Convert string to lowercase 1202292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1212292SN/A (int(*)(int)) tolower); 1222292SN/A 1232292SN/A //Figure out resource sharing policy 1242292SN/A if (policy == "dynamic") { 1252292SN/A iqPolicy = Dynamic; 1262292SN/A 1272292SN/A //Set Max Entries to Total ROB Capacity 1282292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1292292SN/A maxEntries[tid] = numEntries; 1302292SN/A } 1312292SN/A 1322292SN/A } else if (policy == "partitioned") { 1332292SN/A iqPolicy = Partitioned; 1342292SN/A 1352292SN/A //@todo:make work if part_amt doesnt divide evenly. 1362292SN/A int part_amt = numEntries / numThreads; 1372292SN/A 1382292SN/A //Divide ROB up evenly 1392292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1402292SN/A maxEntries[tid] = part_amt; 1412292SN/A } 1422292SN/A 1432292SN/A DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 1442292SN/A "%i entries per thread.\n",part_amt); 1452292SN/A } else if (policy == "threshold") { 1462292SN/A iqPolicy = Threshold; 1472292SN/A 1482292SN/A double threshold = (double)params->smtIQThreshold / 100; 1492292SN/A 1502292SN/A int thresholdIQ = (int)((double)threshold * numEntries); 1512292SN/A 1522292SN/A //Divide up by threshold amount 1532292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1542326SN/A maxEntries[tid] = thresholdIQ; 1552348SN/A } 1562326SN/A 1572326SN/A DPRINTF(IQ, "IQ sharing policy set to Threshold:" 1582348SN/A "%i entries per thread.\n",thresholdIQ); 1592292SN/A } else { 1602292SN/A assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 1612292SN/A "Partitioned, Threshold}"); 1622292SN/A } 1632292SN/A} 1642292SN/A 1652292SN/Atemplate <class Impl> 1661060SN/AInstructionQueue<Impl>::~InstructionQueue() 1671060SN/A{ 1681061SN/A dependGraph.reset(); 1691060SN/A#ifdef DEBUG 1701062SN/A cprintf("Nodes traversed: %i, removed: %i\n", 1711062SN/A dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1722301SN/A#endif 1731062SN/A} 1741062SN/A 1751062SN/Atemplate <class Impl> 1761062SN/Astd::string 1771062SN/AInstructionQueue<Impl>::name() const 1781062SN/A{ 1791062SN/A return cpu->name() + ".iq"; 1801062SN/A} 1811062SN/A 1821062SN/Atemplate <class Impl> 1832301SN/Avoid 1842301SN/AInstructionQueue<Impl>::regStats() 1852301SN/A{ 1862301SN/A using namespace Stats; 1871062SN/A iqInstsAdded 1881062SN/A .name(name() + ".iqInstsAdded") 1891062SN/A .desc("Number of instructions added to the IQ (excludes non-spec)") 1901062SN/A .prereq(iqInstsAdded); 1911062SN/A 1921062SN/A iqNonSpecInstsAdded 1931062SN/A .name(name() + ".iqNonSpecInstsAdded") 1941062SN/A .desc("Number of non-speculative instructions added to the IQ") 1951062SN/A .prereq(iqNonSpecInstsAdded); 1961062SN/A 1971062SN/A iqInstsIssued 1981062SN/A .name(name() + ".iqInstsIssued") 1991062SN/A .desc("Number of instructions issued") 2001062SN/A .prereq(iqInstsIssued); 2011062SN/A 2021062SN/A iqIntInstsIssued 2031062SN/A .name(name() + ".iqIntInstsIssued") 2041062SN/A .desc("Number of integer instructions issued") 2051062SN/A .prereq(iqIntInstsIssued); 2061062SN/A 2071062SN/A iqFloatInstsIssued 2081062SN/A .name(name() + ".iqFloatInstsIssued") 2091062SN/A .desc("Number of float instructions issued") 2101062SN/A .prereq(iqFloatInstsIssued); 2111062SN/A 2121062SN/A iqBranchInstsIssued 2131062SN/A .name(name() + ".iqBranchInstsIssued") 2141062SN/A .desc("Number of branch instructions issued") 2151062SN/A .prereq(iqBranchInstsIssued); 2161062SN/A 2171062SN/A iqMemInstsIssued 2181062SN/A .name(name() + ".iqMemInstsIssued") 2191062SN/A .desc("Number of memory instructions issued") 2201062SN/A .prereq(iqMemInstsIssued); 2211062SN/A 2221062SN/A iqMiscInstsIssued 2231062SN/A .name(name() + ".iqMiscInstsIssued") 2241062SN/A .desc("Number of miscellaneous instructions issued") 2251062SN/A .prereq(iqMiscInstsIssued); 2261062SN/A 2271062SN/A iqSquashedInstsIssued 2281062SN/A .name(name() + ".iqSquashedInstsIssued") 2291062SN/A .desc("Number of squashed instructions issued") 2301062SN/A .prereq(iqSquashedInstsIssued); 2311062SN/A 2321062SN/A iqSquashedInstsExamined 2331062SN/A .name(name() + ".iqSquashedInstsExamined") 2341062SN/A .desc("Number of squashed instructions iterated over during squash;" 2352326SN/A " mainly for profiling") 2362301SN/A .prereq(iqSquashedInstsExamined); 2372301SN/A 2382301SN/A iqSquashedOperandsExamined 2392301SN/A .name(name() + ".iqSquashedOperandsExamined") 2402301SN/A .desc("Number of squashed operands that are examined and possibly " 2412301SN/A "removed from graph") 2422326SN/A .prereq(iqSquashedOperandsExamined); 2432301SN/A 2442326SN/A iqSquashedNonSpecRemoved 2452307SN/A .name(name() + ".iqSquashedNonSpecRemoved") 2462301SN/A .desc("Number of squashed non-spec instructions that were removed") 2472301SN/A .prereq(iqSquashedNonSpecRemoved); 2482307SN/A/* 2492301SN/A queueResDist 2502301SN/A .init(Num_OpClasses, 0, 99, 2) 2512301SN/A .name(name() + ".IQ:residence:") 2522301SN/A .desc("cycles from dispatch to issue") 2532301SN/A .flags(total | pdf | cdf ) 2542301SN/A ; 2552301SN/A for (int i = 0; i < Num_OpClasses; ++i) { 2562301SN/A queueResDist.subname(i, opClassStrings[i]); 2572301SN/A } 2582301SN/A*/ 2592301SN/A numIssuedDist 2602301SN/A .init(0,totalWidth,1) 2612326SN/A .name(name() + ".issued_per_cycle") 2622301SN/A .desc("Number of insts issued each cycle") 2632301SN/A .flags(pdf) 2642301SN/A ; 2652301SN/A/* 2662301SN/A dist_unissued 2672326SN/A .init(Num_OpClasses+2) 2682301SN/A .name(name() + ".unissued_cause") 2692301SN/A .desc("Reason ready instruction not issued") 2702301SN/A .flags(pdf | dist) 2712301SN/A ; 2722301SN/A for (int i=0; i < (Num_OpClasses + 2); ++i) { 2732326SN/A dist_unissued.subname(i, unissued_names[i]); 2742301SN/A } 2752301SN/A*/ 2762301SN/A statIssuedInstType 2772301SN/A .init(numThreads,Enums::Num_OpClass) 2782301SN/A .name(name() + ".FU_type") 2792301SN/A .desc("Type of FU issued") 2802301SN/A .flags(total | pdf | dist) 2812301SN/A ; 2822301SN/A statIssuedInstType.ysubnames(Enums::OpClassStrings); 2832326SN/A 2842301SN/A // 2852301SN/A // How long did instructions for a particular FU type wait prior to issue 2862326SN/A // 2872301SN/A/* 2882301SN/A issueDelayDist 2892301SN/A .init(Num_OpClasses,0,99,2) 2902301SN/A .name(name() + ".") 2912326SN/A .desc("cycles from operands ready to issue") 2922727Sktlim@umich.edu .flags(pdf | cdf) 2932326SN/A ; 2942301SN/A 2952301SN/A for (int i=0; i<Num_OpClasses; ++i) { 2962301SN/A std::stringstream subname; 2972301SN/A subname << opClassStrings[i] << "_delay"; 2982301SN/A issueDelayDist.subname(i, subname.str()); 2992301SN/A } 3002326SN/A*/ 3012301SN/A issueRate 3022301SN/A .name(name() + ".rate") 3032326SN/A .desc("Inst issue rate") 3042301SN/A .flags(total) 3052301SN/A ; 3062301SN/A issueRate = iqInstsIssued / cpu->numCycles; 3072301SN/A 3082301SN/A statFuBusy 3092301SN/A .init(Num_OpClasses) 3102326SN/A .name(name() + ".fu_full") 3112301SN/A .desc("attempts to use FU when none available") 3122301SN/A .flags(pdf | dist) 3132301SN/A ; 3142301SN/A for (int i=0; i < Num_OpClasses; ++i) { 3152326SN/A statFuBusy.subname(i, Enums::OpClassStrings[i]); 3162301SN/A } 3172292SN/A 3182292SN/A fuBusy 3192292SN/A .init(numThreads) 3202292SN/A .name(name() + ".fu_busy_cnt") 3211062SN/A .desc("FU busy when requested") 3221062SN/A .flags(total) 3231062SN/A ; 3241062SN/A 3252307SN/A fuBusyRate 3261060SN/A .name(name() + ".fu_busy_rate") 3272307SN/A .desc("FU busy rate (busy events/executed inst)") 3282307SN/A .flags(total) 3292307SN/A ; 3302307SN/A fuBusyRate = fuBusy / iqInstsIssued; 3312307SN/A 3321060SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 3332307SN/A // Tell mem dependence unit to reg stats as well. 3342307SN/A memDepUnit[tid].regStats(); 3352307SN/A } 3362307SN/A 3372307SN/A intInstQueueReads 3382307SN/A .name(name() + ".int_inst_queue_reads") 3392307SN/A .desc("Number of integer instruction queue reads") 3402307SN/A .flags(total); 3412307SN/A 3422307SN/A intInstQueueWrites 3432307SN/A .name(name() + ".int_inst_queue_writes") 3442307SN/A .desc("Number of integer instruction queue writes") 3452307SN/A .flags(total); 3462307SN/A 3472307SN/A intInstQueueWakeupAccesses 3482307SN/A .name(name() + ".int_inst_queue_wakeup_accesses") 3492307SN/A .desc("Number of integer instruction queue wakeup accesses") 3502307SN/A .flags(total); 3512307SN/A 3522307SN/A fpInstQueueReads 3532307SN/A .name(name() + ".fp_inst_queue_reads") 3542307SN/A .desc("Number of floating instruction queue reads") 3552307SN/A .flags(total); 3562307SN/A 3571060SN/A fpInstQueueWrites 3581060SN/A .name(name() + ".fp_inst_queue_writes") 3591061SN/A .desc("Number of floating instruction queue writes") 3601060SN/A .flags(total); 3612292SN/A 3621060SN/A fpInstQueueWakeupQccesses 3632292SN/A .name(name() + ".fp_inst_queue_wakeup_accesses") 3642292SN/A .desc("Number of floating instruction queue wakeup accesses") 3652064SN/A .flags(total); 3662064SN/A 3672064SN/A intAluAccesses 3682064SN/A .name(name() + ".int_alu_accesses") 3692292SN/A .desc("Number of integer alu accesses") 3702064SN/A .flags(total); 3712292SN/A 3721060SN/A fpAluAccesses 3731060SN/A .name(name() + ".fp_alu_accesses") 3741060SN/A .desc("Number of floating point alu accesses") 3751061SN/A .flags(total); 3761060SN/A 3771060SN/A} 3781060SN/A 3792292SN/Atemplate <class Impl> 3801060SN/Avoid 3811060SN/AInstructionQueue<Impl>::resetState() 3821060SN/A{ 3831060SN/A //Initialize thread IQ counts 3841060SN/A for (ThreadID tid = 0; tid <numThreads; tid++) { 3851684SN/A count[tid] = 0; 3862307SN/A instList[tid].clear(); 3872307SN/A } 3882307SN/A 3892307SN/A // Initialize the number of free IQ entries. 3902326SN/A freeEntries = numEntries; 3912307SN/A 3922307SN/A // Note that in actuality, the registers corresponding to the logical 3932307SN/A // registers start off as ready. However this doesn't matter for the 3942307SN/A // IQ as the instruction should have been correctly told if those 3952307SN/A // registers are ready in rename. Thus it can all be initialized as 3962307SN/A // unready. 3972307SN/A for (int i = 0; i < numPhysRegs; ++i) { 3982307SN/A regScoreboard[i] = false; 3992307SN/A } 4002307SN/A 4012307SN/A for (ThreadID tid = 0; tid < numThreads; ++tid) { 4022307SN/A squashedSeqNum[tid] = 0; 4032307SN/A } 4042307SN/A 4052292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 4062292SN/A while (!readyInsts[i].empty()) 4072292SN/A readyInsts[i].pop(); 4082292SN/A queueOnList[i] = false; 4092292SN/A readyIt[i] = listOrder.end(); 4102292SN/A } 4112292SN/A nonSpecInsts.clear(); 4122292SN/A listOrder.clear(); 4132292SN/A deferredMemInsts.clear(); 4142292SN/A} 4152292SN/A 4162292SN/Atemplate <class Impl> 4172292SN/Avoid 4182292SN/AInstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 4192292SN/A{ 4202292SN/A activeThreads = at_ptr; 4212292SN/A} 4222292SN/A 4232292SN/Atemplate <class Impl> 4242292SN/Avoid 4252292SN/AInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 4262292SN/A{ 4272292SN/A issueToExecuteQueue = i2e_ptr; 4282292SN/A} 4292292SN/A 4302292SN/Atemplate <class Impl> 4312292SN/Avoid 4322292SN/AInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 4332292SN/A{ 4342292SN/A timeBuffer = tb_ptr; 4352292SN/A 4362292SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 4371684SN/A} 4381684SN/A 4391684SN/Atemplate <class Impl> 4401684SN/Avoid 4411684SN/AInstructionQueue<Impl>::switchOut() 4421684SN/A{ 4432292SN/A/* 4442292SN/A if (!instList[0].empty() || (numEntries != freeEntries) || 4452292SN/A !readyInsts[0].empty() || !nonSpecInsts.empty() || !listOrder.empty()) { 4462292SN/A dumpInsts(); 4472292SN/A// assert(0); 4482292SN/A } 4492292SN/A*/ 4501060SN/A resetState(); 4511060SN/A dependGraph.reset(); 4521061SN/A instsToExecute.clear(); 4531060SN/A switchedOut = true; 4541060SN/A for (ThreadID tid = 0; tid < numThreads; ++tid) { 4551060SN/A memDepUnit[tid].switchOut(); 4561060SN/A } 4571060SN/A} 4581060SN/A 4591060SN/Atemplate <class Impl> 4601060SN/Avoid 4611060SN/AInstructionQueue<Impl>::takeOverFrom() 4621060SN/A{ 4631061SN/A switchedOut = false; 4642292SN/A} 4652292SN/A 4662292SN/Atemplate <class Impl> 4672292SN/Aint 4682292SN/AInstructionQueue<Impl>::entryAmount(ThreadID num_threads) 4692292SN/A{ 4702292SN/A if (iqPolicy == Partitioned) { 4712292SN/A return numEntries / num_threads; 4722292SN/A } else { 4732292SN/A return 0; 4742292SN/A } 4752292SN/A} 4762292SN/A 4772292SN/A 4782292SN/Atemplate <class Impl> 4792292SN/Avoid 4802292SN/AInstructionQueue<Impl>::resetEntries() 4812292SN/A{ 4822292SN/A if (iqPolicy != Dynamic || numThreads > 1) { 4832292SN/A int active_threads = activeThreads->size(); 4842292SN/A 4852292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 4862292SN/A list<ThreadID>::iterator end = activeThreads->end(); 4872292SN/A 4882292SN/A while (threads != end) { 4892292SN/A ThreadID tid = *threads++; 4902292SN/A 4912292SN/A if (iqPolicy == Partitioned) { 4921060SN/A maxEntries[tid] = numEntries / active_threads; 4931061SN/A } else if(iqPolicy == Threshold && active_threads == 1) { 4941060SN/A maxEntries[tid] = numEntries; 4951060SN/A } 4961060SN/A } 4971060SN/A } 4982326SN/A} 4992326SN/A 5001060SN/Atemplate <class Impl> 5011060SN/Aunsigned 5021060SN/AInstructionQueue<Impl>::numFreeEntries() 5032292SN/A{ 5041060SN/A return freeEntries; 5052064SN/A} 5061060SN/A 5072292SN/Atemplate <class Impl> 5081060SN/Aunsigned 5091060SN/AInstructionQueue<Impl>::numFreeEntries(ThreadID tid) 5101060SN/A{ 5111060SN/A return maxEntries[tid] - count[tid]; 5121060SN/A} 5131060SN/A 5141060SN/A// Might want to do something more complex if it knows how many instructions 5152326SN/A// will be issued this cycle. 5161060SN/Atemplate <class Impl> 5171061SN/Abool 5182292SN/AInstructionQueue<Impl>::isFull() 5191062SN/A{ 5201062SN/A if (freeEntries == 0) { 5211061SN/A return(true); 5221061SN/A } else { 5231062SN/A return(false); 5241060SN/A } 5252292SN/A} 5262292SN/A 5271060SN/Atemplate <class Impl> 5281060SN/Abool 5291060SN/AInstructionQueue<Impl>::isFull(ThreadID tid) 5301061SN/A{ 5311061SN/A if (numFreeEntries(tid) == 0) { 5322292SN/A return(true); 5331061SN/A } else { 5341061SN/A return(false); 5351061SN/A } 5361061SN/A} 5372292SN/A 5381061SN/Atemplate <class Impl> 5392292SN/Abool 5401061SN/AInstructionQueue<Impl>::hasReadyInsts() 5412326SN/A{ 5422326SN/A if (!listOrder.empty()) { 5432326SN/A return true; 5442064SN/A } 5451061SN/A 5461061SN/A for (int i = 0; i < Num_OpClasses; ++i) { 5472292SN/A if (!readyInsts[i].empty()) { 5481061SN/A return true; 5492064SN/A } 5501061SN/A } 5512292SN/A 5521061SN/A return false; 5531061SN/A} 5541061SN/A 5552326SN/Atemplate <class Impl> 5561061SN/Avoid 5571061SN/AInstructionQueue<Impl>::insert(DynInstPtr &new_inst) 5581061SN/A{ 5592292SN/A new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 5602292SN/A // Make sure the instruction is valid 5611061SN/A assert(new_inst); 5621062SN/A 5631062SN/A DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n", 5642292SN/A new_inst->seqNum, new_inst->pcState()); 5652292SN/A 5662292SN/A assert(freeEntries != 0); 5672292SN/A 5681061SN/A instList[new_inst->threadNumber].push_back(new_inst); 5691061SN/A 5701061SN/A --freeEntries; 5711060SN/A 5722292SN/A new_inst->setInIQ(); 5731060SN/A 5742292SN/A // Look through its source registers (physical regs), and mark any 5751060SN/A // dependencies. 5762292SN/A addToDependents(new_inst); 5772292SN/A 5781060SN/A // Have this instruction set itself as the producer of its destination 5792064SN/A // register(s). 5802333SN/A addToProducers(new_inst); 5812333SN/A 5822333SN/A if (new_inst->isMemRef()) { 5832333SN/A memDepUnit[new_inst->threadNumber].insert(new_inst); 5842333SN/A } else { 5852333SN/A addIfReady(new_inst); 5862333SN/A } 5872333SN/A 5881060SN/A ++iqInstsAdded; 5892333SN/A 5902064SN/A count[new_inst->threadNumber]++; 5912292SN/A 5922292SN/A assert(freeEntries == (numEntries - countInsts())); 5932292SN/A} 5942292SN/A 5952292SN/Atemplate <class Impl> 5962292SN/Avoid 5972292SN/AInstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) 5982292SN/A{ 5992292SN/A // @todo: Clean up this code; can do it by setting inst as unable 6002292SN/A // to issue, then calling normal insert on the inst. 6012292SN/A new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 6022292SN/A 6032292SN/A assert(new_inst); 6042292SN/A 6052292SN/A nonSpecInsts[new_inst->seqNum] = new_inst; 6062292SN/A 6072292SN/A DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s " 6082292SN/A "to the IQ.\n", 6092292SN/A new_inst->seqNum, new_inst->pcState()); 6101060SN/A 6111060SN/A assert(freeEntries != 0); 6122292SN/A 6132292SN/A instList[new_inst->threadNumber].push_back(new_inst); 6142292SN/A 6151060SN/A --freeEntries; 6162292SN/A 6172292SN/A new_inst->setInIQ(); 6182292SN/A 6192292SN/A // Have this instruction set itself as the producer of its destination 6202292SN/A // register(s). 6212292SN/A addToProducers(new_inst); 6222292SN/A 6232292SN/A // If it's a memory instruction, add it to the memory dependency 6242292SN/A // unit. 6252292SN/A if (new_inst->isMemRef()) { 6262292SN/A memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 6272292SN/A } 6282292SN/A 6292292SN/A ++iqNonSpecInstsAdded; 6302292SN/A 6312292SN/A count[new_inst->threadNumber]++; 6322292SN/A 6332292SN/A assert(freeEntries == (numEntries - countInsts())); 6342292SN/A} 6352292SN/A 6362292SN/Atemplate <class Impl> 6371060SN/Avoid 6381060SN/AInstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) 6392292SN/A{ 6401060SN/A memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 6411060SN/A 6422292SN/A insertNonSpec(barr_inst); 6432292SN/A} 6442292SN/A 6452292SN/Atemplate <class Impl> 6462292SN/Atypename Impl::DynInstPtr 6472292SN/AInstructionQueue<Impl>::getInstToExecute() 6482307SN/A{ 6492307SN/A assert(!instsToExecute.empty()); 6502307SN/A DynInstPtr inst = instsToExecute.front(); 6512307SN/A instsToExecute.pop_front(); 6522292SN/A if (inst->isFloating()){ 6532292SN/A fpInstQueueReads++; 6542326SN/A } else { 6552326SN/A intInstQueueReads++; 6562292SN/A } 6572326SN/A return inst; 6582326SN/A} 6592326SN/A 6602333SN/Atemplate <class Impl> 6612333SN/Avoid 6622292SN/AInstructionQueue<Impl>::addToOrderList(OpClass op_class) 6632292SN/A{ 6641061SN/A assert(!readyInsts[op_class].empty()); 6651061SN/A 6661061SN/A ListOrderEntry queue_entry; 6671061SN/A 6681060SN/A queue_entry.queueType = op_class; 6691060SN/A 6701060SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 6712292SN/A 6722292SN/A ListOrderIt list_it = listOrder.begin(); 6731060SN/A ListOrderIt list_end_it = listOrder.end(); 6741060SN/A 6751060SN/A while (list_it != list_end_it) { 6762292SN/A if ((*list_it).oldestInst > queue_entry.oldestInst) { 6772292SN/A break; 6782292SN/A } 6792292SN/A 6802292SN/A list_it++; 6812292SN/A } 6822292SN/A 6832292SN/A readyIt[op_class] = listOrder.insert(list_it, queue_entry); 6842292SN/A queueOnList[op_class] = true; 6852292SN/A} 6862292SN/A 6871060SN/Atemplate <class Impl> 6882333SN/Avoid 6892326SN/AInstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 6902292SN/A{ 6911060SN/A // Get iterator of next item on the list 6922292SN/A // Delete the original iterator 6931060SN/A // Determine if the next item is either the end of the list or younger 6942292SN/A // than the new instruction. If so, then add in a new iterator right here. 6951060SN/A // If not, then move along. 6962292SN/A ListOrderEntry queue_entry; 6971060SN/A OpClass op_class = (*list_order_it).queueType; 6982292SN/A ListOrderIt next_it = list_order_it; 6992292SN/A 7001060SN/A ++next_it; 7012292SN/A 7022292SN/A queue_entry.queueType = op_class; 7032292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 7042292SN/A 7052292SN/A while (next_it != listOrder.end() && 7061060SN/A (*next_it).oldestInst < queue_entry.oldestInst) { 7071060SN/A ++next_it; 7082292SN/A } 7091060SN/A 7102292SN/A readyIt[op_class] = listOrder.insert(next_it, queue_entry); 7112292SN/A} 7122292SN/A 7131060SN/Atemplate <class Impl> 7141060SN/Avoid 7152326SN/AInstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 7162326SN/A{ 7172301SN/A DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 7181060SN/A // The CPU could have been sleeping until this op completed (*extremely* 7192326SN/A // long latency op). Wake it if it was. This may be overkill. 7202326SN/A if (isSwitchedOut()) { 7211060SN/A DPRINTF(IQ, "FU completion not processed, IQ is switched out [sn:%lli]\n", 7222326SN/A inst->seqNum); 7232326SN/A return; 7241060SN/A } 7251060SN/A 7261060SN/A iewStage->wakeCPU(); 7272348SN/A 7282348SN/A if (fu_idx > -1) 7292326SN/A fuPool->freeUnitNextCycle(fu_idx); 7302292SN/A 7312292SN/A // @todo: Ensure that these FU Completions happen at the beginning 7322333SN/A // of a cycle, otherwise they could add too many instructions to 7331060SN/A // the queue. 7342326SN/A issueToExecuteQueue->access(-1)->size++; 7352326SN/A instsToExecute.push_back(inst); 7362326SN/A} 7372326SN/A 7382292SN/A// @todo: Figure out a better way to remove the squashed items from the 7392292SN/A// lists. Checking the top item of each list to see if it's squashed 7402326SN/A// wastes time and forces jumps. 7412326SN/Atemplate <class Impl> 7422326SN/Avoid 7431060SN/AInstructionQueue<Impl>::scheduleReadyInsts() 7442326SN/A{ 7451060SN/A DPRINTF(IQ, "Attempting to schedule ready instructions from " 7462326SN/A "the IQ.\n"); 7472292SN/A 7482348SN/A IssueStruct *i2e_info = issueToExecuteQueue->access(0); 7492348SN/A 7502326SN/A DynInstPtr deferred_mem_inst; 7512292SN/A int total_deferred_mem_issued = 0; 7522292SN/A while (total_deferred_mem_issued < totalWidth && 7532326SN/A (deferred_mem_inst = getDeferredMemInstToExecute()) != 0) { 7542292SN/A issueToExecuteQueue->access(0)->size++; 7551060SN/A instsToExecute.push_back(deferred_mem_inst); 7561060SN/A total_deferred_mem_issued++; 7572292SN/A } 7582292SN/A 7592301SN/A // Have iterator to head of the list 7602292SN/A // While I haven't exceeded bandwidth or reached the end of the list, 7611060SN/A // Try to get a FU that can do what this op needs. 7622292SN/A // If successful, change the oldestInst to the new top of the list, put 7631061SN/A // the queue in the proper place in the list. 7642292SN/A // Increment the iterator. 7652292SN/A // This will avoid trying to schedule a certain op class if there are no 7662292SN/A // FUs that handle it. 7672292SN/A ListOrderIt order_it = listOrder.begin(); 7682292SN/A ListOrderIt order_end_it = listOrder.end(); 7691060SN/A int total_issued = 0; 7701060SN/A 7712064SN/A while (total_issued < (totalWidth - total_deferred_mem_issued) && 7722292SN/A iewStage->canIssue() && 7732064SN/A order_it != order_end_it) { 7742292SN/A OpClass op_class = (*order_it).queueType; 7752292SN/A 7762292SN/A assert(!readyInsts[op_class].empty()); 7772292SN/A 7782301SN/A DynInstPtr issuing_inst = readyInsts[op_class].top(); 7792292SN/A 7802292SN/A issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++; 7812301SN/A 7822292SN/A assert(issuing_inst->seqNum == (*order_it).oldestInst); 7832292SN/A 7842292SN/A if (issuing_inst->isSquashed()) { 7852326SN/A readyInsts[op_class].pop(); 7862292SN/A 7872326SN/A if (!readyInsts[op_class].empty()) { 7882326SN/A moveToYoungerInst(order_it); 7892292SN/A } else { 7901060SN/A readyIt[op_class] = listOrder.end(); 7911060SN/A queueOnList[op_class] = false; 7921062SN/A } 7932326SN/A 7942326SN/A listOrder.erase(order_it++); 7952307SN/A 7962348SN/A ++iqSquashedInstsIssued; 7972292SN/A 7982292SN/A continue; 7992292SN/A } 8002292SN/A 8012292SN/A int idx = -2; 8021060SN/A int op_latency = 1; 8031060SN/A ThreadID tid = issuing_inst->threadNumber; 8041061SN/A 8051060SN/A if (op_class != No_OpClass) { 8061061SN/A idx = fuPool->getUnit(op_class); 8071060SN/A issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++; 8082292SN/A if (idx > -1) { 8092292SN/A op_latency = fuPool->getOpLatency(op_class); 8101062SN/A } 8112292SN/A } 8121060SN/A 8131061SN/A // If we have an instruction that doesn't require a FU, or a 8141060SN/A // valid FU, then schedule for execution. 8152292SN/A if (idx == -2 || idx != -1) { 8162292SN/A if (op_latency == 1) { 8171061SN/A i2e_info->size++; 8181060SN/A instsToExecute.push_back(issuing_inst); 8191062SN/A 8201062SN/A // Add the FU onto the list of FU's to be freed next 8211062SN/A // cycle if we used one. 8222292SN/A if (idx >= 0) 8231062SN/A fuPool->freeUnitNextCycle(idx); 8241060SN/A } else { 8252292SN/A int issue_latency = fuPool->getIssueLatency(op_class); 8262292SN/A // Generate completion event for the FU 8271061SN/A FUCompletion *execution = new FUCompletion(issuing_inst, 8281060SN/A idx, this); 8291060SN/A 8301061SN/A cpu->schedule(execution, curTick() + cpu->ticks(op_latency - 1)); 8311061SN/A 8322292SN/A // @todo: Enforce that issue_latency == 1 or op_latency 8332292SN/A if (issue_latency > 1) { 8342292SN/A // If FU isn't pipelined, then it must be freed 8352292SN/A // upon the execution completing. 8362292SN/A execution->setFreeFU(); 8372292SN/A } else { 8382292SN/A // Add the FU onto the list of FU's to be freed next cycle. 8392292SN/A fuPool->freeUnitNextCycle(idx); 8402292SN/A } 8412292SN/A } 8422292SN/A 8432292SN/A DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 8442292SN/A "[sn:%lli]\n", 8452292SN/A tid, issuing_inst->pcState(), 8462292SN/A issuing_inst->seqNum); 8472292SN/A 8482292SN/A readyInsts[op_class].pop(); 8492301SN/A 8501684SN/A if (!readyInsts[op_class].empty()) { 8511684SN/A moveToYoungerInst(order_it); 8522301SN/A } else { 8532301SN/A readyIt[op_class] = listOrder.end(); 8542292SN/A queueOnList[op_class] = false; 8552292SN/A } 8562292SN/A 8571684SN/A issuing_inst->setIssued(); 8581684SN/A ++total_issued; 8592292SN/A 8602326SN/A if (!issuing_inst->isMemRef()) { 8612326SN/A // Memory instructions can not be freed from the IQ until they 8622326SN/A // complete. 8632326SN/A ++freeEntries; 8641684SN/A count[tid]--; 8652292SN/A issuing_inst->clearInIQ(); 8662292SN/A } else { 8672292SN/A memDepUnit[tid].issue(issuing_inst); 8682292SN/A } 8692292SN/A 8701684SN/A listOrder.erase(order_it++); 8711684SN/A statIssuedInstType[tid][op_class]++; 8721684SN/A iewStage->incrWb(issuing_inst->seqNum); 8731684SN/A } else { 8741684SN/A statFuBusy[op_class]++; 8751684SN/A fuBusy[tid]++; 8761684SN/A ++order_it; 8771684SN/A } 8781684SN/A } 8791684SN/A 8801684SN/A numIssuedDist.sample(total_issued); 8811684SN/A iqInstsIssued+= total_issued; 8821684SN/A 8831684SN/A // If we issued any instructions, tell the CPU we had activity. 8841684SN/A // @todo If the way deferred memory instructions are handeled due to 8851684SN/A // translation changes then the deferredMemInsts condition should be removed 8862292SN/A // from the code below. 8871684SN/A if (total_issued || total_deferred_mem_issued || deferredMemInsts.size()) { 8881684SN/A cpu->activityThisCycle(); 8892326SN/A } else { 8902326SN/A DPRINTF(IQ, "Not able to schedule any instructions.\n"); 8912326SN/A } 8921684SN/A} 8932326SN/A 8942292SN/Atemplate <class Impl> 8952326SN/Avoid 8961684SN/AInstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 8971684SN/A{ 8982326SN/A DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 8992326SN/A "to execute.\n", inst); 9002326SN/A 9012326SN/A NonSpecMapIt inst_it = nonSpecInsts.find(inst); 9021684SN/A 9032326SN/A assert(inst_it != nonSpecInsts.end()); 9041684SN/A 9052326SN/A ThreadID tid = (*inst_it).second->threadNumber; 9061684SN/A 9072301SN/A (*inst_it).second->setAtCommit(); 9081684SN/A 9091684SN/A (*inst_it).second->setCanIssue(); 9102326SN/A 9112326SN/A if (!(*inst_it).second->isMemRef()) { 9122326SN/A addIfReady((*inst_it).second); 9132326SN/A } else { 9141684SN/A memDepUnit[tid].nonSpecInstReady((*inst_it).second); 9151684SN/A } 9161684SN/A 9171684SN/A (*inst_it).second = NULL; 9182301SN/A 9192064SN/A nonSpecInsts.erase(inst_it); 9202064SN/A} 9212064SN/A 9222064SN/Atemplate <class Impl> 9232292SN/Avoid 9242064SN/AInstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 9252292SN/A{ 9262292SN/A DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 9272292SN/A tid,inst); 9282292SN/A 9292326SN/A ListIt iq_it = instList[tid].begin(); 9302326SN/A 9312326SN/A while (iq_it != instList[tid].end() && 9322326SN/A (*iq_it)->seqNum <= inst) { 9332326SN/A ++iq_it; 9342326SN/A instList[tid].pop_front(); 9352326SN/A } 9362326SN/A 9372326SN/A assert(freeEntries == (numEntries - countInsts())); 9382326SN/A} 9392292SN/A 9402292SN/Atemplate <class Impl> 9412292SN/Aint 9422064SN/AInstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 9432064SN/A{ 9442064SN/A int dependents = 0; 9452064SN/A 9462292SN/A // The instruction queue here takes care of both floating and int ops 9472064SN/A if (completed_inst->isFloating()) { 9482292SN/A fpInstQueueWakeupQccesses++; 9492064SN/A } else { 9502064SN/A intInstQueueWakeupAccesses++; 9512064SN/A } 9522064SN/A 9532292SN/A DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 9542064SN/A 9552292SN/A assert(!completed_inst->isSquashed()); 9562292SN/A 9572292SN/A // Tell the memory dependence unit to wake any dependents on this 9582292SN/A // instruction if it is a memory instruction. Also complete the memory 9592292SN/A // instruction at this point since we know it executed without issues. 9602292SN/A // @todo: Might want to rename "completeMemInst" to something that 9612292SN/A // indicates that it won't need to be replayed, and call this 9622292SN/A // earlier. Might not be a big deal. 9632292SN/A if (completed_inst->isMemRef()) { 9642292SN/A memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 9652292SN/A completeMemInst(completed_inst); 9662292SN/A } else if (completed_inst->isMemBarrier() || 9672292SN/A completed_inst->isWriteBarrier()) { 9682292SN/A memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 9692292SN/A } 9702292SN/A 9712292SN/A for (int dest_reg_idx = 0; 9722292SN/A dest_reg_idx < completed_inst->numDestRegs(); 9732292SN/A dest_reg_idx++) 9741684SN/A { 9751684SN/A PhysRegIndex dest_reg = 9761684SN/A completed_inst->renamedDestRegIdx(dest_reg_idx); 9771684SN/A 9781061SN/A // Special case of uniq or control registers. They are not 9791061SN/A // handled by the IQ and thus have no dependency graph entry. 9801061SN/A // @todo Figure out a cleaner way to handle this. 9812292SN/A if (dest_reg >= numPhysRegs) { 9821061SN/A DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg, 9831061SN/A numPhysRegs); 9841061SN/A continue; 9851060SN/A } 9862292SN/A 9871060SN/A DPRINTF(IQ, "Waking any dependents on register %i.\n", 9882292SN/A (int) dest_reg); 9892292SN/A 9901060SN/A //Go through the dependency chain, marking the registers as 9911060SN/A //ready within the waiting instructions. 9921060SN/A DynInstPtr dep_inst = dependGraph.pop(dest_reg); 9932292SN/A 9941060SN/A while (dep_inst) { 9951681SN/A DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] " 9962292SN/A "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 9972292SN/A 9981681SN/A // Might want to give more information to the instruction 9991061SN/A // so that it knows which of its source registers is 10001061SN/A // ready. However that would mean that the dependency 10012292SN/A // graph entries would need to hold the src_reg_idx. 10021060SN/A dep_inst->markSrcRegReady(); 10031060SN/A 10041061SN/A addIfReady(dep_inst); 10051061SN/A 10062292SN/A dep_inst = dependGraph.pop(dest_reg); 10071061SN/A 10082326SN/A ++dependents; 10092326SN/A } 10102326SN/A 10111061SN/A // Reset the head node now that all of its dependents have 10122292SN/A // been woken up. 10132292SN/A assert(dependGraph.empty(dest_reg)); 10141061SN/A dependGraph.clearInst(dest_reg); 10151061SN/A 10161061SN/A // Mark the scoreboard as having that register ready. 10172326SN/A regScoreboard[dest_reg] = true; 10182326SN/A } 10192292SN/A return dependents; 10202326SN/A} 10211061SN/A 10221061SN/Atemplate <class Impl> 10231061SN/Avoid 10242292SN/AInstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 10252292SN/A{ 10262326SN/A OpClass op_class = ready_inst->opClass(); 10272292SN/A 10282292SN/A readyInsts[op_class].push(ready_inst); 10292292SN/A 10302292SN/A // Will need to reorder the list if either a queue is not on the list, 10312292SN/A // or it has an older instruction than last time. 10322292SN/A if (!queueOnList[op_class]) { 10331062SN/A addToOrderList(op_class); 10341061SN/A } else if (readyInsts[op_class].top()->seqNum < 10352292SN/A (*readyIt[op_class]).oldestInst) { 10362336SN/A listOrder.erase(readyIt[op_class]); 10372292SN/A addToOrderList(op_class); 10382292SN/A } 10391061SN/A 10401061SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 10411681SN/A "the ready list, PC %s opclass:%i [sn:%lli].\n", 10421061SN/A ready_inst->pcState(), op_class, ready_inst->seqNum); 10431061SN/A} 10441061SN/A 10451061SN/Atemplate <class Impl> 10461061SN/Avoid 10472326SN/AInstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 10482326SN/A{ 10492326SN/A DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 10502326SN/A 10512326SN/A // Reset DTB translation state 10522326SN/A resched_inst->translationStarted = false; 10532326SN/A resched_inst->translationCompleted = false; 10542326SN/A 10552292SN/A resched_inst->clearCanIssue(); 10561061SN/A memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 10571061SN/A} 10582326SN/A 10591061SN/Atemplate <class Impl> 10601062SN/Avoid 10612292SN/AInstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 10621062SN/A{ 10631061SN/A memDepUnit[replay_inst->threadNumber].replay(replay_inst); 10642064SN/A} 10652292SN/A 10662292SN/Atemplate <class Impl> 10672292SN/Avoid 10681062SN/AInstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 10692292SN/A{ 10701681SN/A ThreadID tid = completed_inst->threadNumber; 10712292SN/A 10721062SN/A DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n", 10731062SN/A completed_inst->pcState(), completed_inst->seqNum); 10741061SN/A 10751061SN/A ++freeEntries; 10761061SN/A 10771061SN/A completed_inst->memOpDone = true; 10781061SN/A 10791061SN/A memDepUnit[tid].completed(completed_inst); 10801061SN/A count[tid]--; 10812292SN/A} 10822292SN/A 10831681SN/Atemplate <class Impl> 10841681SN/Avoid 10852292SN/AInstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst) 10862292SN/A{ 10872292SN/A deferredMemInsts.push_back(deferred_inst); 10882292SN/A} 10891681SN/A 10901681SN/Atemplate <class Impl> 10911061SN/Atypename Impl::DynInstPtr 10922326SN/AInstructionQueue<Impl>::getDeferredMemInstToExecute() 10932326SN/A{ 10942326SN/A for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); 10951061SN/A ++it) { 10961061SN/A if ((*it)->translationCompleted) { 10972326SN/A DynInstPtr ret = *it; 10981062SN/A deferredMemInsts.erase(it); 10991061SN/A return ret; 11001060SN/A } 11011060SN/A } 11021061SN/A return NULL; 11031060SN/A} 11041061SN/A 11051060SN/Atemplate <class Impl> 11061060SN/Avoid 11071060SN/AInstructionQueue<Impl>::violation(DynInstPtr &store, 11081060SN/A DynInstPtr &faulting_load) 11091060SN/A{ 11101060SN/A intInstQueueWrites++; 11111060SN/A memDepUnit[store->threadNumber].violation(store, faulting_load); 11121060SN/A} 11131060SN/A 11141060SN/Atemplate <class Impl> 11151060SN/Avoid 11161060SN/AInstructionQueue<Impl>::squash(ThreadID tid) 11171060SN/A{ 11181060SN/A DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 11191060SN/A "the IQ.\n", tid); 11201060SN/A 11211060SN/A // Read instruction sequence number of last instruction out of the 11221060SN/A // time buffer. 11231061SN/A squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 11241061SN/A 11251061SN/A // Call doSquash if there are insts in the IQ 11262292SN/A if (count[tid] > 0) { 11271060SN/A doSquash(tid); 11281060SN/A } 11291060SN/A 11302326SN/A // Also tell the memory dependence unit to squash. 11311060SN/A memDepUnit[tid].squash(squashedSeqNum[tid], tid); 11321060SN/A} 11331060SN/A 11341060SN/Atemplate <class Impl> 11351060SN/Avoid 11362292SN/AInstructionQueue<Impl>::doSquash(ThreadID tid) 11371060SN/A{ 11381060SN/A // Start at the tail. 11391060SN/A ListIt squash_it = instList[tid].end(); 11402326SN/A --squash_it; 11411060SN/A 11421060SN/A DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 11431060SN/A tid, squashedSeqNum[tid]); 11441060SN/A 11451060SN/A // Squash any instructions younger than the squashed sequence number 11461060SN/A // given. 11471060SN/A while (squash_it != instList[tid].end() && 11481061SN/A (*squash_it)->seqNum > squashedSeqNum[tid]) { 11491060SN/A 11502326SN/A DynInstPtr squashed_inst = (*squash_it); 11511060SN/A squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 11522326SN/A 11532326SN/A // Only handle the instruction if it actually is in the IQ and 11542326SN/A // hasn't already been squashed in the IQ. 11552326SN/A if (squashed_inst->threadNumber != tid || 11561060SN/A squashed_inst->isSquashedInIQ()) { 11571060SN/A --squash_it; 11581060SN/A continue; 11591060SN/A } 11601060SN/A 11611060SN/A if (!squashed_inst->isIssued() || 11621061SN/A (squashed_inst->isMemRef() && 11631061SN/A !squashed_inst->memOpDone)) { 11641061SN/A 11651061SN/A DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", 11661061SN/A tid, squashed_inst->seqNum, squashed_inst->pcState()); 11671061SN/A 11681061SN/A // Remove the instruction from the dependency list. 11691061SN/A if (!squashed_inst->isNonSpeculative() && 11701060SN/A !squashed_inst->isStoreConditional() && 11711060SN/A !squashed_inst->isMemBarrier() && 11722326SN/A !squashed_inst->isWriteBarrier()) { 11732326SN/A 11742292SN/A for (int src_reg_idx = 0; 11752064SN/A src_reg_idx < squashed_inst->numSrcRegs(); 11761062SN/A src_reg_idx++) 11772326SN/A { 11781062SN/A PhysRegIndex src_reg = 11791060SN/A squashed_inst->renamedSrcRegIdx(src_reg_idx); 11801060SN/A 11811060SN/A // Only remove it from the dependency graph if it 11821060SN/A // was placed there in the first place. 11831060SN/A 11841061SN/A // Instead of doing a linked list traversal, we 11851060SN/A // can just remove these squashed instructions 11861061SN/A // either at issue time, or when the register is 11871060SN/A // overwritten. The only downside to this is it 11882326SN/A // leaves more room for error. 11891060SN/A 11901060SN/A if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 11911061SN/A src_reg < numPhysRegs) { 11921060SN/A dependGraph.remove(src_reg, squashed_inst); 11932292SN/A } 11941061SN/A 11952292SN/A 11961061SN/A ++iqSquashedOperandsExamined; 11971062SN/A } 11981062SN/A } else if (!squashed_inst->isStoreConditional() || 11992292SN/A !squashed_inst->isCompleted()) { 12001062SN/A NonSpecMapIt ns_inst_it = 12012292SN/A nonSpecInsts.find(squashed_inst->seqNum); 12022292SN/A 12031062SN/A if (ns_inst_it == nonSpecInsts.end()) { 12042292SN/A assert(squashed_inst->getFault() != NoFault); 12051061SN/A } else { 12062292SN/A 12072292SN/A (*ns_inst_it).second = NULL; 12082292SN/A 12091061SN/A nonSpecInsts.erase(ns_inst_it); 12102292SN/A 12111061SN/A ++iqSquashedNonSpecRemoved; 12122326SN/A } 12132326SN/A } 12142326SN/A 12152326SN/A // Might want to also clear out the head of the dependency graph. 12162326SN/A 12172326SN/A // Mark it as squashed within the IQ. 12182326SN/A squashed_inst->setSquashedInIQ(); 12192326SN/A 12201060SN/A // @todo: Remove this hack where several statuses are set so the 12211060SN/A // inst will flow through the rest of the pipeline. 12221060SN/A squashed_inst->setIssued(); 12231060SN/A squashed_inst->setCanCommit(); 12241061SN/A squashed_inst->clearInIQ(); 12251061SN/A 12261061SN/A //Update Thread IQ Count 12271061SN/A count[squashed_inst->threadNumber]--; 12282698Sktlim@umich.edu 12292292SN/A ++freeEntries; 12302292SN/A } 12312292SN/A 12322698Sktlim@umich.edu instList[tid].erase(squash_it--); 12331061SN/A ++iqSquashedInstsExamined; 12341061SN/A } 12352292SN/A} 12362292SN/A 12371681SN/Atemplate <class Impl> 12382292SN/Abool 12392292SN/AInstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 12402292SN/A{ 12412292SN/A // Loop through the instruction's source registers, adding 12422292SN/A // them to the dependency list if they are not ready. 12432292SN/A int8_t total_src_regs = new_inst->numSrcRegs(); 12442292SN/A bool return_val = false; 12452292SN/A 12462292SN/A for (int src_reg_idx = 0; 12472292SN/A src_reg_idx < total_src_regs; 12482292SN/A src_reg_idx++) 12492292SN/A { 12502292SN/A // Only add it to the dependency graph if it's not ready. 12511061SN/A if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 12521061SN/A PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 12531061SN/A 12541061SN/A // Check the IQ's scoreboard to make sure the register 12552292SN/A // hasn't become ready while the instruction was in flight 12562292SN/A // between stages. Only if it really isn't ready should 12572292SN/A // it be added to the dependency graph. 12581681SN/A if (src_reg >= numPhysRegs) { 12591681SN/A continue; 12601681SN/A } else if (regScoreboard[src_reg] == false) { 12611681SN/A DPRINTF(IQ, "Instruction PC %s has src reg %i that " 12621061SN/A "is being added to the dependency chain.\n", 12631061SN/A new_inst->pcState(), src_reg); 12642292SN/A 12652292SN/A dependGraph.insert(src_reg, new_inst); 12661061SN/A 12672292SN/A // Change the return value to indicate that something 12682292SN/A // was added to the dependency graph. 12691061SN/A return_val = true; 12701061SN/A } else { 12711061SN/A DPRINTF(IQ, "Instruction PC %s has src reg %i that " 12722292SN/A "became ready before it reached the IQ.\n", 12732292SN/A new_inst->pcState(), src_reg); 12741061SN/A // Mark a register ready within the instruction. 12751061SN/A new_inst->markSrcRegReady(src_reg_idx); 12761061SN/A } 12772292SN/A } 12782292SN/A } 12792292SN/A 12801061SN/A return return_val; 12811061SN/A} 12821061SN/A 12831061SN/Atemplate <class Impl> 12841061SN/Avoid 12852292SN/AInstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) 12862292SN/A{ 12872292SN/A // Nothing really needs to be marked when an instruction becomes 12882292SN/A // the producer of a register's value, but for convenience a ptr 12892292SN/A // to the producing instruction will be placed in the head node of 12902292SN/A // the dependency links. 12912292SN/A int8_t total_dest_regs = new_inst->numDestRegs(); 12922292SN/A 12932292SN/A for (int dest_reg_idx = 0; 12942292SN/A dest_reg_idx < total_dest_regs; 12952292SN/A dest_reg_idx++) 12962292SN/A { 12972292SN/A PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 12982292SN/A 12992292SN/A // Instructions that use the misc regs will have a reg number 13001061SN/A // higher than the normal physical registers. In this case these 13012292SN/A // registers are not renamed, and there is no need to track 13022292SN/A // dependencies as these instructions must be executed at commit. 13032292SN/A if (dest_reg >= numPhysRegs) { 13042292SN/A continue; 13052292SN/A } 13062292SN/A 13072292SN/A if (!dependGraph.empty(dest_reg)) { 13082292SN/A dependGraph.dump(); 13092292SN/A panic("Dependency graph %i not empty!", dest_reg); 13102292SN/A } 13112292SN/A 13122292SN/A dependGraph.setInst(dest_reg, new_inst); 13132292SN/A 13142292SN/A // Mark the scoreboard to say it's not yet ready. 13152292SN/A regScoreboard[dest_reg] = false; 13162292SN/A } 13172292SN/A} 13182292SN/A 13192292SN/Atemplate <class Impl> 13202292SN/Avoid 13212292SN/AInstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 13222326SN/A{ 13232326SN/A // If the instruction now has all of its source registers 13242292SN/A // available, then add it to the list of ready instructions. 13252292SN/A if (inst->readyToIssue()) { 13262292SN/A 13272292SN/A //Add the instruction to the proper ready list. 13282292SN/A if (inst->isMemRef()) { 13292292SN/A 13302292SN/A DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 13312292SN/A 13322292SN/A // Message to the mem dependence unit that this instruction has 13332292SN/A // its registers ready. 13342292SN/A memDepUnit[inst->threadNumber].regsReady(inst); 13352292SN/A 13362292SN/A return; 13372292SN/A } 13382292SN/A 13392292SN/A OpClass op_class = inst->opClass(); 13402292SN/A 13412292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 13422292SN/A "the ready list, PC %s opclass:%i [sn:%lli].\n", 13432292SN/A inst->pcState(), op_class, inst->seqNum); 13442292SN/A 13452292SN/A readyInsts[op_class].push(inst); 13462292SN/A 13472348SN/A // Will need to reorder the list if either a queue is not on the list, 13482348SN/A // or it has an older instruction than last time. 13492348SN/A if (!queueOnList[op_class]) { 13502348SN/A addToOrderList(op_class); 13512348SN/A } else if (readyInsts[op_class].top()->seqNum < 13522348SN/A (*readyIt[op_class]).oldestInst) { 13532348SN/A listOrder.erase(readyIt[op_class]); 13542348SN/A addToOrderList(op_class); 13552348SN/A } 13562348SN/A } 13572348SN/A} 13582348SN/A 13592348SN/Atemplate <class Impl> 13602348SN/Aint 13612348SN/AInstructionQueue<Impl>::countInsts() 13622348SN/A{ 13632348SN/A#if 0 13642348SN/A //ksewell:This works but definitely could use a cleaner write 13652348SN/A //with a more intuitive way of counting. Right now it's 13662348SN/A //just brute force .... 13672348SN/A // Change the #if if you want to use this method. 13682348SN/A int total_insts = 0; 13692348SN/A 13702348SN/A for (ThreadID tid = 0; tid < numThreads; ++tid) { 13712348SN/A ListIt count_it = instList[tid].begin(); 13722348SN/A 13732348SN/A while (count_it != instList[tid].end()) { 13742348SN/A if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 13752348SN/A if (!(*count_it)->isIssued()) { 13762348SN/A ++total_insts; 13772348SN/A } else if ((*count_it)->isMemRef() && 13782348SN/A !(*count_it)->memOpDone) { 13792348SN/A // Loads that have not been marked as executed still count 13802348SN/A // towards the total instructions. 13812348SN/A ++total_insts; 13822348SN/A } 13832348SN/A } 13842348SN/A 13852348SN/A ++count_it; 13862348SN/A } 13872348SN/A } 13882292SN/A 1389 return total_insts; 1390#else 1391 return numEntries - freeEntries; 1392#endif 1393} 1394 1395template <class Impl> 1396void 1397InstructionQueue<Impl>::dumpLists() 1398{ 1399 for (int i = 0; i < Num_OpClasses; ++i) { 1400 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 1401 1402 cprintf("\n"); 1403 } 1404 1405 cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 1406 1407 NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 1408 NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 1409 1410 cprintf("Non speculative list: "); 1411 1412 while (non_spec_it != non_spec_end_it) { 1413 cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(), 1414 (*non_spec_it).second->seqNum); 1415 ++non_spec_it; 1416 } 1417 1418 cprintf("\n"); 1419 1420 ListOrderIt list_order_it = listOrder.begin(); 1421 ListOrderIt list_order_end_it = listOrder.end(); 1422 int i = 1; 1423 1424 cprintf("List order: "); 1425 1426 while (list_order_it != list_order_end_it) { 1427 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 1428 (*list_order_it).oldestInst); 1429 1430 ++list_order_it; 1431 ++i; 1432 } 1433 1434 cprintf("\n"); 1435} 1436 1437 1438template <class Impl> 1439void 1440InstructionQueue<Impl>::dumpInsts() 1441{ 1442 for (ThreadID tid = 0; tid < numThreads; ++tid) { 1443 int num = 0; 1444 int valid_num = 0; 1445 ListIt inst_list_it = instList[tid].begin(); 1446 1447 while (inst_list_it != instList[tid].end()) { 1448 cprintf("Instruction:%i\n", num); 1449 if (!(*inst_list_it)->isSquashed()) { 1450 if (!(*inst_list_it)->isIssued()) { 1451 ++valid_num; 1452 cprintf("Count:%i\n", valid_num); 1453 } else if ((*inst_list_it)->isMemRef() && 1454 !(*inst_list_it)->memOpDone) { 1455 // Loads that have not been marked as executed 1456 // still count towards the total instructions. 1457 ++valid_num; 1458 cprintf("Count:%i\n", valid_num); 1459 } 1460 } 1461 1462 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 1463 "Issued:%i\nSquashed:%i\n", 1464 (*inst_list_it)->pcState(), 1465 (*inst_list_it)->seqNum, 1466 (*inst_list_it)->threadNumber, 1467 (*inst_list_it)->isIssued(), 1468 (*inst_list_it)->isSquashed()); 1469 1470 if ((*inst_list_it)->isMemRef()) { 1471 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 1472 } 1473 1474 cprintf("\n"); 1475 1476 inst_list_it++; 1477 ++num; 1478 } 1479 } 1480 1481 cprintf("Insts to Execute list:\n"); 1482 1483 int num = 0; 1484 int valid_num = 0; 1485 ListIt inst_list_it = instsToExecute.begin(); 1486 1487 while (inst_list_it != instsToExecute.end()) 1488 { 1489 cprintf("Instruction:%i\n", 1490 num); 1491 if (!(*inst_list_it)->isSquashed()) { 1492 if (!(*inst_list_it)->isIssued()) { 1493 ++valid_num; 1494 cprintf("Count:%i\n", valid_num); 1495 } else if ((*inst_list_it)->isMemRef() && 1496 !(*inst_list_it)->memOpDone) { 1497 // Loads that have not been marked as executed 1498 // still count towards the total instructions. 1499 ++valid_num; 1500 cprintf("Count:%i\n", valid_num); 1501 } 1502 } 1503 1504 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 1505 "Issued:%i\nSquashed:%i\n", 1506 (*inst_list_it)->pcState(), 1507 (*inst_list_it)->seqNum, 1508 (*inst_list_it)->threadNumber, 1509 (*inst_list_it)->isIssued(), 1510 (*inst_list_it)->isSquashed()); 1511 1512 if ((*inst_list_it)->isMemRef()) { 1513 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 1514 } 1515 1516 cprintf("\n"); 1517 1518 inst_list_it++; 1519 ++num; 1520 } 1521} 1522