inst_queue_impl.hh revision 8232
11689SN/A/* 27944SGiacomo.Gabrielli@arm.com * Copyright (c) 2011 ARM Limited 37944SGiacomo.Gabrielli@arm.com * All rights reserved. 47944SGiacomo.Gabrielli@arm.com * 57944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 67944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 77944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 87944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 97944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 107944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 117944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 127944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 137944SGiacomo.Gabrielli@arm.com * 142326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412831Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 442064SN/A#include <limits> 451060SN/A#include <vector> 461060SN/A 472292SN/A#include "cpu/o3/fu_pool.hh" 481717SN/A#include "cpu/o3/inst_queue.hh" 498232Snate@binkert.org#include "debug/IQ.hh" 504762Snate@binkert.org#include "enums/OpClass.hh" 516221Snate@binkert.org#include "params/DerivO3CPU.hh" 524762Snate@binkert.org#include "sim/core.hh" 531060SN/A 546221Snate@binkert.orgusing namespace std; 555529Snate@binkert.org 561061SN/Atemplate <class Impl> 572292SN/AInstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 585606Snate@binkert.org int fu_idx, InstructionQueue<Impl> *iq_ptr) 595606Snate@binkert.org : Event(Stat_Event_Pri), inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), 605606Snate@binkert.org freeFU(false) 611060SN/A{ 622292SN/A this->setFlags(Event::AutoDelete); 632292SN/A} 642292SN/A 652292SN/Atemplate <class Impl> 662292SN/Avoid 672292SN/AInstructionQueue<Impl>::FUCompletion::process() 682292SN/A{ 692326SN/A iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 702292SN/A inst = NULL; 712292SN/A} 722292SN/A 732292SN/A 742292SN/Atemplate <class Impl> 752292SN/Aconst char * 765336Shines@cs.fsu.eduInstructionQueue<Impl>::FUCompletion::description() const 772292SN/A{ 784873Sstever@eecs.umich.edu return "Functional unit completion"; 792292SN/A} 802292SN/A 812292SN/Atemplate <class Impl> 824329Sktlim@umich.eduInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 835529Snate@binkert.org DerivO3CPUParams *params) 844329Sktlim@umich.edu : cpu(cpu_ptr), 854329Sktlim@umich.edu iewStage(iew_ptr), 864329Sktlim@umich.edu fuPool(params->fuPool), 872292SN/A numEntries(params->numIQEntries), 882292SN/A totalWidth(params->issueWidth), 892292SN/A numPhysIntRegs(params->numPhysIntRegs), 902292SN/A numPhysFloatRegs(params->numPhysFloatRegs), 912292SN/A commitToIEWDelay(params->commitToIEWDelay) 922292SN/A{ 932292SN/A assert(fuPool); 942292SN/A 952307SN/A switchedOut = false; 962307SN/A 975529Snate@binkert.org numThreads = params->numThreads; 981060SN/A 991060SN/A // Set the number of physical registers as the number of int + float 1001060SN/A numPhysRegs = numPhysIntRegs + numPhysFloatRegs; 1011060SN/A 1021060SN/A //Create an entry for each physical register within the 1031060SN/A //dependency graph. 1042326SN/A dependGraph.resize(numPhysRegs); 1051060SN/A 1061060SN/A // Resize the register scoreboard. 1071060SN/A regScoreboard.resize(numPhysRegs); 1081060SN/A 1092292SN/A //Initialize Mem Dependence Units 1106221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1116221Snate@binkert.org memDepUnit[tid].init(params, tid); 1126221Snate@binkert.org memDepUnit[tid].setIQ(this); 1131060SN/A } 1141060SN/A 1152307SN/A resetState(); 1162292SN/A 1172980Sgblack@eecs.umich.edu std::string policy = params->smtIQPolicy; 1182292SN/A 1192292SN/A //Convert string to lowercase 1202292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1212292SN/A (int(*)(int)) tolower); 1222292SN/A 1232292SN/A //Figure out resource sharing policy 1242292SN/A if (policy == "dynamic") { 1252292SN/A iqPolicy = Dynamic; 1262292SN/A 1272292SN/A //Set Max Entries to Total ROB Capacity 1286221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1296221Snate@binkert.org maxEntries[tid] = numEntries; 1302292SN/A } 1312292SN/A 1322292SN/A } else if (policy == "partitioned") { 1332292SN/A iqPolicy = Partitioned; 1342292SN/A 1352292SN/A //@todo:make work if part_amt doesnt divide evenly. 1362292SN/A int part_amt = numEntries / numThreads; 1372292SN/A 1382292SN/A //Divide ROB up evenly 1396221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1406221Snate@binkert.org maxEntries[tid] = part_amt; 1412292SN/A } 1422292SN/A 1432831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 1442292SN/A "%i entries per thread.\n",part_amt); 1452292SN/A } else if (policy == "threshold") { 1462292SN/A iqPolicy = Threshold; 1472292SN/A 1482292SN/A double threshold = (double)params->smtIQThreshold / 100; 1492292SN/A 1502292SN/A int thresholdIQ = (int)((double)threshold * numEntries); 1512292SN/A 1522292SN/A //Divide up by threshold amount 1536221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1546221Snate@binkert.org maxEntries[tid] = thresholdIQ; 1552292SN/A } 1562292SN/A 1572831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Threshold:" 1582292SN/A "%i entries per thread.\n",thresholdIQ); 1592292SN/A } else { 1602292SN/A assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 1612292SN/A "Partitioned, Threshold}"); 1622292SN/A } 1632292SN/A} 1642292SN/A 1652292SN/Atemplate <class Impl> 1662292SN/AInstructionQueue<Impl>::~InstructionQueue() 1672292SN/A{ 1682326SN/A dependGraph.reset(); 1692348SN/A#ifdef DEBUG 1702326SN/A cprintf("Nodes traversed: %i, removed: %i\n", 1712326SN/A dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1722348SN/A#endif 1732292SN/A} 1742292SN/A 1752292SN/Atemplate <class Impl> 1762292SN/Astd::string 1772292SN/AInstructionQueue<Impl>::name() const 1782292SN/A{ 1792292SN/A return cpu->name() + ".iq"; 1801060SN/A} 1811060SN/A 1821061SN/Atemplate <class Impl> 1831060SN/Avoid 1841062SN/AInstructionQueue<Impl>::regStats() 1851062SN/A{ 1862301SN/A using namespace Stats; 1871062SN/A iqInstsAdded 1881062SN/A .name(name() + ".iqInstsAdded") 1891062SN/A .desc("Number of instructions added to the IQ (excludes non-spec)") 1901062SN/A .prereq(iqInstsAdded); 1911062SN/A 1921062SN/A iqNonSpecInstsAdded 1931062SN/A .name(name() + ".iqNonSpecInstsAdded") 1941062SN/A .desc("Number of non-speculative instructions added to the IQ") 1951062SN/A .prereq(iqNonSpecInstsAdded); 1961062SN/A 1972301SN/A iqInstsIssued 1982301SN/A .name(name() + ".iqInstsIssued") 1992301SN/A .desc("Number of instructions issued") 2002301SN/A .prereq(iqInstsIssued); 2011062SN/A 2021062SN/A iqIntInstsIssued 2031062SN/A .name(name() + ".iqIntInstsIssued") 2041062SN/A .desc("Number of integer instructions issued") 2051062SN/A .prereq(iqIntInstsIssued); 2061062SN/A 2071062SN/A iqFloatInstsIssued 2081062SN/A .name(name() + ".iqFloatInstsIssued") 2091062SN/A .desc("Number of float instructions issued") 2101062SN/A .prereq(iqFloatInstsIssued); 2111062SN/A 2121062SN/A iqBranchInstsIssued 2131062SN/A .name(name() + ".iqBranchInstsIssued") 2141062SN/A .desc("Number of branch instructions issued") 2151062SN/A .prereq(iqBranchInstsIssued); 2161062SN/A 2171062SN/A iqMemInstsIssued 2181062SN/A .name(name() + ".iqMemInstsIssued") 2191062SN/A .desc("Number of memory instructions issued") 2201062SN/A .prereq(iqMemInstsIssued); 2211062SN/A 2221062SN/A iqMiscInstsIssued 2231062SN/A .name(name() + ".iqMiscInstsIssued") 2241062SN/A .desc("Number of miscellaneous instructions issued") 2251062SN/A .prereq(iqMiscInstsIssued); 2261062SN/A 2271062SN/A iqSquashedInstsIssued 2281062SN/A .name(name() + ".iqSquashedInstsIssued") 2291062SN/A .desc("Number of squashed instructions issued") 2301062SN/A .prereq(iqSquashedInstsIssued); 2311062SN/A 2321062SN/A iqSquashedInstsExamined 2331062SN/A .name(name() + ".iqSquashedInstsExamined") 2341062SN/A .desc("Number of squashed instructions iterated over during squash;" 2351062SN/A " mainly for profiling") 2361062SN/A .prereq(iqSquashedInstsExamined); 2371062SN/A 2381062SN/A iqSquashedOperandsExamined 2391062SN/A .name(name() + ".iqSquashedOperandsExamined") 2401062SN/A .desc("Number of squashed operands that are examined and possibly " 2411062SN/A "removed from graph") 2421062SN/A .prereq(iqSquashedOperandsExamined); 2431062SN/A 2441062SN/A iqSquashedNonSpecRemoved 2451062SN/A .name(name() + ".iqSquashedNonSpecRemoved") 2461062SN/A .desc("Number of squashed non-spec instructions that were removed") 2471062SN/A .prereq(iqSquashedNonSpecRemoved); 2482361SN/A/* 2492326SN/A queueResDist 2502301SN/A .init(Num_OpClasses, 0, 99, 2) 2512301SN/A .name(name() + ".IQ:residence:") 2522301SN/A .desc("cycles from dispatch to issue") 2532301SN/A .flags(total | pdf | cdf ) 2542301SN/A ; 2552301SN/A for (int i = 0; i < Num_OpClasses; ++i) { 2562326SN/A queueResDist.subname(i, opClassStrings[i]); 2572301SN/A } 2582361SN/A*/ 2592326SN/A numIssuedDist 2602307SN/A .init(0,totalWidth,1) 2612301SN/A .name(name() + ".ISSUE:issued_per_cycle") 2622301SN/A .desc("Number of insts issued each cycle") 2632307SN/A .flags(pdf) 2642301SN/A ; 2652301SN/A/* 2662301SN/A dist_unissued 2672301SN/A .init(Num_OpClasses+2) 2682301SN/A .name(name() + ".ISSUE:unissued_cause") 2692301SN/A .desc("Reason ready instruction not issued") 2702301SN/A .flags(pdf | dist) 2712301SN/A ; 2722301SN/A for (int i=0; i < (Num_OpClasses + 2); ++i) { 2732301SN/A dist_unissued.subname(i, unissued_names[i]); 2742301SN/A } 2752301SN/A*/ 2762326SN/A statIssuedInstType 2774762Snate@binkert.org .init(numThreads,Enums::Num_OpClass) 2782301SN/A .name(name() + ".ISSUE:FU_type") 2792301SN/A .desc("Type of FU issued") 2802301SN/A .flags(total | pdf | dist) 2812301SN/A ; 2824762Snate@binkert.org statIssuedInstType.ysubnames(Enums::OpClassStrings); 2832301SN/A 2842301SN/A // 2852301SN/A // How long did instructions for a particular FU type wait prior to issue 2862301SN/A // 2872361SN/A/* 2882326SN/A issueDelayDist 2892301SN/A .init(Num_OpClasses,0,99,2) 2902301SN/A .name(name() + ".ISSUE:") 2912301SN/A .desc("cycles from operands ready to issue") 2922301SN/A .flags(pdf | cdf) 2932301SN/A ; 2942301SN/A 2952301SN/A for (int i=0; i<Num_OpClasses; ++i) { 2962980Sgblack@eecs.umich.edu std::stringstream subname; 2972301SN/A subname << opClassStrings[i] << "_delay"; 2982326SN/A issueDelayDist.subname(i, subname.str()); 2992301SN/A } 3002361SN/A*/ 3012326SN/A issueRate 3022301SN/A .name(name() + ".ISSUE:rate") 3032301SN/A .desc("Inst issue rate") 3042301SN/A .flags(total) 3052301SN/A ; 3062326SN/A issueRate = iqInstsIssued / cpu->numCycles; 3072727Sktlim@umich.edu 3082326SN/A statFuBusy 3092301SN/A .init(Num_OpClasses) 3102301SN/A .name(name() + ".ISSUE:fu_full") 3112301SN/A .desc("attempts to use FU when none available") 3122301SN/A .flags(pdf | dist) 3132301SN/A ; 3142301SN/A for (int i=0; i < Num_OpClasses; ++i) { 3154762Snate@binkert.org statFuBusy.subname(i, Enums::OpClassStrings[i]); 3162301SN/A } 3172301SN/A 3182326SN/A fuBusy 3192301SN/A .init(numThreads) 3202301SN/A .name(name() + ".ISSUE:fu_busy_cnt") 3212301SN/A .desc("FU busy when requested") 3222301SN/A .flags(total) 3232301SN/A ; 3242301SN/A 3252326SN/A fuBusyRate 3262301SN/A .name(name() + ".ISSUE:fu_busy_rate") 3272301SN/A .desc("FU busy rate (busy events/executed inst)") 3282301SN/A .flags(total) 3292301SN/A ; 3302326SN/A fuBusyRate = fuBusy / iqInstsIssued; 3312301SN/A 3326221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3332292SN/A // Tell mem dependence unit to reg stats as well. 3346221Snate@binkert.org memDepUnit[tid].regStats(); 3352292SN/A } 3367897Shestness@cs.utexas.edu 3377897Shestness@cs.utexas.edu intInstQueueReads 3387897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_reads") 3397897Shestness@cs.utexas.edu .desc("Number of integer instruction queue reads") 3407897Shestness@cs.utexas.edu .flags(total); 3417897Shestness@cs.utexas.edu 3427897Shestness@cs.utexas.edu intInstQueueWrites 3437897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_writes") 3447897Shestness@cs.utexas.edu .desc("Number of integer instruction queue writes") 3457897Shestness@cs.utexas.edu .flags(total); 3467897Shestness@cs.utexas.edu 3477897Shestness@cs.utexas.edu intInstQueueWakeupAccesses 3487897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_wakeup_accesses") 3497897Shestness@cs.utexas.edu .desc("Number of integer instruction queue wakeup accesses") 3507897Shestness@cs.utexas.edu .flags(total); 3517897Shestness@cs.utexas.edu 3527897Shestness@cs.utexas.edu fpInstQueueReads 3537897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_reads") 3547897Shestness@cs.utexas.edu .desc("Number of floating instruction queue reads") 3557897Shestness@cs.utexas.edu .flags(total); 3567897Shestness@cs.utexas.edu 3577897Shestness@cs.utexas.edu fpInstQueueWrites 3587897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_writes") 3597897Shestness@cs.utexas.edu .desc("Number of floating instruction queue writes") 3607897Shestness@cs.utexas.edu .flags(total); 3617897Shestness@cs.utexas.edu 3627897Shestness@cs.utexas.edu fpInstQueueWakeupQccesses 3637897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_wakeup_accesses") 3647897Shestness@cs.utexas.edu .desc("Number of floating instruction queue wakeup accesses") 3657897Shestness@cs.utexas.edu .flags(total); 3667897Shestness@cs.utexas.edu 3677897Shestness@cs.utexas.edu intAluAccesses 3687897Shestness@cs.utexas.edu .name(name() + ".int_alu_accesses") 3697897Shestness@cs.utexas.edu .desc("Number of integer alu accesses") 3707897Shestness@cs.utexas.edu .flags(total); 3717897Shestness@cs.utexas.edu 3727897Shestness@cs.utexas.edu fpAluAccesses 3737897Shestness@cs.utexas.edu .name(name() + ".fp_alu_accesses") 3747897Shestness@cs.utexas.edu .desc("Number of floating point alu accesses") 3757897Shestness@cs.utexas.edu .flags(total); 3767897Shestness@cs.utexas.edu 3771062SN/A} 3781062SN/A 3791062SN/Atemplate <class Impl> 3801062SN/Avoid 3812307SN/AInstructionQueue<Impl>::resetState() 3821060SN/A{ 3832307SN/A //Initialize thread IQ counts 3846221Snate@binkert.org for (ThreadID tid = 0; tid <numThreads; tid++) { 3856221Snate@binkert.org count[tid] = 0; 3866221Snate@binkert.org instList[tid].clear(); 3872307SN/A } 3881060SN/A 3892307SN/A // Initialize the number of free IQ entries. 3902307SN/A freeEntries = numEntries; 3912307SN/A 3922307SN/A // Note that in actuality, the registers corresponding to the logical 3932307SN/A // registers start off as ready. However this doesn't matter for the 3942307SN/A // IQ as the instruction should have been correctly told if those 3952307SN/A // registers are ready in rename. Thus it can all be initialized as 3962307SN/A // unready. 3972307SN/A for (int i = 0; i < numPhysRegs; ++i) { 3982307SN/A regScoreboard[i] = false; 3992307SN/A } 4002307SN/A 4016221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 4026221Snate@binkert.org squashedSeqNum[tid] = 0; 4032307SN/A } 4042307SN/A 4052307SN/A for (int i = 0; i < Num_OpClasses; ++i) { 4062307SN/A while (!readyInsts[i].empty()) 4072307SN/A readyInsts[i].pop(); 4082307SN/A queueOnList[i] = false; 4092307SN/A readyIt[i] = listOrder.end(); 4102307SN/A } 4112307SN/A nonSpecInsts.clear(); 4122307SN/A listOrder.clear(); 4137944SGiacomo.Gabrielli@arm.com deferredMemInsts.clear(); 4141060SN/A} 4151060SN/A 4161061SN/Atemplate <class Impl> 4171060SN/Avoid 4186221Snate@binkert.orgInstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 4191060SN/A{ 4202292SN/A activeThreads = at_ptr; 4212064SN/A} 4222064SN/A 4232064SN/Atemplate <class Impl> 4242064SN/Avoid 4252292SN/AInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 4262064SN/A{ 4274318Sktlim@umich.edu issueToExecuteQueue = i2e_ptr; 4281060SN/A} 4291060SN/A 4301061SN/Atemplate <class Impl> 4311060SN/Avoid 4321060SN/AInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 4331060SN/A{ 4341060SN/A timeBuffer = tb_ptr; 4351060SN/A 4361060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 4371060SN/A} 4381060SN/A 4391684SN/Atemplate <class Impl> 4402307SN/Avoid 4412307SN/AInstructionQueue<Impl>::switchOut() 4422307SN/A{ 4432367SN/A/* 4442367SN/A if (!instList[0].empty() || (numEntries != freeEntries) || 4452367SN/A !readyInsts[0].empty() || !nonSpecInsts.empty() || !listOrder.empty()) { 4462367SN/A dumpInsts(); 4472367SN/A// assert(0); 4482367SN/A } 4492367SN/A*/ 4502307SN/A resetState(); 4512326SN/A dependGraph.reset(); 4522367SN/A instsToExecute.clear(); 4532307SN/A switchedOut = true; 4546221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 4556221Snate@binkert.org memDepUnit[tid].switchOut(); 4562307SN/A } 4572307SN/A} 4582307SN/A 4592307SN/Atemplate <class Impl> 4602307SN/Avoid 4612307SN/AInstructionQueue<Impl>::takeOverFrom() 4622307SN/A{ 4632307SN/A switchedOut = false; 4642307SN/A} 4652307SN/A 4662307SN/Atemplate <class Impl> 4672292SN/Aint 4686221Snate@binkert.orgInstructionQueue<Impl>::entryAmount(ThreadID num_threads) 4692292SN/A{ 4702292SN/A if (iqPolicy == Partitioned) { 4712292SN/A return numEntries / num_threads; 4722292SN/A } else { 4732292SN/A return 0; 4742292SN/A } 4752292SN/A} 4762292SN/A 4772292SN/A 4782292SN/Atemplate <class Impl> 4792292SN/Avoid 4802292SN/AInstructionQueue<Impl>::resetEntries() 4812292SN/A{ 4822292SN/A if (iqPolicy != Dynamic || numThreads > 1) { 4833867Sbinkertn@umich.edu int active_threads = activeThreads->size(); 4842292SN/A 4856221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4866221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4872292SN/A 4883867Sbinkertn@umich.edu while (threads != end) { 4896221Snate@binkert.org ThreadID tid = *threads++; 4903867Sbinkertn@umich.edu 4912292SN/A if (iqPolicy == Partitioned) { 4923867Sbinkertn@umich.edu maxEntries[tid] = numEntries / active_threads; 4932292SN/A } else if(iqPolicy == Threshold && active_threads == 1) { 4943867Sbinkertn@umich.edu maxEntries[tid] = numEntries; 4952292SN/A } 4962292SN/A } 4972292SN/A } 4982292SN/A} 4992292SN/A 5002292SN/Atemplate <class Impl> 5011684SN/Aunsigned 5021684SN/AInstructionQueue<Impl>::numFreeEntries() 5031684SN/A{ 5041684SN/A return freeEntries; 5051684SN/A} 5061684SN/A 5072292SN/Atemplate <class Impl> 5082292SN/Aunsigned 5096221Snate@binkert.orgInstructionQueue<Impl>::numFreeEntries(ThreadID tid) 5102292SN/A{ 5112292SN/A return maxEntries[tid] - count[tid]; 5122292SN/A} 5132292SN/A 5141060SN/A// Might want to do something more complex if it knows how many instructions 5151060SN/A// will be issued this cycle. 5161061SN/Atemplate <class Impl> 5171060SN/Abool 5181060SN/AInstructionQueue<Impl>::isFull() 5191060SN/A{ 5201060SN/A if (freeEntries == 0) { 5211060SN/A return(true); 5221060SN/A } else { 5231060SN/A return(false); 5241060SN/A } 5251060SN/A} 5261060SN/A 5271061SN/Atemplate <class Impl> 5282292SN/Abool 5296221Snate@binkert.orgInstructionQueue<Impl>::isFull(ThreadID tid) 5302292SN/A{ 5312292SN/A if (numFreeEntries(tid) == 0) { 5322292SN/A return(true); 5332292SN/A } else { 5342292SN/A return(false); 5352292SN/A } 5362292SN/A} 5372292SN/A 5382292SN/Atemplate <class Impl> 5392292SN/Abool 5402292SN/AInstructionQueue<Impl>::hasReadyInsts() 5412292SN/A{ 5422292SN/A if (!listOrder.empty()) { 5432292SN/A return true; 5442292SN/A } 5452292SN/A 5462292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 5472292SN/A if (!readyInsts[i].empty()) { 5482292SN/A return true; 5492292SN/A } 5502292SN/A } 5512292SN/A 5522292SN/A return false; 5532292SN/A} 5542292SN/A 5552292SN/Atemplate <class Impl> 5561060SN/Avoid 5571061SN/AInstructionQueue<Impl>::insert(DynInstPtr &new_inst) 5581060SN/A{ 5597897Shestness@cs.utexas.edu new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 5601060SN/A // Make sure the instruction is valid 5611060SN/A assert(new_inst); 5621060SN/A 5637720Sgblack@eecs.umich.edu DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n", 5647720Sgblack@eecs.umich.edu new_inst->seqNum, new_inst->pcState()); 5651060SN/A 5661060SN/A assert(freeEntries != 0); 5671060SN/A 5682292SN/A instList[new_inst->threadNumber].push_back(new_inst); 5691060SN/A 5702064SN/A --freeEntries; 5711060SN/A 5722292SN/A new_inst->setInIQ(); 5731060SN/A 5741060SN/A // Look through its source registers (physical regs), and mark any 5751060SN/A // dependencies. 5761060SN/A addToDependents(new_inst); 5771060SN/A 5781060SN/A // Have this instruction set itself as the producer of its destination 5791060SN/A // register(s). 5802326SN/A addToProducers(new_inst); 5811060SN/A 5821061SN/A if (new_inst->isMemRef()) { 5832292SN/A memDepUnit[new_inst->threadNumber].insert(new_inst); 5841062SN/A } else { 5851062SN/A addIfReady(new_inst); 5861061SN/A } 5871061SN/A 5881062SN/A ++iqInstsAdded; 5891060SN/A 5902292SN/A count[new_inst->threadNumber]++; 5912292SN/A 5921060SN/A assert(freeEntries == (numEntries - countInsts())); 5931060SN/A} 5941060SN/A 5951061SN/Atemplate <class Impl> 5961061SN/Avoid 5972292SN/AInstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) 5981061SN/A{ 5991061SN/A // @todo: Clean up this code; can do it by setting inst as unable 6001061SN/A // to issue, then calling normal insert on the inst. 6017897Shestness@cs.utexas.edu new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 6021061SN/A 6032292SN/A assert(new_inst); 6041061SN/A 6052292SN/A nonSpecInsts[new_inst->seqNum] = new_inst; 6061061SN/A 6077720Sgblack@eecs.umich.edu DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s " 6082326SN/A "to the IQ.\n", 6097720Sgblack@eecs.umich.edu new_inst->seqNum, new_inst->pcState()); 6102064SN/A 6111061SN/A assert(freeEntries != 0); 6121061SN/A 6132292SN/A instList[new_inst->threadNumber].push_back(new_inst); 6141061SN/A 6152064SN/A --freeEntries; 6161061SN/A 6172292SN/A new_inst->setInIQ(); 6181061SN/A 6191061SN/A // Have this instruction set itself as the producer of its destination 6201061SN/A // register(s). 6212326SN/A addToProducers(new_inst); 6221061SN/A 6231061SN/A // If it's a memory instruction, add it to the memory dependency 6241061SN/A // unit. 6252292SN/A if (new_inst->isMemRef()) { 6262292SN/A memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 6271061SN/A } 6281062SN/A 6291062SN/A ++iqNonSpecInstsAdded; 6302292SN/A 6312292SN/A count[new_inst->threadNumber]++; 6322292SN/A 6332292SN/A assert(freeEntries == (numEntries - countInsts())); 6341061SN/A} 6351061SN/A 6361061SN/Atemplate <class Impl> 6371060SN/Avoid 6382292SN/AInstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) 6391060SN/A{ 6402292SN/A memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 6411060SN/A 6422292SN/A insertNonSpec(barr_inst); 6432292SN/A} 6441060SN/A 6452064SN/Atemplate <class Impl> 6462333SN/Atypename Impl::DynInstPtr 6472333SN/AInstructionQueue<Impl>::getInstToExecute() 6482333SN/A{ 6492333SN/A assert(!instsToExecute.empty()); 6502333SN/A DynInstPtr inst = instsToExecute.front(); 6512333SN/A instsToExecute.pop_front(); 6527897Shestness@cs.utexas.edu if (inst->isFloating()){ 6537897Shestness@cs.utexas.edu fpInstQueueReads++; 6547897Shestness@cs.utexas.edu } else { 6557897Shestness@cs.utexas.edu intInstQueueReads++; 6567897Shestness@cs.utexas.edu } 6572333SN/A return inst; 6582333SN/A} 6591060SN/A 6602333SN/Atemplate <class Impl> 6612064SN/Avoid 6622292SN/AInstructionQueue<Impl>::addToOrderList(OpClass op_class) 6632292SN/A{ 6642292SN/A assert(!readyInsts[op_class].empty()); 6652292SN/A 6662292SN/A ListOrderEntry queue_entry; 6672292SN/A 6682292SN/A queue_entry.queueType = op_class; 6692292SN/A 6702292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 6712292SN/A 6722292SN/A ListOrderIt list_it = listOrder.begin(); 6732292SN/A ListOrderIt list_end_it = listOrder.end(); 6742292SN/A 6752292SN/A while (list_it != list_end_it) { 6762292SN/A if ((*list_it).oldestInst > queue_entry.oldestInst) { 6772292SN/A break; 6782292SN/A } 6792292SN/A 6802292SN/A list_it++; 6811060SN/A } 6821060SN/A 6832292SN/A readyIt[op_class] = listOrder.insert(list_it, queue_entry); 6842292SN/A queueOnList[op_class] = true; 6852292SN/A} 6861060SN/A 6872292SN/Atemplate <class Impl> 6882292SN/Avoid 6892292SN/AInstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 6902292SN/A{ 6912292SN/A // Get iterator of next item on the list 6922292SN/A // Delete the original iterator 6932292SN/A // Determine if the next item is either the end of the list or younger 6942292SN/A // than the new instruction. If so, then add in a new iterator right here. 6952292SN/A // If not, then move along. 6962292SN/A ListOrderEntry queue_entry; 6972292SN/A OpClass op_class = (*list_order_it).queueType; 6982292SN/A ListOrderIt next_it = list_order_it; 6992292SN/A 7002292SN/A ++next_it; 7012292SN/A 7022292SN/A queue_entry.queueType = op_class; 7032292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 7042292SN/A 7052292SN/A while (next_it != listOrder.end() && 7062292SN/A (*next_it).oldestInst < queue_entry.oldestInst) { 7072292SN/A ++next_it; 7081060SN/A } 7091060SN/A 7102292SN/A readyIt[op_class] = listOrder.insert(next_it, queue_entry); 7111060SN/A} 7121060SN/A 7132292SN/Atemplate <class Impl> 7142292SN/Avoid 7152292SN/AInstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 7162292SN/A{ 7172367SN/A DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 7182292SN/A // The CPU could have been sleeping until this op completed (*extremely* 7192292SN/A // long latency op). Wake it if it was. This may be overkill. 7202307SN/A if (isSwitchedOut()) { 7212367SN/A DPRINTF(IQ, "FU completion not processed, IQ is switched out [sn:%lli]\n", 7222367SN/A inst->seqNum); 7232307SN/A return; 7242307SN/A } 7252307SN/A 7262292SN/A iewStage->wakeCPU(); 7272292SN/A 7282326SN/A if (fu_idx > -1) 7292326SN/A fuPool->freeUnitNextCycle(fu_idx); 7302292SN/A 7312326SN/A // @todo: Ensure that these FU Completions happen at the beginning 7322326SN/A // of a cycle, otherwise they could add too many instructions to 7332326SN/A // the queue. 7345327Smengke97@hotmail.com issueToExecuteQueue->access(-1)->size++; 7352333SN/A instsToExecute.push_back(inst); 7362292SN/A} 7372292SN/A 7381061SN/A// @todo: Figure out a better way to remove the squashed items from the 7391061SN/A// lists. Checking the top item of each list to see if it's squashed 7401061SN/A// wastes time and forces jumps. 7411061SN/Atemplate <class Impl> 7421060SN/Avoid 7431060SN/AInstructionQueue<Impl>::scheduleReadyInsts() 7441060SN/A{ 7452292SN/A DPRINTF(IQ, "Attempting to schedule ready instructions from " 7462292SN/A "the IQ.\n"); 7471060SN/A 7481060SN/A IssueStruct *i2e_info = issueToExecuteQueue->access(0); 7491060SN/A 7507944SGiacomo.Gabrielli@arm.com DynInstPtr deferred_mem_inst; 7517944SGiacomo.Gabrielli@arm.com int total_deferred_mem_issued = 0; 7527944SGiacomo.Gabrielli@arm.com while (total_deferred_mem_issued < totalWidth && 7537962Ssaidi@eecs.umich.edu (deferred_mem_inst = getDeferredMemInstToExecute()) != 0) { 7547944SGiacomo.Gabrielli@arm.com issueToExecuteQueue->access(0)->size++; 7557944SGiacomo.Gabrielli@arm.com instsToExecute.push_back(deferred_mem_inst); 7567944SGiacomo.Gabrielli@arm.com total_deferred_mem_issued++; 7577944SGiacomo.Gabrielli@arm.com } 7587944SGiacomo.Gabrielli@arm.com 7592292SN/A // Have iterator to head of the list 7602292SN/A // While I haven't exceeded bandwidth or reached the end of the list, 7612292SN/A // Try to get a FU that can do what this op needs. 7622292SN/A // If successful, change the oldestInst to the new top of the list, put 7632292SN/A // the queue in the proper place in the list. 7642292SN/A // Increment the iterator. 7652292SN/A // This will avoid trying to schedule a certain op class if there are no 7662292SN/A // FUs that handle it. 7672292SN/A ListOrderIt order_it = listOrder.begin(); 7682292SN/A ListOrderIt order_end_it = listOrder.end(); 7692292SN/A int total_issued = 0; 7701060SN/A 7717944SGiacomo.Gabrielli@arm.com while (total_issued < (totalWidth - total_deferred_mem_issued) && 7722820Sktlim@umich.edu iewStage->canIssue() && 7732326SN/A order_it != order_end_it) { 7742292SN/A OpClass op_class = (*order_it).queueType; 7751060SN/A 7762292SN/A assert(!readyInsts[op_class].empty()); 7771060SN/A 7782292SN/A DynInstPtr issuing_inst = readyInsts[op_class].top(); 7791060SN/A 7807897Shestness@cs.utexas.edu issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++; 7817897Shestness@cs.utexas.edu 7822292SN/A assert(issuing_inst->seqNum == (*order_it).oldestInst); 7831060SN/A 7842292SN/A if (issuing_inst->isSquashed()) { 7852292SN/A readyInsts[op_class].pop(); 7861060SN/A 7872292SN/A if (!readyInsts[op_class].empty()) { 7882292SN/A moveToYoungerInst(order_it); 7892292SN/A } else { 7902292SN/A readyIt[op_class] = listOrder.end(); 7912292SN/A queueOnList[op_class] = false; 7921060SN/A } 7931060SN/A 7942292SN/A listOrder.erase(order_it++); 7951060SN/A 7962292SN/A ++iqSquashedInstsIssued; 7972292SN/A 7982292SN/A continue; 7991060SN/A } 8001060SN/A 8012326SN/A int idx = -2; 8022326SN/A int op_latency = 1; 8036221Snate@binkert.org ThreadID tid = issuing_inst->threadNumber; 8041060SN/A 8052326SN/A if (op_class != No_OpClass) { 8062326SN/A idx = fuPool->getUnit(op_class); 8077897Shestness@cs.utexas.edu issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++; 8082326SN/A if (idx > -1) { 8092326SN/A op_latency = fuPool->getOpLatency(op_class); 8101060SN/A } 8111060SN/A } 8121060SN/A 8132348SN/A // If we have an instruction that doesn't require a FU, or a 8142348SN/A // valid FU, then schedule for execution. 8152326SN/A if (idx == -2 || idx != -1) { 8162292SN/A if (op_latency == 1) { 8172292SN/A i2e_info->size++; 8182333SN/A instsToExecute.push_back(issuing_inst); 8191060SN/A 8202326SN/A // Add the FU onto the list of FU's to be freed next 8212326SN/A // cycle if we used one. 8222326SN/A if (idx >= 0) 8232326SN/A fuPool->freeUnitNextCycle(idx); 8242292SN/A } else { 8252292SN/A int issue_latency = fuPool->getIssueLatency(op_class); 8262326SN/A // Generate completion event for the FU 8272326SN/A FUCompletion *execution = new FUCompletion(issuing_inst, 8282326SN/A idx, this); 8291060SN/A 8307823Ssteve.reinhardt@amd.com cpu->schedule(execution, curTick() + cpu->ticks(op_latency - 1)); 8311060SN/A 8322326SN/A // @todo: Enforce that issue_latency == 1 or op_latency 8332292SN/A if (issue_latency > 1) { 8342348SN/A // If FU isn't pipelined, then it must be freed 8352348SN/A // upon the execution completing. 8362326SN/A execution->setFreeFU(); 8372292SN/A } else { 8382292SN/A // Add the FU onto the list of FU's to be freed next cycle. 8392326SN/A fuPool->freeUnitNextCycle(idx); 8402292SN/A } 8411060SN/A } 8421060SN/A 8437720Sgblack@eecs.umich.edu DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 8442292SN/A "[sn:%lli]\n", 8457720Sgblack@eecs.umich.edu tid, issuing_inst->pcState(), 8462292SN/A issuing_inst->seqNum); 8471060SN/A 8482292SN/A readyInsts[op_class].pop(); 8491061SN/A 8502292SN/A if (!readyInsts[op_class].empty()) { 8512292SN/A moveToYoungerInst(order_it); 8522292SN/A } else { 8532292SN/A readyIt[op_class] = listOrder.end(); 8542292SN/A queueOnList[op_class] = false; 8551060SN/A } 8561060SN/A 8572064SN/A issuing_inst->setIssued(); 8582292SN/A ++total_issued; 8592064SN/A 8602292SN/A if (!issuing_inst->isMemRef()) { 8612292SN/A // Memory instructions can not be freed from the IQ until they 8622292SN/A // complete. 8632292SN/A ++freeEntries; 8642301SN/A count[tid]--; 8652731Sktlim@umich.edu issuing_inst->clearInIQ(); 8662292SN/A } else { 8672301SN/A memDepUnit[tid].issue(issuing_inst); 8682292SN/A } 8692292SN/A 8702292SN/A listOrder.erase(order_it++); 8712326SN/A statIssuedInstType[tid][op_class]++; 8722820Sktlim@umich.edu iewStage->incrWb(issuing_inst->seqNum); 8732292SN/A } else { 8742326SN/A statFuBusy[op_class]++; 8752326SN/A fuBusy[tid]++; 8762292SN/A ++order_it; 8771060SN/A } 8781060SN/A } 8791062SN/A 8802326SN/A numIssuedDist.sample(total_issued); 8812326SN/A iqInstsIssued+= total_issued; 8822307SN/A 8832348SN/A // If we issued any instructions, tell the CPU we had activity. 8848071SAli.Saidi@ARM.com // @todo If the way deferred memory instructions are handeled due to 8858071SAli.Saidi@ARM.com // translation changes then the deferredMemInsts condition should be removed 8868071SAli.Saidi@ARM.com // from the code below. 8878071SAli.Saidi@ARM.com if (total_issued || total_deferred_mem_issued || deferredMemInsts.size()) { 8882292SN/A cpu->activityThisCycle(); 8892292SN/A } else { 8902292SN/A DPRINTF(IQ, "Not able to schedule any instructions.\n"); 8912292SN/A } 8921060SN/A} 8931060SN/A 8941061SN/Atemplate <class Impl> 8951060SN/Avoid 8961061SN/AInstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 8971060SN/A{ 8982292SN/A DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 8992292SN/A "to execute.\n", inst); 9001062SN/A 9012292SN/A NonSpecMapIt inst_it = nonSpecInsts.find(inst); 9021060SN/A 9031061SN/A assert(inst_it != nonSpecInsts.end()); 9041060SN/A 9056221Snate@binkert.org ThreadID tid = (*inst_it).second->threadNumber; 9062292SN/A 9074033Sktlim@umich.edu (*inst_it).second->setAtCommit(); 9084033Sktlim@umich.edu 9091061SN/A (*inst_it).second->setCanIssue(); 9101060SN/A 9111062SN/A if (!(*inst_it).second->isMemRef()) { 9121062SN/A addIfReady((*inst_it).second); 9131062SN/A } else { 9142292SN/A memDepUnit[tid].nonSpecInstReady((*inst_it).second); 9151062SN/A } 9161060SN/A 9172292SN/A (*inst_it).second = NULL; 9182292SN/A 9191061SN/A nonSpecInsts.erase(inst_it); 9201060SN/A} 9211060SN/A 9221061SN/Atemplate <class Impl> 9231061SN/Avoid 9246221Snate@binkert.orgInstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 9252292SN/A{ 9262292SN/A DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 9272292SN/A tid,inst); 9282292SN/A 9292292SN/A ListIt iq_it = instList[tid].begin(); 9302292SN/A 9312292SN/A while (iq_it != instList[tid].end() && 9322292SN/A (*iq_it)->seqNum <= inst) { 9332292SN/A ++iq_it; 9342292SN/A instList[tid].pop_front(); 9352292SN/A } 9362292SN/A 9372292SN/A assert(freeEntries == (numEntries - countInsts())); 9382292SN/A} 9392292SN/A 9402292SN/Atemplate <class Impl> 9412301SN/Aint 9421684SN/AInstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 9431684SN/A{ 9442301SN/A int dependents = 0; 9452301SN/A 9467897Shestness@cs.utexas.edu // The instruction queue here takes care of both floating and int ops 9477897Shestness@cs.utexas.edu if (completed_inst->isFloating()) { 9487897Shestness@cs.utexas.edu fpInstQueueWakeupQccesses++; 9497897Shestness@cs.utexas.edu } else { 9507897Shestness@cs.utexas.edu intInstQueueWakeupAccesses++; 9517897Shestness@cs.utexas.edu } 9527897Shestness@cs.utexas.edu 9532292SN/A DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 9542292SN/A 9552292SN/A assert(!completed_inst->isSquashed()); 9561684SN/A 9571684SN/A // Tell the memory dependence unit to wake any dependents on this 9582292SN/A // instruction if it is a memory instruction. Also complete the memory 9592326SN/A // instruction at this point since we know it executed without issues. 9602326SN/A // @todo: Might want to rename "completeMemInst" to something that 9612326SN/A // indicates that it won't need to be replayed, and call this 9622326SN/A // earlier. Might not be a big deal. 9631684SN/A if (completed_inst->isMemRef()) { 9642292SN/A memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 9652292SN/A completeMemInst(completed_inst); 9662292SN/A } else if (completed_inst->isMemBarrier() || 9672292SN/A completed_inst->isWriteBarrier()) { 9682292SN/A memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 9691684SN/A } 9701684SN/A 9711684SN/A for (int dest_reg_idx = 0; 9721684SN/A dest_reg_idx < completed_inst->numDestRegs(); 9731684SN/A dest_reg_idx++) 9741684SN/A { 9751684SN/A PhysRegIndex dest_reg = 9761684SN/A completed_inst->renamedDestRegIdx(dest_reg_idx); 9771684SN/A 9781684SN/A // Special case of uniq or control registers. They are not 9791684SN/A // handled by the IQ and thus have no dependency graph entry. 9801684SN/A // @todo Figure out a cleaner way to handle this. 9811684SN/A if (dest_reg >= numPhysRegs) { 9827599Sminkyu.jeong@arm.com DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg, 9837599Sminkyu.jeong@arm.com numPhysRegs); 9841684SN/A continue; 9851684SN/A } 9861684SN/A 9872292SN/A DPRINTF(IQ, "Waking any dependents on register %i.\n", 9881684SN/A (int) dest_reg); 9891684SN/A 9902326SN/A //Go through the dependency chain, marking the registers as 9912326SN/A //ready within the waiting instructions. 9922326SN/A DynInstPtr dep_inst = dependGraph.pop(dest_reg); 9931684SN/A 9942326SN/A while (dep_inst) { 9957599Sminkyu.jeong@arm.com DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] " 9967720Sgblack@eecs.umich.edu "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 9971684SN/A 9981684SN/A // Might want to give more information to the instruction 9992326SN/A // so that it knows which of its source registers is 10002326SN/A // ready. However that would mean that the dependency 10012326SN/A // graph entries would need to hold the src_reg_idx. 10022326SN/A dep_inst->markSrcRegReady(); 10031684SN/A 10042326SN/A addIfReady(dep_inst); 10051684SN/A 10062326SN/A dep_inst = dependGraph.pop(dest_reg); 10071684SN/A 10082301SN/A ++dependents; 10091684SN/A } 10101684SN/A 10112326SN/A // Reset the head node now that all of its dependents have 10122326SN/A // been woken up. 10132326SN/A assert(dependGraph.empty(dest_reg)); 10142326SN/A dependGraph.clearInst(dest_reg); 10151684SN/A 10161684SN/A // Mark the scoreboard as having that register ready. 10171684SN/A regScoreboard[dest_reg] = true; 10181684SN/A } 10192301SN/A return dependents; 10202064SN/A} 10212064SN/A 10222064SN/Atemplate <class Impl> 10232064SN/Avoid 10242292SN/AInstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 10252064SN/A{ 10262292SN/A OpClass op_class = ready_inst->opClass(); 10272292SN/A 10282292SN/A readyInsts[op_class].push(ready_inst); 10292292SN/A 10302326SN/A // Will need to reorder the list if either a queue is not on the list, 10312326SN/A // or it has an older instruction than last time. 10322326SN/A if (!queueOnList[op_class]) { 10332326SN/A addToOrderList(op_class); 10342326SN/A } else if (readyInsts[op_class].top()->seqNum < 10352326SN/A (*readyIt[op_class]).oldestInst) { 10362326SN/A listOrder.erase(readyIt[op_class]); 10372326SN/A addToOrderList(op_class); 10382326SN/A } 10392326SN/A 10402292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 10417720Sgblack@eecs.umich.edu "the ready list, PC %s opclass:%i [sn:%lli].\n", 10427720Sgblack@eecs.umich.edu ready_inst->pcState(), op_class, ready_inst->seqNum); 10432064SN/A} 10442064SN/A 10452064SN/Atemplate <class Impl> 10462064SN/Avoid 10472292SN/AInstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 10482064SN/A{ 10494033Sktlim@umich.edu DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 10507944SGiacomo.Gabrielli@arm.com 10517944SGiacomo.Gabrielli@arm.com // Reset DTB translation state 10527944SGiacomo.Gabrielli@arm.com resched_inst->translationStarted = false; 10537944SGiacomo.Gabrielli@arm.com resched_inst->translationCompleted = false; 10547944SGiacomo.Gabrielli@arm.com 10554033Sktlim@umich.edu resched_inst->clearCanIssue(); 10562292SN/A memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 10572064SN/A} 10582064SN/A 10592064SN/Atemplate <class Impl> 10602064SN/Avoid 10612292SN/AInstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 10622064SN/A{ 10632292SN/A memDepUnit[replay_inst->threadNumber].replay(replay_inst); 10642292SN/A} 10652292SN/A 10662292SN/Atemplate <class Impl> 10672292SN/Avoid 10682292SN/AInstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 10692292SN/A{ 10706221Snate@binkert.org ThreadID tid = completed_inst->threadNumber; 10712292SN/A 10727720Sgblack@eecs.umich.edu DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n", 10737720Sgblack@eecs.umich.edu completed_inst->pcState(), completed_inst->seqNum); 10742292SN/A 10752292SN/A ++freeEntries; 10762292SN/A 10772292SN/A completed_inst->memOpDone = true; 10782292SN/A 10792292SN/A memDepUnit[tid].completed(completed_inst); 10802292SN/A count[tid]--; 10811684SN/A} 10821684SN/A 10831684SN/Atemplate <class Impl> 10841684SN/Avoid 10857944SGiacomo.Gabrielli@arm.comInstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst) 10867944SGiacomo.Gabrielli@arm.com{ 10877944SGiacomo.Gabrielli@arm.com deferredMemInsts.push_back(deferred_inst); 10887944SGiacomo.Gabrielli@arm.com} 10897944SGiacomo.Gabrielli@arm.com 10907944SGiacomo.Gabrielli@arm.comtemplate <class Impl> 10917944SGiacomo.Gabrielli@arm.comtypename Impl::DynInstPtr 10927944SGiacomo.Gabrielli@arm.comInstructionQueue<Impl>::getDeferredMemInstToExecute() 10937944SGiacomo.Gabrielli@arm.com{ 10947944SGiacomo.Gabrielli@arm.com for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); 10957944SGiacomo.Gabrielli@arm.com ++it) { 10967944SGiacomo.Gabrielli@arm.com if ((*it)->translationCompleted) { 10977944SGiacomo.Gabrielli@arm.com DynInstPtr ret = *it; 10987944SGiacomo.Gabrielli@arm.com deferredMemInsts.erase(it); 10997944SGiacomo.Gabrielli@arm.com return ret; 11007944SGiacomo.Gabrielli@arm.com } 11017944SGiacomo.Gabrielli@arm.com } 11027944SGiacomo.Gabrielli@arm.com return NULL; 11037944SGiacomo.Gabrielli@arm.com} 11047944SGiacomo.Gabrielli@arm.com 11057944SGiacomo.Gabrielli@arm.comtemplate <class Impl> 11067944SGiacomo.Gabrielli@arm.comvoid 11071061SN/AInstructionQueue<Impl>::violation(DynInstPtr &store, 11081061SN/A DynInstPtr &faulting_load) 11091061SN/A{ 11107897Shestness@cs.utexas.edu intInstQueueWrites++; 11112292SN/A memDepUnit[store->threadNumber].violation(store, faulting_load); 11121061SN/A} 11131061SN/A 11141061SN/Atemplate <class Impl> 11151060SN/Avoid 11166221Snate@binkert.orgInstructionQueue<Impl>::squash(ThreadID tid) 11171060SN/A{ 11182292SN/A DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 11192292SN/A "the IQ.\n", tid); 11201060SN/A 11211060SN/A // Read instruction sequence number of last instruction out of the 11221060SN/A // time buffer. 11232292SN/A squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 11241060SN/A 11251681SN/A // Call doSquash if there are insts in the IQ 11262292SN/A if (count[tid] > 0) { 11272292SN/A doSquash(tid); 11281681SN/A } 11291061SN/A 11301061SN/A // Also tell the memory dependence unit to squash. 11312292SN/A memDepUnit[tid].squash(squashedSeqNum[tid], tid); 11321060SN/A} 11331060SN/A 11341061SN/Atemplate <class Impl> 11351061SN/Avoid 11366221Snate@binkert.orgInstructionQueue<Impl>::doSquash(ThreadID tid) 11371061SN/A{ 11382326SN/A // Start at the tail. 11392326SN/A ListIt squash_it = instList[tid].end(); 11402326SN/A --squash_it; 11411061SN/A 11422292SN/A DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 11432292SN/A tid, squashedSeqNum[tid]); 11441061SN/A 11451061SN/A // Squash any instructions younger than the squashed sequence number 11461061SN/A // given. 11472326SN/A while (squash_it != instList[tid].end() && 11482326SN/A (*squash_it)->seqNum > squashedSeqNum[tid]) { 11492292SN/A 11502326SN/A DynInstPtr squashed_inst = (*squash_it); 11517897Shestness@cs.utexas.edu squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 11521061SN/A 11531061SN/A // Only handle the instruction if it actually is in the IQ and 11541061SN/A // hasn't already been squashed in the IQ. 11552292SN/A if (squashed_inst->threadNumber != tid || 11562292SN/A squashed_inst->isSquashedInIQ()) { 11572326SN/A --squash_it; 11582292SN/A continue; 11592292SN/A } 11602292SN/A 11612292SN/A if (!squashed_inst->isIssued() || 11622292SN/A (squashed_inst->isMemRef() && 11632292SN/A !squashed_inst->memOpDone)) { 11641062SN/A 11657720Sgblack@eecs.umich.edu DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", 11667720Sgblack@eecs.umich.edu tid, squashed_inst->seqNum, squashed_inst->pcState()); 11672367SN/A 11681061SN/A // Remove the instruction from the dependency list. 11692292SN/A if (!squashed_inst->isNonSpeculative() && 11702336SN/A !squashed_inst->isStoreConditional() && 11712292SN/A !squashed_inst->isMemBarrier() && 11722292SN/A !squashed_inst->isWriteBarrier()) { 11731061SN/A 11741061SN/A for (int src_reg_idx = 0; 11751681SN/A src_reg_idx < squashed_inst->numSrcRegs(); 11761061SN/A src_reg_idx++) 11771061SN/A { 11781061SN/A PhysRegIndex src_reg = 11791061SN/A squashed_inst->renamedSrcRegIdx(src_reg_idx); 11801061SN/A 11812326SN/A // Only remove it from the dependency graph if it 11822326SN/A // was placed there in the first place. 11832326SN/A 11842326SN/A // Instead of doing a linked list traversal, we 11852326SN/A // can just remove these squashed instructions 11862326SN/A // either at issue time, or when the register is 11872326SN/A // overwritten. The only downside to this is it 11882326SN/A // leaves more room for error. 11892292SN/A 11901061SN/A if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 11911061SN/A src_reg < numPhysRegs) { 11922326SN/A dependGraph.remove(src_reg, squashed_inst); 11931061SN/A } 11941062SN/A 11952292SN/A 11961062SN/A ++iqSquashedOperandsExamined; 11971061SN/A } 11984033Sktlim@umich.edu } else if (!squashed_inst->isStoreConditional() || 11994033Sktlim@umich.edu !squashed_inst->isCompleted()) { 12002292SN/A NonSpecMapIt ns_inst_it = 12012292SN/A nonSpecInsts.find(squashed_inst->seqNum); 12022292SN/A assert(ns_inst_it != nonSpecInsts.end()); 12034033Sktlim@umich.edu if (ns_inst_it == nonSpecInsts.end()) { 12044033Sktlim@umich.edu assert(squashed_inst->getFault() != NoFault); 12054033Sktlim@umich.edu } else { 12061062SN/A 12074033Sktlim@umich.edu (*ns_inst_it).second = NULL; 12081681SN/A 12094033Sktlim@umich.edu nonSpecInsts.erase(ns_inst_it); 12101062SN/A 12114033Sktlim@umich.edu ++iqSquashedNonSpecRemoved; 12124033Sktlim@umich.edu } 12131061SN/A } 12141061SN/A 12151061SN/A // Might want to also clear out the head of the dependency graph. 12161061SN/A 12171061SN/A // Mark it as squashed within the IQ. 12181061SN/A squashed_inst->setSquashedInIQ(); 12191061SN/A 12202292SN/A // @todo: Remove this hack where several statuses are set so the 12212292SN/A // inst will flow through the rest of the pipeline. 12221681SN/A squashed_inst->setIssued(); 12231681SN/A squashed_inst->setCanCommit(); 12242731Sktlim@umich.edu squashed_inst->clearInIQ(); 12252292SN/A 12262292SN/A //Update Thread IQ Count 12272292SN/A count[squashed_inst->threadNumber]--; 12281681SN/A 12291681SN/A ++freeEntries; 12301061SN/A } 12311061SN/A 12322326SN/A instList[tid].erase(squash_it--); 12331062SN/A ++iqSquashedInstsExamined; 12341061SN/A } 12351060SN/A} 12361060SN/A 12371061SN/Atemplate <class Impl> 12381060SN/Abool 12391061SN/AInstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 12401060SN/A{ 12411060SN/A // Loop through the instruction's source registers, adding 12421060SN/A // them to the dependency list if they are not ready. 12431060SN/A int8_t total_src_regs = new_inst->numSrcRegs(); 12441060SN/A bool return_val = false; 12451060SN/A 12461060SN/A for (int src_reg_idx = 0; 12471060SN/A src_reg_idx < total_src_regs; 12481060SN/A src_reg_idx++) 12491060SN/A { 12501060SN/A // Only add it to the dependency graph if it's not ready. 12511060SN/A if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 12521060SN/A PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 12531060SN/A 12541060SN/A // Check the IQ's scoreboard to make sure the register 12551060SN/A // hasn't become ready while the instruction was in flight 12561060SN/A // between stages. Only if it really isn't ready should 12571060SN/A // it be added to the dependency graph. 12581061SN/A if (src_reg >= numPhysRegs) { 12591061SN/A continue; 12601061SN/A } else if (regScoreboard[src_reg] == false) { 12617720Sgblack@eecs.umich.edu DPRINTF(IQ, "Instruction PC %s has src reg %i that " 12621060SN/A "is being added to the dependency chain.\n", 12637720Sgblack@eecs.umich.edu new_inst->pcState(), src_reg); 12641060SN/A 12652326SN/A dependGraph.insert(src_reg, new_inst); 12661060SN/A 12671060SN/A // Change the return value to indicate that something 12681060SN/A // was added to the dependency graph. 12691060SN/A return_val = true; 12701060SN/A } else { 12717720Sgblack@eecs.umich.edu DPRINTF(IQ, "Instruction PC %s has src reg %i that " 12721060SN/A "became ready before it reached the IQ.\n", 12737720Sgblack@eecs.umich.edu new_inst->pcState(), src_reg); 12741060SN/A // Mark a register ready within the instruction. 12752326SN/A new_inst->markSrcRegReady(src_reg_idx); 12761060SN/A } 12771060SN/A } 12781060SN/A } 12791060SN/A 12801060SN/A return return_val; 12811060SN/A} 12821060SN/A 12831061SN/Atemplate <class Impl> 12841060SN/Avoid 12852326SN/AInstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) 12861060SN/A{ 12872326SN/A // Nothing really needs to be marked when an instruction becomes 12882326SN/A // the producer of a register's value, but for convenience a ptr 12892326SN/A // to the producing instruction will be placed in the head node of 12902326SN/A // the dependency links. 12911060SN/A int8_t total_dest_regs = new_inst->numDestRegs(); 12921060SN/A 12931060SN/A for (int dest_reg_idx = 0; 12941060SN/A dest_reg_idx < total_dest_regs; 12951060SN/A dest_reg_idx++) 12961060SN/A { 12971061SN/A PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 12981061SN/A 12991061SN/A // Instructions that use the misc regs will have a reg number 13001061SN/A // higher than the normal physical registers. In this case these 13011061SN/A // registers are not renamed, and there is no need to track 13021061SN/A // dependencies as these instructions must be executed at commit. 13031061SN/A if (dest_reg >= numPhysRegs) { 13041061SN/A continue; 13051060SN/A } 13061060SN/A 13072326SN/A if (!dependGraph.empty(dest_reg)) { 13082326SN/A dependGraph.dump(); 13092292SN/A panic("Dependency graph %i not empty!", dest_reg); 13102064SN/A } 13111062SN/A 13122326SN/A dependGraph.setInst(dest_reg, new_inst); 13131062SN/A 13141060SN/A // Mark the scoreboard to say it's not yet ready. 13151060SN/A regScoreboard[dest_reg] = false; 13161060SN/A } 13171060SN/A} 13181060SN/A 13191061SN/Atemplate <class Impl> 13201060SN/Avoid 13211061SN/AInstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 13221060SN/A{ 13232326SN/A // If the instruction now has all of its source registers 13241060SN/A // available, then add it to the list of ready instructions. 13251060SN/A if (inst->readyToIssue()) { 13261061SN/A 13271060SN/A //Add the instruction to the proper ready list. 13282292SN/A if (inst->isMemRef()) { 13291061SN/A 13302292SN/A DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 13311061SN/A 13321062SN/A // Message to the mem dependence unit that this instruction has 13331062SN/A // its registers ready. 13342292SN/A memDepUnit[inst->threadNumber].regsReady(inst); 13351062SN/A 13362292SN/A return; 13372292SN/A } 13381062SN/A 13392292SN/A OpClass op_class = inst->opClass(); 13401061SN/A 13412292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 13427720Sgblack@eecs.umich.edu "the ready list, PC %s opclass:%i [sn:%lli].\n", 13437720Sgblack@eecs.umich.edu inst->pcState(), op_class, inst->seqNum); 13441061SN/A 13452292SN/A readyInsts[op_class].push(inst); 13461061SN/A 13472326SN/A // Will need to reorder the list if either a queue is not on the list, 13482326SN/A // or it has an older instruction than last time. 13492326SN/A if (!queueOnList[op_class]) { 13502326SN/A addToOrderList(op_class); 13512326SN/A } else if (readyInsts[op_class].top()->seqNum < 13522326SN/A (*readyIt[op_class]).oldestInst) { 13532326SN/A listOrder.erase(readyIt[op_class]); 13542326SN/A addToOrderList(op_class); 13551060SN/A } 13561060SN/A } 13571060SN/A} 13581060SN/A 13591061SN/Atemplate <class Impl> 13601061SN/Aint 13611061SN/AInstructionQueue<Impl>::countInsts() 13621061SN/A{ 13632698Sktlim@umich.edu#if 0 13642292SN/A //ksewell:This works but definitely could use a cleaner write 13652292SN/A //with a more intuitive way of counting. Right now it's 13662292SN/A //just brute force .... 13672698Sktlim@umich.edu // Change the #if if you want to use this method. 13681061SN/A int total_insts = 0; 13691061SN/A 13706221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 13716221Snate@binkert.org ListIt count_it = instList[tid].begin(); 13721681SN/A 13736221Snate@binkert.org while (count_it != instList[tid].end()) { 13742292SN/A if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 13752292SN/A if (!(*count_it)->isIssued()) { 13762292SN/A ++total_insts; 13772292SN/A } else if ((*count_it)->isMemRef() && 13782292SN/A !(*count_it)->memOpDone) { 13792292SN/A // Loads that have not been marked as executed still count 13802292SN/A // towards the total instructions. 13812292SN/A ++total_insts; 13822292SN/A } 13832292SN/A } 13842292SN/A 13852292SN/A ++count_it; 13861061SN/A } 13871061SN/A } 13881061SN/A 13891061SN/A return total_insts; 13902292SN/A#else 13912292SN/A return numEntries - freeEntries; 13922292SN/A#endif 13931681SN/A} 13941681SN/A 13951681SN/Atemplate <class Impl> 13961681SN/Avoid 13971061SN/AInstructionQueue<Impl>::dumpLists() 13981061SN/A{ 13992292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 14002292SN/A cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 14011061SN/A 14022292SN/A cprintf("\n"); 14032292SN/A } 14041061SN/A 14051061SN/A cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 14061061SN/A 14072292SN/A NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 14082292SN/A NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 14091061SN/A 14101061SN/A cprintf("Non speculative list: "); 14111061SN/A 14122292SN/A while (non_spec_it != non_spec_end_it) { 14137720Sgblack@eecs.umich.edu cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(), 14142292SN/A (*non_spec_it).second->seqNum); 14151061SN/A ++non_spec_it; 14161061SN/A } 14171061SN/A 14181061SN/A cprintf("\n"); 14191061SN/A 14202292SN/A ListOrderIt list_order_it = listOrder.begin(); 14212292SN/A ListOrderIt list_order_end_it = listOrder.end(); 14222292SN/A int i = 1; 14232292SN/A 14242292SN/A cprintf("List order: "); 14252292SN/A 14262292SN/A while (list_order_it != list_order_end_it) { 14272292SN/A cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 14282292SN/A (*list_order_it).oldestInst); 14292292SN/A 14302292SN/A ++list_order_it; 14312292SN/A ++i; 14322292SN/A } 14332292SN/A 14342292SN/A cprintf("\n"); 14351061SN/A} 14362292SN/A 14372292SN/A 14382292SN/Atemplate <class Impl> 14392292SN/Avoid 14402292SN/AInstructionQueue<Impl>::dumpInsts() 14412292SN/A{ 14426221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 14432292SN/A int num = 0; 14442292SN/A int valid_num = 0; 14456221Snate@binkert.org ListIt inst_list_it = instList[tid].begin(); 14462292SN/A 14476221Snate@binkert.org while (inst_list_it != instList[tid].end()) { 14486221Snate@binkert.org cprintf("Instruction:%i\n", num); 14492292SN/A if (!(*inst_list_it)->isSquashed()) { 14502292SN/A if (!(*inst_list_it)->isIssued()) { 14512292SN/A ++valid_num; 14522292SN/A cprintf("Count:%i\n", valid_num); 14532292SN/A } else if ((*inst_list_it)->isMemRef() && 14542292SN/A !(*inst_list_it)->memOpDone) { 14552326SN/A // Loads that have not been marked as executed 14562326SN/A // still count towards the total instructions. 14572292SN/A ++valid_num; 14582292SN/A cprintf("Count:%i\n", valid_num); 14592292SN/A } 14602292SN/A } 14612292SN/A 14627720Sgblack@eecs.umich.edu cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 14632292SN/A "Issued:%i\nSquashed:%i\n", 14647720Sgblack@eecs.umich.edu (*inst_list_it)->pcState(), 14652292SN/A (*inst_list_it)->seqNum, 14662292SN/A (*inst_list_it)->threadNumber, 14672292SN/A (*inst_list_it)->isIssued(), 14682292SN/A (*inst_list_it)->isSquashed()); 14692292SN/A 14702292SN/A if ((*inst_list_it)->isMemRef()) { 14712292SN/A cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 14722292SN/A } 14732292SN/A 14742292SN/A cprintf("\n"); 14752292SN/A 14762292SN/A inst_list_it++; 14772292SN/A ++num; 14782292SN/A } 14792292SN/A } 14802348SN/A 14812348SN/A cprintf("Insts to Execute list:\n"); 14822348SN/A 14832348SN/A int num = 0; 14842348SN/A int valid_num = 0; 14852348SN/A ListIt inst_list_it = instsToExecute.begin(); 14862348SN/A 14872348SN/A while (inst_list_it != instsToExecute.end()) 14882348SN/A { 14892348SN/A cprintf("Instruction:%i\n", 14902348SN/A num); 14912348SN/A if (!(*inst_list_it)->isSquashed()) { 14922348SN/A if (!(*inst_list_it)->isIssued()) { 14932348SN/A ++valid_num; 14942348SN/A cprintf("Count:%i\n", valid_num); 14952348SN/A } else if ((*inst_list_it)->isMemRef() && 14962348SN/A !(*inst_list_it)->memOpDone) { 14972348SN/A // Loads that have not been marked as executed 14982348SN/A // still count towards the total instructions. 14992348SN/A ++valid_num; 15002348SN/A cprintf("Count:%i\n", valid_num); 15012348SN/A } 15022348SN/A } 15032348SN/A 15047720Sgblack@eecs.umich.edu cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 15052348SN/A "Issued:%i\nSquashed:%i\n", 15067720Sgblack@eecs.umich.edu (*inst_list_it)->pcState(), 15072348SN/A (*inst_list_it)->seqNum, 15082348SN/A (*inst_list_it)->threadNumber, 15092348SN/A (*inst_list_it)->isIssued(), 15102348SN/A (*inst_list_it)->isSquashed()); 15112348SN/A 15122348SN/A if ((*inst_list_it)->isMemRef()) { 15132348SN/A cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 15142348SN/A } 15152348SN/A 15162348SN/A cprintf("\n"); 15172348SN/A 15182348SN/A inst_list_it++; 15192348SN/A ++num; 15202348SN/A } 15212292SN/A} 1522