inst_queue_impl.hh revision 7897
11689SN/A/* 22326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292831Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322064SN/A#include <limits> 331060SN/A#include <vector> 341060SN/A 352292SN/A#include "cpu/o3/fu_pool.hh" 361717SN/A#include "cpu/o3/inst_queue.hh" 374762Snate@binkert.org#include "enums/OpClass.hh" 386221Snate@binkert.org#include "params/DerivO3CPU.hh" 394762Snate@binkert.org#include "sim/core.hh" 401060SN/A 416221Snate@binkert.orgusing namespace std; 425529Snate@binkert.org 431061SN/Atemplate <class Impl> 442292SN/AInstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 455606Snate@binkert.org int fu_idx, InstructionQueue<Impl> *iq_ptr) 465606Snate@binkert.org : Event(Stat_Event_Pri), inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), 475606Snate@binkert.org freeFU(false) 481060SN/A{ 492292SN/A this->setFlags(Event::AutoDelete); 502292SN/A} 512292SN/A 522292SN/Atemplate <class Impl> 532292SN/Avoid 542292SN/AInstructionQueue<Impl>::FUCompletion::process() 552292SN/A{ 562326SN/A iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 572292SN/A inst = NULL; 582292SN/A} 592292SN/A 602292SN/A 612292SN/Atemplate <class Impl> 622292SN/Aconst char * 635336Shines@cs.fsu.eduInstructionQueue<Impl>::FUCompletion::description() const 642292SN/A{ 654873Sstever@eecs.umich.edu return "Functional unit completion"; 662292SN/A} 672292SN/A 682292SN/Atemplate <class Impl> 694329Sktlim@umich.eduInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 705529Snate@binkert.org DerivO3CPUParams *params) 714329Sktlim@umich.edu : cpu(cpu_ptr), 724329Sktlim@umich.edu iewStage(iew_ptr), 734329Sktlim@umich.edu fuPool(params->fuPool), 742292SN/A numEntries(params->numIQEntries), 752292SN/A totalWidth(params->issueWidth), 762292SN/A numPhysIntRegs(params->numPhysIntRegs), 772292SN/A numPhysFloatRegs(params->numPhysFloatRegs), 782292SN/A commitToIEWDelay(params->commitToIEWDelay) 792292SN/A{ 802292SN/A assert(fuPool); 812292SN/A 822307SN/A switchedOut = false; 832307SN/A 845529Snate@binkert.org numThreads = params->numThreads; 851060SN/A 861060SN/A // Set the number of physical registers as the number of int + float 871060SN/A numPhysRegs = numPhysIntRegs + numPhysFloatRegs; 881060SN/A 891060SN/A //Create an entry for each physical register within the 901060SN/A //dependency graph. 912326SN/A dependGraph.resize(numPhysRegs); 921060SN/A 931060SN/A // Resize the register scoreboard. 941060SN/A regScoreboard.resize(numPhysRegs); 951060SN/A 962292SN/A //Initialize Mem Dependence Units 976221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 986221Snate@binkert.org memDepUnit[tid].init(params, tid); 996221Snate@binkert.org memDepUnit[tid].setIQ(this); 1001060SN/A } 1011060SN/A 1022307SN/A resetState(); 1032292SN/A 1042980Sgblack@eecs.umich.edu std::string policy = params->smtIQPolicy; 1052292SN/A 1062292SN/A //Convert string to lowercase 1072292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1082292SN/A (int(*)(int)) tolower); 1092292SN/A 1102292SN/A //Figure out resource sharing policy 1112292SN/A if (policy == "dynamic") { 1122292SN/A iqPolicy = Dynamic; 1132292SN/A 1142292SN/A //Set Max Entries to Total ROB Capacity 1156221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1166221Snate@binkert.org maxEntries[tid] = numEntries; 1172292SN/A } 1182292SN/A 1192292SN/A } else if (policy == "partitioned") { 1202292SN/A iqPolicy = Partitioned; 1212292SN/A 1222292SN/A //@todo:make work if part_amt doesnt divide evenly. 1232292SN/A int part_amt = numEntries / numThreads; 1242292SN/A 1252292SN/A //Divide ROB up evenly 1266221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1276221Snate@binkert.org maxEntries[tid] = part_amt; 1282292SN/A } 1292292SN/A 1302831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 1312292SN/A "%i entries per thread.\n",part_amt); 1322292SN/A } else if (policy == "threshold") { 1332292SN/A iqPolicy = Threshold; 1342292SN/A 1352292SN/A double threshold = (double)params->smtIQThreshold / 100; 1362292SN/A 1372292SN/A int thresholdIQ = (int)((double)threshold * numEntries); 1382292SN/A 1392292SN/A //Divide up by threshold amount 1406221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1416221Snate@binkert.org maxEntries[tid] = thresholdIQ; 1422292SN/A } 1432292SN/A 1442831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Threshold:" 1452292SN/A "%i entries per thread.\n",thresholdIQ); 1462292SN/A } else { 1472292SN/A assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 1482292SN/A "Partitioned, Threshold}"); 1492292SN/A } 1502292SN/A} 1512292SN/A 1522292SN/Atemplate <class Impl> 1532292SN/AInstructionQueue<Impl>::~InstructionQueue() 1542292SN/A{ 1552326SN/A dependGraph.reset(); 1562348SN/A#ifdef DEBUG 1572326SN/A cprintf("Nodes traversed: %i, removed: %i\n", 1582326SN/A dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1592348SN/A#endif 1602292SN/A} 1612292SN/A 1622292SN/Atemplate <class Impl> 1632292SN/Astd::string 1642292SN/AInstructionQueue<Impl>::name() const 1652292SN/A{ 1662292SN/A return cpu->name() + ".iq"; 1671060SN/A} 1681060SN/A 1691061SN/Atemplate <class Impl> 1701060SN/Avoid 1711062SN/AInstructionQueue<Impl>::regStats() 1721062SN/A{ 1732301SN/A using namespace Stats; 1741062SN/A iqInstsAdded 1751062SN/A .name(name() + ".iqInstsAdded") 1761062SN/A .desc("Number of instructions added to the IQ (excludes non-spec)") 1771062SN/A .prereq(iqInstsAdded); 1781062SN/A 1791062SN/A iqNonSpecInstsAdded 1801062SN/A .name(name() + ".iqNonSpecInstsAdded") 1811062SN/A .desc("Number of non-speculative instructions added to the IQ") 1821062SN/A .prereq(iqNonSpecInstsAdded); 1831062SN/A 1842301SN/A iqInstsIssued 1852301SN/A .name(name() + ".iqInstsIssued") 1862301SN/A .desc("Number of instructions issued") 1872301SN/A .prereq(iqInstsIssued); 1881062SN/A 1891062SN/A iqIntInstsIssued 1901062SN/A .name(name() + ".iqIntInstsIssued") 1911062SN/A .desc("Number of integer instructions issued") 1921062SN/A .prereq(iqIntInstsIssued); 1931062SN/A 1941062SN/A iqFloatInstsIssued 1951062SN/A .name(name() + ".iqFloatInstsIssued") 1961062SN/A .desc("Number of float instructions issued") 1971062SN/A .prereq(iqFloatInstsIssued); 1981062SN/A 1991062SN/A iqBranchInstsIssued 2001062SN/A .name(name() + ".iqBranchInstsIssued") 2011062SN/A .desc("Number of branch instructions issued") 2021062SN/A .prereq(iqBranchInstsIssued); 2031062SN/A 2041062SN/A iqMemInstsIssued 2051062SN/A .name(name() + ".iqMemInstsIssued") 2061062SN/A .desc("Number of memory instructions issued") 2071062SN/A .prereq(iqMemInstsIssued); 2081062SN/A 2091062SN/A iqMiscInstsIssued 2101062SN/A .name(name() + ".iqMiscInstsIssued") 2111062SN/A .desc("Number of miscellaneous instructions issued") 2121062SN/A .prereq(iqMiscInstsIssued); 2131062SN/A 2141062SN/A iqSquashedInstsIssued 2151062SN/A .name(name() + ".iqSquashedInstsIssued") 2161062SN/A .desc("Number of squashed instructions issued") 2171062SN/A .prereq(iqSquashedInstsIssued); 2181062SN/A 2191062SN/A iqSquashedInstsExamined 2201062SN/A .name(name() + ".iqSquashedInstsExamined") 2211062SN/A .desc("Number of squashed instructions iterated over during squash;" 2221062SN/A " mainly for profiling") 2231062SN/A .prereq(iqSquashedInstsExamined); 2241062SN/A 2251062SN/A iqSquashedOperandsExamined 2261062SN/A .name(name() + ".iqSquashedOperandsExamined") 2271062SN/A .desc("Number of squashed operands that are examined and possibly " 2281062SN/A "removed from graph") 2291062SN/A .prereq(iqSquashedOperandsExamined); 2301062SN/A 2311062SN/A iqSquashedNonSpecRemoved 2321062SN/A .name(name() + ".iqSquashedNonSpecRemoved") 2331062SN/A .desc("Number of squashed non-spec instructions that were removed") 2341062SN/A .prereq(iqSquashedNonSpecRemoved); 2352361SN/A/* 2362326SN/A queueResDist 2372301SN/A .init(Num_OpClasses, 0, 99, 2) 2382301SN/A .name(name() + ".IQ:residence:") 2392301SN/A .desc("cycles from dispatch to issue") 2402301SN/A .flags(total | pdf | cdf ) 2412301SN/A ; 2422301SN/A for (int i = 0; i < Num_OpClasses; ++i) { 2432326SN/A queueResDist.subname(i, opClassStrings[i]); 2442301SN/A } 2452361SN/A*/ 2462326SN/A numIssuedDist 2472307SN/A .init(0,totalWidth,1) 2482301SN/A .name(name() + ".ISSUE:issued_per_cycle") 2492301SN/A .desc("Number of insts issued each cycle") 2502307SN/A .flags(pdf) 2512301SN/A ; 2522301SN/A/* 2532301SN/A dist_unissued 2542301SN/A .init(Num_OpClasses+2) 2552301SN/A .name(name() + ".ISSUE:unissued_cause") 2562301SN/A .desc("Reason ready instruction not issued") 2572301SN/A .flags(pdf | dist) 2582301SN/A ; 2592301SN/A for (int i=0; i < (Num_OpClasses + 2); ++i) { 2602301SN/A dist_unissued.subname(i, unissued_names[i]); 2612301SN/A } 2622301SN/A*/ 2632326SN/A statIssuedInstType 2644762Snate@binkert.org .init(numThreads,Enums::Num_OpClass) 2652301SN/A .name(name() + ".ISSUE:FU_type") 2662301SN/A .desc("Type of FU issued") 2672301SN/A .flags(total | pdf | dist) 2682301SN/A ; 2694762Snate@binkert.org statIssuedInstType.ysubnames(Enums::OpClassStrings); 2702301SN/A 2712301SN/A // 2722301SN/A // How long did instructions for a particular FU type wait prior to issue 2732301SN/A // 2742361SN/A/* 2752326SN/A issueDelayDist 2762301SN/A .init(Num_OpClasses,0,99,2) 2772301SN/A .name(name() + ".ISSUE:") 2782301SN/A .desc("cycles from operands ready to issue") 2792301SN/A .flags(pdf | cdf) 2802301SN/A ; 2812301SN/A 2822301SN/A for (int i=0; i<Num_OpClasses; ++i) { 2832980Sgblack@eecs.umich.edu std::stringstream subname; 2842301SN/A subname << opClassStrings[i] << "_delay"; 2852326SN/A issueDelayDist.subname(i, subname.str()); 2862301SN/A } 2872361SN/A*/ 2882326SN/A issueRate 2892301SN/A .name(name() + ".ISSUE:rate") 2902301SN/A .desc("Inst issue rate") 2912301SN/A .flags(total) 2922301SN/A ; 2932326SN/A issueRate = iqInstsIssued / cpu->numCycles; 2942727Sktlim@umich.edu 2952326SN/A statFuBusy 2962301SN/A .init(Num_OpClasses) 2972301SN/A .name(name() + ".ISSUE:fu_full") 2982301SN/A .desc("attempts to use FU when none available") 2992301SN/A .flags(pdf | dist) 3002301SN/A ; 3012301SN/A for (int i=0; i < Num_OpClasses; ++i) { 3024762Snate@binkert.org statFuBusy.subname(i, Enums::OpClassStrings[i]); 3032301SN/A } 3042301SN/A 3052326SN/A fuBusy 3062301SN/A .init(numThreads) 3072301SN/A .name(name() + ".ISSUE:fu_busy_cnt") 3082301SN/A .desc("FU busy when requested") 3092301SN/A .flags(total) 3102301SN/A ; 3112301SN/A 3122326SN/A fuBusyRate 3132301SN/A .name(name() + ".ISSUE:fu_busy_rate") 3142301SN/A .desc("FU busy rate (busy events/executed inst)") 3152301SN/A .flags(total) 3162301SN/A ; 3172326SN/A fuBusyRate = fuBusy / iqInstsIssued; 3182301SN/A 3196221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3202292SN/A // Tell mem dependence unit to reg stats as well. 3216221Snate@binkert.org memDepUnit[tid].regStats(); 3222292SN/A } 3237897Shestness@cs.utexas.edu 3247897Shestness@cs.utexas.edu intInstQueueReads 3257897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_reads") 3267897Shestness@cs.utexas.edu .desc("Number of integer instruction queue reads") 3277897Shestness@cs.utexas.edu .flags(total); 3287897Shestness@cs.utexas.edu 3297897Shestness@cs.utexas.edu intInstQueueWrites 3307897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_writes") 3317897Shestness@cs.utexas.edu .desc("Number of integer instruction queue writes") 3327897Shestness@cs.utexas.edu .flags(total); 3337897Shestness@cs.utexas.edu 3347897Shestness@cs.utexas.edu intInstQueueWakeupAccesses 3357897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_wakeup_accesses") 3367897Shestness@cs.utexas.edu .desc("Number of integer instruction queue wakeup accesses") 3377897Shestness@cs.utexas.edu .flags(total); 3387897Shestness@cs.utexas.edu 3397897Shestness@cs.utexas.edu fpInstQueueReads 3407897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_reads") 3417897Shestness@cs.utexas.edu .desc("Number of floating instruction queue reads") 3427897Shestness@cs.utexas.edu .flags(total); 3437897Shestness@cs.utexas.edu 3447897Shestness@cs.utexas.edu fpInstQueueWrites 3457897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_writes") 3467897Shestness@cs.utexas.edu .desc("Number of floating instruction queue writes") 3477897Shestness@cs.utexas.edu .flags(total); 3487897Shestness@cs.utexas.edu 3497897Shestness@cs.utexas.edu fpInstQueueWakeupQccesses 3507897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_wakeup_accesses") 3517897Shestness@cs.utexas.edu .desc("Number of floating instruction queue wakeup accesses") 3527897Shestness@cs.utexas.edu .flags(total); 3537897Shestness@cs.utexas.edu 3547897Shestness@cs.utexas.edu intAluAccesses 3557897Shestness@cs.utexas.edu .name(name() + ".int_alu_accesses") 3567897Shestness@cs.utexas.edu .desc("Number of integer alu accesses") 3577897Shestness@cs.utexas.edu .flags(total); 3587897Shestness@cs.utexas.edu 3597897Shestness@cs.utexas.edu fpAluAccesses 3607897Shestness@cs.utexas.edu .name(name() + ".fp_alu_accesses") 3617897Shestness@cs.utexas.edu .desc("Number of floating point alu accesses") 3627897Shestness@cs.utexas.edu .flags(total); 3637897Shestness@cs.utexas.edu 3641062SN/A} 3651062SN/A 3661062SN/Atemplate <class Impl> 3671062SN/Avoid 3682307SN/AInstructionQueue<Impl>::resetState() 3691060SN/A{ 3702307SN/A //Initialize thread IQ counts 3716221Snate@binkert.org for (ThreadID tid = 0; tid <numThreads; tid++) { 3726221Snate@binkert.org count[tid] = 0; 3736221Snate@binkert.org instList[tid].clear(); 3742307SN/A } 3751060SN/A 3762307SN/A // Initialize the number of free IQ entries. 3772307SN/A freeEntries = numEntries; 3782307SN/A 3792307SN/A // Note that in actuality, the registers corresponding to the logical 3802307SN/A // registers start off as ready. However this doesn't matter for the 3812307SN/A // IQ as the instruction should have been correctly told if those 3822307SN/A // registers are ready in rename. Thus it can all be initialized as 3832307SN/A // unready. 3842307SN/A for (int i = 0; i < numPhysRegs; ++i) { 3852307SN/A regScoreboard[i] = false; 3862307SN/A } 3872307SN/A 3886221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 3896221Snate@binkert.org squashedSeqNum[tid] = 0; 3902307SN/A } 3912307SN/A 3922307SN/A for (int i = 0; i < Num_OpClasses; ++i) { 3932307SN/A while (!readyInsts[i].empty()) 3942307SN/A readyInsts[i].pop(); 3952307SN/A queueOnList[i] = false; 3962307SN/A readyIt[i] = listOrder.end(); 3972307SN/A } 3982307SN/A nonSpecInsts.clear(); 3992307SN/A listOrder.clear(); 4001060SN/A} 4011060SN/A 4021061SN/Atemplate <class Impl> 4031060SN/Avoid 4046221Snate@binkert.orgInstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 4051060SN/A{ 4062292SN/A activeThreads = at_ptr; 4072064SN/A} 4082064SN/A 4092064SN/Atemplate <class Impl> 4102064SN/Avoid 4112292SN/AInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 4122064SN/A{ 4134318Sktlim@umich.edu issueToExecuteQueue = i2e_ptr; 4141060SN/A} 4151060SN/A 4161061SN/Atemplate <class Impl> 4171060SN/Avoid 4181060SN/AInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 4191060SN/A{ 4201060SN/A timeBuffer = tb_ptr; 4211060SN/A 4221060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 4231060SN/A} 4241060SN/A 4251684SN/Atemplate <class Impl> 4262307SN/Avoid 4272307SN/AInstructionQueue<Impl>::switchOut() 4282307SN/A{ 4292367SN/A/* 4302367SN/A if (!instList[0].empty() || (numEntries != freeEntries) || 4312367SN/A !readyInsts[0].empty() || !nonSpecInsts.empty() || !listOrder.empty()) { 4322367SN/A dumpInsts(); 4332367SN/A// assert(0); 4342367SN/A } 4352367SN/A*/ 4362307SN/A resetState(); 4372326SN/A dependGraph.reset(); 4382367SN/A instsToExecute.clear(); 4392307SN/A switchedOut = true; 4406221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 4416221Snate@binkert.org memDepUnit[tid].switchOut(); 4422307SN/A } 4432307SN/A} 4442307SN/A 4452307SN/Atemplate <class Impl> 4462307SN/Avoid 4472307SN/AInstructionQueue<Impl>::takeOverFrom() 4482307SN/A{ 4492307SN/A switchedOut = false; 4502307SN/A} 4512307SN/A 4522307SN/Atemplate <class Impl> 4532292SN/Aint 4546221Snate@binkert.orgInstructionQueue<Impl>::entryAmount(ThreadID num_threads) 4552292SN/A{ 4562292SN/A if (iqPolicy == Partitioned) { 4572292SN/A return numEntries / num_threads; 4582292SN/A } else { 4592292SN/A return 0; 4602292SN/A } 4612292SN/A} 4622292SN/A 4632292SN/A 4642292SN/Atemplate <class Impl> 4652292SN/Avoid 4662292SN/AInstructionQueue<Impl>::resetEntries() 4672292SN/A{ 4682292SN/A if (iqPolicy != Dynamic || numThreads > 1) { 4693867Sbinkertn@umich.edu int active_threads = activeThreads->size(); 4702292SN/A 4716221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4726221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4732292SN/A 4743867Sbinkertn@umich.edu while (threads != end) { 4756221Snate@binkert.org ThreadID tid = *threads++; 4763867Sbinkertn@umich.edu 4772292SN/A if (iqPolicy == Partitioned) { 4783867Sbinkertn@umich.edu maxEntries[tid] = numEntries / active_threads; 4792292SN/A } else if(iqPolicy == Threshold && active_threads == 1) { 4803867Sbinkertn@umich.edu maxEntries[tid] = numEntries; 4812292SN/A } 4822292SN/A } 4832292SN/A } 4842292SN/A} 4852292SN/A 4862292SN/Atemplate <class Impl> 4871684SN/Aunsigned 4881684SN/AInstructionQueue<Impl>::numFreeEntries() 4891684SN/A{ 4901684SN/A return freeEntries; 4911684SN/A} 4921684SN/A 4932292SN/Atemplate <class Impl> 4942292SN/Aunsigned 4956221Snate@binkert.orgInstructionQueue<Impl>::numFreeEntries(ThreadID tid) 4962292SN/A{ 4972292SN/A return maxEntries[tid] - count[tid]; 4982292SN/A} 4992292SN/A 5001060SN/A// Might want to do something more complex if it knows how many instructions 5011060SN/A// will be issued this cycle. 5021061SN/Atemplate <class Impl> 5031060SN/Abool 5041060SN/AInstructionQueue<Impl>::isFull() 5051060SN/A{ 5061060SN/A if (freeEntries == 0) { 5071060SN/A return(true); 5081060SN/A } else { 5091060SN/A return(false); 5101060SN/A } 5111060SN/A} 5121060SN/A 5131061SN/Atemplate <class Impl> 5142292SN/Abool 5156221Snate@binkert.orgInstructionQueue<Impl>::isFull(ThreadID tid) 5162292SN/A{ 5172292SN/A if (numFreeEntries(tid) == 0) { 5182292SN/A return(true); 5192292SN/A } else { 5202292SN/A return(false); 5212292SN/A } 5222292SN/A} 5232292SN/A 5242292SN/Atemplate <class Impl> 5252292SN/Abool 5262292SN/AInstructionQueue<Impl>::hasReadyInsts() 5272292SN/A{ 5282292SN/A if (!listOrder.empty()) { 5292292SN/A return true; 5302292SN/A } 5312292SN/A 5322292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 5332292SN/A if (!readyInsts[i].empty()) { 5342292SN/A return true; 5352292SN/A } 5362292SN/A } 5372292SN/A 5382292SN/A return false; 5392292SN/A} 5402292SN/A 5412292SN/Atemplate <class Impl> 5421060SN/Avoid 5431061SN/AInstructionQueue<Impl>::insert(DynInstPtr &new_inst) 5441060SN/A{ 5457897Shestness@cs.utexas.edu new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 5461060SN/A // Make sure the instruction is valid 5471060SN/A assert(new_inst); 5481060SN/A 5497720Sgblack@eecs.umich.edu DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n", 5507720Sgblack@eecs.umich.edu new_inst->seqNum, new_inst->pcState()); 5511060SN/A 5521060SN/A assert(freeEntries != 0); 5531060SN/A 5542292SN/A instList[new_inst->threadNumber].push_back(new_inst); 5551060SN/A 5562064SN/A --freeEntries; 5571060SN/A 5582292SN/A new_inst->setInIQ(); 5591060SN/A 5601060SN/A // Look through its source registers (physical regs), and mark any 5611060SN/A // dependencies. 5621060SN/A addToDependents(new_inst); 5631060SN/A 5641060SN/A // Have this instruction set itself as the producer of its destination 5651060SN/A // register(s). 5662326SN/A addToProducers(new_inst); 5671060SN/A 5681061SN/A if (new_inst->isMemRef()) { 5692292SN/A memDepUnit[new_inst->threadNumber].insert(new_inst); 5701062SN/A } else { 5711062SN/A addIfReady(new_inst); 5721061SN/A } 5731061SN/A 5741062SN/A ++iqInstsAdded; 5751060SN/A 5762292SN/A count[new_inst->threadNumber]++; 5772292SN/A 5781060SN/A assert(freeEntries == (numEntries - countInsts())); 5791060SN/A} 5801060SN/A 5811061SN/Atemplate <class Impl> 5821061SN/Avoid 5832292SN/AInstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) 5841061SN/A{ 5851061SN/A // @todo: Clean up this code; can do it by setting inst as unable 5861061SN/A // to issue, then calling normal insert on the inst. 5877897Shestness@cs.utexas.edu new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 5881061SN/A 5892292SN/A assert(new_inst); 5901061SN/A 5912292SN/A nonSpecInsts[new_inst->seqNum] = new_inst; 5921061SN/A 5937720Sgblack@eecs.umich.edu DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s " 5942326SN/A "to the IQ.\n", 5957720Sgblack@eecs.umich.edu new_inst->seqNum, new_inst->pcState()); 5962064SN/A 5971061SN/A assert(freeEntries != 0); 5981061SN/A 5992292SN/A instList[new_inst->threadNumber].push_back(new_inst); 6001061SN/A 6012064SN/A --freeEntries; 6021061SN/A 6032292SN/A new_inst->setInIQ(); 6041061SN/A 6051061SN/A // Have this instruction set itself as the producer of its destination 6061061SN/A // register(s). 6072326SN/A addToProducers(new_inst); 6081061SN/A 6091061SN/A // If it's a memory instruction, add it to the memory dependency 6101061SN/A // unit. 6112292SN/A if (new_inst->isMemRef()) { 6122292SN/A memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 6131061SN/A } 6141062SN/A 6151062SN/A ++iqNonSpecInstsAdded; 6162292SN/A 6172292SN/A count[new_inst->threadNumber]++; 6182292SN/A 6192292SN/A assert(freeEntries == (numEntries - countInsts())); 6201061SN/A} 6211061SN/A 6221061SN/Atemplate <class Impl> 6231060SN/Avoid 6242292SN/AInstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) 6251060SN/A{ 6262292SN/A memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 6271060SN/A 6282292SN/A insertNonSpec(barr_inst); 6292292SN/A} 6301060SN/A 6312064SN/Atemplate <class Impl> 6322333SN/Atypename Impl::DynInstPtr 6332333SN/AInstructionQueue<Impl>::getInstToExecute() 6342333SN/A{ 6352333SN/A assert(!instsToExecute.empty()); 6362333SN/A DynInstPtr inst = instsToExecute.front(); 6372333SN/A instsToExecute.pop_front(); 6387897Shestness@cs.utexas.edu if (inst->isFloating()){ 6397897Shestness@cs.utexas.edu fpInstQueueReads++; 6407897Shestness@cs.utexas.edu } else { 6417897Shestness@cs.utexas.edu intInstQueueReads++; 6427897Shestness@cs.utexas.edu } 6432333SN/A return inst; 6442333SN/A} 6451060SN/A 6462333SN/Atemplate <class Impl> 6472064SN/Avoid 6482292SN/AInstructionQueue<Impl>::addToOrderList(OpClass op_class) 6492292SN/A{ 6502292SN/A assert(!readyInsts[op_class].empty()); 6512292SN/A 6522292SN/A ListOrderEntry queue_entry; 6532292SN/A 6542292SN/A queue_entry.queueType = op_class; 6552292SN/A 6562292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 6572292SN/A 6582292SN/A ListOrderIt list_it = listOrder.begin(); 6592292SN/A ListOrderIt list_end_it = listOrder.end(); 6602292SN/A 6612292SN/A while (list_it != list_end_it) { 6622292SN/A if ((*list_it).oldestInst > queue_entry.oldestInst) { 6632292SN/A break; 6642292SN/A } 6652292SN/A 6662292SN/A list_it++; 6671060SN/A } 6681060SN/A 6692292SN/A readyIt[op_class] = listOrder.insert(list_it, queue_entry); 6702292SN/A queueOnList[op_class] = true; 6712292SN/A} 6721060SN/A 6732292SN/Atemplate <class Impl> 6742292SN/Avoid 6752292SN/AInstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 6762292SN/A{ 6772292SN/A // Get iterator of next item on the list 6782292SN/A // Delete the original iterator 6792292SN/A // Determine if the next item is either the end of the list or younger 6802292SN/A // than the new instruction. If so, then add in a new iterator right here. 6812292SN/A // If not, then move along. 6822292SN/A ListOrderEntry queue_entry; 6832292SN/A OpClass op_class = (*list_order_it).queueType; 6842292SN/A ListOrderIt next_it = list_order_it; 6852292SN/A 6862292SN/A ++next_it; 6872292SN/A 6882292SN/A queue_entry.queueType = op_class; 6892292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 6902292SN/A 6912292SN/A while (next_it != listOrder.end() && 6922292SN/A (*next_it).oldestInst < queue_entry.oldestInst) { 6932292SN/A ++next_it; 6941060SN/A } 6951060SN/A 6962292SN/A readyIt[op_class] = listOrder.insert(next_it, queue_entry); 6971060SN/A} 6981060SN/A 6992292SN/Atemplate <class Impl> 7002292SN/Avoid 7012292SN/AInstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 7022292SN/A{ 7032367SN/A DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 7042292SN/A // The CPU could have been sleeping until this op completed (*extremely* 7052292SN/A // long latency op). Wake it if it was. This may be overkill. 7062307SN/A if (isSwitchedOut()) { 7072367SN/A DPRINTF(IQ, "FU completion not processed, IQ is switched out [sn:%lli]\n", 7082367SN/A inst->seqNum); 7092307SN/A return; 7102307SN/A } 7112307SN/A 7122292SN/A iewStage->wakeCPU(); 7132292SN/A 7142326SN/A if (fu_idx > -1) 7152326SN/A fuPool->freeUnitNextCycle(fu_idx); 7162292SN/A 7172326SN/A // @todo: Ensure that these FU Completions happen at the beginning 7182326SN/A // of a cycle, otherwise they could add too many instructions to 7192326SN/A // the queue. 7205327Smengke97@hotmail.com issueToExecuteQueue->access(-1)->size++; 7212333SN/A instsToExecute.push_back(inst); 7222292SN/A} 7232292SN/A 7241061SN/A// @todo: Figure out a better way to remove the squashed items from the 7251061SN/A// lists. Checking the top item of each list to see if it's squashed 7261061SN/A// wastes time and forces jumps. 7271061SN/Atemplate <class Impl> 7281060SN/Avoid 7291060SN/AInstructionQueue<Impl>::scheduleReadyInsts() 7301060SN/A{ 7312292SN/A DPRINTF(IQ, "Attempting to schedule ready instructions from " 7322292SN/A "the IQ.\n"); 7331060SN/A 7341060SN/A IssueStruct *i2e_info = issueToExecuteQueue->access(0); 7351060SN/A 7362292SN/A // Have iterator to head of the list 7372292SN/A // While I haven't exceeded bandwidth or reached the end of the list, 7382292SN/A // Try to get a FU that can do what this op needs. 7392292SN/A // If successful, change the oldestInst to the new top of the list, put 7402292SN/A // the queue in the proper place in the list. 7412292SN/A // Increment the iterator. 7422292SN/A // This will avoid trying to schedule a certain op class if there are no 7432292SN/A // FUs that handle it. 7442292SN/A ListOrderIt order_it = listOrder.begin(); 7452292SN/A ListOrderIt order_end_it = listOrder.end(); 7462292SN/A int total_issued = 0; 7471060SN/A 7482333SN/A while (total_issued < totalWidth && 7492820Sktlim@umich.edu iewStage->canIssue() && 7502326SN/A order_it != order_end_it) { 7512292SN/A OpClass op_class = (*order_it).queueType; 7521060SN/A 7532292SN/A assert(!readyInsts[op_class].empty()); 7541060SN/A 7552292SN/A DynInstPtr issuing_inst = readyInsts[op_class].top(); 7561060SN/A 7577897Shestness@cs.utexas.edu issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++; 7587897Shestness@cs.utexas.edu 7592292SN/A assert(issuing_inst->seqNum == (*order_it).oldestInst); 7601060SN/A 7612292SN/A if (issuing_inst->isSquashed()) { 7622292SN/A readyInsts[op_class].pop(); 7631060SN/A 7642292SN/A if (!readyInsts[op_class].empty()) { 7652292SN/A moveToYoungerInst(order_it); 7662292SN/A } else { 7672292SN/A readyIt[op_class] = listOrder.end(); 7682292SN/A queueOnList[op_class] = false; 7691060SN/A } 7701060SN/A 7712292SN/A listOrder.erase(order_it++); 7721060SN/A 7732292SN/A ++iqSquashedInstsIssued; 7742292SN/A 7752292SN/A continue; 7761060SN/A } 7771060SN/A 7782326SN/A int idx = -2; 7792326SN/A int op_latency = 1; 7806221Snate@binkert.org ThreadID tid = issuing_inst->threadNumber; 7811060SN/A 7822326SN/A if (op_class != No_OpClass) { 7832326SN/A idx = fuPool->getUnit(op_class); 7847897Shestness@cs.utexas.edu issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++; 7852326SN/A if (idx > -1) { 7862326SN/A op_latency = fuPool->getOpLatency(op_class); 7871060SN/A } 7881060SN/A } 7891060SN/A 7902348SN/A // If we have an instruction that doesn't require a FU, or a 7912348SN/A // valid FU, then schedule for execution. 7922326SN/A if (idx == -2 || idx != -1) { 7932292SN/A if (op_latency == 1) { 7942292SN/A i2e_info->size++; 7952333SN/A instsToExecute.push_back(issuing_inst); 7961060SN/A 7972326SN/A // Add the FU onto the list of FU's to be freed next 7982326SN/A // cycle if we used one. 7992326SN/A if (idx >= 0) 8002326SN/A fuPool->freeUnitNextCycle(idx); 8012292SN/A } else { 8022292SN/A int issue_latency = fuPool->getIssueLatency(op_class); 8032326SN/A // Generate completion event for the FU 8042326SN/A FUCompletion *execution = new FUCompletion(issuing_inst, 8052326SN/A idx, this); 8061060SN/A 8077823Ssteve.reinhardt@amd.com cpu->schedule(execution, curTick() + cpu->ticks(op_latency - 1)); 8081060SN/A 8092326SN/A // @todo: Enforce that issue_latency == 1 or op_latency 8102292SN/A if (issue_latency > 1) { 8112348SN/A // If FU isn't pipelined, then it must be freed 8122348SN/A // upon the execution completing. 8132326SN/A execution->setFreeFU(); 8142292SN/A } else { 8152292SN/A // Add the FU onto the list of FU's to be freed next cycle. 8162326SN/A fuPool->freeUnitNextCycle(idx); 8172292SN/A } 8181060SN/A } 8191060SN/A 8207720Sgblack@eecs.umich.edu DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 8212292SN/A "[sn:%lli]\n", 8227720Sgblack@eecs.umich.edu tid, issuing_inst->pcState(), 8232292SN/A issuing_inst->seqNum); 8241060SN/A 8252292SN/A readyInsts[op_class].pop(); 8261061SN/A 8272292SN/A if (!readyInsts[op_class].empty()) { 8282292SN/A moveToYoungerInst(order_it); 8292292SN/A } else { 8302292SN/A readyIt[op_class] = listOrder.end(); 8312292SN/A queueOnList[op_class] = false; 8321060SN/A } 8331060SN/A 8342064SN/A issuing_inst->setIssued(); 8352292SN/A ++total_issued; 8362064SN/A 8372292SN/A if (!issuing_inst->isMemRef()) { 8382292SN/A // Memory instructions can not be freed from the IQ until they 8392292SN/A // complete. 8402292SN/A ++freeEntries; 8412301SN/A count[tid]--; 8422731Sktlim@umich.edu issuing_inst->clearInIQ(); 8432292SN/A } else { 8442301SN/A memDepUnit[tid].issue(issuing_inst); 8452292SN/A } 8462292SN/A 8472292SN/A listOrder.erase(order_it++); 8482326SN/A statIssuedInstType[tid][op_class]++; 8492820Sktlim@umich.edu iewStage->incrWb(issuing_inst->seqNum); 8502292SN/A } else { 8512326SN/A statFuBusy[op_class]++; 8522326SN/A fuBusy[tid]++; 8532292SN/A ++order_it; 8541060SN/A } 8551060SN/A } 8561062SN/A 8572326SN/A numIssuedDist.sample(total_issued); 8582326SN/A iqInstsIssued+= total_issued; 8592307SN/A 8602348SN/A // If we issued any instructions, tell the CPU we had activity. 8612292SN/A if (total_issued) { 8622292SN/A cpu->activityThisCycle(); 8632292SN/A } else { 8642292SN/A DPRINTF(IQ, "Not able to schedule any instructions.\n"); 8652292SN/A } 8661060SN/A} 8671060SN/A 8681061SN/Atemplate <class Impl> 8691060SN/Avoid 8701061SN/AInstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 8711060SN/A{ 8722292SN/A DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 8732292SN/A "to execute.\n", inst); 8741062SN/A 8752292SN/A NonSpecMapIt inst_it = nonSpecInsts.find(inst); 8761060SN/A 8771061SN/A assert(inst_it != nonSpecInsts.end()); 8781060SN/A 8796221Snate@binkert.org ThreadID tid = (*inst_it).second->threadNumber; 8802292SN/A 8814033Sktlim@umich.edu (*inst_it).second->setAtCommit(); 8824033Sktlim@umich.edu 8831061SN/A (*inst_it).second->setCanIssue(); 8841060SN/A 8851062SN/A if (!(*inst_it).second->isMemRef()) { 8861062SN/A addIfReady((*inst_it).second); 8871062SN/A } else { 8882292SN/A memDepUnit[tid].nonSpecInstReady((*inst_it).second); 8891062SN/A } 8901060SN/A 8912292SN/A (*inst_it).second = NULL; 8922292SN/A 8931061SN/A nonSpecInsts.erase(inst_it); 8941060SN/A} 8951060SN/A 8961061SN/Atemplate <class Impl> 8971061SN/Avoid 8986221Snate@binkert.orgInstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 8992292SN/A{ 9002292SN/A DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 9012292SN/A tid,inst); 9022292SN/A 9032292SN/A ListIt iq_it = instList[tid].begin(); 9042292SN/A 9052292SN/A while (iq_it != instList[tid].end() && 9062292SN/A (*iq_it)->seqNum <= inst) { 9072292SN/A ++iq_it; 9082292SN/A instList[tid].pop_front(); 9092292SN/A } 9102292SN/A 9112292SN/A assert(freeEntries == (numEntries - countInsts())); 9122292SN/A} 9132292SN/A 9142292SN/Atemplate <class Impl> 9152301SN/Aint 9161684SN/AInstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 9171684SN/A{ 9182301SN/A int dependents = 0; 9192301SN/A 9207897Shestness@cs.utexas.edu // The instruction queue here takes care of both floating and int ops 9217897Shestness@cs.utexas.edu if (completed_inst->isFloating()) { 9227897Shestness@cs.utexas.edu fpInstQueueWakeupQccesses++; 9237897Shestness@cs.utexas.edu } else { 9247897Shestness@cs.utexas.edu intInstQueueWakeupAccesses++; 9257897Shestness@cs.utexas.edu } 9267897Shestness@cs.utexas.edu 9272292SN/A DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 9282292SN/A 9292292SN/A assert(!completed_inst->isSquashed()); 9301684SN/A 9311684SN/A // Tell the memory dependence unit to wake any dependents on this 9322292SN/A // instruction if it is a memory instruction. Also complete the memory 9332326SN/A // instruction at this point since we know it executed without issues. 9342326SN/A // @todo: Might want to rename "completeMemInst" to something that 9352326SN/A // indicates that it won't need to be replayed, and call this 9362326SN/A // earlier. Might not be a big deal. 9371684SN/A if (completed_inst->isMemRef()) { 9382292SN/A memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 9392292SN/A completeMemInst(completed_inst); 9402292SN/A } else if (completed_inst->isMemBarrier() || 9412292SN/A completed_inst->isWriteBarrier()) { 9422292SN/A memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 9431684SN/A } 9441684SN/A 9451684SN/A for (int dest_reg_idx = 0; 9461684SN/A dest_reg_idx < completed_inst->numDestRegs(); 9471684SN/A dest_reg_idx++) 9481684SN/A { 9491684SN/A PhysRegIndex dest_reg = 9501684SN/A completed_inst->renamedDestRegIdx(dest_reg_idx); 9511684SN/A 9521684SN/A // Special case of uniq or control registers. They are not 9531684SN/A // handled by the IQ and thus have no dependency graph entry. 9541684SN/A // @todo Figure out a cleaner way to handle this. 9551684SN/A if (dest_reg >= numPhysRegs) { 9567599Sminkyu.jeong@arm.com DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg, 9577599Sminkyu.jeong@arm.com numPhysRegs); 9581684SN/A continue; 9591684SN/A } 9601684SN/A 9612292SN/A DPRINTF(IQ, "Waking any dependents on register %i.\n", 9621684SN/A (int) dest_reg); 9631684SN/A 9642326SN/A //Go through the dependency chain, marking the registers as 9652326SN/A //ready within the waiting instructions. 9662326SN/A DynInstPtr dep_inst = dependGraph.pop(dest_reg); 9671684SN/A 9682326SN/A while (dep_inst) { 9697599Sminkyu.jeong@arm.com DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] " 9707720Sgblack@eecs.umich.edu "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 9711684SN/A 9721684SN/A // Might want to give more information to the instruction 9732326SN/A // so that it knows which of its source registers is 9742326SN/A // ready. However that would mean that the dependency 9752326SN/A // graph entries would need to hold the src_reg_idx. 9762326SN/A dep_inst->markSrcRegReady(); 9771684SN/A 9782326SN/A addIfReady(dep_inst); 9791684SN/A 9802326SN/A dep_inst = dependGraph.pop(dest_reg); 9811684SN/A 9822301SN/A ++dependents; 9831684SN/A } 9841684SN/A 9852326SN/A // Reset the head node now that all of its dependents have 9862326SN/A // been woken up. 9872326SN/A assert(dependGraph.empty(dest_reg)); 9882326SN/A dependGraph.clearInst(dest_reg); 9891684SN/A 9901684SN/A // Mark the scoreboard as having that register ready. 9911684SN/A regScoreboard[dest_reg] = true; 9921684SN/A } 9932301SN/A return dependents; 9942064SN/A} 9952064SN/A 9962064SN/Atemplate <class Impl> 9972064SN/Avoid 9982292SN/AInstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 9992064SN/A{ 10002292SN/A OpClass op_class = ready_inst->opClass(); 10012292SN/A 10022292SN/A readyInsts[op_class].push(ready_inst); 10032292SN/A 10042326SN/A // Will need to reorder the list if either a queue is not on the list, 10052326SN/A // or it has an older instruction than last time. 10062326SN/A if (!queueOnList[op_class]) { 10072326SN/A addToOrderList(op_class); 10082326SN/A } else if (readyInsts[op_class].top()->seqNum < 10092326SN/A (*readyIt[op_class]).oldestInst) { 10102326SN/A listOrder.erase(readyIt[op_class]); 10112326SN/A addToOrderList(op_class); 10122326SN/A } 10132326SN/A 10142292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 10157720Sgblack@eecs.umich.edu "the ready list, PC %s opclass:%i [sn:%lli].\n", 10167720Sgblack@eecs.umich.edu ready_inst->pcState(), op_class, ready_inst->seqNum); 10172064SN/A} 10182064SN/A 10192064SN/Atemplate <class Impl> 10202064SN/Avoid 10212292SN/AInstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 10222064SN/A{ 10234033Sktlim@umich.edu DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 10244033Sktlim@umich.edu resched_inst->clearCanIssue(); 10252292SN/A memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 10262064SN/A} 10272064SN/A 10282064SN/Atemplate <class Impl> 10292064SN/Avoid 10302292SN/AInstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 10312064SN/A{ 10322292SN/A memDepUnit[replay_inst->threadNumber].replay(replay_inst); 10332292SN/A} 10342292SN/A 10352292SN/Atemplate <class Impl> 10362292SN/Avoid 10372292SN/AInstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 10382292SN/A{ 10396221Snate@binkert.org ThreadID tid = completed_inst->threadNumber; 10402292SN/A 10417720Sgblack@eecs.umich.edu DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n", 10427720Sgblack@eecs.umich.edu completed_inst->pcState(), completed_inst->seqNum); 10432292SN/A 10442292SN/A ++freeEntries; 10452292SN/A 10462292SN/A completed_inst->memOpDone = true; 10472292SN/A 10482292SN/A memDepUnit[tid].completed(completed_inst); 10492292SN/A count[tid]--; 10501684SN/A} 10511684SN/A 10521684SN/Atemplate <class Impl> 10531684SN/Avoid 10541061SN/AInstructionQueue<Impl>::violation(DynInstPtr &store, 10551061SN/A DynInstPtr &faulting_load) 10561061SN/A{ 10577897Shestness@cs.utexas.edu intInstQueueWrites++; 10582292SN/A memDepUnit[store->threadNumber].violation(store, faulting_load); 10591061SN/A} 10601061SN/A 10611061SN/Atemplate <class Impl> 10621060SN/Avoid 10636221Snate@binkert.orgInstructionQueue<Impl>::squash(ThreadID tid) 10641060SN/A{ 10652292SN/A DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 10662292SN/A "the IQ.\n", tid); 10671060SN/A 10681060SN/A // Read instruction sequence number of last instruction out of the 10691060SN/A // time buffer. 10702292SN/A squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 10711060SN/A 10721681SN/A // Call doSquash if there are insts in the IQ 10732292SN/A if (count[tid] > 0) { 10742292SN/A doSquash(tid); 10751681SN/A } 10761061SN/A 10771061SN/A // Also tell the memory dependence unit to squash. 10782292SN/A memDepUnit[tid].squash(squashedSeqNum[tid], tid); 10791060SN/A} 10801060SN/A 10811061SN/Atemplate <class Impl> 10821061SN/Avoid 10836221Snate@binkert.orgInstructionQueue<Impl>::doSquash(ThreadID tid) 10841061SN/A{ 10852326SN/A // Start at the tail. 10862326SN/A ListIt squash_it = instList[tid].end(); 10872326SN/A --squash_it; 10881061SN/A 10892292SN/A DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 10902292SN/A tid, squashedSeqNum[tid]); 10911061SN/A 10921061SN/A // Squash any instructions younger than the squashed sequence number 10931061SN/A // given. 10942326SN/A while (squash_it != instList[tid].end() && 10952326SN/A (*squash_it)->seqNum > squashedSeqNum[tid]) { 10962292SN/A 10972326SN/A DynInstPtr squashed_inst = (*squash_it); 10987897Shestness@cs.utexas.edu squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 10991061SN/A 11001061SN/A // Only handle the instruction if it actually is in the IQ and 11011061SN/A // hasn't already been squashed in the IQ. 11022292SN/A if (squashed_inst->threadNumber != tid || 11032292SN/A squashed_inst->isSquashedInIQ()) { 11042326SN/A --squash_it; 11052292SN/A continue; 11062292SN/A } 11072292SN/A 11082292SN/A if (!squashed_inst->isIssued() || 11092292SN/A (squashed_inst->isMemRef() && 11102292SN/A !squashed_inst->memOpDone)) { 11111062SN/A 11127720Sgblack@eecs.umich.edu DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", 11137720Sgblack@eecs.umich.edu tid, squashed_inst->seqNum, squashed_inst->pcState()); 11142367SN/A 11151061SN/A // Remove the instruction from the dependency list. 11162292SN/A if (!squashed_inst->isNonSpeculative() && 11172336SN/A !squashed_inst->isStoreConditional() && 11182292SN/A !squashed_inst->isMemBarrier() && 11192292SN/A !squashed_inst->isWriteBarrier()) { 11201061SN/A 11211061SN/A for (int src_reg_idx = 0; 11221681SN/A src_reg_idx < squashed_inst->numSrcRegs(); 11231061SN/A src_reg_idx++) 11241061SN/A { 11251061SN/A PhysRegIndex src_reg = 11261061SN/A squashed_inst->renamedSrcRegIdx(src_reg_idx); 11271061SN/A 11282326SN/A // Only remove it from the dependency graph if it 11292326SN/A // was placed there in the first place. 11302326SN/A 11312326SN/A // Instead of doing a linked list traversal, we 11322326SN/A // can just remove these squashed instructions 11332326SN/A // either at issue time, or when the register is 11342326SN/A // overwritten. The only downside to this is it 11352326SN/A // leaves more room for error. 11362292SN/A 11371061SN/A if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 11381061SN/A src_reg < numPhysRegs) { 11392326SN/A dependGraph.remove(src_reg, squashed_inst); 11401061SN/A } 11411062SN/A 11422292SN/A 11431062SN/A ++iqSquashedOperandsExamined; 11441061SN/A } 11454033Sktlim@umich.edu } else if (!squashed_inst->isStoreConditional() || 11464033Sktlim@umich.edu !squashed_inst->isCompleted()) { 11472292SN/A NonSpecMapIt ns_inst_it = 11482292SN/A nonSpecInsts.find(squashed_inst->seqNum); 11492292SN/A assert(ns_inst_it != nonSpecInsts.end()); 11504033Sktlim@umich.edu if (ns_inst_it == nonSpecInsts.end()) { 11514033Sktlim@umich.edu assert(squashed_inst->getFault() != NoFault); 11524033Sktlim@umich.edu } else { 11531062SN/A 11544033Sktlim@umich.edu (*ns_inst_it).second = NULL; 11551681SN/A 11564033Sktlim@umich.edu nonSpecInsts.erase(ns_inst_it); 11571062SN/A 11584033Sktlim@umich.edu ++iqSquashedNonSpecRemoved; 11594033Sktlim@umich.edu } 11601061SN/A } 11611061SN/A 11621061SN/A // Might want to also clear out the head of the dependency graph. 11631061SN/A 11641061SN/A // Mark it as squashed within the IQ. 11651061SN/A squashed_inst->setSquashedInIQ(); 11661061SN/A 11672292SN/A // @todo: Remove this hack where several statuses are set so the 11682292SN/A // inst will flow through the rest of the pipeline. 11691681SN/A squashed_inst->setIssued(); 11701681SN/A squashed_inst->setCanCommit(); 11712731Sktlim@umich.edu squashed_inst->clearInIQ(); 11722292SN/A 11732292SN/A //Update Thread IQ Count 11742292SN/A count[squashed_inst->threadNumber]--; 11751681SN/A 11761681SN/A ++freeEntries; 11771061SN/A } 11781061SN/A 11792326SN/A instList[tid].erase(squash_it--); 11801062SN/A ++iqSquashedInstsExamined; 11811061SN/A } 11821060SN/A} 11831060SN/A 11841061SN/Atemplate <class Impl> 11851060SN/Abool 11861061SN/AInstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 11871060SN/A{ 11881060SN/A // Loop through the instruction's source registers, adding 11891060SN/A // them to the dependency list if they are not ready. 11901060SN/A int8_t total_src_regs = new_inst->numSrcRegs(); 11911060SN/A bool return_val = false; 11921060SN/A 11931060SN/A for (int src_reg_idx = 0; 11941060SN/A src_reg_idx < total_src_regs; 11951060SN/A src_reg_idx++) 11961060SN/A { 11971060SN/A // Only add it to the dependency graph if it's not ready. 11981060SN/A if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 11991060SN/A PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 12001060SN/A 12011060SN/A // Check the IQ's scoreboard to make sure the register 12021060SN/A // hasn't become ready while the instruction was in flight 12031060SN/A // between stages. Only if it really isn't ready should 12041060SN/A // it be added to the dependency graph. 12051061SN/A if (src_reg >= numPhysRegs) { 12061061SN/A continue; 12071061SN/A } else if (regScoreboard[src_reg] == false) { 12087720Sgblack@eecs.umich.edu DPRINTF(IQ, "Instruction PC %s has src reg %i that " 12091060SN/A "is being added to the dependency chain.\n", 12107720Sgblack@eecs.umich.edu new_inst->pcState(), src_reg); 12111060SN/A 12122326SN/A dependGraph.insert(src_reg, new_inst); 12131060SN/A 12141060SN/A // Change the return value to indicate that something 12151060SN/A // was added to the dependency graph. 12161060SN/A return_val = true; 12171060SN/A } else { 12187720Sgblack@eecs.umich.edu DPRINTF(IQ, "Instruction PC %s has src reg %i that " 12191060SN/A "became ready before it reached the IQ.\n", 12207720Sgblack@eecs.umich.edu new_inst->pcState(), src_reg); 12211060SN/A // Mark a register ready within the instruction. 12222326SN/A new_inst->markSrcRegReady(src_reg_idx); 12231060SN/A } 12241060SN/A } 12251060SN/A } 12261060SN/A 12271060SN/A return return_val; 12281060SN/A} 12291060SN/A 12301061SN/Atemplate <class Impl> 12311060SN/Avoid 12322326SN/AInstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) 12331060SN/A{ 12342326SN/A // Nothing really needs to be marked when an instruction becomes 12352326SN/A // the producer of a register's value, but for convenience a ptr 12362326SN/A // to the producing instruction will be placed in the head node of 12372326SN/A // the dependency links. 12381060SN/A int8_t total_dest_regs = new_inst->numDestRegs(); 12391060SN/A 12401060SN/A for (int dest_reg_idx = 0; 12411060SN/A dest_reg_idx < total_dest_regs; 12421060SN/A dest_reg_idx++) 12431060SN/A { 12441061SN/A PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 12451061SN/A 12461061SN/A // Instructions that use the misc regs will have a reg number 12471061SN/A // higher than the normal physical registers. In this case these 12481061SN/A // registers are not renamed, and there is no need to track 12491061SN/A // dependencies as these instructions must be executed at commit. 12501061SN/A if (dest_reg >= numPhysRegs) { 12511061SN/A continue; 12521060SN/A } 12531060SN/A 12542326SN/A if (!dependGraph.empty(dest_reg)) { 12552326SN/A dependGraph.dump(); 12562292SN/A panic("Dependency graph %i not empty!", dest_reg); 12572064SN/A } 12581062SN/A 12592326SN/A dependGraph.setInst(dest_reg, new_inst); 12601062SN/A 12611060SN/A // Mark the scoreboard to say it's not yet ready. 12621060SN/A regScoreboard[dest_reg] = false; 12631060SN/A } 12641060SN/A} 12651060SN/A 12661061SN/Atemplate <class Impl> 12671060SN/Avoid 12681061SN/AInstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 12691060SN/A{ 12702326SN/A // If the instruction now has all of its source registers 12711060SN/A // available, then add it to the list of ready instructions. 12721060SN/A if (inst->readyToIssue()) { 12731061SN/A 12741060SN/A //Add the instruction to the proper ready list. 12752292SN/A if (inst->isMemRef()) { 12761061SN/A 12772292SN/A DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 12781061SN/A 12791062SN/A // Message to the mem dependence unit that this instruction has 12801062SN/A // its registers ready. 12812292SN/A memDepUnit[inst->threadNumber].regsReady(inst); 12821062SN/A 12832292SN/A return; 12842292SN/A } 12851062SN/A 12862292SN/A OpClass op_class = inst->opClass(); 12871061SN/A 12882292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 12897720Sgblack@eecs.umich.edu "the ready list, PC %s opclass:%i [sn:%lli].\n", 12907720Sgblack@eecs.umich.edu inst->pcState(), op_class, inst->seqNum); 12911061SN/A 12922292SN/A readyInsts[op_class].push(inst); 12931061SN/A 12942326SN/A // Will need to reorder the list if either a queue is not on the list, 12952326SN/A // or it has an older instruction than last time. 12962326SN/A if (!queueOnList[op_class]) { 12972326SN/A addToOrderList(op_class); 12982326SN/A } else if (readyInsts[op_class].top()->seqNum < 12992326SN/A (*readyIt[op_class]).oldestInst) { 13002326SN/A listOrder.erase(readyIt[op_class]); 13012326SN/A addToOrderList(op_class); 13021060SN/A } 13031060SN/A } 13041060SN/A} 13051060SN/A 13061061SN/Atemplate <class Impl> 13071061SN/Aint 13081061SN/AInstructionQueue<Impl>::countInsts() 13091061SN/A{ 13102698Sktlim@umich.edu#if 0 13112292SN/A //ksewell:This works but definitely could use a cleaner write 13122292SN/A //with a more intuitive way of counting. Right now it's 13132292SN/A //just brute force .... 13142698Sktlim@umich.edu // Change the #if if you want to use this method. 13151061SN/A int total_insts = 0; 13161061SN/A 13176221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 13186221Snate@binkert.org ListIt count_it = instList[tid].begin(); 13191681SN/A 13206221Snate@binkert.org while (count_it != instList[tid].end()) { 13212292SN/A if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 13222292SN/A if (!(*count_it)->isIssued()) { 13232292SN/A ++total_insts; 13242292SN/A } else if ((*count_it)->isMemRef() && 13252292SN/A !(*count_it)->memOpDone) { 13262292SN/A // Loads that have not been marked as executed still count 13272292SN/A // towards the total instructions. 13282292SN/A ++total_insts; 13292292SN/A } 13302292SN/A } 13312292SN/A 13322292SN/A ++count_it; 13331061SN/A } 13341061SN/A } 13351061SN/A 13361061SN/A return total_insts; 13372292SN/A#else 13382292SN/A return numEntries - freeEntries; 13392292SN/A#endif 13401681SN/A} 13411681SN/A 13421681SN/Atemplate <class Impl> 13431681SN/Avoid 13441061SN/AInstructionQueue<Impl>::dumpLists() 13451061SN/A{ 13462292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 13472292SN/A cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 13481061SN/A 13492292SN/A cprintf("\n"); 13502292SN/A } 13511061SN/A 13521061SN/A cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 13531061SN/A 13542292SN/A NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 13552292SN/A NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 13561061SN/A 13571061SN/A cprintf("Non speculative list: "); 13581061SN/A 13592292SN/A while (non_spec_it != non_spec_end_it) { 13607720Sgblack@eecs.umich.edu cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(), 13612292SN/A (*non_spec_it).second->seqNum); 13621061SN/A ++non_spec_it; 13631061SN/A } 13641061SN/A 13651061SN/A cprintf("\n"); 13661061SN/A 13672292SN/A ListOrderIt list_order_it = listOrder.begin(); 13682292SN/A ListOrderIt list_order_end_it = listOrder.end(); 13692292SN/A int i = 1; 13702292SN/A 13712292SN/A cprintf("List order: "); 13722292SN/A 13732292SN/A while (list_order_it != list_order_end_it) { 13742292SN/A cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 13752292SN/A (*list_order_it).oldestInst); 13762292SN/A 13772292SN/A ++list_order_it; 13782292SN/A ++i; 13792292SN/A } 13802292SN/A 13812292SN/A cprintf("\n"); 13821061SN/A} 13832292SN/A 13842292SN/A 13852292SN/Atemplate <class Impl> 13862292SN/Avoid 13872292SN/AInstructionQueue<Impl>::dumpInsts() 13882292SN/A{ 13896221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 13902292SN/A int num = 0; 13912292SN/A int valid_num = 0; 13926221Snate@binkert.org ListIt inst_list_it = instList[tid].begin(); 13932292SN/A 13946221Snate@binkert.org while (inst_list_it != instList[tid].end()) { 13956221Snate@binkert.org cprintf("Instruction:%i\n", num); 13962292SN/A if (!(*inst_list_it)->isSquashed()) { 13972292SN/A if (!(*inst_list_it)->isIssued()) { 13982292SN/A ++valid_num; 13992292SN/A cprintf("Count:%i\n", valid_num); 14002292SN/A } else if ((*inst_list_it)->isMemRef() && 14012292SN/A !(*inst_list_it)->memOpDone) { 14022326SN/A // Loads that have not been marked as executed 14032326SN/A // still count towards the total instructions. 14042292SN/A ++valid_num; 14052292SN/A cprintf("Count:%i\n", valid_num); 14062292SN/A } 14072292SN/A } 14082292SN/A 14097720Sgblack@eecs.umich.edu cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 14102292SN/A "Issued:%i\nSquashed:%i\n", 14117720Sgblack@eecs.umich.edu (*inst_list_it)->pcState(), 14122292SN/A (*inst_list_it)->seqNum, 14132292SN/A (*inst_list_it)->threadNumber, 14142292SN/A (*inst_list_it)->isIssued(), 14152292SN/A (*inst_list_it)->isSquashed()); 14162292SN/A 14172292SN/A if ((*inst_list_it)->isMemRef()) { 14182292SN/A cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 14192292SN/A } 14202292SN/A 14212292SN/A cprintf("\n"); 14222292SN/A 14232292SN/A inst_list_it++; 14242292SN/A ++num; 14252292SN/A } 14262292SN/A } 14272348SN/A 14282348SN/A cprintf("Insts to Execute list:\n"); 14292348SN/A 14302348SN/A int num = 0; 14312348SN/A int valid_num = 0; 14322348SN/A ListIt inst_list_it = instsToExecute.begin(); 14332348SN/A 14342348SN/A while (inst_list_it != instsToExecute.end()) 14352348SN/A { 14362348SN/A cprintf("Instruction:%i\n", 14372348SN/A num); 14382348SN/A if (!(*inst_list_it)->isSquashed()) { 14392348SN/A if (!(*inst_list_it)->isIssued()) { 14402348SN/A ++valid_num; 14412348SN/A cprintf("Count:%i\n", valid_num); 14422348SN/A } else if ((*inst_list_it)->isMemRef() && 14432348SN/A !(*inst_list_it)->memOpDone) { 14442348SN/A // Loads that have not been marked as executed 14452348SN/A // still count towards the total instructions. 14462348SN/A ++valid_num; 14472348SN/A cprintf("Count:%i\n", valid_num); 14482348SN/A } 14492348SN/A } 14502348SN/A 14517720Sgblack@eecs.umich.edu cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 14522348SN/A "Issued:%i\nSquashed:%i\n", 14537720Sgblack@eecs.umich.edu (*inst_list_it)->pcState(), 14542348SN/A (*inst_list_it)->seqNum, 14552348SN/A (*inst_list_it)->threadNumber, 14562348SN/A (*inst_list_it)->isIssued(), 14572348SN/A (*inst_list_it)->isSquashed()); 14582348SN/A 14592348SN/A if ((*inst_list_it)->isMemRef()) { 14602348SN/A cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 14612348SN/A } 14622348SN/A 14632348SN/A cprintf("\n"); 14642348SN/A 14652348SN/A inst_list_it++; 14662348SN/A ++num; 14672348SN/A } 14682292SN/A} 1469