inst_queue_impl.hh revision 6221
12068SN/A/* 22068SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 32068SN/A * All rights reserved. 42068SN/A * 52068SN/A * Redistribution and use in source and binary forms, with or without 62068SN/A * modification, are permitted provided that the following conditions are 72068SN/A * met: redistributions of source code must retain the above copyright 82068SN/A * notice, this list of conditions and the following disclaimer; 92068SN/A * redistributions in binary form must reproduce the above copyright 102068SN/A * notice, this list of conditions and the following disclaimer in the 112068SN/A * documentation and/or other materials provided with the distribution; 122068SN/A * neither the name of the copyright holders nor the names of its 132068SN/A * contributors may be used to endorse or promote products derived from 142068SN/A * this software without specific prior written permission. 152068SN/A * 162068SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172068SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182068SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192068SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202068SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212068SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222068SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232068SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242068SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252068SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262068SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272068SN/A * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292665Ssaidi@eecs.umich.edu * Korey Sewell 302665Ssaidi@eecs.umich.edu */ 312068SN/A 322649Ssaidi@eecs.umich.edu#include <limits> 332649Ssaidi@eecs.umich.edu#include <vector> 342649Ssaidi@eecs.umich.edu 352649Ssaidi@eecs.umich.edu#include "cpu/o3/fu_pool.hh" 362649Ssaidi@eecs.umich.edu#include "cpu/o3/inst_queue.hh" 372068SN/A#include "enums/OpClass.hh" 382068SN/A#include "params/DerivO3CPU.hh" 392068SN/A#include "sim/core.hh" 402068SN/A 412068SN/Ausing namespace std; 422068SN/A 432068SN/Atemplate <class Impl> 442068SN/AInstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 452068SN/A int fu_idx, InstructionQueue<Impl> *iq_ptr) 465736Snate@binkert.org : Event(Stat_Event_Pri), inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), 472068SN/A freeFU(false) 482068SN/A{ 496181Sksewell@umich.edu this->setFlags(Event::AutoDelete); 506181Sksewell@umich.edu} 512068SN/A 522068SN/Atemplate <class Impl> 532068SN/Avoid 542068SN/AInstructionQueue<Impl>::FUCompletion::process() 552068SN/A{ 562068SN/A iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 572068SN/A inst = NULL; 582068SN/A} 592068SN/A 602068SN/A 612068SN/Atemplate <class Impl> 622068SN/Aconst char * 632068SN/AInstructionQueue<Impl>::FUCompletion::description() const 642068SN/A{ 652068SN/A return "Functional unit completion"; 662068SN/A} 672068SN/A 682068SN/Atemplate <class Impl> 696181Sksewell@umich.eduInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 706181Sksewell@umich.edu DerivO3CPUParams *params) 712068SN/A : cpu(cpu_ptr), 722068SN/A iewStage(iew_ptr), 732068SN/A fuPool(params->fuPool), 742068SN/A numEntries(params->numIQEntries), 752068SN/A totalWidth(params->issueWidth), 762068SN/A numPhysIntRegs(params->numPhysIntRegs), 772068SN/A numPhysFloatRegs(params->numPhysFloatRegs), 782068SN/A commitToIEWDelay(params->commitToIEWDelay) 792068SN/A{ 802068SN/A assert(fuPool); 812068SN/A 822068SN/A switchedOut = false; 832068SN/A 842068SN/A numThreads = params->numThreads; 852068SN/A 866181Sksewell@umich.edu // Set the number of physical registers as the number of int + float 876181Sksewell@umich.edu numPhysRegs = numPhysIntRegs + numPhysFloatRegs; 882068SN/A 892068SN/A //Create an entry for each physical register within the 902068SN/A //dependency graph. 912068SN/A dependGraph.resize(numPhysRegs); 922068SN/A 932068SN/A // Resize the register scoreboard. 942068SN/A regScoreboard.resize(numPhysRegs); 952068SN/A 962068SN/A //Initialize Mem Dependence Units 972068SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 982068SN/A memDepUnit[tid].init(params, tid); 992068SN/A memDepUnit[tid].setIQ(this); 1002068SN/A } 1012068SN/A 1022068SN/A resetState(); 1032068SN/A 1042068SN/A std::string policy = params->smtIQPolicy; 1052068SN/A 1062068SN/A //Convert string to lowercase 1072068SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1082068SN/A (int(*)(int)) tolower); 1092068SN/A 1102068SN/A //Figure out resource sharing policy 1112068SN/A if (policy == "dynamic") { 1122068SN/A iqPolicy = Dynamic; 1133953Sstever@eecs.umich.edu 1142068SN/A //Set Max Entries to Total ROB Capacity 1152068SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1162068SN/A maxEntries[tid] = numEntries; 1172068SN/A } 1182068SN/A 1192068SN/A } else if (policy == "partitioned") { 1202068SN/A iqPolicy = Partitioned; 1212068SN/A 1222068SN/A //@todo:make work if part_amt doesnt divide evenly. 1232068SN/A int part_amt = numEntries / numThreads; 1242068SN/A 1252068SN/A //Divide ROB up evenly 1262068SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1272068SN/A maxEntries[tid] = part_amt; 1282068SN/A } 1292068SN/A 1302227SN/A DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 1312068SN/A "%i entries per thread.\n",part_amt); 1322068SN/A } else if (policy == "threshold") { 1332095SN/A iqPolicy = Threshold; 1346181Sksewell@umich.edu 1356181Sksewell@umich.edu double threshold = (double)params->smtIQThreshold / 100; 1362095SN/A 1372095SN/A int thresholdIQ = (int)((double)threshold * numEntries); 1382095SN/A 1392068SN/A //Divide up by threshold amount 1402068SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1412068SN/A maxEntries[tid] = thresholdIQ; 1422095SN/A } 1436181Sksewell@umich.edu 1446181Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Threshold:" 1456181Sksewell@umich.edu "%i entries per thread.\n",thresholdIQ); 1466181Sksewell@umich.edu } else { 1472095SN/A assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 1482132SN/A "Partitioned, Threshold}"); 1492095SN/A } 1502095SN/A} 1512095SN/A 1522095SN/Atemplate <class Impl> 1533349Sbinkertn@umich.eduInstructionQueue<Impl>::~InstructionQueue() 1542623SN/A{ 1552095SN/A dependGraph.reset(); 1562095SN/A#ifdef DEBUG 1576181Sksewell@umich.edu cprintf("Nodes traversed: %i, removed: %i\n", 1586181Sksewell@umich.edu dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1596181Sksewell@umich.edu#endif 1602068SN/A} 1613953Sstever@eecs.umich.edu 1622068SN/Atemplate <class Impl> 1633953Sstever@eecs.umich.edustd::string 1642068SN/AInstructionQueue<Impl>::name() const 1652068SN/A{ 1666181Sksewell@umich.edu return cpu->name() + ".iq"; 1676181Sksewell@umich.edu} 1682068SN/A 1692068SN/Atemplate <class Impl> 1702132SN/Avoid 1712068SN/AInstructionQueue<Impl>::regStats() 1722068SN/A{ 1732068SN/A using namespace Stats; 1742068SN/A iqInstsAdded 1753953Sstever@eecs.umich.edu .name(name() + ".iqInstsAdded") 1762068SN/A .desc("Number of instructions added to the IQ (excludes non-spec)") 1772090SN/A .prereq(iqInstsAdded); 1782068SN/A 1792068SN/A iqNonSpecInstsAdded 1802068SN/A .name(name() + ".iqNonSpecInstsAdded") 1812068SN/A .desc("Number of non-speculative instructions added to the IQ") 1822068SN/A .prereq(iqNonSpecInstsAdded); 1832068SN/A 1842068SN/A iqInstsIssued 1852068SN/A .name(name() + ".iqInstsIssued") 1862068SN/A .desc("Number of instructions issued") 1872069SN/A .prereq(iqInstsIssued); 1882132SN/A 1892068SN/A iqIntInstsIssued 1902068SN/A .name(name() + ".iqIntInstsIssued") 1912068SN/A .desc("Number of integer instructions issued") 1922132SN/A .prereq(iqIntInstsIssued); 1932068SN/A 1942068SN/A iqFloatInstsIssued 1952068SN/A .name(name() + ".iqFloatInstsIssued") 1962069SN/A .desc("Number of float instructions issued") 1972068SN/A .prereq(iqFloatInstsIssued); 1982068SN/A 1992090SN/A iqBranchInstsIssued 2008442Sgblack@eecs.umich.edu .name(name() + ".iqBranchInstsIssued") 2012068SN/A .desc("Number of branch instructions issued") 2022068SN/A .prereq(iqBranchInstsIssued); 2032068SN/A 2042090SN/A iqMemInstsIssued 2052069SN/A .name(name() + ".iqMemInstsIssued") 2062069SN/A .desc("Number of memory instructions issued") 2072069SN/A .prereq(iqMemInstsIssued); 2082069SN/A 2092069SN/A iqMiscInstsIssued 2102069SN/A .name(name() + ".iqMiscInstsIssued") 2112069SN/A .desc("Number of miscellaneous instructions issued") 2122069SN/A .prereq(iqMiscInstsIssued); 2132095SN/A 2142132SN/A iqSquashedInstsIssued 2152095SN/A .name(name() + ".iqSquashedInstsIssued") 2162095SN/A .desc("Number of squashed instructions issued") 2172095SN/A .prereq(iqSquashedInstsIssued); 2182132SN/A 2192095SN/A iqSquashedInstsExamined 2202095SN/A .name(name() + ".iqSquashedInstsExamined") 2212095SN/A .desc("Number of squashed instructions iterated over during squash;" 2222095SN/A " mainly for profiling") 2232095SN/A .prereq(iqSquashedInstsExamined); 2242095SN/A 2252098SN/A iqSquashedOperandsExamined 2268442Sgblack@eecs.umich.edu .name(name() + ".iqSquashedOperandsExamined") 2272095SN/A .desc("Number of squashed operands that are examined and possibly " 2282095SN/A "removed from graph") 2292095SN/A .prereq(iqSquashedOperandsExamined); 2302095SN/A 2312095SN/A iqSquashedNonSpecRemoved 2322095SN/A .name(name() + ".iqSquashedNonSpecRemoved") 2332095SN/A .desc("Number of squashed non-spec instructions that were removed") 2342095SN/A .prereq(iqSquashedNonSpecRemoved); 2353349Sbinkertn@umich.edu/* 2362095SN/A queueResDist 2372095SN/A .init(Num_OpClasses, 0, 99, 2) 2382095SN/A .name(name() + ".IQ:residence:") 2392132SN/A .desc("cycles from dispatch to issue") 2402095SN/A .flags(total | pdf | cdf ) 2412095SN/A ; 2422506SN/A for (int i = 0; i < Num_OpClasses; ++i) { 2432095SN/A queueResDist.subname(i, opClassStrings[i]); 2448442Sgblack@eecs.umich.edu } 2452095SN/A*/ 2462098SN/A numIssuedDist 2472095SN/A .init(0,totalWidth,1) 2482095SN/A .name(name() + ".ISSUE:issued_per_cycle") 2492095SN/A .desc("Number of insts issued each cycle") 2502098SN/A .flags(pdf) 2512095SN/A ; 2522095SN/A/* 2532095SN/A dist_unissued 2542095SN/A .init(Num_OpClasses+2) 2552095SN/A .name(name() + ".ISSUE:unissued_cause") 2562095SN/A .desc("Reason ready instruction not issued") 2572095SN/A .flags(pdf | dist) 2582095SN/A ; 2592069SN/A for (int i=0; i < (Num_OpClasses + 2); ++i) { 2602132SN/A dist_unissued.subname(i, unissued_names[i]); 2612069SN/A } 2622069SN/A*/ 2632069SN/A statIssuedInstType 2642132SN/A .init(numThreads,Enums::Num_OpClass) 2654027Sstever@eecs.umich.edu .name(name() + ".ISSUE:FU_type") 2664027Sstever@eecs.umich.edu .desc("Type of FU issued") 2674027Sstever@eecs.umich.edu .flags(total | pdf | dist) 2684027Sstever@eecs.umich.edu ; 2694027Sstever@eecs.umich.edu statIssuedInstType.ysubnames(Enums::OpClassStrings); 2704027Sstever@eecs.umich.edu 2714027Sstever@eecs.umich.edu // 2724027Sstever@eecs.umich.edu // How long did instructions for a particular FU type wait prior to issue 2734027Sstever@eecs.umich.edu // 2744027Sstever@eecs.umich.edu/* 2754027Sstever@eecs.umich.edu issueDelayDist 2768442Sgblack@eecs.umich.edu .init(Num_OpClasses,0,99,2) 2778442Sgblack@eecs.umich.edu .name(name() + ".ISSUE:") 2784027Sstever@eecs.umich.edu .desc("cycles from operands ready to issue") 2794027Sstever@eecs.umich.edu .flags(pdf | cdf) 2804027Sstever@eecs.umich.edu ; 2814027Sstever@eecs.umich.edu 2824027Sstever@eecs.umich.edu for (int i=0; i<Num_OpClasses; ++i) { 2834027Sstever@eecs.umich.edu std::stringstream subname; 2844027Sstever@eecs.umich.edu subname << opClassStrings[i] << "_delay"; 2854027Sstever@eecs.umich.edu issueDelayDist.subname(i, subname.str()); 2864027Sstever@eecs.umich.edu } 2874027Sstever@eecs.umich.edu*/ 2884027Sstever@eecs.umich.edu issueRate 2894027Sstever@eecs.umich.edu .name(name() + ".ISSUE:rate") 2904027Sstever@eecs.umich.edu .desc("Inst issue rate") 2914027Sstever@eecs.umich.edu .flags(total) 2924027Sstever@eecs.umich.edu ; 2934027Sstever@eecs.umich.edu issueRate = iqInstsIssued / cpu->numCycles; 2944027Sstever@eecs.umich.edu 2954027Sstever@eecs.umich.edu statFuBusy 2964027Sstever@eecs.umich.edu .init(Num_OpClasses) 2974027Sstever@eecs.umich.edu .name(name() + ".ISSUE:fu_full") 2982069SN/A .desc("attempts to use FU when none available") 2992069SN/A .flags(pdf | dist) 3002069SN/A ; 3012069SN/A for (int i=0; i < Num_OpClasses; ++i) { 3022069SN/A statFuBusy.subname(i, Enums::OpClassStrings[i]); 3032069SN/A } 3042069SN/A 3052090SN/A fuBusy 3062069SN/A .init(numThreads) 3072069SN/A .name(name() + ".ISSUE:fu_busy_cnt") 3082069SN/A .desc("FU busy when requested") 3092090SN/A .flags(total) 3108442Sgblack@eecs.umich.edu ; 3118442Sgblack@eecs.umich.edu 3122069SN/A fuBusyRate 3132069SN/A .name(name() + ".ISSUE:fu_busy_rate") 3142090SN/A .desc("FU busy rate (busy events/executed inst)") 3152069SN/A .flags(total) 3162069SN/A ; 3172069SN/A fuBusyRate = fuBusy / iqInstsIssued; 3182090SN/A 3192069SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 3202069SN/A // Tell mem dependence unit to reg stats as well. 3212069SN/A memDepUnit[tid].regStats(); 3222069SN/A } 3232069SN/A} 3242069SN/A 3252069SN/Atemplate <class Impl> 3262095SN/Avoid 3272132SN/AInstructionQueue<Impl>::resetState() 3282095SN/A{ 3292095SN/A //Initialize thread IQ counts 3302095SN/A for (ThreadID tid = 0; tid <numThreads; tid++) { 3312132SN/A count[tid] = 0; 3322095SN/A instList[tid].clear(); 3332095SN/A } 3342506SN/A 3352095SN/A // Initialize the number of free IQ entries. 3362095SN/A freeEntries = numEntries; 3372095SN/A 3382098SN/A // Note that in actuality, the registers corresponding to the logical 3392095SN/A // registers start off as ready. However this doesn't matter for the 3402095SN/A // IQ as the instruction should have been correctly told if those 3412095SN/A // registers are ready in rename. Thus it can all be initialized as 3422098SN/A // unready. 3438442Sgblack@eecs.umich.edu for (int i = 0; i < numPhysRegs; ++i) { 3448442Sgblack@eecs.umich.edu regScoreboard[i] = false; 3452095SN/A } 3462095SN/A 3472095SN/A for (ThreadID tid = 0; tid < numThreads; ++tid) { 3482095SN/A squashedSeqNum[tid] = 0; 3492095SN/A } 3502095SN/A 3512095SN/A for (int i = 0; i < Num_OpClasses; ++i) { 3522095SN/A while (!readyInsts[i].empty()) 3533349Sbinkertn@umich.edu readyInsts[i].pop(); 3542095SN/A queueOnList[i] = false; 3552095SN/A readyIt[i] = listOrder.end(); 3562095SN/A } 3577712Sgblack@eecs.umich.edu nonSpecInsts.clear(); 3582623SN/A listOrder.clear(); 3592623SN/A} 3602623SN/A 3612623SN/Atemplate <class Impl> 3622623SN/Avoid 3633349Sbinkertn@umich.eduInstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3642623SN/A{ 3652623SN/A activeThreads = at_ptr; 3662623SN/A} 3672623SN/A 3682623SN/Atemplate <class Impl> 3692623SN/Avoid 3702623SN/AInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 3712623SN/A{ 3724040Ssaidi@eecs.umich.edu issueToExecuteQueue = i2e_ptr; 3732095SN/A} 3742098SN/A 3752095SN/Atemplate <class Impl> 3762095SN/Avoid 3772095SN/AInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3782098SN/A{ 3792095SN/A timeBuffer = tb_ptr; 3802095SN/A 3812095SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3822095SN/A} 3832095SN/A 3842095SN/Atemplate <class Impl> 3852095SN/Avoid 3862069SN/AInstructionQueue<Impl>::switchOut() 3872069SN/A{ 3882132SN/A/* 3892068SN/A if (!instList[0].empty() || (numEntries != freeEntries) || 3902068SN/A !readyInsts[0].empty() || !nonSpecInsts.empty() || !listOrder.empty()) { 3912068SN/A dumpInsts(); 3922132SN/A// assert(0); 3932068SN/A } 3942068SN/A*/ 3952068SN/A resetState(); 3962069SN/A dependGraph.reset(); 3972068SN/A instsToExecute.clear(); 3982068SN/A switchedOut = true; 3998406Sksewell@umich.edu for (ThreadID tid = 0; tid < numThreads; ++tid) { 4002090SN/A memDepUnit[tid].switchOut(); 4012069SN/A } 4022068SN/A} 4032068SN/A 4042090SN/Atemplate <class Impl> 4052068SN/Avoid 4062068SN/AInstructionQueue<Impl>::takeOverFrom() 4072068SN/A{ 4087725SAli.Saidi@ARM.com switchedOut = false; 4097725SAli.Saidi@ARM.com} 4102095SN/A 4112132SN/Atemplate <class Impl> 4122095SN/Aint 4132095SN/AInstructionQueue<Impl>::entryAmount(ThreadID num_threads) 4146185Sksewell@umich.edu{ 4156185Sksewell@umich.edu if (iqPolicy == Partitioned) { 4162098SN/A return numEntries / num_threads; 4172095SN/A } else { 4182095SN/A return 0; 4192095SN/A } 4202095SN/A} 4212095SN/A 4223349Sbinkertn@umich.edu 4232095SN/Atemplate <class Impl> 4242095SN/Avoid 4252095SN/AInstructionQueue<Impl>::resetEntries() 4266185Sksewell@umich.edu{ 4276185Sksewell@umich.edu if (iqPolicy != Dynamic || numThreads > 1) { 4282110SN/A int active_threads = activeThreads->size(); 4292098SN/A 4302095SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 4312095SN/A list<ThreadID>::iterator end = activeThreads->end(); 4322095SN/A 4336179Sksewell@umich.edu while (threads != end) { 4342068SN/A ThreadID tid = *threads++; 4352068SN/A 4362068SN/A if (iqPolicy == Partitioned) { 4372068SN/A maxEntries[tid] = numEntries / active_threads; 4382068SN/A } else if(iqPolicy == Threshold && active_threads == 1) { 4392068SN/A maxEntries[tid] = numEntries; 4402068SN/A } 4412068SN/A } 4422068SN/A } 4432068SN/A} 4442068SN/A 4452068SN/Atemplate <class Impl> 4462068SN/Aunsigned 4472068SN/AInstructionQueue<Impl>::numFreeEntries() 4482068SN/A{ 4492068SN/A return freeEntries; 4502068SN/A} 4512068SN/A 4522068SN/Atemplate <class Impl> 4532068SN/Aunsigned 4542068SN/AInstructionQueue<Impl>::numFreeEntries(ThreadID tid) 4552068SN/A{ 4562068SN/A return maxEntries[tid] - count[tid]; 4572068SN/A} 4582068SN/A 4592068SN/A// Might want to do something more complex if it knows how many instructions 4602068SN/A// will be issued this cycle. 4612075SN/Atemplate <class Impl> 4622075SN/Abool 4632069SN/AInstructionQueue<Impl>::isFull() 4642075SN/A{ 4652075SN/A if (freeEntries == 0) { 4662075SN/A return(true); 4672068SN/A } else { 4682068SN/A return(false); 4692068SN/A } 4702068SN/A} 4712068SN/A 4722068SN/Atemplate <class Impl> 4732068SN/Abool 4743953Sstever@eecs.umich.eduInstructionQueue<Impl>::isFull(ThreadID tid) 4753953Sstever@eecs.umich.edu{ 4763953Sstever@eecs.umich.edu if (numFreeEntries(tid) == 0) { 4773953Sstever@eecs.umich.edu return(true); 4783953Sstever@eecs.umich.edu } else { 4793953Sstever@eecs.umich.edu return(false); 4803953Sstever@eecs.umich.edu } 4813953Sstever@eecs.umich.edu} 4823953Sstever@eecs.umich.edu 4832068SN/Atemplate <class Impl> 4842068SN/Abool 4855736Snate@binkert.orgInstructionQueue<Impl>::hasReadyInsts() 4865745Snate@binkert.org{ 4872068SN/A if (!listOrder.empty()) { 4882068SN/A return true; 4892068SN/A } 4902069SN/A 4912623SN/A for (int i = 0; i < Num_OpClasses; ++i) { 4924027Sstever@eecs.umich.edu if (!readyInsts[i].empty()) { 4934027Sstever@eecs.umich.edu return true; 4942623SN/A } 4952623SN/A } 4962069SN/A 4972095SN/A return false; 4982095SN/A} 4992069SN/A 5002068SN/Atemplate <class Impl> 5013953Sstever@eecs.umich.eduvoid 5026181Sksewell@umich.eduInstructionQueue<Impl>::insert(DynInstPtr &new_inst) 5032068SN/A{ 5046181Sksewell@umich.edu // Make sure the instruction is valid 5056181Sksewell@umich.edu assert(new_inst); 5063953Sstever@eecs.umich.edu 5076192Sksewell@umich.edu DPRINTF(IQ, "Adding instruction [sn:%lli] PC %#x to the IQ.\n", 5082068SN/A new_inst->seqNum, new_inst->readPC()); 5092068SN/A 5102075SN/A assert(freeEntries != 0); 5112075SN/A 5122068SN/A instList[new_inst->threadNumber].push_back(new_inst); 5132075SN/A 5142069SN/A --freeEntries; 5152069SN/A 5162068SN/A new_inst->setInIQ(); 5172068SN/A 5182068SN/A // Look through its source registers (physical regs), and mark any 5192068SN/A // dependencies. 5202075SN/A addToDependents(new_inst); 5212075SN/A 5222068SN/A // Have this instruction set itself as the producer of its destination 5232068SN/A // register(s). 5242075SN/A addToProducers(new_inst); 5252069SN/A 5262069SN/A if (new_inst->isMemRef()) { 5272068SN/A memDepUnit[new_inst->threadNumber].insert(new_inst); 5282068SN/A } else { 5292068SN/A addIfReady(new_inst); 5302075SN/A } 5312075SN/A 5322075SN/A ++iqInstsAdded; 5332075SN/A 5342075SN/A count[new_inst->threadNumber]++; 5356739Sgblack@eecs.umich.edu 5367725SAli.Saidi@ARM.com assert(freeEntries == (numEntries - countInsts())); 5372068SN/A} 5382068SN/A 5397725SAli.Saidi@ARM.comtemplate <class Impl> 5402075SN/Avoid 5412068SN/AInstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) 5422068SN/A{ 5432068SN/A // @todo: Clean up this code; can do it by setting inst as unable 5442068SN/A // to issue, then calling normal insert on the inst. 5452068SN/A 5462068SN/A assert(new_inst); 5472068SN/A 5482075SN/A nonSpecInsts[new_inst->seqNum] = new_inst; 5492075SN/A 5502068SN/A DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %#x " 5512075SN/A "to the IQ.\n", 5522069SN/A new_inst->seqNum, new_inst->readPC()); 5532068SN/A 5542068SN/A assert(freeEntries != 0); 5552068SN/A 5562075SN/A instList[new_inst->threadNumber].push_back(new_inst); 5572075SN/A 5582075SN/A --freeEntries; 5592068SN/A 5602075SN/A new_inst->setInIQ(); 5612623SN/A 5622068SN/A // Have this instruction set itself as the producer of its destination 5632068SN/A // register(s). 5642068SN/A addToProducers(new_inst); 5652068SN/A 5662075SN/A // If it's a memory instruction, add it to the memory dependency 5672075SN/A // unit. 5682068SN/A if (new_inst->isMemRef()) { 5692075SN/A memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 5702069SN/A } 5712068SN/A 5722068SN/A ++iqNonSpecInstsAdded; 5732068SN/A 574 count[new_inst->threadNumber]++; 575 576 assert(freeEntries == (numEntries - countInsts())); 577} 578 579template <class Impl> 580void 581InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) 582{ 583 memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 584 585 insertNonSpec(barr_inst); 586} 587 588template <class Impl> 589typename Impl::DynInstPtr 590InstructionQueue<Impl>::getInstToExecute() 591{ 592 assert(!instsToExecute.empty()); 593 DynInstPtr inst = instsToExecute.front(); 594 instsToExecute.pop_front(); 595 return inst; 596} 597 598template <class Impl> 599void 600InstructionQueue<Impl>::addToOrderList(OpClass op_class) 601{ 602 assert(!readyInsts[op_class].empty()); 603 604 ListOrderEntry queue_entry; 605 606 queue_entry.queueType = op_class; 607 608 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 609 610 ListOrderIt list_it = listOrder.begin(); 611 ListOrderIt list_end_it = listOrder.end(); 612 613 while (list_it != list_end_it) { 614 if ((*list_it).oldestInst > queue_entry.oldestInst) { 615 break; 616 } 617 618 list_it++; 619 } 620 621 readyIt[op_class] = listOrder.insert(list_it, queue_entry); 622 queueOnList[op_class] = true; 623} 624 625template <class Impl> 626void 627InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 628{ 629 // Get iterator of next item on the list 630 // Delete the original iterator 631 // Determine if the next item is either the end of the list or younger 632 // than the new instruction. If so, then add in a new iterator right here. 633 // If not, then move along. 634 ListOrderEntry queue_entry; 635 OpClass op_class = (*list_order_it).queueType; 636 ListOrderIt next_it = list_order_it; 637 638 ++next_it; 639 640 queue_entry.queueType = op_class; 641 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 642 643 while (next_it != listOrder.end() && 644 (*next_it).oldestInst < queue_entry.oldestInst) { 645 ++next_it; 646 } 647 648 readyIt[op_class] = listOrder.insert(next_it, queue_entry); 649} 650 651template <class Impl> 652void 653InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 654{ 655 DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 656 // The CPU could have been sleeping until this op completed (*extremely* 657 // long latency op). Wake it if it was. This may be overkill. 658 if (isSwitchedOut()) { 659 DPRINTF(IQ, "FU completion not processed, IQ is switched out [sn:%lli]\n", 660 inst->seqNum); 661 return; 662 } 663 664 iewStage->wakeCPU(); 665 666 if (fu_idx > -1) 667 fuPool->freeUnitNextCycle(fu_idx); 668 669 // @todo: Ensure that these FU Completions happen at the beginning 670 // of a cycle, otherwise they could add too many instructions to 671 // the queue. 672 issueToExecuteQueue->access(-1)->size++; 673 instsToExecute.push_back(inst); 674} 675 676// @todo: Figure out a better way to remove the squashed items from the 677// lists. Checking the top item of each list to see if it's squashed 678// wastes time and forces jumps. 679template <class Impl> 680void 681InstructionQueue<Impl>::scheduleReadyInsts() 682{ 683 DPRINTF(IQ, "Attempting to schedule ready instructions from " 684 "the IQ.\n"); 685 686 IssueStruct *i2e_info = issueToExecuteQueue->access(0); 687 688 // Have iterator to head of the list 689 // While I haven't exceeded bandwidth or reached the end of the list, 690 // Try to get a FU that can do what this op needs. 691 // If successful, change the oldestInst to the new top of the list, put 692 // the queue in the proper place in the list. 693 // Increment the iterator. 694 // This will avoid trying to schedule a certain op class if there are no 695 // FUs that handle it. 696 ListOrderIt order_it = listOrder.begin(); 697 ListOrderIt order_end_it = listOrder.end(); 698 int total_issued = 0; 699 700 while (total_issued < totalWidth && 701 iewStage->canIssue() && 702 order_it != order_end_it) { 703 OpClass op_class = (*order_it).queueType; 704 705 assert(!readyInsts[op_class].empty()); 706 707 DynInstPtr issuing_inst = readyInsts[op_class].top(); 708 709 assert(issuing_inst->seqNum == (*order_it).oldestInst); 710 711 if (issuing_inst->isSquashed()) { 712 readyInsts[op_class].pop(); 713 714 if (!readyInsts[op_class].empty()) { 715 moveToYoungerInst(order_it); 716 } else { 717 readyIt[op_class] = listOrder.end(); 718 queueOnList[op_class] = false; 719 } 720 721 listOrder.erase(order_it++); 722 723 ++iqSquashedInstsIssued; 724 725 continue; 726 } 727 728 int idx = -2; 729 int op_latency = 1; 730 ThreadID tid = issuing_inst->threadNumber; 731 732 if (op_class != No_OpClass) { 733 idx = fuPool->getUnit(op_class); 734 735 if (idx > -1) { 736 op_latency = fuPool->getOpLatency(op_class); 737 } 738 } 739 740 // If we have an instruction that doesn't require a FU, or a 741 // valid FU, then schedule for execution. 742 if (idx == -2 || idx != -1) { 743 if (op_latency == 1) { 744 i2e_info->size++; 745 instsToExecute.push_back(issuing_inst); 746 747 // Add the FU onto the list of FU's to be freed next 748 // cycle if we used one. 749 if (idx >= 0) 750 fuPool->freeUnitNextCycle(idx); 751 } else { 752 int issue_latency = fuPool->getIssueLatency(op_class); 753 // Generate completion event for the FU 754 FUCompletion *execution = new FUCompletion(issuing_inst, 755 idx, this); 756 757 cpu->schedule(execution, curTick + cpu->ticks(op_latency - 1)); 758 759 // @todo: Enforce that issue_latency == 1 or op_latency 760 if (issue_latency > 1) { 761 // If FU isn't pipelined, then it must be freed 762 // upon the execution completing. 763 execution->setFreeFU(); 764 } else { 765 // Add the FU onto the list of FU's to be freed next cycle. 766 fuPool->freeUnitNextCycle(idx); 767 } 768 } 769 770 DPRINTF(IQ, "Thread %i: Issuing instruction PC %#x " 771 "[sn:%lli]\n", 772 tid, issuing_inst->readPC(), 773 issuing_inst->seqNum); 774 775 readyInsts[op_class].pop(); 776 777 if (!readyInsts[op_class].empty()) { 778 moveToYoungerInst(order_it); 779 } else { 780 readyIt[op_class] = listOrder.end(); 781 queueOnList[op_class] = false; 782 } 783 784 issuing_inst->setIssued(); 785 ++total_issued; 786 787 if (!issuing_inst->isMemRef()) { 788 // Memory instructions can not be freed from the IQ until they 789 // complete. 790 ++freeEntries; 791 count[tid]--; 792 issuing_inst->clearInIQ(); 793 } else { 794 memDepUnit[tid].issue(issuing_inst); 795 } 796 797 listOrder.erase(order_it++); 798 statIssuedInstType[tid][op_class]++; 799 iewStage->incrWb(issuing_inst->seqNum); 800 } else { 801 statFuBusy[op_class]++; 802 fuBusy[tid]++; 803 ++order_it; 804 } 805 } 806 807 numIssuedDist.sample(total_issued); 808 iqInstsIssued+= total_issued; 809 810 // If we issued any instructions, tell the CPU we had activity. 811 if (total_issued) { 812 cpu->activityThisCycle(); 813 } else { 814 DPRINTF(IQ, "Not able to schedule any instructions.\n"); 815 } 816} 817 818template <class Impl> 819void 820InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 821{ 822 DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 823 "to execute.\n", inst); 824 825 NonSpecMapIt inst_it = nonSpecInsts.find(inst); 826 827 assert(inst_it != nonSpecInsts.end()); 828 829 ThreadID tid = (*inst_it).second->threadNumber; 830 831 (*inst_it).second->setAtCommit(); 832 833 (*inst_it).second->setCanIssue(); 834 835 if (!(*inst_it).second->isMemRef()) { 836 addIfReady((*inst_it).second); 837 } else { 838 memDepUnit[tid].nonSpecInstReady((*inst_it).second); 839 } 840 841 (*inst_it).second = NULL; 842 843 nonSpecInsts.erase(inst_it); 844} 845 846template <class Impl> 847void 848InstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 849{ 850 DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 851 tid,inst); 852 853 ListIt iq_it = instList[tid].begin(); 854 855 while (iq_it != instList[tid].end() && 856 (*iq_it)->seqNum <= inst) { 857 ++iq_it; 858 instList[tid].pop_front(); 859 } 860 861 assert(freeEntries == (numEntries - countInsts())); 862} 863 864template <class Impl> 865int 866InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 867{ 868 int dependents = 0; 869 870 DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 871 872 assert(!completed_inst->isSquashed()); 873 874 // Tell the memory dependence unit to wake any dependents on this 875 // instruction if it is a memory instruction. Also complete the memory 876 // instruction at this point since we know it executed without issues. 877 // @todo: Might want to rename "completeMemInst" to something that 878 // indicates that it won't need to be replayed, and call this 879 // earlier. Might not be a big deal. 880 if (completed_inst->isMemRef()) { 881 memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 882 completeMemInst(completed_inst); 883 } else if (completed_inst->isMemBarrier() || 884 completed_inst->isWriteBarrier()) { 885 memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 886 } 887 888 for (int dest_reg_idx = 0; 889 dest_reg_idx < completed_inst->numDestRegs(); 890 dest_reg_idx++) 891 { 892 PhysRegIndex dest_reg = 893 completed_inst->renamedDestRegIdx(dest_reg_idx); 894 895 // Special case of uniq or control registers. They are not 896 // handled by the IQ and thus have no dependency graph entry. 897 // @todo Figure out a cleaner way to handle this. 898 if (dest_reg >= numPhysRegs) { 899 continue; 900 } 901 902 DPRINTF(IQ, "Waking any dependents on register %i.\n", 903 (int) dest_reg); 904 905 //Go through the dependency chain, marking the registers as 906 //ready within the waiting instructions. 907 DynInstPtr dep_inst = dependGraph.pop(dest_reg); 908 909 while (dep_inst) { 910 DPRINTF(IQ, "Waking up a dependent instruction, PC%#x.\n", 911 dep_inst->readPC()); 912 913 // Might want to give more information to the instruction 914 // so that it knows which of its source registers is 915 // ready. However that would mean that the dependency 916 // graph entries would need to hold the src_reg_idx. 917 dep_inst->markSrcRegReady(); 918 919 addIfReady(dep_inst); 920 921 dep_inst = dependGraph.pop(dest_reg); 922 923 ++dependents; 924 } 925 926 // Reset the head node now that all of its dependents have 927 // been woken up. 928 assert(dependGraph.empty(dest_reg)); 929 dependGraph.clearInst(dest_reg); 930 931 // Mark the scoreboard as having that register ready. 932 regScoreboard[dest_reg] = true; 933 } 934 return dependents; 935} 936 937template <class Impl> 938void 939InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 940{ 941 OpClass op_class = ready_inst->opClass(); 942 943 readyInsts[op_class].push(ready_inst); 944 945 // Will need to reorder the list if either a queue is not on the list, 946 // or it has an older instruction than last time. 947 if (!queueOnList[op_class]) { 948 addToOrderList(op_class); 949 } else if (readyInsts[op_class].top()->seqNum < 950 (*readyIt[op_class]).oldestInst) { 951 listOrder.erase(readyIt[op_class]); 952 addToOrderList(op_class); 953 } 954 955 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 956 "the ready list, PC %#x opclass:%i [sn:%lli].\n", 957 ready_inst->readPC(), op_class, ready_inst->seqNum); 958} 959 960template <class Impl> 961void 962InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 963{ 964 DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 965 resched_inst->clearCanIssue(); 966 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 967} 968 969template <class Impl> 970void 971InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 972{ 973 memDepUnit[replay_inst->threadNumber].replay(replay_inst); 974} 975 976template <class Impl> 977void 978InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 979{ 980 ThreadID tid = completed_inst->threadNumber; 981 982 DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n", 983 completed_inst->readPC(), completed_inst->seqNum); 984 985 ++freeEntries; 986 987 completed_inst->memOpDone = true; 988 989 memDepUnit[tid].completed(completed_inst); 990 count[tid]--; 991} 992 993template <class Impl> 994void 995InstructionQueue<Impl>::violation(DynInstPtr &store, 996 DynInstPtr &faulting_load) 997{ 998 memDepUnit[store->threadNumber].violation(store, faulting_load); 999} 1000 1001template <class Impl> 1002void 1003InstructionQueue<Impl>::squash(ThreadID tid) 1004{ 1005 DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 1006 "the IQ.\n", tid); 1007 1008 // Read instruction sequence number of last instruction out of the 1009 // time buffer. 1010 squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 1011 1012 // Call doSquash if there are insts in the IQ 1013 if (count[tid] > 0) { 1014 doSquash(tid); 1015 } 1016 1017 // Also tell the memory dependence unit to squash. 1018 memDepUnit[tid].squash(squashedSeqNum[tid], tid); 1019} 1020 1021template <class Impl> 1022void 1023InstructionQueue<Impl>::doSquash(ThreadID tid) 1024{ 1025 // Start at the tail. 1026 ListIt squash_it = instList[tid].end(); 1027 --squash_it; 1028 1029 DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 1030 tid, squashedSeqNum[tid]); 1031 1032 // Squash any instructions younger than the squashed sequence number 1033 // given. 1034 while (squash_it != instList[tid].end() && 1035 (*squash_it)->seqNum > squashedSeqNum[tid]) { 1036 1037 DynInstPtr squashed_inst = (*squash_it); 1038 1039 // Only handle the instruction if it actually is in the IQ and 1040 // hasn't already been squashed in the IQ. 1041 if (squashed_inst->threadNumber != tid || 1042 squashed_inst->isSquashedInIQ()) { 1043 --squash_it; 1044 continue; 1045 } 1046 1047 if (!squashed_inst->isIssued() || 1048 (squashed_inst->isMemRef() && 1049 !squashed_inst->memOpDone)) { 1050 1051 DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x " 1052 "squashed.\n", 1053 tid, squashed_inst->seqNum, squashed_inst->readPC()); 1054 1055 // Remove the instruction from the dependency list. 1056 if (!squashed_inst->isNonSpeculative() && 1057 !squashed_inst->isStoreConditional() && 1058 !squashed_inst->isMemBarrier() && 1059 !squashed_inst->isWriteBarrier()) { 1060 1061 for (int src_reg_idx = 0; 1062 src_reg_idx < squashed_inst->numSrcRegs(); 1063 src_reg_idx++) 1064 { 1065 PhysRegIndex src_reg = 1066 squashed_inst->renamedSrcRegIdx(src_reg_idx); 1067 1068 // Only remove it from the dependency graph if it 1069 // was placed there in the first place. 1070 1071 // Instead of doing a linked list traversal, we 1072 // can just remove these squashed instructions 1073 // either at issue time, or when the register is 1074 // overwritten. The only downside to this is it 1075 // leaves more room for error. 1076 1077 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 1078 src_reg < numPhysRegs) { 1079 dependGraph.remove(src_reg, squashed_inst); 1080 } 1081 1082 1083 ++iqSquashedOperandsExamined; 1084 } 1085 } else if (!squashed_inst->isStoreConditional() || 1086 !squashed_inst->isCompleted()) { 1087 NonSpecMapIt ns_inst_it = 1088 nonSpecInsts.find(squashed_inst->seqNum); 1089 assert(ns_inst_it != nonSpecInsts.end()); 1090 if (ns_inst_it == nonSpecInsts.end()) { 1091 assert(squashed_inst->getFault() != NoFault); 1092 } else { 1093 1094 (*ns_inst_it).second = NULL; 1095 1096 nonSpecInsts.erase(ns_inst_it); 1097 1098 ++iqSquashedNonSpecRemoved; 1099 } 1100 } 1101 1102 // Might want to also clear out the head of the dependency graph. 1103 1104 // Mark it as squashed within the IQ. 1105 squashed_inst->setSquashedInIQ(); 1106 1107 // @todo: Remove this hack where several statuses are set so the 1108 // inst will flow through the rest of the pipeline. 1109 squashed_inst->setIssued(); 1110 squashed_inst->setCanCommit(); 1111 squashed_inst->clearInIQ(); 1112 1113 //Update Thread IQ Count 1114 count[squashed_inst->threadNumber]--; 1115 1116 ++freeEntries; 1117 } 1118 1119 instList[tid].erase(squash_it--); 1120 ++iqSquashedInstsExamined; 1121 } 1122} 1123 1124template <class Impl> 1125bool 1126InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 1127{ 1128 // Loop through the instruction's source registers, adding 1129 // them to the dependency list if they are not ready. 1130 int8_t total_src_regs = new_inst->numSrcRegs(); 1131 bool return_val = false; 1132 1133 for (int src_reg_idx = 0; 1134 src_reg_idx < total_src_regs; 1135 src_reg_idx++) 1136 { 1137 // Only add it to the dependency graph if it's not ready. 1138 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 1139 PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 1140 1141 // Check the IQ's scoreboard to make sure the register 1142 // hasn't become ready while the instruction was in flight 1143 // between stages. Only if it really isn't ready should 1144 // it be added to the dependency graph. 1145 if (src_reg >= numPhysRegs) { 1146 continue; 1147 } else if (regScoreboard[src_reg] == false) { 1148 DPRINTF(IQ, "Instruction PC %#x has src reg %i that " 1149 "is being added to the dependency chain.\n", 1150 new_inst->readPC(), src_reg); 1151 1152 dependGraph.insert(src_reg, new_inst); 1153 1154 // Change the return value to indicate that something 1155 // was added to the dependency graph. 1156 return_val = true; 1157 } else { 1158 DPRINTF(IQ, "Instruction PC %#x has src reg %i that " 1159 "became ready before it reached the IQ.\n", 1160 new_inst->readPC(), src_reg); 1161 // Mark a register ready within the instruction. 1162 new_inst->markSrcRegReady(src_reg_idx); 1163 } 1164 } 1165 } 1166 1167 return return_val; 1168} 1169 1170template <class Impl> 1171void 1172InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) 1173{ 1174 // Nothing really needs to be marked when an instruction becomes 1175 // the producer of a register's value, but for convenience a ptr 1176 // to the producing instruction will be placed in the head node of 1177 // the dependency links. 1178 int8_t total_dest_regs = new_inst->numDestRegs(); 1179 1180 for (int dest_reg_idx = 0; 1181 dest_reg_idx < total_dest_regs; 1182 dest_reg_idx++) 1183 { 1184 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 1185 1186 // Instructions that use the misc regs will have a reg number 1187 // higher than the normal physical registers. In this case these 1188 // registers are not renamed, and there is no need to track 1189 // dependencies as these instructions must be executed at commit. 1190 if (dest_reg >= numPhysRegs) { 1191 continue; 1192 } 1193 1194 if (!dependGraph.empty(dest_reg)) { 1195 dependGraph.dump(); 1196 panic("Dependency graph %i not empty!", dest_reg); 1197 } 1198 1199 dependGraph.setInst(dest_reg, new_inst); 1200 1201 // Mark the scoreboard to say it's not yet ready. 1202 regScoreboard[dest_reg] = false; 1203 } 1204} 1205 1206template <class Impl> 1207void 1208InstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 1209{ 1210 // If the instruction now has all of its source registers 1211 // available, then add it to the list of ready instructions. 1212 if (inst->readyToIssue()) { 1213 1214 //Add the instruction to the proper ready list. 1215 if (inst->isMemRef()) { 1216 1217 DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 1218 1219 // Message to the mem dependence unit that this instruction has 1220 // its registers ready. 1221 memDepUnit[inst->threadNumber].regsReady(inst); 1222 1223 return; 1224 } 1225 1226 OpClass op_class = inst->opClass(); 1227 1228 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 1229 "the ready list, PC %#x opclass:%i [sn:%lli].\n", 1230 inst->readPC(), op_class, inst->seqNum); 1231 1232 readyInsts[op_class].push(inst); 1233 1234 // Will need to reorder the list if either a queue is not on the list, 1235 // or it has an older instruction than last time. 1236 if (!queueOnList[op_class]) { 1237 addToOrderList(op_class); 1238 } else if (readyInsts[op_class].top()->seqNum < 1239 (*readyIt[op_class]).oldestInst) { 1240 listOrder.erase(readyIt[op_class]); 1241 addToOrderList(op_class); 1242 } 1243 } 1244} 1245 1246template <class Impl> 1247int 1248InstructionQueue<Impl>::countInsts() 1249{ 1250#if 0 1251 //ksewell:This works but definitely could use a cleaner write 1252 //with a more intuitive way of counting. Right now it's 1253 //just brute force .... 1254 // Change the #if if you want to use this method. 1255 int total_insts = 0; 1256 1257 for (ThreadID tid = 0; tid < numThreads; ++tid) { 1258 ListIt count_it = instList[tid].begin(); 1259 1260 while (count_it != instList[tid].end()) { 1261 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 1262 if (!(*count_it)->isIssued()) { 1263 ++total_insts; 1264 } else if ((*count_it)->isMemRef() && 1265 !(*count_it)->memOpDone) { 1266 // Loads that have not been marked as executed still count 1267 // towards the total instructions. 1268 ++total_insts; 1269 } 1270 } 1271 1272 ++count_it; 1273 } 1274 } 1275 1276 return total_insts; 1277#else 1278 return numEntries - freeEntries; 1279#endif 1280} 1281 1282template <class Impl> 1283void 1284InstructionQueue<Impl>::dumpLists() 1285{ 1286 for (int i = 0; i < Num_OpClasses; ++i) { 1287 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 1288 1289 cprintf("\n"); 1290 } 1291 1292 cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 1293 1294 NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 1295 NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 1296 1297 cprintf("Non speculative list: "); 1298 1299 while (non_spec_it != non_spec_end_it) { 1300 cprintf("%#x [sn:%lli]", (*non_spec_it).second->readPC(), 1301 (*non_spec_it).second->seqNum); 1302 ++non_spec_it; 1303 } 1304 1305 cprintf("\n"); 1306 1307 ListOrderIt list_order_it = listOrder.begin(); 1308 ListOrderIt list_order_end_it = listOrder.end(); 1309 int i = 1; 1310 1311 cprintf("List order: "); 1312 1313 while (list_order_it != list_order_end_it) { 1314 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 1315 (*list_order_it).oldestInst); 1316 1317 ++list_order_it; 1318 ++i; 1319 } 1320 1321 cprintf("\n"); 1322} 1323 1324 1325template <class Impl> 1326void 1327InstructionQueue<Impl>::dumpInsts() 1328{ 1329 for (ThreadID tid = 0; tid < numThreads; ++tid) { 1330 int num = 0; 1331 int valid_num = 0; 1332 ListIt inst_list_it = instList[tid].begin(); 1333 1334 while (inst_list_it != instList[tid].end()) { 1335 cprintf("Instruction:%i\n", num); 1336 if (!(*inst_list_it)->isSquashed()) { 1337 if (!(*inst_list_it)->isIssued()) { 1338 ++valid_num; 1339 cprintf("Count:%i\n", valid_num); 1340 } else if ((*inst_list_it)->isMemRef() && 1341 !(*inst_list_it)->memOpDone) { 1342 // Loads that have not been marked as executed 1343 // still count towards the total instructions. 1344 ++valid_num; 1345 cprintf("Count:%i\n", valid_num); 1346 } 1347 } 1348 1349 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n" 1350 "Issued:%i\nSquashed:%i\n", 1351 (*inst_list_it)->readPC(), 1352 (*inst_list_it)->seqNum, 1353 (*inst_list_it)->threadNumber, 1354 (*inst_list_it)->isIssued(), 1355 (*inst_list_it)->isSquashed()); 1356 1357 if ((*inst_list_it)->isMemRef()) { 1358 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 1359 } 1360 1361 cprintf("\n"); 1362 1363 inst_list_it++; 1364 ++num; 1365 } 1366 } 1367 1368 cprintf("Insts to Execute list:\n"); 1369 1370 int num = 0; 1371 int valid_num = 0; 1372 ListIt inst_list_it = instsToExecute.begin(); 1373 1374 while (inst_list_it != instsToExecute.end()) 1375 { 1376 cprintf("Instruction:%i\n", 1377 num); 1378 if (!(*inst_list_it)->isSquashed()) { 1379 if (!(*inst_list_it)->isIssued()) { 1380 ++valid_num; 1381 cprintf("Count:%i\n", valid_num); 1382 } else if ((*inst_list_it)->isMemRef() && 1383 !(*inst_list_it)->memOpDone) { 1384 // Loads that have not been marked as executed 1385 // still count towards the total instructions. 1386 ++valid_num; 1387 cprintf("Count:%i\n", valid_num); 1388 } 1389 } 1390 1391 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n" 1392 "Issued:%i\nSquashed:%i\n", 1393 (*inst_list_it)->readPC(), 1394 (*inst_list_it)->seqNum, 1395 (*inst_list_it)->threadNumber, 1396 (*inst_list_it)->isIssued(), 1397 (*inst_list_it)->isSquashed()); 1398 1399 if ((*inst_list_it)->isMemRef()) { 1400 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 1401 } 1402 1403 cprintf("\n"); 1404 1405 inst_list_it++; 1406 ++num; 1407 } 1408} 1409