inst_queue_impl.hh revision 3093
11689SN/A/* 22326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292831Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322064SN/A#include <limits> 331060SN/A#include <vector> 341060SN/A 351696SN/A#include "sim/root.hh" 361689SN/A 372292SN/A#include "cpu/o3/fu_pool.hh" 381717SN/A#include "cpu/o3/inst_queue.hh" 391060SN/A 401061SN/Atemplate <class Impl> 412292SN/AInstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 422292SN/A int fu_idx, 432292SN/A InstructionQueue<Impl> *iq_ptr) 442292SN/A : Event(&mainEventQueue, Stat_Event_Pri), 452326SN/A inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 461060SN/A{ 472292SN/A this->setFlags(Event::AutoDelete); 482292SN/A} 492292SN/A 502292SN/Atemplate <class Impl> 512292SN/Avoid 522292SN/AInstructionQueue<Impl>::FUCompletion::process() 532292SN/A{ 542326SN/A iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 552292SN/A inst = NULL; 562292SN/A} 572292SN/A 582292SN/A 592292SN/Atemplate <class Impl> 602292SN/Aconst char * 612292SN/AInstructionQueue<Impl>::FUCompletion::description() 622292SN/A{ 632292SN/A return "Functional unit completion event"; 642292SN/A} 652292SN/A 662292SN/Atemplate <class Impl> 672292SN/AInstructionQueue<Impl>::InstructionQueue(Params *params) 682669Sktlim@umich.edu : fuPool(params->fuPool), 692292SN/A numEntries(params->numIQEntries), 702292SN/A totalWidth(params->issueWidth), 712292SN/A numPhysIntRegs(params->numPhysIntRegs), 722292SN/A numPhysFloatRegs(params->numPhysFloatRegs), 732292SN/A commitToIEWDelay(params->commitToIEWDelay) 742292SN/A{ 752292SN/A assert(fuPool); 762292SN/A 772307SN/A switchedOut = false; 782307SN/A 792292SN/A numThreads = params->numberOfThreads; 801060SN/A 811060SN/A // Set the number of physical registers as the number of int + float 821060SN/A numPhysRegs = numPhysIntRegs + numPhysFloatRegs; 831060SN/A 842292SN/A DPRINTF(IQ, "There are %i physical registers.\n", numPhysRegs); 851060SN/A 861060SN/A //Create an entry for each physical register within the 871060SN/A //dependency graph. 882326SN/A dependGraph.resize(numPhysRegs); 891060SN/A 901060SN/A // Resize the register scoreboard. 911060SN/A regScoreboard.resize(numPhysRegs); 921060SN/A 932292SN/A //Initialize Mem Dependence Units 942292SN/A for (int i = 0; i < numThreads; i++) { 952292SN/A memDepUnit[i].init(params,i); 962292SN/A memDepUnit[i].setIQ(this); 971060SN/A } 981060SN/A 992307SN/A resetState(); 1002292SN/A 1012980Sgblack@eecs.umich.edu std::string policy = params->smtIQPolicy; 1022292SN/A 1032292SN/A //Convert string to lowercase 1042292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1052292SN/A (int(*)(int)) tolower); 1062292SN/A 1072292SN/A //Figure out resource sharing policy 1082292SN/A if (policy == "dynamic") { 1092292SN/A iqPolicy = Dynamic; 1102292SN/A 1112292SN/A //Set Max Entries to Total ROB Capacity 1122292SN/A for (int i = 0; i < numThreads; i++) { 1132292SN/A maxEntries[i] = numEntries; 1142292SN/A } 1152292SN/A 1162292SN/A } else if (policy == "partitioned") { 1172292SN/A iqPolicy = Partitioned; 1182292SN/A 1192292SN/A //@todo:make work if part_amt doesnt divide evenly. 1202292SN/A int part_amt = numEntries / numThreads; 1212292SN/A 1222292SN/A //Divide ROB up evenly 1232292SN/A for (int i = 0; i < numThreads; i++) { 1242292SN/A maxEntries[i] = part_amt; 1252292SN/A } 1262292SN/A 1272831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 1282292SN/A "%i entries per thread.\n",part_amt); 1292292SN/A 1302292SN/A } else if (policy == "threshold") { 1312292SN/A iqPolicy = Threshold; 1322292SN/A 1332292SN/A double threshold = (double)params->smtIQThreshold / 100; 1342292SN/A 1352292SN/A int thresholdIQ = (int)((double)threshold * numEntries); 1362292SN/A 1372292SN/A //Divide up by threshold amount 1382292SN/A for (int i = 0; i < numThreads; i++) { 1392292SN/A maxEntries[i] = thresholdIQ; 1402292SN/A } 1412292SN/A 1422831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Threshold:" 1432292SN/A "%i entries per thread.\n",thresholdIQ); 1442292SN/A } else { 1452292SN/A assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 1462292SN/A "Partitioned, Threshold}"); 1472292SN/A } 1482292SN/A} 1492292SN/A 1502292SN/Atemplate <class Impl> 1512292SN/AInstructionQueue<Impl>::~InstructionQueue() 1522292SN/A{ 1532326SN/A dependGraph.reset(); 1542348SN/A#ifdef DEBUG 1552326SN/A cprintf("Nodes traversed: %i, removed: %i\n", 1562326SN/A dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1572348SN/A#endif 1582292SN/A} 1592292SN/A 1602292SN/Atemplate <class Impl> 1612292SN/Astd::string 1622292SN/AInstructionQueue<Impl>::name() const 1632292SN/A{ 1642292SN/A return cpu->name() + ".iq"; 1651060SN/A} 1661060SN/A 1671061SN/Atemplate <class Impl> 1681060SN/Avoid 1691062SN/AInstructionQueue<Impl>::regStats() 1701062SN/A{ 1712301SN/A using namespace Stats; 1721062SN/A iqInstsAdded 1731062SN/A .name(name() + ".iqInstsAdded") 1741062SN/A .desc("Number of instructions added to the IQ (excludes non-spec)") 1751062SN/A .prereq(iqInstsAdded); 1761062SN/A 1771062SN/A iqNonSpecInstsAdded 1781062SN/A .name(name() + ".iqNonSpecInstsAdded") 1791062SN/A .desc("Number of non-speculative instructions added to the IQ") 1801062SN/A .prereq(iqNonSpecInstsAdded); 1811062SN/A 1822301SN/A iqInstsIssued 1832301SN/A .name(name() + ".iqInstsIssued") 1842301SN/A .desc("Number of instructions issued") 1852301SN/A .prereq(iqInstsIssued); 1861062SN/A 1871062SN/A iqIntInstsIssued 1881062SN/A .name(name() + ".iqIntInstsIssued") 1891062SN/A .desc("Number of integer instructions issued") 1901062SN/A .prereq(iqIntInstsIssued); 1911062SN/A 1921062SN/A iqFloatInstsIssued 1931062SN/A .name(name() + ".iqFloatInstsIssued") 1941062SN/A .desc("Number of float instructions issued") 1951062SN/A .prereq(iqFloatInstsIssued); 1961062SN/A 1971062SN/A iqBranchInstsIssued 1981062SN/A .name(name() + ".iqBranchInstsIssued") 1991062SN/A .desc("Number of branch instructions issued") 2001062SN/A .prereq(iqBranchInstsIssued); 2011062SN/A 2021062SN/A iqMemInstsIssued 2031062SN/A .name(name() + ".iqMemInstsIssued") 2041062SN/A .desc("Number of memory instructions issued") 2051062SN/A .prereq(iqMemInstsIssued); 2061062SN/A 2071062SN/A iqMiscInstsIssued 2081062SN/A .name(name() + ".iqMiscInstsIssued") 2091062SN/A .desc("Number of miscellaneous instructions issued") 2101062SN/A .prereq(iqMiscInstsIssued); 2111062SN/A 2121062SN/A iqSquashedInstsIssued 2131062SN/A .name(name() + ".iqSquashedInstsIssued") 2141062SN/A .desc("Number of squashed instructions issued") 2151062SN/A .prereq(iqSquashedInstsIssued); 2161062SN/A 2171062SN/A iqSquashedInstsExamined 2181062SN/A .name(name() + ".iqSquashedInstsExamined") 2191062SN/A .desc("Number of squashed instructions iterated over during squash;" 2201062SN/A " mainly for profiling") 2211062SN/A .prereq(iqSquashedInstsExamined); 2221062SN/A 2231062SN/A iqSquashedOperandsExamined 2241062SN/A .name(name() + ".iqSquashedOperandsExamined") 2251062SN/A .desc("Number of squashed operands that are examined and possibly " 2261062SN/A "removed from graph") 2271062SN/A .prereq(iqSquashedOperandsExamined); 2281062SN/A 2291062SN/A iqSquashedNonSpecRemoved 2301062SN/A .name(name() + ".iqSquashedNonSpecRemoved") 2311062SN/A .desc("Number of squashed non-spec instructions that were removed") 2321062SN/A .prereq(iqSquashedNonSpecRemoved); 2331062SN/A 2342326SN/A queueResDist 2352301SN/A .init(Num_OpClasses, 0, 99, 2) 2362301SN/A .name(name() + ".IQ:residence:") 2372301SN/A .desc("cycles from dispatch to issue") 2382301SN/A .flags(total | pdf | cdf ) 2392301SN/A ; 2402301SN/A for (int i = 0; i < Num_OpClasses; ++i) { 2412326SN/A queueResDist.subname(i, opClassStrings[i]); 2422301SN/A } 2432326SN/A numIssuedDist 2442307SN/A .init(0,totalWidth,1) 2452301SN/A .name(name() + ".ISSUE:issued_per_cycle") 2462301SN/A .desc("Number of insts issued each cycle") 2472307SN/A .flags(pdf) 2482301SN/A ; 2492301SN/A/* 2502301SN/A dist_unissued 2512301SN/A .init(Num_OpClasses+2) 2522301SN/A .name(name() + ".ISSUE:unissued_cause") 2532301SN/A .desc("Reason ready instruction not issued") 2542301SN/A .flags(pdf | dist) 2552301SN/A ; 2562301SN/A for (int i=0; i < (Num_OpClasses + 2); ++i) { 2572301SN/A dist_unissued.subname(i, unissued_names[i]); 2582301SN/A } 2592301SN/A*/ 2602326SN/A statIssuedInstType 2612301SN/A .init(numThreads,Num_OpClasses) 2622301SN/A .name(name() + ".ISSUE:FU_type") 2632301SN/A .desc("Type of FU issued") 2642301SN/A .flags(total | pdf | dist) 2652301SN/A ; 2662326SN/A statIssuedInstType.ysubnames(opClassStrings); 2672301SN/A 2682301SN/A // 2692301SN/A // How long did instructions for a particular FU type wait prior to issue 2702301SN/A // 2712301SN/A 2722326SN/A issueDelayDist 2732301SN/A .init(Num_OpClasses,0,99,2) 2742301SN/A .name(name() + ".ISSUE:") 2752301SN/A .desc("cycles from operands ready to issue") 2762301SN/A .flags(pdf | cdf) 2772301SN/A ; 2782301SN/A 2792301SN/A for (int i=0; i<Num_OpClasses; ++i) { 2802980Sgblack@eecs.umich.edu std::stringstream subname; 2812301SN/A subname << opClassStrings[i] << "_delay"; 2822326SN/A issueDelayDist.subname(i, subname.str()); 2832301SN/A } 2842301SN/A 2852326SN/A issueRate 2862301SN/A .name(name() + ".ISSUE:rate") 2872301SN/A .desc("Inst issue rate") 2882301SN/A .flags(total) 2892301SN/A ; 2902326SN/A issueRate = iqInstsIssued / cpu->numCycles; 2912727Sktlim@umich.edu 2922326SN/A statFuBusy 2932301SN/A .init(Num_OpClasses) 2942301SN/A .name(name() + ".ISSUE:fu_full") 2952301SN/A .desc("attempts to use FU when none available") 2962301SN/A .flags(pdf | dist) 2972301SN/A ; 2982301SN/A for (int i=0; i < Num_OpClasses; ++i) { 2992326SN/A statFuBusy.subname(i, opClassStrings[i]); 3002301SN/A } 3012301SN/A 3022326SN/A fuBusy 3032301SN/A .init(numThreads) 3042301SN/A .name(name() + ".ISSUE:fu_busy_cnt") 3052301SN/A .desc("FU busy when requested") 3062301SN/A .flags(total) 3072301SN/A ; 3082301SN/A 3092326SN/A fuBusyRate 3102301SN/A .name(name() + ".ISSUE:fu_busy_rate") 3112301SN/A .desc("FU busy rate (busy events/executed inst)") 3122301SN/A .flags(total) 3132301SN/A ; 3142326SN/A fuBusyRate = fuBusy / iqInstsIssued; 3152301SN/A 3162292SN/A for ( int i=0; i < numThreads; i++) { 3172292SN/A // Tell mem dependence unit to reg stats as well. 3182292SN/A memDepUnit[i].regStats(); 3192292SN/A } 3201062SN/A} 3211062SN/A 3221062SN/Atemplate <class Impl> 3231062SN/Avoid 3242307SN/AInstructionQueue<Impl>::resetState() 3251060SN/A{ 3262307SN/A //Initialize thread IQ counts 3272307SN/A for (int i = 0; i <numThreads; i++) { 3282307SN/A count[i] = 0; 3292307SN/A instList[i].clear(); 3302307SN/A } 3311060SN/A 3322307SN/A // Initialize the number of free IQ entries. 3332307SN/A freeEntries = numEntries; 3342307SN/A 3352307SN/A // Note that in actuality, the registers corresponding to the logical 3362307SN/A // registers start off as ready. However this doesn't matter for the 3372307SN/A // IQ as the instruction should have been correctly told if those 3382307SN/A // registers are ready in rename. Thus it can all be initialized as 3392307SN/A // unready. 3402307SN/A for (int i = 0; i < numPhysRegs; ++i) { 3412307SN/A regScoreboard[i] = false; 3422307SN/A } 3432307SN/A 3442307SN/A for (int i = 0; i < numThreads; ++i) { 3452307SN/A squashedSeqNum[i] = 0; 3462307SN/A } 3472307SN/A 3482307SN/A for (int i = 0; i < Num_OpClasses; ++i) { 3492307SN/A while (!readyInsts[i].empty()) 3502307SN/A readyInsts[i].pop(); 3512307SN/A queueOnList[i] = false; 3522307SN/A readyIt[i] = listOrder.end(); 3532307SN/A } 3542307SN/A nonSpecInsts.clear(); 3552307SN/A listOrder.clear(); 3561060SN/A} 3571060SN/A 3581061SN/Atemplate <class Impl> 3591060SN/Avoid 3602980Sgblack@eecs.umich.eduInstructionQueue<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 3611060SN/A{ 3622292SN/A DPRINTF(IQ, "Setting active threads list pointer.\n"); 3632292SN/A activeThreads = at_ptr; 3642064SN/A} 3652064SN/A 3662064SN/Atemplate <class Impl> 3672064SN/Avoid 3682292SN/AInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 3692064SN/A{ 3702292SN/A DPRINTF(IQ, "Set the issue to execute queue.\n"); 3711060SN/A issueToExecuteQueue = i2e_ptr; 3721060SN/A} 3731060SN/A 3741061SN/Atemplate <class Impl> 3751060SN/Avoid 3761060SN/AInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3771060SN/A{ 3782292SN/A DPRINTF(IQ, "Set the time buffer.\n"); 3791060SN/A timeBuffer = tb_ptr; 3801060SN/A 3811060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3821060SN/A} 3831060SN/A 3841684SN/Atemplate <class Impl> 3852307SN/Avoid 3862307SN/AInstructionQueue<Impl>::switchOut() 3872307SN/A{ 3882307SN/A resetState(); 3892326SN/A dependGraph.reset(); 3902307SN/A switchedOut = true; 3912307SN/A for (int i = 0; i < numThreads; ++i) { 3922307SN/A memDepUnit[i].switchOut(); 3932307SN/A } 3942307SN/A} 3952307SN/A 3962307SN/Atemplate <class Impl> 3972307SN/Avoid 3982307SN/AInstructionQueue<Impl>::takeOverFrom() 3992307SN/A{ 4002307SN/A switchedOut = false; 4012307SN/A} 4022307SN/A 4032307SN/Atemplate <class Impl> 4042292SN/Aint 4052292SN/AInstructionQueue<Impl>::entryAmount(int num_threads) 4062292SN/A{ 4072292SN/A if (iqPolicy == Partitioned) { 4082292SN/A return numEntries / num_threads; 4092292SN/A } else { 4102292SN/A return 0; 4112292SN/A } 4122292SN/A} 4132292SN/A 4142292SN/A 4152292SN/Atemplate <class Impl> 4162292SN/Avoid 4172292SN/AInstructionQueue<Impl>::resetEntries() 4182292SN/A{ 4192292SN/A if (iqPolicy != Dynamic || numThreads > 1) { 4202292SN/A int active_threads = (*activeThreads).size(); 4212292SN/A 4222980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 4232980Sgblack@eecs.umich.edu std::list<unsigned>::iterator list_end = (*activeThreads).end(); 4242292SN/A 4252292SN/A while (threads != list_end) { 4262292SN/A if (iqPolicy == Partitioned) { 4272292SN/A maxEntries[*threads++] = numEntries / active_threads; 4282292SN/A } else if(iqPolicy == Threshold && active_threads == 1) { 4292292SN/A maxEntries[*threads++] = numEntries; 4302292SN/A } 4312292SN/A } 4322292SN/A } 4332292SN/A} 4342292SN/A 4352292SN/Atemplate <class Impl> 4361684SN/Aunsigned 4371684SN/AInstructionQueue<Impl>::numFreeEntries() 4381684SN/A{ 4391684SN/A return freeEntries; 4401684SN/A} 4411684SN/A 4422292SN/Atemplate <class Impl> 4432292SN/Aunsigned 4442292SN/AInstructionQueue<Impl>::numFreeEntries(unsigned tid) 4452292SN/A{ 4462292SN/A return maxEntries[tid] - count[tid]; 4472292SN/A} 4482292SN/A 4491060SN/A// Might want to do something more complex if it knows how many instructions 4501060SN/A// will be issued this cycle. 4511061SN/Atemplate <class Impl> 4521060SN/Abool 4531060SN/AInstructionQueue<Impl>::isFull() 4541060SN/A{ 4551060SN/A if (freeEntries == 0) { 4561060SN/A return(true); 4571060SN/A } else { 4581060SN/A return(false); 4591060SN/A } 4601060SN/A} 4611060SN/A 4621061SN/Atemplate <class Impl> 4632292SN/Abool 4642292SN/AInstructionQueue<Impl>::isFull(unsigned tid) 4652292SN/A{ 4662292SN/A if (numFreeEntries(tid) == 0) { 4672292SN/A return(true); 4682292SN/A } else { 4692292SN/A return(false); 4702292SN/A } 4712292SN/A} 4722292SN/A 4732292SN/Atemplate <class Impl> 4742292SN/Abool 4752292SN/AInstructionQueue<Impl>::hasReadyInsts() 4762292SN/A{ 4772292SN/A if (!listOrder.empty()) { 4782292SN/A return true; 4792292SN/A } 4802292SN/A 4812292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 4822292SN/A if (!readyInsts[i].empty()) { 4832292SN/A return true; 4842292SN/A } 4852292SN/A } 4862292SN/A 4872292SN/A return false; 4882292SN/A} 4892292SN/A 4902292SN/Atemplate <class Impl> 4911060SN/Avoid 4921061SN/AInstructionQueue<Impl>::insert(DynInstPtr &new_inst) 4931060SN/A{ 4941060SN/A // Make sure the instruction is valid 4951060SN/A assert(new_inst); 4961060SN/A 4972326SN/A DPRINTF(IQ, "Adding instruction [sn:%lli] PC %#x to the IQ.\n", 4982326SN/A new_inst->seqNum, new_inst->readPC()); 4991060SN/A 5001060SN/A assert(freeEntries != 0); 5011060SN/A 5022292SN/A instList[new_inst->threadNumber].push_back(new_inst); 5031060SN/A 5042064SN/A --freeEntries; 5051060SN/A 5062292SN/A new_inst->setInIQ(); 5071060SN/A 5081060SN/A // Look through its source registers (physical regs), and mark any 5091060SN/A // dependencies. 5101060SN/A addToDependents(new_inst); 5111060SN/A 5121060SN/A // Have this instruction set itself as the producer of its destination 5131060SN/A // register(s). 5142326SN/A addToProducers(new_inst); 5151060SN/A 5161061SN/A if (new_inst->isMemRef()) { 5172292SN/A memDepUnit[new_inst->threadNumber].insert(new_inst); 5181062SN/A } else { 5191062SN/A addIfReady(new_inst); 5201061SN/A } 5211061SN/A 5221062SN/A ++iqInstsAdded; 5231060SN/A 5242292SN/A count[new_inst->threadNumber]++; 5252292SN/A 5261060SN/A assert(freeEntries == (numEntries - countInsts())); 5271060SN/A} 5281060SN/A 5291061SN/Atemplate <class Impl> 5301061SN/Avoid 5312292SN/AInstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) 5321061SN/A{ 5331061SN/A // @todo: Clean up this code; can do it by setting inst as unable 5341061SN/A // to issue, then calling normal insert on the inst. 5351061SN/A 5362292SN/A assert(new_inst); 5371061SN/A 5382292SN/A nonSpecInsts[new_inst->seqNum] = new_inst; 5391061SN/A 5402326SN/A DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %#x " 5412326SN/A "to the IQ.\n", 5422326SN/A new_inst->seqNum, new_inst->readPC()); 5432064SN/A 5441061SN/A assert(freeEntries != 0); 5451061SN/A 5462292SN/A instList[new_inst->threadNumber].push_back(new_inst); 5471061SN/A 5482064SN/A --freeEntries; 5491061SN/A 5502292SN/A new_inst->setInIQ(); 5511061SN/A 5521061SN/A // Have this instruction set itself as the producer of its destination 5531061SN/A // register(s). 5542326SN/A addToProducers(new_inst); 5551061SN/A 5561061SN/A // If it's a memory instruction, add it to the memory dependency 5571061SN/A // unit. 5582292SN/A if (new_inst->isMemRef()) { 5592292SN/A memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 5601061SN/A } 5611062SN/A 5621062SN/A ++iqNonSpecInstsAdded; 5632292SN/A 5642292SN/A count[new_inst->threadNumber]++; 5652292SN/A 5662292SN/A assert(freeEntries == (numEntries - countInsts())); 5671061SN/A} 5681061SN/A 5691061SN/Atemplate <class Impl> 5701060SN/Avoid 5712292SN/AInstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) 5721060SN/A{ 5732292SN/A memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 5741060SN/A 5752292SN/A insertNonSpec(barr_inst); 5762292SN/A} 5771060SN/A 5782064SN/Atemplate <class Impl> 5792333SN/Atypename Impl::DynInstPtr 5802333SN/AInstructionQueue<Impl>::getInstToExecute() 5812333SN/A{ 5822333SN/A assert(!instsToExecute.empty()); 5832333SN/A DynInstPtr inst = instsToExecute.front(); 5842333SN/A instsToExecute.pop_front(); 5852333SN/A return inst; 5862333SN/A} 5871060SN/A 5882333SN/Atemplate <class Impl> 5892064SN/Avoid 5902292SN/AInstructionQueue<Impl>::addToOrderList(OpClass op_class) 5912292SN/A{ 5922292SN/A assert(!readyInsts[op_class].empty()); 5932292SN/A 5942292SN/A ListOrderEntry queue_entry; 5952292SN/A 5962292SN/A queue_entry.queueType = op_class; 5972292SN/A 5982292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 5992292SN/A 6002292SN/A ListOrderIt list_it = listOrder.begin(); 6012292SN/A ListOrderIt list_end_it = listOrder.end(); 6022292SN/A 6032292SN/A while (list_it != list_end_it) { 6042292SN/A if ((*list_it).oldestInst > queue_entry.oldestInst) { 6052292SN/A break; 6062292SN/A } 6072292SN/A 6082292SN/A list_it++; 6091060SN/A } 6101060SN/A 6112292SN/A readyIt[op_class] = listOrder.insert(list_it, queue_entry); 6122292SN/A queueOnList[op_class] = true; 6132292SN/A} 6141060SN/A 6152292SN/Atemplate <class Impl> 6162292SN/Avoid 6172292SN/AInstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 6182292SN/A{ 6192292SN/A // Get iterator of next item on the list 6202292SN/A // Delete the original iterator 6212292SN/A // Determine if the next item is either the end of the list or younger 6222292SN/A // than the new instruction. If so, then add in a new iterator right here. 6232292SN/A // If not, then move along. 6242292SN/A ListOrderEntry queue_entry; 6252292SN/A OpClass op_class = (*list_order_it).queueType; 6262292SN/A ListOrderIt next_it = list_order_it; 6272292SN/A 6282292SN/A ++next_it; 6292292SN/A 6302292SN/A queue_entry.queueType = op_class; 6312292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 6322292SN/A 6332292SN/A while (next_it != listOrder.end() && 6342292SN/A (*next_it).oldestInst < queue_entry.oldestInst) { 6352292SN/A ++next_it; 6361060SN/A } 6371060SN/A 6382292SN/A readyIt[op_class] = listOrder.insert(next_it, queue_entry); 6391060SN/A} 6401060SN/A 6412292SN/Atemplate <class Impl> 6422292SN/Avoid 6432292SN/AInstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 6442292SN/A{ 6452292SN/A // The CPU could have been sleeping until this op completed (*extremely* 6462292SN/A // long latency op). Wake it if it was. This may be overkill. 6472307SN/A if (isSwitchedOut()) { 6482307SN/A return; 6492307SN/A } 6502307SN/A 6512292SN/A iewStage->wakeCPU(); 6522292SN/A 6532326SN/A if (fu_idx > -1) 6542326SN/A fuPool->freeUnitNextCycle(fu_idx); 6552292SN/A 6562326SN/A // @todo: Ensure that these FU Completions happen at the beginning 6572326SN/A // of a cycle, otherwise they could add too many instructions to 6582326SN/A // the queue. 6592333SN/A issueToExecuteQueue->access(0)->size++; 6602333SN/A instsToExecute.push_back(inst); 6612292SN/A} 6622292SN/A 6631061SN/A// @todo: Figure out a better way to remove the squashed items from the 6641061SN/A// lists. Checking the top item of each list to see if it's squashed 6651061SN/A// wastes time and forces jumps. 6661061SN/Atemplate <class Impl> 6671060SN/Avoid 6681060SN/AInstructionQueue<Impl>::scheduleReadyInsts() 6691060SN/A{ 6702292SN/A DPRINTF(IQ, "Attempting to schedule ready instructions from " 6712292SN/A "the IQ.\n"); 6721060SN/A 6731060SN/A IssueStruct *i2e_info = issueToExecuteQueue->access(0); 6741060SN/A 6752292SN/A // Have iterator to head of the list 6762292SN/A // While I haven't exceeded bandwidth or reached the end of the list, 6772292SN/A // Try to get a FU that can do what this op needs. 6782292SN/A // If successful, change the oldestInst to the new top of the list, put 6792292SN/A // the queue in the proper place in the list. 6802292SN/A // Increment the iterator. 6812292SN/A // This will avoid trying to schedule a certain op class if there are no 6822292SN/A // FUs that handle it. 6832292SN/A ListOrderIt order_it = listOrder.begin(); 6842292SN/A ListOrderIt order_end_it = listOrder.end(); 6852292SN/A int total_issued = 0; 6861060SN/A 6872333SN/A while (total_issued < totalWidth && 6882820Sktlim@umich.edu iewStage->canIssue() && 6892326SN/A order_it != order_end_it) { 6902292SN/A OpClass op_class = (*order_it).queueType; 6911060SN/A 6922292SN/A assert(!readyInsts[op_class].empty()); 6931060SN/A 6942292SN/A DynInstPtr issuing_inst = readyInsts[op_class].top(); 6951060SN/A 6962292SN/A assert(issuing_inst->seqNum == (*order_it).oldestInst); 6971060SN/A 6982292SN/A if (issuing_inst->isSquashed()) { 6992292SN/A readyInsts[op_class].pop(); 7001060SN/A 7012292SN/A if (!readyInsts[op_class].empty()) { 7022292SN/A moveToYoungerInst(order_it); 7032292SN/A } else { 7042292SN/A readyIt[op_class] = listOrder.end(); 7052292SN/A queueOnList[op_class] = false; 7061060SN/A } 7071060SN/A 7082292SN/A listOrder.erase(order_it++); 7091060SN/A 7102292SN/A ++iqSquashedInstsIssued; 7112292SN/A 7122292SN/A continue; 7131060SN/A } 7141060SN/A 7152326SN/A int idx = -2; 7162326SN/A int op_latency = 1; 7172301SN/A int tid = issuing_inst->threadNumber; 7181060SN/A 7192326SN/A if (op_class != No_OpClass) { 7202326SN/A idx = fuPool->getUnit(op_class); 7211060SN/A 7222326SN/A if (idx > -1) { 7232326SN/A op_latency = fuPool->getOpLatency(op_class); 7241060SN/A } 7251060SN/A } 7261060SN/A 7272348SN/A // If we have an instruction that doesn't require a FU, or a 7282348SN/A // valid FU, then schedule for execution. 7292326SN/A if (idx == -2 || idx != -1) { 7302292SN/A if (op_latency == 1) { 7312292SN/A i2e_info->size++; 7322333SN/A instsToExecute.push_back(issuing_inst); 7331060SN/A 7342326SN/A // Add the FU onto the list of FU's to be freed next 7352326SN/A // cycle if we used one. 7362326SN/A if (idx >= 0) 7372326SN/A fuPool->freeUnitNextCycle(idx); 7382292SN/A } else { 7392292SN/A int issue_latency = fuPool->getIssueLatency(op_class); 7402326SN/A // Generate completion event for the FU 7412326SN/A FUCompletion *execution = new FUCompletion(issuing_inst, 7422326SN/A idx, this); 7431060SN/A 7442326SN/A execution->schedule(curTick + cpu->cycles(issue_latency - 1)); 7451060SN/A 7462326SN/A // @todo: Enforce that issue_latency == 1 or op_latency 7472292SN/A if (issue_latency > 1) { 7482348SN/A // If FU isn't pipelined, then it must be freed 7492348SN/A // upon the execution completing. 7502326SN/A execution->setFreeFU(); 7512292SN/A } else { 7522292SN/A // Add the FU onto the list of FU's to be freed next cycle. 7532326SN/A fuPool->freeUnitNextCycle(idx); 7542292SN/A } 7551060SN/A } 7561060SN/A 7572292SN/A DPRINTF(IQ, "Thread %i: Issuing instruction PC %#x " 7582292SN/A "[sn:%lli]\n", 7592301SN/A tid, issuing_inst->readPC(), 7602292SN/A issuing_inst->seqNum); 7611060SN/A 7622292SN/A readyInsts[op_class].pop(); 7631061SN/A 7642292SN/A if (!readyInsts[op_class].empty()) { 7652292SN/A moveToYoungerInst(order_it); 7662292SN/A } else { 7672292SN/A readyIt[op_class] = listOrder.end(); 7682292SN/A queueOnList[op_class] = false; 7691060SN/A } 7701060SN/A 7712064SN/A issuing_inst->setIssued(); 7722292SN/A ++total_issued; 7732064SN/A 7742292SN/A if (!issuing_inst->isMemRef()) { 7752292SN/A // Memory instructions can not be freed from the IQ until they 7762292SN/A // complete. 7772292SN/A ++freeEntries; 7782301SN/A count[tid]--; 7792731Sktlim@umich.edu issuing_inst->clearInIQ(); 7802292SN/A } else { 7812301SN/A memDepUnit[tid].issue(issuing_inst); 7822292SN/A } 7832292SN/A 7842292SN/A listOrder.erase(order_it++); 7852326SN/A statIssuedInstType[tid][op_class]++; 7862820Sktlim@umich.edu iewStage->incrWb(issuing_inst->seqNum); 7872292SN/A } else { 7882326SN/A statFuBusy[op_class]++; 7892326SN/A fuBusy[tid]++; 7902292SN/A ++order_it; 7911060SN/A } 7921060SN/A } 7931062SN/A 7942326SN/A numIssuedDist.sample(total_issued); 7952326SN/A iqInstsIssued+= total_issued; 7962307SN/A 7972348SN/A // If we issued any instructions, tell the CPU we had activity. 7982292SN/A if (total_issued) { 7992292SN/A cpu->activityThisCycle(); 8002292SN/A } else { 8012292SN/A DPRINTF(IQ, "Not able to schedule any instructions.\n"); 8022292SN/A } 8031060SN/A} 8041060SN/A 8051061SN/Atemplate <class Impl> 8061060SN/Avoid 8071061SN/AInstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 8081060SN/A{ 8092292SN/A DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 8102292SN/A "to execute.\n", inst); 8111062SN/A 8122292SN/A NonSpecMapIt inst_it = nonSpecInsts.find(inst); 8131060SN/A 8141061SN/A assert(inst_it != nonSpecInsts.end()); 8151060SN/A 8162292SN/A unsigned tid = (*inst_it).second->threadNumber; 8172292SN/A 8181061SN/A (*inst_it).second->setCanIssue(); 8191060SN/A 8201062SN/A if (!(*inst_it).second->isMemRef()) { 8211062SN/A addIfReady((*inst_it).second); 8221062SN/A } else { 8232292SN/A memDepUnit[tid].nonSpecInstReady((*inst_it).second); 8241062SN/A } 8251060SN/A 8262292SN/A (*inst_it).second = NULL; 8272292SN/A 8281061SN/A nonSpecInsts.erase(inst_it); 8291060SN/A} 8301060SN/A 8311061SN/Atemplate <class Impl> 8321061SN/Avoid 8332292SN/AInstructionQueue<Impl>::commit(const InstSeqNum &inst, unsigned tid) 8342292SN/A{ 8352292SN/A DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 8362292SN/A tid,inst); 8372292SN/A 8382292SN/A ListIt iq_it = instList[tid].begin(); 8392292SN/A 8402292SN/A while (iq_it != instList[tid].end() && 8412292SN/A (*iq_it)->seqNum <= inst) { 8422292SN/A ++iq_it; 8432292SN/A instList[tid].pop_front(); 8442292SN/A } 8452292SN/A 8462292SN/A assert(freeEntries == (numEntries - countInsts())); 8472292SN/A} 8482292SN/A 8492292SN/Atemplate <class Impl> 8502301SN/Aint 8511684SN/AInstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 8521684SN/A{ 8532301SN/A int dependents = 0; 8542301SN/A 8552292SN/A DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 8562292SN/A 8572292SN/A assert(!completed_inst->isSquashed()); 8581684SN/A 8591684SN/A // Tell the memory dependence unit to wake any dependents on this 8602292SN/A // instruction if it is a memory instruction. Also complete the memory 8612326SN/A // instruction at this point since we know it executed without issues. 8622326SN/A // @todo: Might want to rename "completeMemInst" to something that 8632326SN/A // indicates that it won't need to be replayed, and call this 8642326SN/A // earlier. Might not be a big deal. 8651684SN/A if (completed_inst->isMemRef()) { 8662292SN/A memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 8672292SN/A completeMemInst(completed_inst); 8682292SN/A } else if (completed_inst->isMemBarrier() || 8692292SN/A completed_inst->isWriteBarrier()) { 8702292SN/A memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 8711684SN/A } 8721684SN/A 8731684SN/A for (int dest_reg_idx = 0; 8741684SN/A dest_reg_idx < completed_inst->numDestRegs(); 8751684SN/A dest_reg_idx++) 8761684SN/A { 8771684SN/A PhysRegIndex dest_reg = 8781684SN/A completed_inst->renamedDestRegIdx(dest_reg_idx); 8791684SN/A 8801684SN/A // Special case of uniq or control registers. They are not 8811684SN/A // handled by the IQ and thus have no dependency graph entry. 8821684SN/A // @todo Figure out a cleaner way to handle this. 8831684SN/A if (dest_reg >= numPhysRegs) { 8841684SN/A continue; 8851684SN/A } 8861684SN/A 8872292SN/A DPRINTF(IQ, "Waking any dependents on register %i.\n", 8881684SN/A (int) dest_reg); 8891684SN/A 8902326SN/A //Go through the dependency chain, marking the registers as 8912326SN/A //ready within the waiting instructions. 8922326SN/A DynInstPtr dep_inst = dependGraph.pop(dest_reg); 8931684SN/A 8942326SN/A while (dep_inst) { 8952292SN/A DPRINTF(IQ, "Waking up a dependent instruction, PC%#x.\n", 8962326SN/A dep_inst->readPC()); 8971684SN/A 8981684SN/A // Might want to give more information to the instruction 8992326SN/A // so that it knows which of its source registers is 9002326SN/A // ready. However that would mean that the dependency 9012326SN/A // graph entries would need to hold the src_reg_idx. 9022326SN/A dep_inst->markSrcRegReady(); 9031684SN/A 9042326SN/A addIfReady(dep_inst); 9051684SN/A 9062326SN/A dep_inst = dependGraph.pop(dest_reg); 9071684SN/A 9082301SN/A ++dependents; 9091684SN/A } 9101684SN/A 9112326SN/A // Reset the head node now that all of its dependents have 9122326SN/A // been woken up. 9132326SN/A assert(dependGraph.empty(dest_reg)); 9142326SN/A dependGraph.clearInst(dest_reg); 9151684SN/A 9161684SN/A // Mark the scoreboard as having that register ready. 9171684SN/A regScoreboard[dest_reg] = true; 9181684SN/A } 9192301SN/A return dependents; 9202064SN/A} 9212064SN/A 9222064SN/Atemplate <class Impl> 9232064SN/Avoid 9242292SN/AInstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 9252064SN/A{ 9262292SN/A OpClass op_class = ready_inst->opClass(); 9272292SN/A 9282292SN/A readyInsts[op_class].push(ready_inst); 9292292SN/A 9302326SN/A // Will need to reorder the list if either a queue is not on the list, 9312326SN/A // or it has an older instruction than last time. 9322326SN/A if (!queueOnList[op_class]) { 9332326SN/A addToOrderList(op_class); 9342326SN/A } else if (readyInsts[op_class].top()->seqNum < 9352326SN/A (*readyIt[op_class]).oldestInst) { 9362326SN/A listOrder.erase(readyIt[op_class]); 9372326SN/A addToOrderList(op_class); 9382326SN/A } 9392326SN/A 9402292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 9412292SN/A "the ready list, PC %#x opclass:%i [sn:%lli].\n", 9422292SN/A ready_inst->readPC(), op_class, ready_inst->seqNum); 9432064SN/A} 9442064SN/A 9452064SN/Atemplate <class Impl> 9462064SN/Avoid 9472292SN/AInstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 9482064SN/A{ 9492292SN/A memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 9502064SN/A} 9512064SN/A 9522064SN/Atemplate <class Impl> 9532064SN/Avoid 9542292SN/AInstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 9552064SN/A{ 9562292SN/A memDepUnit[replay_inst->threadNumber].replay(replay_inst); 9572292SN/A} 9582292SN/A 9592292SN/Atemplate <class Impl> 9602292SN/Avoid 9612292SN/AInstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 9622292SN/A{ 9632292SN/A int tid = completed_inst->threadNumber; 9642292SN/A 9652292SN/A DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n", 9662292SN/A completed_inst->readPC(), completed_inst->seqNum); 9672292SN/A 9682292SN/A ++freeEntries; 9692292SN/A 9702292SN/A completed_inst->memOpDone = true; 9712292SN/A 9722292SN/A memDepUnit[tid].completed(completed_inst); 9732292SN/A 9742292SN/A count[tid]--; 9751684SN/A} 9761684SN/A 9771684SN/Atemplate <class Impl> 9781684SN/Avoid 9791061SN/AInstructionQueue<Impl>::violation(DynInstPtr &store, 9801061SN/A DynInstPtr &faulting_load) 9811061SN/A{ 9822292SN/A memDepUnit[store->threadNumber].violation(store, faulting_load); 9831061SN/A} 9841061SN/A 9851061SN/Atemplate <class Impl> 9861060SN/Avoid 9872292SN/AInstructionQueue<Impl>::squash(unsigned tid) 9881060SN/A{ 9892292SN/A DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 9902292SN/A "the IQ.\n", tid); 9911060SN/A 9921060SN/A // Read instruction sequence number of last instruction out of the 9931060SN/A // time buffer. 9943093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 9953093Sksewell@umich.edu squashedSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum; 9963093Sksewell@umich.edu#else 9972292SN/A squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 9982935Sksewell@umich.edu#endif 9991060SN/A 10001681SN/A // Call doSquash if there are insts in the IQ 10012292SN/A if (count[tid] > 0) { 10022292SN/A doSquash(tid); 10031681SN/A } 10041061SN/A 10051061SN/A // Also tell the memory dependence unit to squash. 10062292SN/A memDepUnit[tid].squash(squashedSeqNum[tid], tid); 10071060SN/A} 10081060SN/A 10091061SN/Atemplate <class Impl> 10101061SN/Avoid 10112292SN/AInstructionQueue<Impl>::doSquash(unsigned tid) 10121061SN/A{ 10132326SN/A // Start at the tail. 10142326SN/A ListIt squash_it = instList[tid].end(); 10152326SN/A --squash_it; 10161061SN/A 10172292SN/A DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 10182292SN/A tid, squashedSeqNum[tid]); 10191061SN/A 10201061SN/A // Squash any instructions younger than the squashed sequence number 10211061SN/A // given. 10222326SN/A while (squash_it != instList[tid].end() && 10232326SN/A (*squash_it)->seqNum > squashedSeqNum[tid]) { 10242292SN/A 10252326SN/A DynInstPtr squashed_inst = (*squash_it); 10261061SN/A 10271061SN/A // Only handle the instruction if it actually is in the IQ and 10281061SN/A // hasn't already been squashed in the IQ. 10292292SN/A if (squashed_inst->threadNumber != tid || 10302292SN/A squashed_inst->isSquashedInIQ()) { 10312326SN/A --squash_it; 10322292SN/A continue; 10332292SN/A } 10342292SN/A 10352292SN/A if (!squashed_inst->isIssued() || 10362292SN/A (squashed_inst->isMemRef() && 10372292SN/A !squashed_inst->memOpDone)) { 10381062SN/A 10391061SN/A // Remove the instruction from the dependency list. 10402292SN/A if (!squashed_inst->isNonSpeculative() && 10412336SN/A !squashed_inst->isStoreConditional() && 10422292SN/A !squashed_inst->isMemBarrier() && 10432292SN/A !squashed_inst->isWriteBarrier()) { 10441061SN/A 10451061SN/A for (int src_reg_idx = 0; 10461681SN/A src_reg_idx < squashed_inst->numSrcRegs(); 10471061SN/A src_reg_idx++) 10481061SN/A { 10491061SN/A PhysRegIndex src_reg = 10501061SN/A squashed_inst->renamedSrcRegIdx(src_reg_idx); 10511061SN/A 10522326SN/A // Only remove it from the dependency graph if it 10532326SN/A // was placed there in the first place. 10542326SN/A 10552326SN/A // Instead of doing a linked list traversal, we 10562326SN/A // can just remove these squashed instructions 10572326SN/A // either at issue time, or when the register is 10582326SN/A // overwritten. The only downside to this is it 10592326SN/A // leaves more room for error. 10602292SN/A 10611061SN/A if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 10621061SN/A src_reg < numPhysRegs) { 10632326SN/A dependGraph.remove(src_reg, squashed_inst); 10641061SN/A } 10651062SN/A 10662292SN/A 10671062SN/A ++iqSquashedOperandsExamined; 10681061SN/A } 10692064SN/A } else { 10702292SN/A NonSpecMapIt ns_inst_it = 10712292SN/A nonSpecInsts.find(squashed_inst->seqNum); 10722292SN/A assert(ns_inst_it != nonSpecInsts.end()); 10731062SN/A 10742292SN/A (*ns_inst_it).second = NULL; 10751681SN/A 10762292SN/A nonSpecInsts.erase(ns_inst_it); 10771062SN/A 10781062SN/A ++iqSquashedNonSpecRemoved; 10791061SN/A } 10801061SN/A 10811061SN/A // Might want to also clear out the head of the dependency graph. 10821061SN/A 10831061SN/A // Mark it as squashed within the IQ. 10841061SN/A squashed_inst->setSquashedInIQ(); 10851061SN/A 10862292SN/A // @todo: Remove this hack where several statuses are set so the 10872292SN/A // inst will flow through the rest of the pipeline. 10881681SN/A squashed_inst->setIssued(); 10891681SN/A squashed_inst->setCanCommit(); 10902731Sktlim@umich.edu squashed_inst->clearInIQ(); 10912292SN/A 10922292SN/A //Update Thread IQ Count 10932292SN/A count[squashed_inst->threadNumber]--; 10941681SN/A 10951681SN/A ++freeEntries; 10961061SN/A 10972326SN/A DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x " 10982326SN/A "squashed.\n", 10992326SN/A tid, squashed_inst->seqNum, squashed_inst->readPC()); 11001061SN/A } 11011061SN/A 11022326SN/A instList[tid].erase(squash_it--); 11031062SN/A ++iqSquashedInstsExamined; 11041061SN/A } 11051060SN/A} 11061060SN/A 11071061SN/Atemplate <class Impl> 11081060SN/Abool 11091061SN/AInstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 11101060SN/A{ 11111060SN/A // Loop through the instruction's source registers, adding 11121060SN/A // them to the dependency list if they are not ready. 11131060SN/A int8_t total_src_regs = new_inst->numSrcRegs(); 11141060SN/A bool return_val = false; 11151060SN/A 11161060SN/A for (int src_reg_idx = 0; 11171060SN/A src_reg_idx < total_src_regs; 11181060SN/A src_reg_idx++) 11191060SN/A { 11201060SN/A // Only add it to the dependency graph if it's not ready. 11211060SN/A if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 11221060SN/A PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 11231060SN/A 11241060SN/A // Check the IQ's scoreboard to make sure the register 11251060SN/A // hasn't become ready while the instruction was in flight 11261060SN/A // between stages. Only if it really isn't ready should 11271060SN/A // it be added to the dependency graph. 11281061SN/A if (src_reg >= numPhysRegs) { 11291061SN/A continue; 11301061SN/A } else if (regScoreboard[src_reg] == false) { 11312292SN/A DPRINTF(IQ, "Instruction PC %#x has src reg %i that " 11321060SN/A "is being added to the dependency chain.\n", 11331060SN/A new_inst->readPC(), src_reg); 11341060SN/A 11352326SN/A dependGraph.insert(src_reg, new_inst); 11361060SN/A 11371060SN/A // Change the return value to indicate that something 11381060SN/A // was added to the dependency graph. 11391060SN/A return_val = true; 11401060SN/A } else { 11412292SN/A DPRINTF(IQ, "Instruction PC %#x has src reg %i that " 11421060SN/A "became ready before it reached the IQ.\n", 11431060SN/A new_inst->readPC(), src_reg); 11441060SN/A // Mark a register ready within the instruction. 11452326SN/A new_inst->markSrcRegReady(src_reg_idx); 11461060SN/A } 11471060SN/A } 11481060SN/A } 11491060SN/A 11501060SN/A return return_val; 11511060SN/A} 11521060SN/A 11531061SN/Atemplate <class Impl> 11541060SN/Avoid 11552326SN/AInstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) 11561060SN/A{ 11572326SN/A // Nothing really needs to be marked when an instruction becomes 11582326SN/A // the producer of a register's value, but for convenience a ptr 11592326SN/A // to the producing instruction will be placed in the head node of 11602326SN/A // the dependency links. 11611060SN/A int8_t total_dest_regs = new_inst->numDestRegs(); 11621060SN/A 11631060SN/A for (int dest_reg_idx = 0; 11641060SN/A dest_reg_idx < total_dest_regs; 11651060SN/A dest_reg_idx++) 11661060SN/A { 11671061SN/A PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 11681061SN/A 11691061SN/A // Instructions that use the misc regs will have a reg number 11701061SN/A // higher than the normal physical registers. In this case these 11711061SN/A // registers are not renamed, and there is no need to track 11721061SN/A // dependencies as these instructions must be executed at commit. 11731061SN/A if (dest_reg >= numPhysRegs) { 11741061SN/A continue; 11751060SN/A } 11761060SN/A 11772326SN/A if (!dependGraph.empty(dest_reg)) { 11782326SN/A dependGraph.dump(); 11792292SN/A panic("Dependency graph %i not empty!", dest_reg); 11802064SN/A } 11811062SN/A 11822326SN/A dependGraph.setInst(dest_reg, new_inst); 11831062SN/A 11841060SN/A // Mark the scoreboard to say it's not yet ready. 11851060SN/A regScoreboard[dest_reg] = false; 11861060SN/A } 11871060SN/A} 11881060SN/A 11891061SN/Atemplate <class Impl> 11901060SN/Avoid 11911061SN/AInstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 11921060SN/A{ 11932326SN/A // If the instruction now has all of its source registers 11941060SN/A // available, then add it to the list of ready instructions. 11951060SN/A if (inst->readyToIssue()) { 11961061SN/A 11971060SN/A //Add the instruction to the proper ready list. 11982292SN/A if (inst->isMemRef()) { 11991061SN/A 12002292SN/A DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 12011061SN/A 12021062SN/A // Message to the mem dependence unit that this instruction has 12031062SN/A // its registers ready. 12042292SN/A memDepUnit[inst->threadNumber].regsReady(inst); 12051062SN/A 12062292SN/A return; 12072292SN/A } 12081062SN/A 12092292SN/A OpClass op_class = inst->opClass(); 12101061SN/A 12112292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 12122292SN/A "the ready list, PC %#x opclass:%i [sn:%lli].\n", 12132292SN/A inst->readPC(), op_class, inst->seqNum); 12141061SN/A 12152292SN/A readyInsts[op_class].push(inst); 12161061SN/A 12172326SN/A // Will need to reorder the list if either a queue is not on the list, 12182326SN/A // or it has an older instruction than last time. 12192326SN/A if (!queueOnList[op_class]) { 12202326SN/A addToOrderList(op_class); 12212326SN/A } else if (readyInsts[op_class].top()->seqNum < 12222326SN/A (*readyIt[op_class]).oldestInst) { 12232326SN/A listOrder.erase(readyIt[op_class]); 12242326SN/A addToOrderList(op_class); 12251060SN/A } 12261060SN/A } 12271060SN/A} 12281060SN/A 12291061SN/Atemplate <class Impl> 12301061SN/Aint 12311061SN/AInstructionQueue<Impl>::countInsts() 12321061SN/A{ 12332698Sktlim@umich.edu#if 0 12342292SN/A //ksewell:This works but definitely could use a cleaner write 12352292SN/A //with a more intuitive way of counting. Right now it's 12362292SN/A //just brute force .... 12372698Sktlim@umich.edu // Change the #if if you want to use this method. 12381061SN/A int total_insts = 0; 12391061SN/A 12402292SN/A for (int i = 0; i < numThreads; ++i) { 12412292SN/A ListIt count_it = instList[i].begin(); 12421681SN/A 12432292SN/A while (count_it != instList[i].end()) { 12442292SN/A if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 12452292SN/A if (!(*count_it)->isIssued()) { 12462292SN/A ++total_insts; 12472292SN/A } else if ((*count_it)->isMemRef() && 12482292SN/A !(*count_it)->memOpDone) { 12492292SN/A // Loads that have not been marked as executed still count 12502292SN/A // towards the total instructions. 12512292SN/A ++total_insts; 12522292SN/A } 12532292SN/A } 12542292SN/A 12552292SN/A ++count_it; 12561061SN/A } 12571061SN/A } 12581061SN/A 12591061SN/A return total_insts; 12602292SN/A#else 12612292SN/A return numEntries - freeEntries; 12622292SN/A#endif 12631681SN/A} 12641681SN/A 12651681SN/Atemplate <class Impl> 12661681SN/Avoid 12671061SN/AInstructionQueue<Impl>::dumpLists() 12681061SN/A{ 12692292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 12702292SN/A cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 12711061SN/A 12722292SN/A cprintf("\n"); 12732292SN/A } 12741061SN/A 12751061SN/A cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 12761061SN/A 12772292SN/A NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 12782292SN/A NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 12791061SN/A 12801061SN/A cprintf("Non speculative list: "); 12811061SN/A 12822292SN/A while (non_spec_it != non_spec_end_it) { 12832292SN/A cprintf("%#x [sn:%lli]", (*non_spec_it).second->readPC(), 12842292SN/A (*non_spec_it).second->seqNum); 12851061SN/A ++non_spec_it; 12861061SN/A } 12871061SN/A 12881061SN/A cprintf("\n"); 12891061SN/A 12902292SN/A ListOrderIt list_order_it = listOrder.begin(); 12912292SN/A ListOrderIt list_order_end_it = listOrder.end(); 12922292SN/A int i = 1; 12932292SN/A 12942292SN/A cprintf("List order: "); 12952292SN/A 12962292SN/A while (list_order_it != list_order_end_it) { 12972292SN/A cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 12982292SN/A (*list_order_it).oldestInst); 12992292SN/A 13002292SN/A ++list_order_it; 13012292SN/A ++i; 13022292SN/A } 13032292SN/A 13042292SN/A cprintf("\n"); 13051061SN/A} 13062292SN/A 13072292SN/A 13082292SN/Atemplate <class Impl> 13092292SN/Avoid 13102292SN/AInstructionQueue<Impl>::dumpInsts() 13112292SN/A{ 13122292SN/A for (int i = 0; i < numThreads; ++i) { 13132292SN/A int num = 0; 13142292SN/A int valid_num = 0; 13152292SN/A ListIt inst_list_it = instList[i].begin(); 13162292SN/A 13172292SN/A while (inst_list_it != instList[i].end()) 13182292SN/A { 13192292SN/A cprintf("Instruction:%i\n", 13202292SN/A num); 13212292SN/A if (!(*inst_list_it)->isSquashed()) { 13222292SN/A if (!(*inst_list_it)->isIssued()) { 13232292SN/A ++valid_num; 13242292SN/A cprintf("Count:%i\n", valid_num); 13252292SN/A } else if ((*inst_list_it)->isMemRef() && 13262292SN/A !(*inst_list_it)->memOpDone) { 13272326SN/A // Loads that have not been marked as executed 13282326SN/A // still count towards the total instructions. 13292292SN/A ++valid_num; 13302292SN/A cprintf("Count:%i\n", valid_num); 13312292SN/A } 13322292SN/A } 13332292SN/A 13342292SN/A cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n" 13352292SN/A "Issued:%i\nSquashed:%i\n", 13362292SN/A (*inst_list_it)->readPC(), 13372292SN/A (*inst_list_it)->seqNum, 13382292SN/A (*inst_list_it)->threadNumber, 13392292SN/A (*inst_list_it)->isIssued(), 13402292SN/A (*inst_list_it)->isSquashed()); 13412292SN/A 13422292SN/A if ((*inst_list_it)->isMemRef()) { 13432292SN/A cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 13442292SN/A } 13452292SN/A 13462292SN/A cprintf("\n"); 13472292SN/A 13482292SN/A inst_list_it++; 13492292SN/A ++num; 13502292SN/A } 13512292SN/A } 13522348SN/A 13532348SN/A cprintf("Insts to Execute list:\n"); 13542348SN/A 13552348SN/A int num = 0; 13562348SN/A int valid_num = 0; 13572348SN/A ListIt inst_list_it = instsToExecute.begin(); 13582348SN/A 13592348SN/A while (inst_list_it != instsToExecute.end()) 13602348SN/A { 13612348SN/A cprintf("Instruction:%i\n", 13622348SN/A num); 13632348SN/A if (!(*inst_list_it)->isSquashed()) { 13642348SN/A if (!(*inst_list_it)->isIssued()) { 13652348SN/A ++valid_num; 13662348SN/A cprintf("Count:%i\n", valid_num); 13672348SN/A } else if ((*inst_list_it)->isMemRef() && 13682348SN/A !(*inst_list_it)->memOpDone) { 13692348SN/A // Loads that have not been marked as executed 13702348SN/A // still count towards the total instructions. 13712348SN/A ++valid_num; 13722348SN/A cprintf("Count:%i\n", valid_num); 13732348SN/A } 13742348SN/A } 13752348SN/A 13762348SN/A cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n" 13772348SN/A "Issued:%i\nSquashed:%i\n", 13782348SN/A (*inst_list_it)->readPC(), 13792348SN/A (*inst_list_it)->seqNum, 13802348SN/A (*inst_list_it)->threadNumber, 13812348SN/A (*inst_list_it)->isIssued(), 13822348SN/A (*inst_list_it)->isSquashed()); 13832348SN/A 13842348SN/A if ((*inst_list_it)->isMemRef()) { 13852348SN/A cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 13862348SN/A } 13872348SN/A 13882348SN/A cprintf("\n"); 13892348SN/A 13902348SN/A inst_list_it++; 13912348SN/A ++num; 13922348SN/A } 13932292SN/A} 1394