inst_queue_impl.hh revision 14025
111251Sradhika.jagtap@ARM.com/* 211251Sradhika.jagtap@ARM.com * Copyright (c) 2011-2014, 2017-2019 ARM Limited 311251Sradhika.jagtap@ARM.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 411251Sradhika.jagtap@ARM.com * All rights reserved. 511251Sradhika.jagtap@ARM.com * 611251Sradhika.jagtap@ARM.com * The license below extends only to copyright in the software and shall 711251Sradhika.jagtap@ARM.com * not be construed as granting a license to any other intellectual 811251Sradhika.jagtap@ARM.com * property including but not limited to intellectual property relating 911251Sradhika.jagtap@ARM.com * to a hardware implementation of the functionality of the software 1011251Sradhika.jagtap@ARM.com * licensed hereunder. You may use the software subject to the license 1111251Sradhika.jagtap@ARM.com * terms below provided that you ensure that this notice is replicated 1211251Sradhika.jagtap@ARM.com * unmodified and in its entirety in all distributions of the software, 1311251Sradhika.jagtap@ARM.com * modified or unmodified, in source code or in binary form. 1411251Sradhika.jagtap@ARM.com * 1511251Sradhika.jagtap@ARM.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 1611251Sradhika.jagtap@ARM.com * All rights reserved. 1711251Sradhika.jagtap@ARM.com * 1811251Sradhika.jagtap@ARM.com * Redistribution and use in source and binary forms, with or without 1911251Sradhika.jagtap@ARM.com * modification, are permitted provided that the following conditions are 2011251Sradhika.jagtap@ARM.com * met: redistributions of source code must retain the above copyright 2111251Sradhika.jagtap@ARM.com * notice, this list of conditions and the following disclaimer; 2211251Sradhika.jagtap@ARM.com * redistributions in binary form must reproduce the above copyright 2311251Sradhika.jagtap@ARM.com * notice, this list of conditions and the following disclaimer in the 2411251Sradhika.jagtap@ARM.com * documentation and/or other materials provided with the distribution; 2511251Sradhika.jagtap@ARM.com * neither the name of the copyright holders nor the names of its 2611251Sradhika.jagtap@ARM.com * contributors may be used to endorse or promote products derived from 2711251Sradhika.jagtap@ARM.com * this software without specific prior written permission. 2811251Sradhika.jagtap@ARM.com * 2911251Sradhika.jagtap@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3011251Sradhika.jagtap@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3111251Sradhika.jagtap@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3211251Sradhika.jagtap@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3311251Sradhika.jagtap@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3411251Sradhika.jagtap@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3511251Sradhika.jagtap@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3611251Sradhika.jagtap@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3711251Sradhika.jagtap@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3811251Sradhika.jagtap@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3911251Sradhika.jagtap@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4012564Sgabeblack@google.com * 4113774Sandreas.sandberg@arm.com * Authors: Kevin Lim 4212564Sgabeblack@google.com * Korey Sewell 4311251Sradhika.jagtap@ARM.com */ 4411251Sradhika.jagtap@ARM.com 4511251Sradhika.jagtap@ARM.com#ifndef __CPU_O3_INST_QUEUE_IMPL_HH__ 4611251Sradhika.jagtap@ARM.com#define __CPU_O3_INST_QUEUE_IMPL_HH__ 4711682Sandreas.hansson@arm.com 4811251Sradhika.jagtap@ARM.com#include <limits> 4911682Sandreas.hansson@arm.com#include <vector> 5011682Sandreas.hansson@arm.com 5111682Sandreas.hansson@arm.com#include "base/logging.hh" 5211682Sandreas.hansson@arm.com#include "cpu/o3/fu_pool.hh" 5311682Sandreas.hansson@arm.com#include "cpu/o3/inst_queue.hh" 5411251Sradhika.jagtap@ARM.com#include "debug/IQ.hh" 5511251Sradhika.jagtap@ARM.com#include "enums/OpClass.hh" 5611251Sradhika.jagtap@ARM.com#include "params/DerivO3CPU.hh" 5711251Sradhika.jagtap@ARM.com#include "sim/core.hh" 5811251Sradhika.jagtap@ARM.com 5912564Sgabeblack@google.com// clang complains about std::set being overloaded with Packet::set if 6012564Sgabeblack@google.com// we open up the entire namespace std 6111251Sradhika.jagtap@ARM.comusing std::list; 6211251Sradhika.jagtap@ARM.com 6311251Sradhika.jagtap@ARM.comtemplate <class Impl> 6411251Sradhika.jagtap@ARM.comInstructionQueue<Impl>::FUCompletion::FUCompletion(const DynInstPtr &_inst, 6511251Sradhika.jagtap@ARM.com int fu_idx, InstructionQueue<Impl> *iq_ptr) 6612564Sgabeblack@google.com : Event(Stat_Event_Pri, AutoDelete), 6711251Sradhika.jagtap@ARM.com inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 6811251Sradhika.jagtap@ARM.com{ 6911251Sradhika.jagtap@ARM.com} 7011251Sradhika.jagtap@ARM.com 7112014Sgabeblack@google.comtemplate <class Impl> 7211251Sradhika.jagtap@ARM.comvoid 7312014Sgabeblack@google.comInstructionQueue<Impl>::FUCompletion::process() 7411251Sradhika.jagtap@ARM.com{ 7511251Sradhika.jagtap@ARM.com iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 7611251Sradhika.jagtap@ARM.com inst = NULL; 7711251Sradhika.jagtap@ARM.com} 7811251Sradhika.jagtap@ARM.com 7911251Sradhika.jagtap@ARM.com 8011251Sradhika.jagtap@ARM.comtemplate <class Impl> 8111251Sradhika.jagtap@ARM.comconst char * 8211251Sradhika.jagtap@ARM.comInstructionQueue<Impl>::FUCompletion::description() const 8311251Sradhika.jagtap@ARM.com{ 8411251Sradhika.jagtap@ARM.com return "Functional unit completion"; 8511251Sradhika.jagtap@ARM.com} 8611251Sradhika.jagtap@ARM.com 8711251Sradhika.jagtap@ARM.comtemplate <class Impl> 8811251Sradhika.jagtap@ARM.comInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 8911251Sradhika.jagtap@ARM.com DerivO3CPUParams *params) 9011251Sradhika.jagtap@ARM.com : cpu(cpu_ptr), 9111251Sradhika.jagtap@ARM.com iewStage(iew_ptr), 9211251Sradhika.jagtap@ARM.com fuPool(params->fuPool), 9311251Sradhika.jagtap@ARM.com iqPolicy(params->smtIQPolicy), 9411251Sradhika.jagtap@ARM.com numEntries(params->numIQEntries), 9511251Sradhika.jagtap@ARM.com totalWidth(params->issueWidth), 9611251Sradhika.jagtap@ARM.com commitToIEWDelay(params->commitToIEWDelay) 9711251Sradhika.jagtap@ARM.com{ 9811251Sradhika.jagtap@ARM.com assert(fuPool); 9911251Sradhika.jagtap@ARM.com 10011251Sradhika.jagtap@ARM.com numThreads = params->numThreads; 10111251Sradhika.jagtap@ARM.com 10211251Sradhika.jagtap@ARM.com // Set the number of total physical registers 10311251Sradhika.jagtap@ARM.com // As the vector registers have two addressing modes, they are added twice 10411251Sradhika.jagtap@ARM.com numPhysRegs = params->numPhysIntRegs + params->numPhysFloatRegs + 10511251Sradhika.jagtap@ARM.com params->numPhysVecRegs + 10611251Sradhika.jagtap@ARM.com params->numPhysVecRegs * TheISA::NumVecElemPerVecReg + 10711251Sradhika.jagtap@ARM.com params->numPhysVecPredRegs + 10811251Sradhika.jagtap@ARM.com params->numPhysCCRegs; 10911251Sradhika.jagtap@ARM.com 11012430Schenzou@uchicago.edu //Create an entry for each physical register within the 11112430Schenzou@uchicago.edu //dependency graph. 11212430Schenzou@uchicago.edu dependGraph.resize(numPhysRegs); 11312430Schenzou@uchicago.edu 11412430Schenzou@uchicago.edu // Resize the register scoreboard. 11511251Sradhika.jagtap@ARM.com regScoreboard.resize(numPhysRegs); 11611251Sradhika.jagtap@ARM.com 11711251Sradhika.jagtap@ARM.com //Initialize Mem Dependence Units 11811251Sradhika.jagtap@ARM.com for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 11911251Sradhika.jagtap@ARM.com memDepUnit[tid].init(params, tid); 12011251Sradhika.jagtap@ARM.com memDepUnit[tid].setIQ(this); 12111251Sradhika.jagtap@ARM.com } 12211251Sradhika.jagtap@ARM.com 12311251Sradhika.jagtap@ARM.com resetState(); 12411251Sradhika.jagtap@ARM.com 12511251Sradhika.jagtap@ARM.com //Figure out resource sharing policy 12611251Sradhika.jagtap@ARM.com if (iqPolicy == SMTQueuePolicy::Dynamic) { 12711251Sradhika.jagtap@ARM.com //Set Max Entries to Total ROB Capacity 128 for (ThreadID tid = 0; tid < numThreads; tid++) { 129 maxEntries[tid] = numEntries; 130 } 131 132 } else if (iqPolicy == SMTQueuePolicy::Partitioned) { 133 //@todo:make work if part_amt doesnt divide evenly. 134 int part_amt = numEntries / numThreads; 135 136 //Divide ROB up evenly 137 for (ThreadID tid = 0; tid < numThreads; tid++) { 138 maxEntries[tid] = part_amt; 139 } 140 141 DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 142 "%i entries per thread.\n",part_amt); 143 } else if (iqPolicy == SMTQueuePolicy::Threshold) { 144 double threshold = (double)params->smtIQThreshold / 100; 145 146 int thresholdIQ = (int)((double)threshold * numEntries); 147 148 //Divide up by threshold amount 149 for (ThreadID tid = 0; tid < numThreads; tid++) { 150 maxEntries[tid] = thresholdIQ; 151 } 152 153 DPRINTF(IQ, "IQ sharing policy set to Threshold:" 154 "%i entries per thread.\n",thresholdIQ); 155 } 156 for (ThreadID tid = numThreads; tid < Impl::MaxThreads; tid++) { 157 maxEntries[tid] = 0; 158 } 159} 160 161template <class Impl> 162InstructionQueue<Impl>::~InstructionQueue() 163{ 164 dependGraph.reset(); 165#ifdef DEBUG 166 cprintf("Nodes traversed: %i, removed: %i\n", 167 dependGraph.nodesTraversed, dependGraph.nodesRemoved); 168#endif 169} 170 171template <class Impl> 172std::string 173InstructionQueue<Impl>::name() const 174{ 175 return cpu->name() + ".iq"; 176} 177 178template <class Impl> 179void 180InstructionQueue<Impl>::regStats() 181{ 182 using namespace Stats; 183 iqInstsAdded 184 .name(name() + ".iqInstsAdded") 185 .desc("Number of instructions added to the IQ (excludes non-spec)") 186 .prereq(iqInstsAdded); 187 188 iqNonSpecInstsAdded 189 .name(name() + ".iqNonSpecInstsAdded") 190 .desc("Number of non-speculative instructions added to the IQ") 191 .prereq(iqNonSpecInstsAdded); 192 193 iqInstsIssued 194 .name(name() + ".iqInstsIssued") 195 .desc("Number of instructions issued") 196 .prereq(iqInstsIssued); 197 198 iqIntInstsIssued 199 .name(name() + ".iqIntInstsIssued") 200 .desc("Number of integer instructions issued") 201 .prereq(iqIntInstsIssued); 202 203 iqFloatInstsIssued 204 .name(name() + ".iqFloatInstsIssued") 205 .desc("Number of float instructions issued") 206 .prereq(iqFloatInstsIssued); 207 208 iqBranchInstsIssued 209 .name(name() + ".iqBranchInstsIssued") 210 .desc("Number of branch instructions issued") 211 .prereq(iqBranchInstsIssued); 212 213 iqMemInstsIssued 214 .name(name() + ".iqMemInstsIssued") 215 .desc("Number of memory instructions issued") 216 .prereq(iqMemInstsIssued); 217 218 iqMiscInstsIssued 219 .name(name() + ".iqMiscInstsIssued") 220 .desc("Number of miscellaneous instructions issued") 221 .prereq(iqMiscInstsIssued); 222 223 iqSquashedInstsIssued 224 .name(name() + ".iqSquashedInstsIssued") 225 .desc("Number of squashed instructions issued") 226 .prereq(iqSquashedInstsIssued); 227 228 iqSquashedInstsExamined 229 .name(name() + ".iqSquashedInstsExamined") 230 .desc("Number of squashed instructions iterated over during squash;" 231 " mainly for profiling") 232 .prereq(iqSquashedInstsExamined); 233 234 iqSquashedOperandsExamined 235 .name(name() + ".iqSquashedOperandsExamined") 236 .desc("Number of squashed operands that are examined and possibly " 237 "removed from graph") 238 .prereq(iqSquashedOperandsExamined); 239 240 iqSquashedNonSpecRemoved 241 .name(name() + ".iqSquashedNonSpecRemoved") 242 .desc("Number of squashed non-spec instructions that were removed") 243 .prereq(iqSquashedNonSpecRemoved); 244/* 245 queueResDist 246 .init(Num_OpClasses, 0, 99, 2) 247 .name(name() + ".IQ:residence:") 248 .desc("cycles from dispatch to issue") 249 .flags(total | pdf | cdf ) 250 ; 251 for (int i = 0; i < Num_OpClasses; ++i) { 252 queueResDist.subname(i, opClassStrings[i]); 253 } 254*/ 255 numIssuedDist 256 .init(0,totalWidth,1) 257 .name(name() + ".issued_per_cycle") 258 .desc("Number of insts issued each cycle") 259 .flags(pdf) 260 ; 261/* 262 dist_unissued 263 .init(Num_OpClasses+2) 264 .name(name() + ".unissued_cause") 265 .desc("Reason ready instruction not issued") 266 .flags(pdf | dist) 267 ; 268 for (int i=0; i < (Num_OpClasses + 2); ++i) { 269 dist_unissued.subname(i, unissued_names[i]); 270 } 271*/ 272 statIssuedInstType 273 .init(numThreads,Enums::Num_OpClass) 274 .name(name() + ".FU_type") 275 .desc("Type of FU issued") 276 .flags(total | pdf | dist) 277 ; 278 statIssuedInstType.ysubnames(Enums::OpClassStrings); 279 280 // 281 // How long did instructions for a particular FU type wait prior to issue 282 // 283/* 284 issueDelayDist 285 .init(Num_OpClasses,0,99,2) 286 .name(name() + ".") 287 .desc("cycles from operands ready to issue") 288 .flags(pdf | cdf) 289 ; 290 291 for (int i=0; i<Num_OpClasses; ++i) { 292 std::stringstream subname; 293 subname << opClassStrings[i] << "_delay"; 294 issueDelayDist.subname(i, subname.str()); 295 } 296*/ 297 issueRate 298 .name(name() + ".rate") 299 .desc("Inst issue rate") 300 .flags(total) 301 ; 302 issueRate = iqInstsIssued / cpu->numCycles; 303 304 statFuBusy 305 .init(Num_OpClasses) 306 .name(name() + ".fu_full") 307 .desc("attempts to use FU when none available") 308 .flags(pdf | dist) 309 ; 310 for (int i=0; i < Num_OpClasses; ++i) { 311 statFuBusy.subname(i, Enums::OpClassStrings[i]); 312 } 313 314 fuBusy 315 .init(numThreads) 316 .name(name() + ".fu_busy_cnt") 317 .desc("FU busy when requested") 318 .flags(total) 319 ; 320 321 fuBusyRate 322 .name(name() + ".fu_busy_rate") 323 .desc("FU busy rate (busy events/executed inst)") 324 .flags(total) 325 ; 326 fuBusyRate = fuBusy / iqInstsIssued; 327 328 for (ThreadID tid = 0; tid < numThreads; tid++) { 329 // Tell mem dependence unit to reg stats as well. 330 memDepUnit[tid].regStats(); 331 } 332 333 intInstQueueReads 334 .name(name() + ".int_inst_queue_reads") 335 .desc("Number of integer instruction queue reads") 336 .flags(total); 337 338 intInstQueueWrites 339 .name(name() + ".int_inst_queue_writes") 340 .desc("Number of integer instruction queue writes") 341 .flags(total); 342 343 intInstQueueWakeupAccesses 344 .name(name() + ".int_inst_queue_wakeup_accesses") 345 .desc("Number of integer instruction queue wakeup accesses") 346 .flags(total); 347 348 fpInstQueueReads 349 .name(name() + ".fp_inst_queue_reads") 350 .desc("Number of floating instruction queue reads") 351 .flags(total); 352 353 fpInstQueueWrites 354 .name(name() + ".fp_inst_queue_writes") 355 .desc("Number of floating instruction queue writes") 356 .flags(total); 357 358 fpInstQueueWakeupAccesses 359 .name(name() + ".fp_inst_queue_wakeup_accesses") 360 .desc("Number of floating instruction queue wakeup accesses") 361 .flags(total); 362 363 vecInstQueueReads 364 .name(name() + ".vec_inst_queue_reads") 365 .desc("Number of vector instruction queue reads") 366 .flags(total); 367 368 vecInstQueueWrites 369 .name(name() + ".vec_inst_queue_writes") 370 .desc("Number of vector instruction queue writes") 371 .flags(total); 372 373 vecInstQueueWakeupAccesses 374 .name(name() + ".vec_inst_queue_wakeup_accesses") 375 .desc("Number of vector instruction queue wakeup accesses") 376 .flags(total); 377 378 intAluAccesses 379 .name(name() + ".int_alu_accesses") 380 .desc("Number of integer alu accesses") 381 .flags(total); 382 383 fpAluAccesses 384 .name(name() + ".fp_alu_accesses") 385 .desc("Number of floating point alu accesses") 386 .flags(total); 387 388 vecAluAccesses 389 .name(name() + ".vec_alu_accesses") 390 .desc("Number of vector alu accesses") 391 .flags(total); 392 393} 394 395template <class Impl> 396void 397InstructionQueue<Impl>::resetState() 398{ 399 //Initialize thread IQ counts 400 for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 401 count[tid] = 0; 402 instList[tid].clear(); 403 } 404 405 // Initialize the number of free IQ entries. 406 freeEntries = numEntries; 407 408 // Note that in actuality, the registers corresponding to the logical 409 // registers start off as ready. However this doesn't matter for the 410 // IQ as the instruction should have been correctly told if those 411 // registers are ready in rename. Thus it can all be initialized as 412 // unready. 413 for (int i = 0; i < numPhysRegs; ++i) { 414 regScoreboard[i] = false; 415 } 416 417 for (ThreadID tid = 0; tid < Impl::MaxThreads; ++tid) { 418 squashedSeqNum[tid] = 0; 419 } 420 421 for (int i = 0; i < Num_OpClasses; ++i) { 422 while (!readyInsts[i].empty()) 423 readyInsts[i].pop(); 424 queueOnList[i] = false; 425 readyIt[i] = listOrder.end(); 426 } 427 nonSpecInsts.clear(); 428 listOrder.clear(); 429 deferredMemInsts.clear(); 430 blockedMemInsts.clear(); 431 retryMemInsts.clear(); 432 wbOutstanding = 0; 433} 434 435template <class Impl> 436void 437InstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 438{ 439 activeThreads = at_ptr; 440} 441 442template <class Impl> 443void 444InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 445{ 446 issueToExecuteQueue = i2e_ptr; 447} 448 449template <class Impl> 450void 451InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 452{ 453 timeBuffer = tb_ptr; 454 455 fromCommit = timeBuffer->getWire(-commitToIEWDelay); 456} 457 458template <class Impl> 459bool 460InstructionQueue<Impl>::isDrained() const 461{ 462 bool drained = dependGraph.empty() && 463 instsToExecute.empty() && 464 wbOutstanding == 0; 465 for (ThreadID tid = 0; tid < numThreads; ++tid) 466 drained = drained && memDepUnit[tid].isDrained(); 467 468 return drained; 469} 470 471template <class Impl> 472void 473InstructionQueue<Impl>::drainSanityCheck() const 474{ 475 assert(dependGraph.empty()); 476 assert(instsToExecute.empty()); 477 for (ThreadID tid = 0; tid < numThreads; ++tid) 478 memDepUnit[tid].drainSanityCheck(); 479} 480 481template <class Impl> 482void 483InstructionQueue<Impl>::takeOverFrom() 484{ 485 resetState(); 486} 487 488template <class Impl> 489int 490InstructionQueue<Impl>::entryAmount(ThreadID num_threads) 491{ 492 if (iqPolicy == SMTQueuePolicy::Partitioned) { 493 return numEntries / num_threads; 494 } else { 495 return 0; 496 } 497} 498 499 500template <class Impl> 501void 502InstructionQueue<Impl>::resetEntries() 503{ 504 if (iqPolicy != SMTQueuePolicy::Dynamic || numThreads > 1) { 505 int active_threads = activeThreads->size(); 506 507 list<ThreadID>::iterator threads = activeThreads->begin(); 508 list<ThreadID>::iterator end = activeThreads->end(); 509 510 while (threads != end) { 511 ThreadID tid = *threads++; 512 513 if (iqPolicy == SMTQueuePolicy::Partitioned) { 514 maxEntries[tid] = numEntries / active_threads; 515 } else if (iqPolicy == SMTQueuePolicy::Threshold && 516 active_threads == 1) { 517 maxEntries[tid] = numEntries; 518 } 519 } 520 } 521} 522 523template <class Impl> 524unsigned 525InstructionQueue<Impl>::numFreeEntries() 526{ 527 return freeEntries; 528} 529 530template <class Impl> 531unsigned 532InstructionQueue<Impl>::numFreeEntries(ThreadID tid) 533{ 534 return maxEntries[tid] - count[tid]; 535} 536 537// Might want to do something more complex if it knows how many instructions 538// will be issued this cycle. 539template <class Impl> 540bool 541InstructionQueue<Impl>::isFull() 542{ 543 if (freeEntries == 0) { 544 return(true); 545 } else { 546 return(false); 547 } 548} 549 550template <class Impl> 551bool 552InstructionQueue<Impl>::isFull(ThreadID tid) 553{ 554 if (numFreeEntries(tid) == 0) { 555 return(true); 556 } else { 557 return(false); 558 } 559} 560 561template <class Impl> 562bool 563InstructionQueue<Impl>::hasReadyInsts() 564{ 565 if (!listOrder.empty()) { 566 return true; 567 } 568 569 for (int i = 0; i < Num_OpClasses; ++i) { 570 if (!readyInsts[i].empty()) { 571 return true; 572 } 573 } 574 575 return false; 576} 577 578template <class Impl> 579void 580InstructionQueue<Impl>::insert(const DynInstPtr &new_inst) 581{ 582 if (new_inst->isFloating()) { 583 fpInstQueueWrites++; 584 } else if (new_inst->isVector()) { 585 vecInstQueueWrites++; 586 } else { 587 intInstQueueWrites++; 588 } 589 // Make sure the instruction is valid 590 assert(new_inst); 591 592 DPRINTF(IQ, "Adding instruction [sn:%llu] PC %s to the IQ.\n", 593 new_inst->seqNum, new_inst->pcState()); 594 595 assert(freeEntries != 0); 596 597 instList[new_inst->threadNumber].push_back(new_inst); 598 599 --freeEntries; 600 601 new_inst->setInIQ(); 602 603 // Look through its source registers (physical regs), and mark any 604 // dependencies. 605 addToDependents(new_inst); 606 607 // Have this instruction set itself as the producer of its destination 608 // register(s). 609 addToProducers(new_inst); 610 611 if (new_inst->isMemRef()) { 612 memDepUnit[new_inst->threadNumber].insert(new_inst); 613 } else { 614 addIfReady(new_inst); 615 } 616 617 ++iqInstsAdded; 618 619 count[new_inst->threadNumber]++; 620 621 assert(freeEntries == (numEntries - countInsts())); 622} 623 624template <class Impl> 625void 626InstructionQueue<Impl>::insertNonSpec(const DynInstPtr &new_inst) 627{ 628 // @todo: Clean up this code; can do it by setting inst as unable 629 // to issue, then calling normal insert on the inst. 630 if (new_inst->isFloating()) { 631 fpInstQueueWrites++; 632 } else if (new_inst->isVector()) { 633 vecInstQueueWrites++; 634 } else { 635 intInstQueueWrites++; 636 } 637 638 assert(new_inst); 639 640 nonSpecInsts[new_inst->seqNum] = new_inst; 641 642 DPRINTF(IQ, "Adding non-speculative instruction [sn:%llu] PC %s " 643 "to the IQ.\n", 644 new_inst->seqNum, new_inst->pcState()); 645 646 assert(freeEntries != 0); 647 648 instList[new_inst->threadNumber].push_back(new_inst); 649 650 --freeEntries; 651 652 new_inst->setInIQ(); 653 654 // Have this instruction set itself as the producer of its destination 655 // register(s). 656 addToProducers(new_inst); 657 658 // If it's a memory instruction, add it to the memory dependency 659 // unit. 660 if (new_inst->isMemRef()) { 661 memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 662 } 663 664 ++iqNonSpecInstsAdded; 665 666 count[new_inst->threadNumber]++; 667 668 assert(freeEntries == (numEntries - countInsts())); 669} 670 671template <class Impl> 672void 673InstructionQueue<Impl>::insertBarrier(const DynInstPtr &barr_inst) 674{ 675 memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 676 677 insertNonSpec(barr_inst); 678} 679 680template <class Impl> 681typename Impl::DynInstPtr 682InstructionQueue<Impl>::getInstToExecute() 683{ 684 assert(!instsToExecute.empty()); 685 DynInstPtr inst = std::move(instsToExecute.front()); 686 instsToExecute.pop_front(); 687 if (inst->isFloating()) { 688 fpInstQueueReads++; 689 } else if (inst->isVector()) { 690 vecInstQueueReads++; 691 } else { 692 intInstQueueReads++; 693 } 694 return inst; 695} 696 697template <class Impl> 698void 699InstructionQueue<Impl>::addToOrderList(OpClass op_class) 700{ 701 assert(!readyInsts[op_class].empty()); 702 703 ListOrderEntry queue_entry; 704 705 queue_entry.queueType = op_class; 706 707 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 708 709 ListOrderIt list_it = listOrder.begin(); 710 ListOrderIt list_end_it = listOrder.end(); 711 712 while (list_it != list_end_it) { 713 if ((*list_it).oldestInst > queue_entry.oldestInst) { 714 break; 715 } 716 717 list_it++; 718 } 719 720 readyIt[op_class] = listOrder.insert(list_it, queue_entry); 721 queueOnList[op_class] = true; 722} 723 724template <class Impl> 725void 726InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 727{ 728 // Get iterator of next item on the list 729 // Delete the original iterator 730 // Determine if the next item is either the end of the list or younger 731 // than the new instruction. If so, then add in a new iterator right here. 732 // If not, then move along. 733 ListOrderEntry queue_entry; 734 OpClass op_class = (*list_order_it).queueType; 735 ListOrderIt next_it = list_order_it; 736 737 ++next_it; 738 739 queue_entry.queueType = op_class; 740 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 741 742 while (next_it != listOrder.end() && 743 (*next_it).oldestInst < queue_entry.oldestInst) { 744 ++next_it; 745 } 746 747 readyIt[op_class] = listOrder.insert(next_it, queue_entry); 748} 749 750template <class Impl> 751void 752InstructionQueue<Impl>::processFUCompletion(const DynInstPtr &inst, int fu_idx) 753{ 754 DPRINTF(IQ, "Processing FU completion [sn:%llu]\n", inst->seqNum); 755 assert(!cpu->switchedOut()); 756 // The CPU could have been sleeping until this op completed (*extremely* 757 // long latency op). Wake it if it was. This may be overkill. 758 --wbOutstanding; 759 iewStage->wakeCPU(); 760 761 if (fu_idx > -1) 762 fuPool->freeUnitNextCycle(fu_idx); 763 764 // @todo: Ensure that these FU Completions happen at the beginning 765 // of a cycle, otherwise they could add too many instructions to 766 // the queue. 767 issueToExecuteQueue->access(-1)->size++; 768 instsToExecute.push_back(inst); 769} 770 771// @todo: Figure out a better way to remove the squashed items from the 772// lists. Checking the top item of each list to see if it's squashed 773// wastes time and forces jumps. 774template <class Impl> 775void 776InstructionQueue<Impl>::scheduleReadyInsts() 777{ 778 DPRINTF(IQ, "Attempting to schedule ready instructions from " 779 "the IQ.\n"); 780 781 IssueStruct *i2e_info = issueToExecuteQueue->access(0); 782 783 DynInstPtr mem_inst; 784 while (mem_inst = std::move(getDeferredMemInstToExecute())) { 785 addReadyMemInst(mem_inst); 786 } 787 788 // See if any cache blocked instructions are able to be executed 789 while (mem_inst = std::move(getBlockedMemInstToExecute())) { 790 addReadyMemInst(mem_inst); 791 } 792 793 // Have iterator to head of the list 794 // While I haven't exceeded bandwidth or reached the end of the list, 795 // Try to get a FU that can do what this op needs. 796 // If successful, change the oldestInst to the new top of the list, put 797 // the queue in the proper place in the list. 798 // Increment the iterator. 799 // This will avoid trying to schedule a certain op class if there are no 800 // FUs that handle it. 801 int total_issued = 0; 802 ListOrderIt order_it = listOrder.begin(); 803 ListOrderIt order_end_it = listOrder.end(); 804 805 while (total_issued < totalWidth && order_it != order_end_it) { 806 OpClass op_class = (*order_it).queueType; 807 808 assert(!readyInsts[op_class].empty()); 809 810 DynInstPtr issuing_inst = readyInsts[op_class].top(); 811 812 if (issuing_inst->isFloating()) { 813 fpInstQueueReads++; 814 } else if (issuing_inst->isVector()) { 815 vecInstQueueReads++; 816 } else { 817 intInstQueueReads++; 818 } 819 820 assert(issuing_inst->seqNum == (*order_it).oldestInst); 821 822 if (issuing_inst->isSquashed()) { 823 readyInsts[op_class].pop(); 824 825 if (!readyInsts[op_class].empty()) { 826 moveToYoungerInst(order_it); 827 } else { 828 readyIt[op_class] = listOrder.end(); 829 queueOnList[op_class] = false; 830 } 831 832 listOrder.erase(order_it++); 833 834 ++iqSquashedInstsIssued; 835 836 continue; 837 } 838 839 int idx = FUPool::NoCapableFU; 840 Cycles op_latency = Cycles(1); 841 ThreadID tid = issuing_inst->threadNumber; 842 843 if (op_class != No_OpClass) { 844 idx = fuPool->getUnit(op_class); 845 if (issuing_inst->isFloating()) { 846 fpAluAccesses++; 847 } else if (issuing_inst->isVector()) { 848 vecAluAccesses++; 849 } else { 850 intAluAccesses++; 851 } 852 if (idx > FUPool::NoFreeFU) { 853 op_latency = fuPool->getOpLatency(op_class); 854 } 855 } 856 857 // If we have an instruction that doesn't require a FU, or a 858 // valid FU, then schedule for execution. 859 if (idx != FUPool::NoFreeFU) { 860 if (op_latency == Cycles(1)) { 861 i2e_info->size++; 862 instsToExecute.push_back(issuing_inst); 863 864 // Add the FU onto the list of FU's to be freed next 865 // cycle if we used one. 866 if (idx >= 0) 867 fuPool->freeUnitNextCycle(idx); 868 } else { 869 bool pipelined = fuPool->isPipelined(op_class); 870 // Generate completion event for the FU 871 ++wbOutstanding; 872 FUCompletion *execution = new FUCompletion(issuing_inst, 873 idx, this); 874 875 cpu->schedule(execution, 876 cpu->clockEdge(Cycles(op_latency - 1))); 877 878 if (!pipelined) { 879 // If FU isn't pipelined, then it must be freed 880 // upon the execution completing. 881 execution->setFreeFU(); 882 } else { 883 // Add the FU onto the list of FU's to be freed next cycle. 884 fuPool->freeUnitNextCycle(idx); 885 } 886 } 887 888 DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 889 "[sn:%llu]\n", 890 tid, issuing_inst->pcState(), 891 issuing_inst->seqNum); 892 893 readyInsts[op_class].pop(); 894 895 if (!readyInsts[op_class].empty()) { 896 moveToYoungerInst(order_it); 897 } else { 898 readyIt[op_class] = listOrder.end(); 899 queueOnList[op_class] = false; 900 } 901 902 issuing_inst->setIssued(); 903 ++total_issued; 904 905#if TRACING_ON 906 issuing_inst->issueTick = curTick() - issuing_inst->fetchTick; 907#endif 908 909 if (!issuing_inst->isMemRef()) { 910 // Memory instructions can not be freed from the IQ until they 911 // complete. 912 ++freeEntries; 913 count[tid]--; 914 issuing_inst->clearInIQ(); 915 } else { 916 memDepUnit[tid].issue(issuing_inst); 917 } 918 919 listOrder.erase(order_it++); 920 statIssuedInstType[tid][op_class]++; 921 } else { 922 statFuBusy[op_class]++; 923 fuBusy[tid]++; 924 ++order_it; 925 } 926 } 927 928 numIssuedDist.sample(total_issued); 929 iqInstsIssued+= total_issued; 930 931 // If we issued any instructions, tell the CPU we had activity. 932 // @todo If the way deferred memory instructions are handeled due to 933 // translation changes then the deferredMemInsts condition should be removed 934 // from the code below. 935 if (total_issued || !retryMemInsts.empty() || !deferredMemInsts.empty()) { 936 cpu->activityThisCycle(); 937 } else { 938 DPRINTF(IQ, "Not able to schedule any instructions.\n"); 939 } 940} 941 942template <class Impl> 943void 944InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 945{ 946 DPRINTF(IQ, "Marking nonspeculative instruction [sn:%llu] as ready " 947 "to execute.\n", inst); 948 949 NonSpecMapIt inst_it = nonSpecInsts.find(inst); 950 951 assert(inst_it != nonSpecInsts.end()); 952 953 ThreadID tid = (*inst_it).second->threadNumber; 954 955 (*inst_it).second->setAtCommit(); 956 957 (*inst_it).second->setCanIssue(); 958 959 if (!(*inst_it).second->isMemRef()) { 960 addIfReady((*inst_it).second); 961 } else { 962 memDepUnit[tid].nonSpecInstReady((*inst_it).second); 963 } 964 965 (*inst_it).second = NULL; 966 967 nonSpecInsts.erase(inst_it); 968} 969 970template <class Impl> 971void 972InstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 973{ 974 DPRINTF(IQ, "[tid:%i] Committing instructions older than [sn:%llu]\n", 975 tid,inst); 976 977 ListIt iq_it = instList[tid].begin(); 978 979 while (iq_it != instList[tid].end() && 980 (*iq_it)->seqNum <= inst) { 981 ++iq_it; 982 instList[tid].pop_front(); 983 } 984 985 assert(freeEntries == (numEntries - countInsts())); 986} 987 988template <class Impl> 989int 990InstructionQueue<Impl>::wakeDependents(const DynInstPtr &completed_inst) 991{ 992 int dependents = 0; 993 994 // The instruction queue here takes care of both floating and int ops 995 if (completed_inst->isFloating()) { 996 fpInstQueueWakeupAccesses++; 997 } else if (completed_inst->isVector()) { 998 vecInstQueueWakeupAccesses++; 999 } else { 1000 intInstQueueWakeupAccesses++; 1001 } 1002 1003 DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 1004 1005 assert(!completed_inst->isSquashed()); 1006 1007 // Tell the memory dependence unit to wake any dependents on this 1008 // instruction if it is a memory instruction. Also complete the memory 1009 // instruction at this point since we know it executed without issues. 1010 // @todo: Might want to rename "completeMemInst" to something that 1011 // indicates that it won't need to be replayed, and call this 1012 // earlier. Might not be a big deal. 1013 if (completed_inst->isMemRef()) { 1014 memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 1015 completeMemInst(completed_inst); 1016 } else if (completed_inst->isMemBarrier() || 1017 completed_inst->isWriteBarrier()) { 1018 memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 1019 } 1020 1021 for (int dest_reg_idx = 0; 1022 dest_reg_idx < completed_inst->numDestRegs(); 1023 dest_reg_idx++) 1024 { 1025 PhysRegIdPtr dest_reg = 1026 completed_inst->renamedDestRegIdx(dest_reg_idx); 1027 1028 // Special case of uniq or control registers. They are not 1029 // handled by the IQ and thus have no dependency graph entry. 1030 if (dest_reg->isFixedMapping()) { 1031 DPRINTF(IQ, "Reg %d [%s] is part of a fix mapping, skipping\n", 1032 dest_reg->index(), dest_reg->className()); 1033 continue; 1034 } 1035 1036 // Avoid waking up dependents if the register is pinned 1037 dest_reg->decrNumPinnedWritesToComplete(); 1038 if (dest_reg->isPinned()) 1039 completed_inst->setPinnedRegsWritten(); 1040 1041 if (dest_reg->getNumPinnedWritesToComplete() != 0) { 1042 DPRINTF(IQ, "Reg %d [%s] is pinned, skipping\n", 1043 dest_reg->index(), dest_reg->className()); 1044 continue; 1045 } 1046 1047 DPRINTF(IQ, "Waking any dependents on register %i (%s).\n", 1048 dest_reg->index(), 1049 dest_reg->className()); 1050 1051 //Go through the dependency chain, marking the registers as 1052 //ready within the waiting instructions. 1053 DynInstPtr dep_inst = dependGraph.pop(dest_reg->flatIndex()); 1054 1055 while (dep_inst) { 1056 DPRINTF(IQ, "Waking up a dependent instruction, [sn:%llu] " 1057 "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 1058 1059 // Might want to give more information to the instruction 1060 // so that it knows which of its source registers is 1061 // ready. However that would mean that the dependency 1062 // graph entries would need to hold the src_reg_idx. 1063 dep_inst->markSrcRegReady(); 1064 1065 addIfReady(dep_inst); 1066 1067 dep_inst = dependGraph.pop(dest_reg->flatIndex()); 1068 1069 ++dependents; 1070 } 1071 1072 // Reset the head node now that all of its dependents have 1073 // been woken up. 1074 assert(dependGraph.empty(dest_reg->flatIndex())); 1075 dependGraph.clearInst(dest_reg->flatIndex()); 1076 1077 // Mark the scoreboard as having that register ready. 1078 regScoreboard[dest_reg->flatIndex()] = true; 1079 } 1080 return dependents; 1081} 1082 1083template <class Impl> 1084void 1085InstructionQueue<Impl>::addReadyMemInst(const DynInstPtr &ready_inst) 1086{ 1087 OpClass op_class = ready_inst->opClass(); 1088 1089 readyInsts[op_class].push(ready_inst); 1090 1091 // Will need to reorder the list if either a queue is not on the list, 1092 // or it has an older instruction than last time. 1093 if (!queueOnList[op_class]) { 1094 addToOrderList(op_class); 1095 } else if (readyInsts[op_class].top()->seqNum < 1096 (*readyIt[op_class]).oldestInst) { 1097 listOrder.erase(readyIt[op_class]); 1098 addToOrderList(op_class); 1099 } 1100 1101 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 1102 "the ready list, PC %s opclass:%i [sn:%llu].\n", 1103 ready_inst->pcState(), op_class, ready_inst->seqNum); 1104} 1105 1106template <class Impl> 1107void 1108InstructionQueue<Impl>::rescheduleMemInst(const DynInstPtr &resched_inst) 1109{ 1110 DPRINTF(IQ, "Rescheduling mem inst [sn:%llu]\n", resched_inst->seqNum); 1111 1112 // Reset DTB translation state 1113 resched_inst->translationStarted(false); 1114 resched_inst->translationCompleted(false); 1115 1116 resched_inst->clearCanIssue(); 1117 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 1118} 1119 1120template <class Impl> 1121void 1122InstructionQueue<Impl>::replayMemInst(const DynInstPtr &replay_inst) 1123{ 1124 memDepUnit[replay_inst->threadNumber].replay(); 1125} 1126 1127template <class Impl> 1128void 1129InstructionQueue<Impl>::completeMemInst(const DynInstPtr &completed_inst) 1130{ 1131 ThreadID tid = completed_inst->threadNumber; 1132 1133 DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%llu]\n", 1134 completed_inst->pcState(), completed_inst->seqNum); 1135 1136 ++freeEntries; 1137 1138 completed_inst->memOpDone(true); 1139 1140 memDepUnit[tid].completed(completed_inst); 1141 count[tid]--; 1142} 1143 1144template <class Impl> 1145void 1146InstructionQueue<Impl>::deferMemInst(const DynInstPtr &deferred_inst) 1147{ 1148 deferredMemInsts.push_back(deferred_inst); 1149} 1150 1151template <class Impl> 1152void 1153InstructionQueue<Impl>::blockMemInst(const DynInstPtr &blocked_inst) 1154{ 1155 blocked_inst->clearIssued(); 1156 blocked_inst->clearCanIssue(); 1157 blockedMemInsts.push_back(blocked_inst); 1158} 1159 1160template <class Impl> 1161void 1162InstructionQueue<Impl>::cacheUnblocked() 1163{ 1164 retryMemInsts.splice(retryMemInsts.end(), blockedMemInsts); 1165 // Get the CPU ticking again 1166 cpu->wakeCPU(); 1167} 1168 1169template <class Impl> 1170typename Impl::DynInstPtr 1171InstructionQueue<Impl>::getDeferredMemInstToExecute() 1172{ 1173 for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); 1174 ++it) { 1175 if ((*it)->translationCompleted() || (*it)->isSquashed()) { 1176 DynInstPtr mem_inst = std::move(*it); 1177 deferredMemInsts.erase(it); 1178 return mem_inst; 1179 } 1180 } 1181 return nullptr; 1182} 1183 1184template <class Impl> 1185typename Impl::DynInstPtr 1186InstructionQueue<Impl>::getBlockedMemInstToExecute() 1187{ 1188 if (retryMemInsts.empty()) { 1189 return nullptr; 1190 } else { 1191 DynInstPtr mem_inst = std::move(retryMemInsts.front()); 1192 retryMemInsts.pop_front(); 1193 return mem_inst; 1194 } 1195} 1196 1197template <class Impl> 1198void 1199InstructionQueue<Impl>::violation(const DynInstPtr &store, 1200 const DynInstPtr &faulting_load) 1201{ 1202 intInstQueueWrites++; 1203 memDepUnit[store->threadNumber].violation(store, faulting_load); 1204} 1205 1206template <class Impl> 1207void 1208InstructionQueue<Impl>::squash(ThreadID tid) 1209{ 1210 DPRINTF(IQ, "[tid:%i] Starting to squash instructions in " 1211 "the IQ.\n", tid); 1212 1213 // Read instruction sequence number of last instruction out of the 1214 // time buffer. 1215 squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 1216 1217 doSquash(tid); 1218 1219 // Also tell the memory dependence unit to squash. 1220 memDepUnit[tid].squash(squashedSeqNum[tid], tid); 1221} 1222 1223template <class Impl> 1224void 1225InstructionQueue<Impl>::doSquash(ThreadID tid) 1226{ 1227 // Start at the tail. 1228 ListIt squash_it = instList[tid].end(); 1229 --squash_it; 1230 1231 DPRINTF(IQ, "[tid:%i] Squashing until sequence number %i!\n", 1232 tid, squashedSeqNum[tid]); 1233 1234 // Squash any instructions younger than the squashed sequence number 1235 // given. 1236 while (squash_it != instList[tid].end() && 1237 (*squash_it)->seqNum > squashedSeqNum[tid]) { 1238 1239 DynInstPtr squashed_inst = (*squash_it); 1240 if (squashed_inst->isFloating()) { 1241 fpInstQueueWrites++; 1242 } else if (squashed_inst->isVector()) { 1243 vecInstQueueWrites++; 1244 } else { 1245 intInstQueueWrites++; 1246 } 1247 1248 // Only handle the instruction if it actually is in the IQ and 1249 // hasn't already been squashed in the IQ. 1250 if (squashed_inst->threadNumber != tid || 1251 squashed_inst->isSquashedInIQ()) { 1252 --squash_it; 1253 continue; 1254 } 1255 1256 if (!squashed_inst->isIssued() || 1257 (squashed_inst->isMemRef() && 1258 !squashed_inst->memOpDone())) { 1259 1260 DPRINTF(IQ, "[tid:%i] Instruction [sn:%llu] PC %s squashed.\n", 1261 tid, squashed_inst->seqNum, squashed_inst->pcState()); 1262 1263 bool is_acq_rel = squashed_inst->isMemBarrier() && 1264 (squashed_inst->isLoad() || 1265 squashed_inst->isAtomic() || 1266 (squashed_inst->isStore() && 1267 !squashed_inst->isStoreConditional())); 1268 1269 // Remove the instruction from the dependency list. 1270 if (is_acq_rel || 1271 (!squashed_inst->isNonSpeculative() && 1272 !squashed_inst->isStoreConditional() && 1273 !squashed_inst->isAtomic() && 1274 !squashed_inst->isMemBarrier() && 1275 !squashed_inst->isWriteBarrier())) { 1276 1277 for (int src_reg_idx = 0; 1278 src_reg_idx < squashed_inst->numSrcRegs(); 1279 src_reg_idx++) 1280 { 1281 PhysRegIdPtr src_reg = 1282 squashed_inst->renamedSrcRegIdx(src_reg_idx); 1283 1284 // Only remove it from the dependency graph if it 1285 // was placed there in the first place. 1286 1287 // Instead of doing a linked list traversal, we 1288 // can just remove these squashed instructions 1289 // either at issue time, or when the register is 1290 // overwritten. The only downside to this is it 1291 // leaves more room for error. 1292 1293 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 1294 !src_reg->isFixedMapping()) { 1295 dependGraph.remove(src_reg->flatIndex(), 1296 squashed_inst); 1297 } 1298 1299 ++iqSquashedOperandsExamined; 1300 } 1301 1302 } else if (!squashed_inst->isStoreConditional() || 1303 !squashed_inst->isCompleted()) { 1304 NonSpecMapIt ns_inst_it = 1305 nonSpecInsts.find(squashed_inst->seqNum); 1306 1307 // we remove non-speculative instructions from 1308 // nonSpecInsts already when they are ready, and so we 1309 // cannot always expect to find them 1310 if (ns_inst_it == nonSpecInsts.end()) { 1311 // loads that became ready but stalled on a 1312 // blocked cache are alreayd removed from 1313 // nonSpecInsts, and have not faulted 1314 assert(squashed_inst->getFault() != NoFault || 1315 squashed_inst->isMemRef()); 1316 } else { 1317 1318 (*ns_inst_it).second = NULL; 1319 1320 nonSpecInsts.erase(ns_inst_it); 1321 1322 ++iqSquashedNonSpecRemoved; 1323 } 1324 } 1325 1326 // Might want to also clear out the head of the dependency graph. 1327 1328 // Mark it as squashed within the IQ. 1329 squashed_inst->setSquashedInIQ(); 1330 1331 // @todo: Remove this hack where several statuses are set so the 1332 // inst will flow through the rest of the pipeline. 1333 squashed_inst->setIssued(); 1334 squashed_inst->setCanCommit(); 1335 squashed_inst->clearInIQ(); 1336 1337 //Update Thread IQ Count 1338 count[squashed_inst->threadNumber]--; 1339 1340 ++freeEntries; 1341 } 1342 1343 // IQ clears out the heads of the dependency graph only when 1344 // instructions reach writeback stage. If an instruction is squashed 1345 // before writeback stage, its head of dependency graph would not be 1346 // cleared out; it holds the instruction's DynInstPtr. This prevents 1347 // freeing the squashed instruction's DynInst. 1348 // Thus, we need to manually clear out the squashed instructions' heads 1349 // of dependency graph. 1350 for (int dest_reg_idx = 0; 1351 dest_reg_idx < squashed_inst->numDestRegs(); 1352 dest_reg_idx++) 1353 { 1354 PhysRegIdPtr dest_reg = 1355 squashed_inst->renamedDestRegIdx(dest_reg_idx); 1356 if (dest_reg->isFixedMapping()){ 1357 continue; 1358 } 1359 assert(dependGraph.empty(dest_reg->flatIndex())); 1360 dependGraph.clearInst(dest_reg->flatIndex()); 1361 } 1362 instList[tid].erase(squash_it--); 1363 ++iqSquashedInstsExamined; 1364 } 1365} 1366 1367template <class Impl> 1368bool 1369InstructionQueue<Impl>::addToDependents(const DynInstPtr &new_inst) 1370{ 1371 // Loop through the instruction's source registers, adding 1372 // them to the dependency list if they are not ready. 1373 int8_t total_src_regs = new_inst->numSrcRegs(); 1374 bool return_val = false; 1375 1376 for (int src_reg_idx = 0; 1377 src_reg_idx < total_src_regs; 1378 src_reg_idx++) 1379 { 1380 // Only add it to the dependency graph if it's not ready. 1381 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 1382 PhysRegIdPtr src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 1383 1384 // Check the IQ's scoreboard to make sure the register 1385 // hasn't become ready while the instruction was in flight 1386 // between stages. Only if it really isn't ready should 1387 // it be added to the dependency graph. 1388 if (src_reg->isFixedMapping()) { 1389 continue; 1390 } else if (!regScoreboard[src_reg->flatIndex()]) { 1391 DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that " 1392 "is being added to the dependency chain.\n", 1393 new_inst->pcState(), src_reg->index(), 1394 src_reg->className()); 1395 1396 dependGraph.insert(src_reg->flatIndex(), new_inst); 1397 1398 // Change the return value to indicate that something 1399 // was added to the dependency graph. 1400 return_val = true; 1401 } else { 1402 DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that " 1403 "became ready before it reached the IQ.\n", 1404 new_inst->pcState(), src_reg->index(), 1405 src_reg->className()); 1406 // Mark a register ready within the instruction. 1407 new_inst->markSrcRegReady(src_reg_idx); 1408 } 1409 } 1410 } 1411 1412 return return_val; 1413} 1414 1415template <class Impl> 1416void 1417InstructionQueue<Impl>::addToProducers(const DynInstPtr &new_inst) 1418{ 1419 // Nothing really needs to be marked when an instruction becomes 1420 // the producer of a register's value, but for convenience a ptr 1421 // to the producing instruction will be placed in the head node of 1422 // the dependency links. 1423 int8_t total_dest_regs = new_inst->numDestRegs(); 1424 1425 for (int dest_reg_idx = 0; 1426 dest_reg_idx < total_dest_regs; 1427 dest_reg_idx++) 1428 { 1429 PhysRegIdPtr dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 1430 1431 // Some registers have fixed mapping, and there is no need to track 1432 // dependencies as these instructions must be executed at commit. 1433 if (dest_reg->isFixedMapping()) { 1434 continue; 1435 } 1436 1437 if (!dependGraph.empty(dest_reg->flatIndex())) { 1438 dependGraph.dump(); 1439 panic("Dependency graph %i (%s) (flat: %i) not empty!", 1440 dest_reg->index(), dest_reg->className(), 1441 dest_reg->flatIndex()); 1442 } 1443 1444 dependGraph.setInst(dest_reg->flatIndex(), new_inst); 1445 1446 // Mark the scoreboard to say it's not yet ready. 1447 regScoreboard[dest_reg->flatIndex()] = false; 1448 } 1449} 1450 1451template <class Impl> 1452void 1453InstructionQueue<Impl>::addIfReady(const DynInstPtr &inst) 1454{ 1455 // If the instruction now has all of its source registers 1456 // available, then add it to the list of ready instructions. 1457 if (inst->readyToIssue()) { 1458 1459 //Add the instruction to the proper ready list. 1460 if (inst->isMemRef()) { 1461 1462 DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 1463 1464 // Message to the mem dependence unit that this instruction has 1465 // its registers ready. 1466 memDepUnit[inst->threadNumber].regsReady(inst); 1467 1468 return; 1469 } 1470 1471 OpClass op_class = inst->opClass(); 1472 1473 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 1474 "the ready list, PC %s opclass:%i [sn:%llu].\n", 1475 inst->pcState(), op_class, inst->seqNum); 1476 1477 readyInsts[op_class].push(inst); 1478 1479 // Will need to reorder the list if either a queue is not on the list, 1480 // or it has an older instruction than last time. 1481 if (!queueOnList[op_class]) { 1482 addToOrderList(op_class); 1483 } else if (readyInsts[op_class].top()->seqNum < 1484 (*readyIt[op_class]).oldestInst) { 1485 listOrder.erase(readyIt[op_class]); 1486 addToOrderList(op_class); 1487 } 1488 } 1489} 1490 1491template <class Impl> 1492int 1493InstructionQueue<Impl>::countInsts() 1494{ 1495 return numEntries - freeEntries; 1496} 1497 1498template <class Impl> 1499void 1500InstructionQueue<Impl>::dumpLists() 1501{ 1502 for (int i = 0; i < Num_OpClasses; ++i) { 1503 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 1504 1505 cprintf("\n"); 1506 } 1507 1508 cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 1509 1510 NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 1511 NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 1512 1513 cprintf("Non speculative list: "); 1514 1515 while (non_spec_it != non_spec_end_it) { 1516 cprintf("%s [sn:%llu]", (*non_spec_it).second->pcState(), 1517 (*non_spec_it).second->seqNum); 1518 ++non_spec_it; 1519 } 1520 1521 cprintf("\n"); 1522 1523 ListOrderIt list_order_it = listOrder.begin(); 1524 ListOrderIt list_order_end_it = listOrder.end(); 1525 int i = 1; 1526 1527 cprintf("List order: "); 1528 1529 while (list_order_it != list_order_end_it) { 1530 cprintf("%i OpClass:%i [sn:%llu] ", i, (*list_order_it).queueType, 1531 (*list_order_it).oldestInst); 1532 1533 ++list_order_it; 1534 ++i; 1535 } 1536 1537 cprintf("\n"); 1538} 1539 1540 1541template <class Impl> 1542void 1543InstructionQueue<Impl>::dumpInsts() 1544{ 1545 for (ThreadID tid = 0; tid < numThreads; ++tid) { 1546 int num = 0; 1547 int valid_num = 0; 1548 ListIt inst_list_it = instList[tid].begin(); 1549 1550 while (inst_list_it != instList[tid].end()) { 1551 cprintf("Instruction:%i\n", num); 1552 if (!(*inst_list_it)->isSquashed()) { 1553 if (!(*inst_list_it)->isIssued()) { 1554 ++valid_num; 1555 cprintf("Count:%i\n", valid_num); 1556 } else if ((*inst_list_it)->isMemRef() && 1557 !(*inst_list_it)->memOpDone()) { 1558 // Loads that have not been marked as executed 1559 // still count towards the total instructions. 1560 ++valid_num; 1561 cprintf("Count:%i\n", valid_num); 1562 } 1563 } 1564 1565 cprintf("PC: %s\n[sn:%llu]\n[tid:%i]\n" 1566 "Issued:%i\nSquashed:%i\n", 1567 (*inst_list_it)->pcState(), 1568 (*inst_list_it)->seqNum, 1569 (*inst_list_it)->threadNumber, 1570 (*inst_list_it)->isIssued(), 1571 (*inst_list_it)->isSquashed()); 1572 1573 if ((*inst_list_it)->isMemRef()) { 1574 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 1575 } 1576 1577 cprintf("\n"); 1578 1579 inst_list_it++; 1580 ++num; 1581 } 1582 } 1583 1584 cprintf("Insts to Execute list:\n"); 1585 1586 int num = 0; 1587 int valid_num = 0; 1588 ListIt inst_list_it = instsToExecute.begin(); 1589 1590 while (inst_list_it != instsToExecute.end()) 1591 { 1592 cprintf("Instruction:%i\n", 1593 num); 1594 if (!(*inst_list_it)->isSquashed()) { 1595 if (!(*inst_list_it)->isIssued()) { 1596 ++valid_num; 1597 cprintf("Count:%i\n", valid_num); 1598 } else if ((*inst_list_it)->isMemRef() && 1599 !(*inst_list_it)->memOpDone()) { 1600 // Loads that have not been marked as executed 1601 // still count towards the total instructions. 1602 ++valid_num; 1603 cprintf("Count:%i\n", valid_num); 1604 } 1605 } 1606 1607 cprintf("PC: %s\n[sn:%llu]\n[tid:%i]\n" 1608 "Issued:%i\nSquashed:%i\n", 1609 (*inst_list_it)->pcState(), 1610 (*inst_list_it)->seqNum, 1611 (*inst_list_it)->threadNumber, 1612 (*inst_list_it)->isIssued(), 1613 (*inst_list_it)->isSquashed()); 1614 1615 if ((*inst_list_it)->isMemRef()) { 1616 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 1617 } 1618 1619 cprintf("\n"); 1620 1621 inst_list_it++; 1622 ++num; 1623 } 1624} 1625 1626#endif//__CPU_O3_INST_QUEUE_IMPL_HH__ 1627