inst_queue_impl.hh revision 13610
11689SN/A/* 22326SN/A * Copyright (c) 2011-2014, 2017-2018 ARM Limited 31689SN/A * Copyright (c) 2013 Advanced Micro Devices, Inc. 41689SN/A * All rights reserved. 51689SN/A * 61689SN/A * The license below extends only to copyright in the software and shall 71689SN/A * not be construed as granting a license to any other intellectual 81689SN/A * property including but not limited to intellectual property relating 91689SN/A * to a hardware implementation of the functionality of the software 101689SN/A * licensed hereunder. You may use the software subject to the license 111689SN/A * terms below provided that you ensure that this notice is replicated 121689SN/A * unmodified and in its entirety in all distributions of the software, 131689SN/A * modified or unmodified, in source code or in binary form. 141689SN/A * 151689SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 272665Ssaidi@eecs.umich.edu * this software without specific prior written permission. 282665Ssaidi@eecs.umich.edu * 292831Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322064SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351696SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381717SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 401061SN/A * 412292SN/A * Authors: Kevin Lim 422292SN/A * Korey Sewell 432292SN/A */ 442292SN/A 452326SN/A#ifndef __CPU_O3_INST_QUEUE_IMPL_HH__ 461060SN/A#define __CPU_O3_INST_QUEUE_IMPL_HH__ 472292SN/A 482292SN/A#include <limits> 492292SN/A#include <vector> 502292SN/A 512292SN/A#include "base/logging.hh" 522292SN/A#include "cpu/o3/fu_pool.hh" 532292SN/A#include "cpu/o3/inst_queue.hh" 542326SN/A#include "debug/IQ.hh" 552292SN/A#include "enums/OpClass.hh" 562292SN/A#include "params/DerivO3CPU.hh" 572292SN/A#include "sim/core.hh" 582292SN/A 592292SN/A// clang complains about std::set being overloaded with Packet::set if 602292SN/A// we open up the entire namespace std 612292SN/Ausing std::list; 622292SN/A 632292SN/Atemplate <class Impl> 642292SN/AInstructionQueue<Impl>::FUCompletion::FUCompletion(const DynInstPtr &_inst, 652292SN/A int fu_idx, InstructionQueue<Impl> *iq_ptr) 662292SN/A : Event(Stat_Event_Pri, AutoDelete), 672292SN/A inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 682669Sktlim@umich.edu{ 692292SN/A} 702292SN/A 712292SN/Atemplate <class Impl> 722292SN/Avoid 732292SN/AInstructionQueue<Impl>::FUCompletion::process() 742292SN/A{ 752292SN/A iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 762292SN/A inst = NULL; 772307SN/A} 782307SN/A 792292SN/A 801060SN/Atemplate <class Impl> 811060SN/Aconst char * 821060SN/AInstructionQueue<Impl>::FUCompletion::description() const 831060SN/A{ 842292SN/A return "Functional unit completion"; 851060SN/A} 861060SN/A 871060SN/Atemplate <class Impl> 882326SN/AInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 891060SN/A DerivO3CPUParams *params) 901060SN/A : cpu(cpu_ptr), 911060SN/A iewStage(iew_ptr), 921060SN/A fuPool(params->fuPool), 932292SN/A iqPolicy(params->smtIQPolicy), 942292SN/A numEntries(params->numIQEntries), 952292SN/A totalWidth(params->issueWidth), 962292SN/A commitToIEWDelay(params->commitToIEWDelay) 971060SN/A{ 981060SN/A assert(fuPool); 992307SN/A 1002292SN/A numThreads = params->numThreads; 1012980Sgblack@eecs.umich.edu 1022292SN/A // Set the number of total physical registers 1032292SN/A // As the vector registers have two addressing modes, they are added twice 1042292SN/A numPhysRegs = params->numPhysIntRegs + params->numPhysFloatRegs + 1052292SN/A params->numPhysVecRegs + 1062292SN/A params->numPhysVecRegs * TheISA::NumVecElemPerVecReg + 1072292SN/A params->numPhysVecPredRegs + 1082292SN/A params->numPhysCCRegs; 1092292SN/A 1102292SN/A //Create an entry for each physical register within the 1112292SN/A //dependency graph. 1122292SN/A dependGraph.resize(numPhysRegs); 1132292SN/A 1142292SN/A // Resize the register scoreboard. 1152292SN/A regScoreboard.resize(numPhysRegs); 1162292SN/A 1172292SN/A //Initialize Mem Dependence Units 1182292SN/A for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 1192292SN/A memDepUnit[tid].init(params, tid); 1202292SN/A memDepUnit[tid].setIQ(this); 1212292SN/A } 1222292SN/A 1232292SN/A resetState(); 1242292SN/A 1252292SN/A //Figure out resource sharing policy 1262292SN/A if (iqPolicy == SMTQueuePolicy::Dynamic) { 1272831Sksewell@umich.edu //Set Max Entries to Total ROB Capacity 1282292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1292292SN/A maxEntries[tid] = numEntries; 1302292SN/A } 1312292SN/A 1322292SN/A } else if (iqPolicy == SMTQueuePolicy::Partitioned) { 1332292SN/A //@todo:make work if part_amt doesnt divide evenly. 1342292SN/A int part_amt = numEntries / numThreads; 1352292SN/A 1362292SN/A //Divide ROB up evenly 1372292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1382292SN/A maxEntries[tid] = part_amt; 1392292SN/A } 1402292SN/A 1412292SN/A DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 1422831Sksewell@umich.edu "%i entries per thread.\n",part_amt); 1432292SN/A } else if (iqPolicy == SMTQueuePolicy::Threshold) { 1442292SN/A double threshold = (double)params->smtIQThreshold / 100; 1452292SN/A 1462292SN/A int thresholdIQ = (int)((double)threshold * numEntries); 1472292SN/A 1482292SN/A //Divide up by threshold amount 1492292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1502292SN/A maxEntries[tid] = thresholdIQ; 1512292SN/A } 1522292SN/A 1532326SN/A DPRINTF(IQ, "IQ sharing policy set to Threshold:" 1542348SN/A "%i entries per thread.\n",thresholdIQ); 1552326SN/A } 1562326SN/A for (ThreadID tid = numThreads; tid < Impl::MaxThreads; tid++) { 1572348SN/A maxEntries[tid] = 0; 1582292SN/A } 1592292SN/A} 1602292SN/A 1612292SN/Atemplate <class Impl> 1622292SN/AInstructionQueue<Impl>::~InstructionQueue() 1632292SN/A{ 1642292SN/A dependGraph.reset(); 1651060SN/A#ifdef DEBUG 1661060SN/A cprintf("Nodes traversed: %i, removed: %i\n", 1671061SN/A dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1681060SN/A#endif 1691062SN/A} 1701062SN/A 1712301SN/Atemplate <class Impl> 1721062SN/Astd::string 1731062SN/AInstructionQueue<Impl>::name() const 1741062SN/A{ 1751062SN/A return cpu->name() + ".iq"; 1761062SN/A} 1771062SN/A 1781062SN/Atemplate <class Impl> 1791062SN/Avoid 1801062SN/AInstructionQueue<Impl>::regStats() 1811062SN/A{ 1822301SN/A using namespace Stats; 1832301SN/A iqInstsAdded 1842301SN/A .name(name() + ".iqInstsAdded") 1852301SN/A .desc("Number of instructions added to the IQ (excludes non-spec)") 1861062SN/A .prereq(iqInstsAdded); 1871062SN/A 1881062SN/A iqNonSpecInstsAdded 1891062SN/A .name(name() + ".iqNonSpecInstsAdded") 1901062SN/A .desc("Number of non-speculative instructions added to the IQ") 1911062SN/A .prereq(iqNonSpecInstsAdded); 1921062SN/A 1931062SN/A iqInstsIssued 1941062SN/A .name(name() + ".iqInstsIssued") 1951062SN/A .desc("Number of instructions issued") 1961062SN/A .prereq(iqInstsIssued); 1971062SN/A 1981062SN/A iqIntInstsIssued 1991062SN/A .name(name() + ".iqIntInstsIssued") 2001062SN/A .desc("Number of integer instructions issued") 2011062SN/A .prereq(iqIntInstsIssued); 2021062SN/A 2031062SN/A iqFloatInstsIssued 2041062SN/A .name(name() + ".iqFloatInstsIssued") 2051062SN/A .desc("Number of float instructions issued") 2061062SN/A .prereq(iqFloatInstsIssued); 2071062SN/A 2081062SN/A iqBranchInstsIssued 2091062SN/A .name(name() + ".iqBranchInstsIssued") 2101062SN/A .desc("Number of branch instructions issued") 2111062SN/A .prereq(iqBranchInstsIssued); 2121062SN/A 2131062SN/A iqMemInstsIssued 2141062SN/A .name(name() + ".iqMemInstsIssued") 2151062SN/A .desc("Number of memory instructions issued") 2161062SN/A .prereq(iqMemInstsIssued); 2171062SN/A 2181062SN/A iqMiscInstsIssued 2191062SN/A .name(name() + ".iqMiscInstsIssued") 2201062SN/A .desc("Number of miscellaneous instructions issued") 2211062SN/A .prereq(iqMiscInstsIssued); 2221062SN/A 2231062SN/A iqSquashedInstsIssued 2241062SN/A .name(name() + ".iqSquashedInstsIssued") 2251062SN/A .desc("Number of squashed instructions issued") 2261062SN/A .prereq(iqSquashedInstsIssued); 2271062SN/A 2281062SN/A iqSquashedInstsExamined 2291062SN/A .name(name() + ".iqSquashedInstsExamined") 2301062SN/A .desc("Number of squashed instructions iterated over during squash;" 2311062SN/A " mainly for profiling") 2321062SN/A .prereq(iqSquashedInstsExamined); 2331062SN/A 2342326SN/A iqSquashedOperandsExamined 2352301SN/A .name(name() + ".iqSquashedOperandsExamined") 2362301SN/A .desc("Number of squashed operands that are examined and possibly " 2372301SN/A "removed from graph") 2382301SN/A .prereq(iqSquashedOperandsExamined); 2392301SN/A 2402301SN/A iqSquashedNonSpecRemoved 2412326SN/A .name(name() + ".iqSquashedNonSpecRemoved") 2422301SN/A .desc("Number of squashed non-spec instructions that were removed") 2432326SN/A .prereq(iqSquashedNonSpecRemoved); 2442307SN/A/* 2452301SN/A queueResDist 2462301SN/A .init(Num_OpClasses, 0, 99, 2) 2472307SN/A .name(name() + ".IQ:residence:") 2482301SN/A .desc("cycles from dispatch to issue") 2492301SN/A .flags(total | pdf | cdf ) 2502301SN/A ; 2512301SN/A for (int i = 0; i < Num_OpClasses; ++i) { 2522301SN/A queueResDist.subname(i, opClassStrings[i]); 2532301SN/A } 2542301SN/A*/ 2552301SN/A numIssuedDist 2562301SN/A .init(0,totalWidth,1) 2572301SN/A .name(name() + ".issued_per_cycle") 2582301SN/A .desc("Number of insts issued each cycle") 2592301SN/A .flags(pdf) 2602326SN/A ; 2612301SN/A/* 2622301SN/A dist_unissued 2632301SN/A .init(Num_OpClasses+2) 2642301SN/A .name(name() + ".unissued_cause") 2652301SN/A .desc("Reason ready instruction not issued") 2662326SN/A .flags(pdf | dist) 2672301SN/A ; 2682301SN/A for (int i=0; i < (Num_OpClasses + 2); ++i) { 2692301SN/A dist_unissued.subname(i, unissued_names[i]); 2702301SN/A } 2712301SN/A*/ 2722326SN/A statIssuedInstType 2732301SN/A .init(numThreads,Enums::Num_OpClass) 2742301SN/A .name(name() + ".FU_type") 2752301SN/A .desc("Type of FU issued") 2762301SN/A .flags(total | pdf | dist) 2772301SN/A ; 2782301SN/A statIssuedInstType.ysubnames(Enums::OpClassStrings); 2792301SN/A 2802980Sgblack@eecs.umich.edu // 2812301SN/A // How long did instructions for a particular FU type wait prior to issue 2822326SN/A // 2832301SN/A/* 2842301SN/A issueDelayDist 2852326SN/A .init(Num_OpClasses,0,99,2) 2862301SN/A .name(name() + ".") 2872301SN/A .desc("cycles from operands ready to issue") 2882301SN/A .flags(pdf | cdf) 2892301SN/A ; 2902326SN/A 2912727Sktlim@umich.edu for (int i=0; i<Num_OpClasses; ++i) { 2922326SN/A std::stringstream subname; 2932301SN/A subname << opClassStrings[i] << "_delay"; 2942301SN/A issueDelayDist.subname(i, subname.str()); 2952301SN/A } 2962301SN/A*/ 2972301SN/A issueRate 2982301SN/A .name(name() + ".rate") 2992326SN/A .desc("Inst issue rate") 3002301SN/A .flags(total) 3012301SN/A ; 3022326SN/A issueRate = iqInstsIssued / cpu->numCycles; 3032301SN/A 3042301SN/A statFuBusy 3052301SN/A .init(Num_OpClasses) 3062301SN/A .name(name() + ".fu_full") 3072301SN/A .desc("attempts to use FU when none available") 3082301SN/A .flags(pdf | dist) 3092326SN/A ; 3102301SN/A for (int i=0; i < Num_OpClasses; ++i) { 3112301SN/A statFuBusy.subname(i, Enums::OpClassStrings[i]); 3122301SN/A } 3132301SN/A 3142326SN/A fuBusy 3152301SN/A .init(numThreads) 3162292SN/A .name(name() + ".fu_busy_cnt") 3172292SN/A .desc("FU busy when requested") 3182292SN/A .flags(total) 3192292SN/A ; 3201062SN/A 3211062SN/A fuBusyRate 3221062SN/A .name(name() + ".fu_busy_rate") 3231062SN/A .desc("FU busy rate (busy events/executed inst)") 3242307SN/A .flags(total) 3251060SN/A ; 3262307SN/A fuBusyRate = fuBusy / iqInstsIssued; 3272307SN/A 3282307SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 3292307SN/A // Tell mem dependence unit to reg stats as well. 3302307SN/A memDepUnit[tid].regStats(); 3311060SN/A } 3322307SN/A 3332307SN/A intInstQueueReads 3342307SN/A .name(name() + ".int_inst_queue_reads") 3352307SN/A .desc("Number of integer instruction queue reads") 3362307SN/A .flags(total); 3372307SN/A 3382307SN/A intInstQueueWrites 3392307SN/A .name(name() + ".int_inst_queue_writes") 3402307SN/A .desc("Number of integer instruction queue writes") 3412307SN/A .flags(total); 3422307SN/A 3432307SN/A intInstQueueWakeupAccesses 3442307SN/A .name(name() + ".int_inst_queue_wakeup_accesses") 3452307SN/A .desc("Number of integer instruction queue wakeup accesses") 3462307SN/A .flags(total); 3472307SN/A 3482307SN/A fpInstQueueReads 3492307SN/A .name(name() + ".fp_inst_queue_reads") 3502307SN/A .desc("Number of floating instruction queue reads") 3512307SN/A .flags(total); 3522307SN/A 3532307SN/A fpInstQueueWrites 3542307SN/A .name(name() + ".fp_inst_queue_writes") 3552307SN/A .desc("Number of floating instruction queue writes") 3561060SN/A .flags(total); 3571060SN/A 3581061SN/A fpInstQueueWakeupAccesses 3591060SN/A .name(name() + ".fp_inst_queue_wakeup_accesses") 3602980Sgblack@eecs.umich.edu .desc("Number of floating instruction queue wakeup accesses") 3611060SN/A .flags(total); 3622292SN/A 3632292SN/A vecInstQueueReads 3642064SN/A .name(name() + ".vec_inst_queue_reads") 3652064SN/A .desc("Number of vector instruction queue reads") 3662064SN/A .flags(total); 3672064SN/A 3682292SN/A vecInstQueueWrites 3692064SN/A .name(name() + ".vec_inst_queue_writes") 3702292SN/A .desc("Number of vector instruction queue writes") 3711060SN/A .flags(total); 3721060SN/A 3731060SN/A vecInstQueueWakeupAccesses 3741061SN/A .name(name() + ".vec_inst_queue_wakeup_accesses") 3751060SN/A .desc("Number of vector instruction queue wakeup accesses") 3761060SN/A .flags(total); 3771060SN/A 3782292SN/A intAluAccesses 3791060SN/A .name(name() + ".int_alu_accesses") 3801060SN/A .desc("Number of integer alu accesses") 3811060SN/A .flags(total); 3821060SN/A 3831060SN/A fpAluAccesses 3841684SN/A .name(name() + ".fp_alu_accesses") 3852307SN/A .desc("Number of floating point alu accesses") 3862307SN/A .flags(total); 3872307SN/A 3882307SN/A vecAluAccesses 3892326SN/A .name(name() + ".vec_alu_accesses") 3902307SN/A .desc("Number of vector alu accesses") 3912307SN/A .flags(total); 3922307SN/A 3932307SN/A} 3942307SN/A 3952307SN/Atemplate <class Impl> 3962307SN/Avoid 3972307SN/AInstructionQueue<Impl>::resetState() 3982307SN/A{ 3992307SN/A //Initialize thread IQ counts 4002307SN/A for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 4012307SN/A count[tid] = 0; 4022307SN/A instList[tid].clear(); 4032307SN/A } 4042292SN/A 4052292SN/A // Initialize the number of free IQ entries. 4062292SN/A freeEntries = numEntries; 4072292SN/A 4082292SN/A // Note that in actuality, the registers corresponding to the logical 4092292SN/A // registers start off as ready. However this doesn't matter for the 4102292SN/A // IQ as the instruction should have been correctly told if those 4112292SN/A // registers are ready in rename. Thus it can all be initialized as 4122292SN/A // unready. 4132292SN/A for (int i = 0; i < numPhysRegs; ++i) { 4142292SN/A regScoreboard[i] = false; 4152292SN/A } 4162292SN/A 4172292SN/A for (ThreadID tid = 0; tid < Impl::MaxThreads; ++tid) { 4182292SN/A squashedSeqNum[tid] = 0; 4192292SN/A } 4202292SN/A 4212292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 4222980Sgblack@eecs.umich.edu while (!readyInsts[i].empty()) 4232980Sgblack@eecs.umich.edu readyInsts[i].pop(); 4242292SN/A queueOnList[i] = false; 4252292SN/A readyIt[i] = listOrder.end(); 4262292SN/A } 4272292SN/A nonSpecInsts.clear(); 4282292SN/A listOrder.clear(); 4292292SN/A deferredMemInsts.clear(); 4302292SN/A blockedMemInsts.clear(); 4312292SN/A retryMemInsts.clear(); 4322292SN/A wbOutstanding = 0; 4332292SN/A} 4342292SN/A 4352292SN/Atemplate <class Impl> 4361684SN/Avoid 4371684SN/AInstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 4381684SN/A{ 4391684SN/A activeThreads = at_ptr; 4401684SN/A} 4411684SN/A 4422292SN/Atemplate <class Impl> 4432292SN/Avoid 4442292SN/AInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 4452292SN/A{ 4462292SN/A issueToExecuteQueue = i2e_ptr; 4472292SN/A} 4482292SN/A 4491060SN/Atemplate <class Impl> 4501060SN/Avoid 4511061SN/AInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 4521060SN/A{ 4531060SN/A timeBuffer = tb_ptr; 4541060SN/A 4551060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 4561060SN/A} 4571060SN/A 4581060SN/Atemplate <class Impl> 4591060SN/Abool 4601060SN/AInstructionQueue<Impl>::isDrained() const 4611060SN/A{ 4621061SN/A bool drained = dependGraph.empty() && 4632292SN/A instsToExecute.empty() && 4642292SN/A wbOutstanding == 0; 4652292SN/A for (ThreadID tid = 0; tid < numThreads; ++tid) 4662292SN/A drained = drained && memDepUnit[tid].isDrained(); 4672292SN/A 4682292SN/A return drained; 4692292SN/A} 4702292SN/A 4712292SN/Atemplate <class Impl> 4722292SN/Avoid 4732292SN/AInstructionQueue<Impl>::drainSanityCheck() const 4742292SN/A{ 4752292SN/A assert(dependGraph.empty()); 4762292SN/A assert(instsToExecute.empty()); 4772292SN/A for (ThreadID tid = 0; tid < numThreads; ++tid) 4782292SN/A memDepUnit[tid].drainSanityCheck(); 4792292SN/A} 4802292SN/A 4812292SN/Atemplate <class Impl> 4822292SN/Avoid 4832292SN/AInstructionQueue<Impl>::takeOverFrom() 4842292SN/A{ 4852292SN/A resetState(); 4862292SN/A} 4872292SN/A 4882292SN/Atemplate <class Impl> 4892292SN/Aint 4902292SN/AInstructionQueue<Impl>::entryAmount(ThreadID num_threads) 4911060SN/A{ 4921061SN/A if (iqPolicy == SMTQueuePolicy::Partitioned) { 4931060SN/A return numEntries / num_threads; 4941060SN/A } else { 4951060SN/A return 0; 4961060SN/A } 4972326SN/A} 4982326SN/A 4991060SN/A 5001060SN/Atemplate <class Impl> 5011060SN/Avoid 5022292SN/AInstructionQueue<Impl>::resetEntries() 5031060SN/A{ 5042064SN/A if (iqPolicy != SMTQueuePolicy::Dynamic || numThreads > 1) { 5051060SN/A int active_threads = activeThreads->size(); 5062292SN/A 5071060SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 5081060SN/A list<ThreadID>::iterator end = activeThreads->end(); 5091060SN/A 5101060SN/A while (threads != end) { 5111060SN/A ThreadID tid = *threads++; 5121060SN/A 5131060SN/A if (iqPolicy == SMTQueuePolicy::Partitioned) { 5142326SN/A maxEntries[tid] = numEntries / active_threads; 5151060SN/A } else if (iqPolicy == SMTQueuePolicy::Threshold && 5161061SN/A active_threads == 1) { 5172292SN/A maxEntries[tid] = numEntries; 5181062SN/A } 5191062SN/A } 5201061SN/A } 5211061SN/A} 5221062SN/A 5231060SN/Atemplate <class Impl> 5242292SN/Aunsigned 5252292SN/AInstructionQueue<Impl>::numFreeEntries() 5261060SN/A{ 5271060SN/A return freeEntries; 5281060SN/A} 5291061SN/A 5301061SN/Atemplate <class Impl> 5312292SN/Aunsigned 5321061SN/AInstructionQueue<Impl>::numFreeEntries(ThreadID tid) 5331061SN/A{ 5341061SN/A return maxEntries[tid] - count[tid]; 5351061SN/A} 5362292SN/A 5371061SN/A// Might want to do something more complex if it knows how many instructions 5382292SN/A// will be issued this cycle. 5391061SN/Atemplate <class Impl> 5402326SN/Abool 5412326SN/AInstructionQueue<Impl>::isFull() 5422326SN/A{ 5432064SN/A if (freeEntries == 0) { 5441061SN/A return(true); 5451061SN/A } else { 5462292SN/A return(false); 5471061SN/A } 5482064SN/A} 5491061SN/A 5502292SN/Atemplate <class Impl> 5511061SN/Abool 5521061SN/AInstructionQueue<Impl>::isFull(ThreadID tid) 5531061SN/A{ 5542326SN/A if (numFreeEntries(tid) == 0) { 5551061SN/A return(true); 5561061SN/A } else { 5571061SN/A return(false); 5582292SN/A } 5592292SN/A} 5601061SN/A 5611062SN/Atemplate <class Impl> 5621062SN/Abool 5632292SN/AInstructionQueue<Impl>::hasReadyInsts() 5642292SN/A{ 5652292SN/A if (!listOrder.empty()) { 5662292SN/A return true; 5671061SN/A } 5681061SN/A 5691061SN/A for (int i = 0; i < Num_OpClasses; ++i) { 5701060SN/A if (!readyInsts[i].empty()) { 5712292SN/A return true; 5721060SN/A } 5732292SN/A } 5741060SN/A 5752292SN/A return false; 5762292SN/A} 5771060SN/A 5782064SN/Atemplate <class Impl> 5792333SN/Avoid 5802333SN/AInstructionQueue<Impl>::insert(const DynInstPtr &new_inst) 5812333SN/A{ 5822333SN/A if (new_inst->isFloating()) { 5832333SN/A fpInstQueueWrites++; 5842333SN/A } else if (new_inst->isVector()) { 5852333SN/A vecInstQueueWrites++; 5862333SN/A } else { 5871060SN/A intInstQueueWrites++; 5882333SN/A } 5892064SN/A // Make sure the instruction is valid 5902292SN/A assert(new_inst); 5912292SN/A 5922292SN/A DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n", 5932292SN/A new_inst->seqNum, new_inst->pcState()); 5942292SN/A 5952292SN/A assert(freeEntries != 0); 5962292SN/A 5972292SN/A instList[new_inst->threadNumber].push_back(new_inst); 5982292SN/A 5992292SN/A --freeEntries; 6002292SN/A 6012292SN/A new_inst->setInIQ(); 6022292SN/A 6032292SN/A // Look through its source registers (physical regs), and mark any 6042292SN/A // dependencies. 6052292SN/A addToDependents(new_inst); 6062292SN/A 6072292SN/A // Have this instruction set itself as the producer of its destination 6082292SN/A // register(s). 6091060SN/A addToProducers(new_inst); 6101060SN/A 6112292SN/A if (new_inst->isMemRef()) { 6122292SN/A memDepUnit[new_inst->threadNumber].insert(new_inst); 6132292SN/A } else { 6141060SN/A addIfReady(new_inst); 6152292SN/A } 6162292SN/A 6172292SN/A ++iqInstsAdded; 6182292SN/A 6192292SN/A count[new_inst->threadNumber]++; 6202292SN/A 6212292SN/A assert(freeEntries == (numEntries - countInsts())); 6222292SN/A} 6232292SN/A 6242292SN/Atemplate <class Impl> 6252292SN/Avoid 6262292SN/AInstructionQueue<Impl>::insertNonSpec(const DynInstPtr &new_inst) 6272292SN/A{ 6282292SN/A // @todo: Clean up this code; can do it by setting inst as unable 6292292SN/A // to issue, then calling normal insert on the inst. 6302292SN/A if (new_inst->isFloating()) { 6312292SN/A fpInstQueueWrites++; 6322292SN/A } else if (new_inst->isVector()) { 6332292SN/A vecInstQueueWrites++; 6342292SN/A } else { 6352292SN/A intInstQueueWrites++; 6361060SN/A } 6371060SN/A 6382292SN/A assert(new_inst); 6391060SN/A 6401060SN/A nonSpecInsts[new_inst->seqNum] = new_inst; 6412292SN/A 6422292SN/A DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s " 6432292SN/A "to the IQ.\n", 6442292SN/A new_inst->seqNum, new_inst->pcState()); 6452292SN/A 6462292SN/A assert(freeEntries != 0); 6472307SN/A 6482307SN/A instList[new_inst->threadNumber].push_back(new_inst); 6492307SN/A 6502307SN/A --freeEntries; 6512292SN/A 6522292SN/A new_inst->setInIQ(); 6532326SN/A 6542326SN/A // Have this instruction set itself as the producer of its destination 6552292SN/A // register(s). 6562326SN/A addToProducers(new_inst); 6572326SN/A 6582326SN/A // If it's a memory instruction, add it to the memory dependency 6592333SN/A // unit. 6602333SN/A if (new_inst->isMemRef()) { 6612292SN/A memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 6622292SN/A } 6631061SN/A 6641061SN/A ++iqNonSpecInstsAdded; 6651061SN/A 6661061SN/A count[new_inst->threadNumber]++; 6671060SN/A 6681060SN/A assert(freeEntries == (numEntries - countInsts())); 6691060SN/A} 6702292SN/A 6712292SN/Atemplate <class Impl> 6721060SN/Avoid 6731060SN/AInstructionQueue<Impl>::insertBarrier(const DynInstPtr &barr_inst) 6741060SN/A{ 6752292SN/A memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 6762292SN/A 6772292SN/A insertNonSpec(barr_inst); 6782292SN/A} 6792292SN/A 6802292SN/Atemplate <class Impl> 6812292SN/Atypename Impl::DynInstPtr 6822292SN/AInstructionQueue<Impl>::getInstToExecute() 6832292SN/A{ 6842292SN/A assert(!instsToExecute.empty()); 6852292SN/A DynInstPtr inst = std::move(instsToExecute.front()); 6861060SN/A instsToExecute.pop_front(); 6872333SN/A if (inst->isFloating()) { 6882820Sktlim@umich.edu fpInstQueueReads++; 6892326SN/A } else if (inst->isVector()) { 6902292SN/A vecInstQueueReads++; 6911060SN/A } else { 6922292SN/A intInstQueueReads++; 6931060SN/A } 6942292SN/A return inst; 6951060SN/A} 6962292SN/A 6971060SN/Atemplate <class Impl> 6982292SN/Avoid 6992292SN/AInstructionQueue<Impl>::addToOrderList(OpClass op_class) 7001060SN/A{ 7012292SN/A assert(!readyInsts[op_class].empty()); 7022292SN/A 7032292SN/A ListOrderEntry queue_entry; 7042292SN/A 7052292SN/A queue_entry.queueType = op_class; 7061060SN/A 7071060SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 7082292SN/A 7091060SN/A ListOrderIt list_it = listOrder.begin(); 7102292SN/A ListOrderIt list_end_it = listOrder.end(); 7112292SN/A 7122292SN/A while (list_it != list_end_it) { 7131060SN/A if ((*list_it).oldestInst > queue_entry.oldestInst) { 7141060SN/A break; 7152326SN/A } 7162326SN/A 7172301SN/A list_it++; 7181060SN/A } 7192326SN/A 7202326SN/A readyIt[op_class] = listOrder.insert(list_it, queue_entry); 7211060SN/A queueOnList[op_class] = true; 7222326SN/A} 7232326SN/A 7241060SN/Atemplate <class Impl> 7251060SN/Avoid 7261060SN/AInstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 7272348SN/A{ 7282348SN/A // Get iterator of next item on the list 7292326SN/A // Delete the original iterator 7302292SN/A // Determine if the next item is either the end of the list or younger 7312292SN/A // than the new instruction. If so, then add in a new iterator right here. 7322333SN/A // If not, then move along. 7331060SN/A ListOrderEntry queue_entry; 7342326SN/A OpClass op_class = (*list_order_it).queueType; 7352326SN/A ListOrderIt next_it = list_order_it; 7362326SN/A 7372326SN/A ++next_it; 7382292SN/A 7392292SN/A queue_entry.queueType = op_class; 7402326SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 7412326SN/A 7422326SN/A while (next_it != listOrder.end() && 7431060SN/A (*next_it).oldestInst < queue_entry.oldestInst) { 7442326SN/A ++next_it; 7451060SN/A } 7462326SN/A 7472292SN/A readyIt[op_class] = listOrder.insert(next_it, queue_entry); 7482348SN/A} 7492348SN/A 7502326SN/Atemplate <class Impl> 7512292SN/Avoid 7522292SN/AInstructionQueue<Impl>::processFUCompletion(const DynInstPtr &inst, int fu_idx) 7532326SN/A{ 7542292SN/A DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 7551060SN/A assert(!cpu->switchedOut()); 7561060SN/A // The CPU could have been sleeping until this op completed (*extremely* 7572292SN/A // long latency op). Wake it if it was. This may be overkill. 7582292SN/A --wbOutstanding; 7592301SN/A iewStage->wakeCPU(); 7602292SN/A 7611060SN/A if (fu_idx > -1) 7622292SN/A fuPool->freeUnitNextCycle(fu_idx); 7631061SN/A 7642292SN/A // @todo: Ensure that these FU Completions happen at the beginning 7652292SN/A // of a cycle, otherwise they could add too many instructions to 7662292SN/A // the queue. 7672292SN/A issueToExecuteQueue->access(-1)->size++; 7682292SN/A instsToExecute.push_back(inst); 7691060SN/A} 7701060SN/A 7712064SN/A// @todo: Figure out a better way to remove the squashed items from the 7722292SN/A// lists. Checking the top item of each list to see if it's squashed 7732064SN/A// wastes time and forces jumps. 7742292SN/Atemplate <class Impl> 7752292SN/Avoid 7762292SN/AInstructionQueue<Impl>::scheduleReadyInsts() 7772292SN/A{ 7782301SN/A DPRINTF(IQ, "Attempting to schedule ready instructions from " 7792731Sktlim@umich.edu "the IQ.\n"); 7802292SN/A 7812301SN/A IssueStruct *i2e_info = issueToExecuteQueue->access(0); 7822292SN/A 7832292SN/A DynInstPtr mem_inst; 7842292SN/A while (mem_inst = std::move(getDeferredMemInstToExecute())) { 7852326SN/A addReadyMemInst(mem_inst); 7862820Sktlim@umich.edu } 7872292SN/A 7882326SN/A // See if any cache blocked instructions are able to be executed 7892326SN/A while (mem_inst = std::move(getBlockedMemInstToExecute())) { 7902292SN/A addReadyMemInst(mem_inst); 7911060SN/A } 7921060SN/A 7931062SN/A // Have iterator to head of the list 7942326SN/A // While I haven't exceeded bandwidth or reached the end of the list, 7952326SN/A // Try to get a FU that can do what this op needs. 7962307SN/A // If successful, change the oldestInst to the new top of the list, put 7972348SN/A // the queue in the proper place in the list. 7982292SN/A // Increment the iterator. 7992292SN/A // This will avoid trying to schedule a certain op class if there are no 8002292SN/A // FUs that handle it. 8012292SN/A int total_issued = 0; 8022292SN/A ListOrderIt order_it = listOrder.begin(); 8031060SN/A ListOrderIt order_end_it = listOrder.end(); 8041060SN/A 8051061SN/A while (total_issued < totalWidth && order_it != order_end_it) { 8061060SN/A OpClass op_class = (*order_it).queueType; 8071061SN/A 8081060SN/A assert(!readyInsts[op_class].empty()); 8092292SN/A 8102292SN/A DynInstPtr issuing_inst = readyInsts[op_class].top(); 8111062SN/A 8122292SN/A if (issuing_inst->isFloating()) { 8131060SN/A fpInstQueueReads++; 8141061SN/A } else if (issuing_inst->isVector()) { 8151060SN/A vecInstQueueReads++; 8162292SN/A } else { 8172292SN/A intInstQueueReads++; 8181061SN/A } 8191060SN/A 8201062SN/A assert(issuing_inst->seqNum == (*order_it).oldestInst); 8211062SN/A 8221062SN/A if (issuing_inst->isSquashed()) { 8232292SN/A readyInsts[op_class].pop(); 8241062SN/A 8251060SN/A if (!readyInsts[op_class].empty()) { 8262292SN/A moveToYoungerInst(order_it); 8272292SN/A } else { 8281061SN/A readyIt[op_class] = listOrder.end(); 8291060SN/A queueOnList[op_class] = false; 8301060SN/A } 8311061SN/A 8321061SN/A listOrder.erase(order_it++); 8332292SN/A 8342292SN/A ++iqSquashedInstsIssued; 8352292SN/A 8362292SN/A continue; 8372292SN/A } 8382292SN/A 8392292SN/A int idx = FUPool::NoCapableFU; 8402292SN/A Cycles op_latency = Cycles(1); 8412292SN/A ThreadID tid = issuing_inst->threadNumber; 8422292SN/A 8432292SN/A if (op_class != No_OpClass) { 8442292SN/A idx = fuPool->getUnit(op_class); 8452292SN/A if (issuing_inst->isFloating()) { 8462292SN/A fpAluAccesses++; 8472292SN/A } else if (issuing_inst->isVector()) { 8482292SN/A vecAluAccesses++; 8492292SN/A } else { 8502301SN/A intAluAccesses++; 8511684SN/A } 8521684SN/A if (idx > FUPool::NoFreeFU) { 8532301SN/A op_latency = fuPool->getOpLatency(op_class); 8542301SN/A } 8552292SN/A } 8562292SN/A 8572292SN/A // If we have an instruction that doesn't require a FU, or a 8581684SN/A // valid FU, then schedule for execution. 8591684SN/A if (idx != FUPool::NoFreeFU) { 8602292SN/A if (op_latency == Cycles(1)) { 8612326SN/A i2e_info->size++; 8622326SN/A instsToExecute.push_back(issuing_inst); 8632326SN/A 8642326SN/A // Add the FU onto the list of FU's to be freed next 8651684SN/A // cycle if we used one. 8662292SN/A if (idx >= 0) 8672292SN/A fuPool->freeUnitNextCycle(idx); 8682292SN/A } else { 8692292SN/A bool pipelined = fuPool->isPipelined(op_class); 8702292SN/A // Generate completion event for the FU 8711684SN/A ++wbOutstanding; 8721684SN/A FUCompletion *execution = new FUCompletion(issuing_inst, 8731684SN/A idx, this); 8741684SN/A 8751684SN/A cpu->schedule(execution, 8761684SN/A cpu->clockEdge(Cycles(op_latency - 1))); 8771684SN/A 8781684SN/A if (!pipelined) { 8791684SN/A // If FU isn't pipelined, then it must be freed 8801684SN/A // upon the execution completing. 8811684SN/A execution->setFreeFU(); 8821684SN/A } else { 8831684SN/A // Add the FU onto the list of FU's to be freed next cycle. 8841684SN/A fuPool->freeUnitNextCycle(idx); 8851684SN/A } 8861684SN/A } 8872292SN/A 8881684SN/A DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 8891684SN/A "[sn:%lli]\n", 8902326SN/A tid, issuing_inst->pcState(), 8912326SN/A issuing_inst->seqNum); 8922326SN/A 8931684SN/A readyInsts[op_class].pop(); 8942326SN/A 8952292SN/A if (!readyInsts[op_class].empty()) { 8962326SN/A moveToYoungerInst(order_it); 8971684SN/A } else { 8981684SN/A readyIt[op_class] = listOrder.end(); 8992326SN/A queueOnList[op_class] = false; 9002326SN/A } 9012326SN/A 9022326SN/A issuing_inst->setIssued(); 9031684SN/A ++total_issued; 9042326SN/A 9051684SN/A#if TRACING_ON 9062326SN/A issuing_inst->issueTick = curTick() - issuing_inst->fetchTick; 9071684SN/A#endif 9082301SN/A 9091684SN/A if (!issuing_inst->isMemRef()) { 9101684SN/A // Memory instructions can not be freed from the IQ until they 9112326SN/A // complete. 9122326SN/A ++freeEntries; 9132326SN/A count[tid]--; 9142326SN/A issuing_inst->clearInIQ(); 9151684SN/A } else { 9161684SN/A memDepUnit[tid].issue(issuing_inst); 9171684SN/A } 9181684SN/A 9192301SN/A listOrder.erase(order_it++); 9202064SN/A statIssuedInstType[tid][op_class]++; 9212064SN/A } else { 9222064SN/A statFuBusy[op_class]++; 9232064SN/A fuBusy[tid]++; 9242292SN/A ++order_it; 9252064SN/A } 9262292SN/A } 9272292SN/A 9282292SN/A numIssuedDist.sample(total_issued); 9292292SN/A iqInstsIssued+= total_issued; 9302326SN/A 9312326SN/A // If we issued any instructions, tell the CPU we had activity. 9322326SN/A // @todo If the way deferred memory instructions are handeled due to 9332326SN/A // translation changes then the deferredMemInsts condition should be removed 9342326SN/A // from the code below. 9352326SN/A if (total_issued || !retryMemInsts.empty() || !deferredMemInsts.empty()) { 9362326SN/A cpu->activityThisCycle(); 9372326SN/A } else { 9382326SN/A DPRINTF(IQ, "Not able to schedule any instructions.\n"); 9392326SN/A } 9402292SN/A} 9412292SN/A 9422292SN/Atemplate <class Impl> 9432064SN/Avoid 9442064SN/AInstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 9452064SN/A{ 9462064SN/A DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 9472292SN/A "to execute.\n", inst); 9482064SN/A 9492292SN/A NonSpecMapIt inst_it = nonSpecInsts.find(inst); 9502064SN/A 9512064SN/A assert(inst_it != nonSpecInsts.end()); 9522064SN/A 9532064SN/A ThreadID tid = (*inst_it).second->threadNumber; 9542292SN/A 9552064SN/A (*inst_it).second->setAtCommit(); 9562292SN/A 9572292SN/A (*inst_it).second->setCanIssue(); 9582292SN/A 9592292SN/A if (!(*inst_it).second->isMemRef()) { 9602292SN/A addIfReady((*inst_it).second); 9612292SN/A } else { 9622292SN/A memDepUnit[tid].nonSpecInstReady((*inst_it).second); 9632292SN/A } 9642292SN/A 9652292SN/A (*inst_it).second = NULL; 9662292SN/A 9672292SN/A nonSpecInsts.erase(inst_it); 9682292SN/A} 9692292SN/A 9702292SN/Atemplate <class Impl> 9712292SN/Avoid 9722292SN/AInstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 9732292SN/A{ 9742292SN/A DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 9751684SN/A tid,inst); 9761684SN/A 9771684SN/A ListIt iq_it = instList[tid].begin(); 9781684SN/A 9791061SN/A while (iq_it != instList[tid].end() && 9801061SN/A (*iq_it)->seqNum <= inst) { 9811061SN/A ++iq_it; 9822292SN/A instList[tid].pop_front(); 9831061SN/A } 9841061SN/A 9851061SN/A assert(freeEntries == (numEntries - countInsts())); 9861060SN/A} 9872292SN/A 9881060SN/Atemplate <class Impl> 9892292SN/Aint 9902292SN/AInstructionQueue<Impl>::wakeDependents(const DynInstPtr &completed_inst) 9911060SN/A{ 9921060SN/A int dependents = 0; 9931060SN/A 9942935Sksewell@umich.edu // The instruction queue here takes care of both floating and int ops 9952292SN/A if (completed_inst->isFloating()) { 9962935Sksewell@umich.edu fpInstQueueWakeupAccesses++; 9972935Sksewell@umich.edu } else if (completed_inst->isVector()) { 9982935Sksewell@umich.edu vecInstQueueWakeupAccesses++; 9991060SN/A } else { 10001681SN/A intInstQueueWakeupAccesses++; 10012292SN/A } 10022292SN/A 10031681SN/A DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 10041061SN/A 10051061SN/A assert(!completed_inst->isSquashed()); 10062292SN/A 10071060SN/A // Tell the memory dependence unit to wake any dependents on this 10081060SN/A // instruction if it is a memory instruction. Also complete the memory 10091061SN/A // instruction at this point since we know it executed without issues. 10101061SN/A // @todo: Might want to rename "completeMemInst" to something that 10112292SN/A // indicates that it won't need to be replayed, and call this 10121061SN/A // earlier. Might not be a big deal. 10132326SN/A if (completed_inst->isMemRef()) { 10142326SN/A memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 10152326SN/A completeMemInst(completed_inst); 10161061SN/A } else if (completed_inst->isMemBarrier() || 10172292SN/A completed_inst->isWriteBarrier()) { 10182292SN/A memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 10191061SN/A } 10201061SN/A 10211061SN/A for (int dest_reg_idx = 0; 10222326SN/A dest_reg_idx < completed_inst->numDestRegs(); 10232326SN/A dest_reg_idx++) 10242292SN/A { 10252326SN/A PhysRegIdPtr dest_reg = 10261061SN/A completed_inst->renamedDestRegIdx(dest_reg_idx); 10271061SN/A 10281061SN/A // Special case of uniq or control registers. They are not 10292292SN/A // handled by the IQ and thus have no dependency graph entry. 10302292SN/A if (dest_reg->isFixedMapping()) { 10312326SN/A DPRINTF(IQ, "Reg %d [%s] is part of a fix mapping, skipping\n", 10322292SN/A dest_reg->index(), dest_reg->className()); 10332292SN/A continue; 10342292SN/A } 10352292SN/A 10362292SN/A DPRINTF(IQ, "Waking any dependents on register %i (%s).\n", 10372292SN/A dest_reg->index(), 10381062SN/A dest_reg->className()); 10391061SN/A 10402292SN/A //Go through the dependency chain, marking the registers as 10412336SN/A //ready within the waiting instructions. 10422292SN/A DynInstPtr dep_inst = dependGraph.pop(dest_reg->flatIndex()); 10432292SN/A 10441061SN/A while (dep_inst) { 10451061SN/A DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] " 10461681SN/A "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 10471061SN/A 10481061SN/A // Might want to give more information to the instruction 10491061SN/A // so that it knows which of its source registers is 10501061SN/A // ready. However that would mean that the dependency 10511061SN/A // graph entries would need to hold the src_reg_idx. 10522326SN/A dep_inst->markSrcRegReady(); 10532326SN/A 10542326SN/A addIfReady(dep_inst); 10552326SN/A 10562326SN/A dep_inst = dependGraph.pop(dest_reg->flatIndex()); 10572326SN/A 10582326SN/A ++dependents; 10592326SN/A } 10602292SN/A 10611061SN/A // Reset the head node now that all of its dependents have 10621061SN/A // been woken up. 10632326SN/A assert(dependGraph.empty(dest_reg->flatIndex())); 10641061SN/A dependGraph.clearInst(dest_reg->flatIndex()); 10651062SN/A 10662292SN/A // Mark the scoreboard as having that register ready. 10671062SN/A regScoreboard[dest_reg->flatIndex()] = true; 10681061SN/A } 10692064SN/A return dependents; 10702292SN/A} 10712292SN/A 10722292SN/Atemplate <class Impl> 10731062SN/Avoid 10742292SN/AInstructionQueue<Impl>::addReadyMemInst(const DynInstPtr &ready_inst) 10751681SN/A{ 10762292SN/A OpClass op_class = ready_inst->opClass(); 10771062SN/A 10781062SN/A readyInsts[op_class].push(ready_inst); 10791061SN/A 10801061SN/A // Will need to reorder the list if either a queue is not on the list, 10811061SN/A // or it has an older instruction than last time. 10821061SN/A if (!queueOnList[op_class]) { 10831061SN/A addToOrderList(op_class); 10841061SN/A } else if (readyInsts[op_class].top()->seqNum < 10851061SN/A (*readyIt[op_class]).oldestInst) { 10862292SN/A listOrder.erase(readyIt[op_class]); 10872292SN/A addToOrderList(op_class); 10881681SN/A } 10891681SN/A 10902731Sktlim@umich.edu DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 10912292SN/A "the ready list, PC %s opclass:%i [sn:%lli].\n", 10922292SN/A ready_inst->pcState(), op_class, ready_inst->seqNum); 10932292SN/A} 10941681SN/A 10951681SN/Atemplate <class Impl> 10961061SN/Avoid 10972326SN/AInstructionQueue<Impl>::rescheduleMemInst(const DynInstPtr &resched_inst) 10982326SN/A{ 10992326SN/A DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 11001061SN/A 11011061SN/A // Reset DTB translation state 11022326SN/A resched_inst->translationStarted(false); 11031062SN/A resched_inst->translationCompleted(false); 11041061SN/A 11051060SN/A resched_inst->clearCanIssue(); 11061060SN/A memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 11071061SN/A} 11081060SN/A 11091061SN/Atemplate <class Impl> 11101060SN/Avoid 11111060SN/AInstructionQueue<Impl>::replayMemInst(const DynInstPtr &replay_inst) 11121060SN/A{ 11131060SN/A memDepUnit[replay_inst->threadNumber].replay(); 11141060SN/A} 11151060SN/A 11161060SN/Atemplate <class Impl> 11171060SN/Avoid 11181060SN/AInstructionQueue<Impl>::completeMemInst(const DynInstPtr &completed_inst) 11191060SN/A{ 11201060SN/A ThreadID tid = completed_inst->threadNumber; 11211060SN/A 11221060SN/A DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n", 11231060SN/A completed_inst->pcState(), completed_inst->seqNum); 11241060SN/A 11251060SN/A ++freeEntries; 11261060SN/A 11271060SN/A completed_inst->memOpDone(true); 11281061SN/A 11291061SN/A memDepUnit[tid].completed(completed_inst); 11301061SN/A count[tid]--; 11312292SN/A} 11321060SN/A 11331060SN/Atemplate <class Impl> 11341060SN/Avoid 11352326SN/AInstructionQueue<Impl>::deferMemInst(const DynInstPtr &deferred_inst) 11361060SN/A{ 11371060SN/A deferredMemInsts.push_back(deferred_inst); 11381060SN/A} 11391060SN/A 11401060SN/Atemplate <class Impl> 11412292SN/Avoid 11421060SN/AInstructionQueue<Impl>::blockMemInst(const DynInstPtr &blocked_inst) 11431060SN/A{ 11441060SN/A blocked_inst->clearIssued(); 11452326SN/A blocked_inst->clearCanIssue(); 11461060SN/A blockedMemInsts.push_back(blocked_inst); 11471060SN/A} 11481060SN/A 11491060SN/Atemplate <class Impl> 11501060SN/Avoid 11511060SN/AInstructionQueue<Impl>::cacheUnblocked() 11521060SN/A{ 11531061SN/A retryMemInsts.splice(retryMemInsts.end(), blockedMemInsts); 11541060SN/A // Get the CPU ticking again 11552326SN/A cpu->wakeCPU(); 11561060SN/A} 11572326SN/A 11582326SN/Atemplate <class Impl> 11592326SN/Atypename Impl::DynInstPtr 11602326SN/AInstructionQueue<Impl>::getDeferredMemInstToExecute() 11611060SN/A{ 11621060SN/A for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); 11631060SN/A ++it) { 11641060SN/A if ((*it)->translationCompleted() || (*it)->isSquashed()) { 11651060SN/A DynInstPtr mem_inst = std::move(*it); 11661060SN/A deferredMemInsts.erase(it); 11671061SN/A return mem_inst; 11681061SN/A } 11691061SN/A } 11701061SN/A return nullptr; 11711061SN/A} 11721061SN/A 11731061SN/Atemplate <class Impl> 11741061SN/Atypename Impl::DynInstPtr 11751060SN/AInstructionQueue<Impl>::getBlockedMemInstToExecute() 11761060SN/A{ 11772326SN/A if (retryMemInsts.empty()) { 11782326SN/A return nullptr; 11792292SN/A } else { 11802064SN/A DynInstPtr mem_inst = std::move(retryMemInsts.front()); 11811062SN/A retryMemInsts.pop_front(); 11822326SN/A return mem_inst; 11831062SN/A } 11841060SN/A} 11851060SN/A 11861060SN/Atemplate <class Impl> 11871060SN/Avoid 11881060SN/AInstructionQueue<Impl>::violation(const DynInstPtr &store, 11891061SN/A const DynInstPtr &faulting_load) 11901060SN/A{ 11911061SN/A intInstQueueWrites++; 11921060SN/A memDepUnit[store->threadNumber].violation(store, faulting_load); 11932326SN/A} 11941060SN/A 11951060SN/Atemplate <class Impl> 11961061SN/Avoid 11971060SN/AInstructionQueue<Impl>::squash(ThreadID tid) 11982292SN/A{ 11991061SN/A DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 12002292SN/A "the IQ.\n", tid); 12011061SN/A 12021062SN/A // Read instruction sequence number of last instruction out of the 12031062SN/A // time buffer. 12042292SN/A squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 12051062SN/A 12062292SN/A doSquash(tid); 12072292SN/A 12081062SN/A // Also tell the memory dependence unit to squash. 12092292SN/A memDepUnit[tid].squash(squashedSeqNum[tid], tid); 12101061SN/A} 12112292SN/A 12122292SN/Atemplate <class Impl> 12132292SN/Avoid 12141061SN/AInstructionQueue<Impl>::doSquash(ThreadID tid) 12152292SN/A{ 12161061SN/A // Start at the tail. 12172326SN/A ListIt squash_it = instList[tid].end(); 12182326SN/A --squash_it; 12192326SN/A 12202326SN/A DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 12212326SN/A tid, squashedSeqNum[tid]); 12222326SN/A 12232326SN/A // Squash any instructions younger than the squashed sequence number 12242326SN/A // given. 12251060SN/A while (squash_it != instList[tid].end() && 12261060SN/A (*squash_it)->seqNum > squashedSeqNum[tid]) { 12271060SN/A 12281060SN/A DynInstPtr squashed_inst = (*squash_it); 12291061SN/A if (squashed_inst->isFloating()) { 12301061SN/A fpInstQueueWrites++; 12311061SN/A } else if (squashed_inst->isVector()) { 12321061SN/A vecInstQueueWrites++; 12332698Sktlim@umich.edu } else { 12342292SN/A intInstQueueWrites++; 12352292SN/A } 12362292SN/A 12372698Sktlim@umich.edu // Only handle the instruction if it actually is in the IQ and 12381061SN/A // hasn't already been squashed in the IQ. 12391061SN/A if (squashed_inst->threadNumber != tid || 12402292SN/A squashed_inst->isSquashedInIQ()) { 12412292SN/A --squash_it; 12421681SN/A continue; 12432292SN/A } 12442292SN/A 12452292SN/A if (!squashed_inst->isIssued() || 12462292SN/A (squashed_inst->isMemRef() && 12472292SN/A !squashed_inst->memOpDone())) { 12482292SN/A 12492292SN/A DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", 12502292SN/A tid, squashed_inst->seqNum, squashed_inst->pcState()); 12512292SN/A 12522292SN/A bool is_acq_rel = squashed_inst->isMemBarrier() && 12532292SN/A (squashed_inst->isLoad() || 12542292SN/A (squashed_inst->isStore() && 12552292SN/A !squashed_inst->isStoreConditional())); 12561061SN/A 12571061SN/A // Remove the instruction from the dependency list. 12581061SN/A if (is_acq_rel || 12591061SN/A (!squashed_inst->isNonSpeculative() && 12602292SN/A !squashed_inst->isStoreConditional() && 12612292SN/A !squashed_inst->isMemBarrier() && 12622292SN/A !squashed_inst->isWriteBarrier())) { 12631681SN/A 12641681SN/A for (int src_reg_idx = 0; 12651681SN/A src_reg_idx < squashed_inst->numSrcRegs(); 12661681SN/A src_reg_idx++) 12671061SN/A { 12681061SN/A PhysRegIdPtr src_reg = 12692292SN/A squashed_inst->renamedSrcRegIdx(src_reg_idx); 12702292SN/A 12711061SN/A // Only remove it from the dependency graph if it 12722292SN/A // was placed there in the first place. 12732292SN/A 12741061SN/A // Instead of doing a linked list traversal, we 12751061SN/A // can just remove these squashed instructions 12761061SN/A // either at issue time, or when the register is 12772292SN/A // overwritten. The only downside to this is it 12782292SN/A // leaves more room for error. 12791061SN/A 12801061SN/A if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 12811061SN/A !src_reg->isFixedMapping()) { 12822292SN/A dependGraph.remove(src_reg->flatIndex(), 12832292SN/A squashed_inst); 12842292SN/A } 12851061SN/A 12861061SN/A ++iqSquashedOperandsExamined; 12871061SN/A } 12881061SN/A 12891061SN/A } else if (!squashed_inst->isStoreConditional() || 12902292SN/A !squashed_inst->isCompleted()) { 12912292SN/A NonSpecMapIt ns_inst_it = 12922292SN/A nonSpecInsts.find(squashed_inst->seqNum); 12932292SN/A 12942292SN/A // we remove non-speculative instructions from 12952292SN/A // nonSpecInsts already when they are ready, and so we 12962292SN/A // cannot always expect to find them 12972292SN/A if (ns_inst_it == nonSpecInsts.end()) { 12982292SN/A // loads that became ready but stalled on a 12992292SN/A // blocked cache are alreayd removed from 13002292SN/A // nonSpecInsts, and have not faulted 13012292SN/A assert(squashed_inst->getFault() != NoFault || 13022292SN/A squashed_inst->isMemRef()); 13032292SN/A } else { 13042292SN/A 13051061SN/A (*ns_inst_it).second = NULL; 13062292SN/A 13072292SN/A nonSpecInsts.erase(ns_inst_it); 13082292SN/A 13092292SN/A ++iqSquashedNonSpecRemoved; 13102292SN/A } 13112292SN/A } 13122292SN/A 13132292SN/A // Might want to also clear out the head of the dependency graph. 13142292SN/A 13152292SN/A // Mark it as squashed within the IQ. 13162292SN/A squashed_inst->setSquashedInIQ(); 13172292SN/A 13182292SN/A // @todo: Remove this hack where several statuses are set so the 13192292SN/A // inst will flow through the rest of the pipeline. 13202292SN/A squashed_inst->setIssued(); 13212292SN/A squashed_inst->setCanCommit(); 13222292SN/A squashed_inst->clearInIQ(); 13232292SN/A 13242292SN/A //Update Thread IQ Count 13252292SN/A count[squashed_inst->threadNumber]--; 13262292SN/A 13272326SN/A ++freeEntries; 13282326SN/A } 13292292SN/A 13302292SN/A // IQ clears out the heads of the dependency graph only when 13312292SN/A // instructions reach writeback stage. If an instruction is squashed 13322292SN/A // before writeback stage, its head of dependency graph would not be 13332292SN/A // cleared out; it holds the instruction's DynInstPtr. This prevents 13342292SN/A // freeing the squashed instruction's DynInst. 13352292SN/A // Thus, we need to manually clear out the squashed instructions' heads 13362292SN/A // of dependency graph. 13372292SN/A for (int dest_reg_idx = 0; 13382292SN/A dest_reg_idx < squashed_inst->numDestRegs(); 13392292SN/A dest_reg_idx++) 13402292SN/A { 13412292SN/A PhysRegIdPtr dest_reg = 13422292SN/A squashed_inst->renamedDestRegIdx(dest_reg_idx); 13432292SN/A if (dest_reg->isFixedMapping()){ 13442292SN/A continue; 13452292SN/A } 13462292SN/A assert(dependGraph.empty(dest_reg->flatIndex())); 13472292SN/A dependGraph.clearInst(dest_reg->flatIndex()); 13482292SN/A } 13492292SN/A instList[tid].erase(squash_it--); 13502292SN/A ++iqSquashedInstsExamined; 13512292SN/A } 13522348SN/A} 13532348SN/A 13542348SN/Atemplate <class Impl> 13552348SN/Abool 13562348SN/AInstructionQueue<Impl>::addToDependents(const DynInstPtr &new_inst) 13572348SN/A{ 13582348SN/A // Loop through the instruction's source registers, adding 13592348SN/A // them to the dependency list if they are not ready. 13602348SN/A int8_t total_src_regs = new_inst->numSrcRegs(); 13612348SN/A bool return_val = false; 13622348SN/A 13632348SN/A for (int src_reg_idx = 0; 13642348SN/A src_reg_idx < total_src_regs; 13652348SN/A src_reg_idx++) 13662348SN/A { 13672348SN/A // Only add it to the dependency graph if it's not ready. 13682348SN/A if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 13692348SN/A PhysRegIdPtr src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 13702348SN/A 13712348SN/A // Check the IQ's scoreboard to make sure the register 13722348SN/A // hasn't become ready while the instruction was in flight 13732348SN/A // between stages. Only if it really isn't ready should 13742348SN/A // it be added to the dependency graph. 13752348SN/A if (src_reg->isFixedMapping()) { 13762348SN/A continue; 13772348SN/A } else if (!regScoreboard[src_reg->flatIndex()]) { 13782348SN/A DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that " 13792348SN/A "is being added to the dependency chain.\n", 13802348SN/A new_inst->pcState(), src_reg->index(), 13812348SN/A src_reg->className()); 13822348SN/A 13832348SN/A dependGraph.insert(src_reg->flatIndex(), new_inst); 13842348SN/A 13852348SN/A // Change the return value to indicate that something 13862348SN/A // was added to the dependency graph. 13872348SN/A return_val = true; 13882348SN/A } else { 13892348SN/A DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that " 13902348SN/A "became ready before it reached the IQ.\n", 13912348SN/A new_inst->pcState(), src_reg->index(), 13922348SN/A src_reg->className()); 13932292SN/A // Mark a register ready within the instruction. 1394 new_inst->markSrcRegReady(src_reg_idx); 1395 } 1396 } 1397 } 1398 1399 return return_val; 1400} 1401 1402template <class Impl> 1403void 1404InstructionQueue<Impl>::addToProducers(const DynInstPtr &new_inst) 1405{ 1406 // Nothing really needs to be marked when an instruction becomes 1407 // the producer of a register's value, but for convenience a ptr 1408 // to the producing instruction will be placed in the head node of 1409 // the dependency links. 1410 int8_t total_dest_regs = new_inst->numDestRegs(); 1411 1412 for (int dest_reg_idx = 0; 1413 dest_reg_idx < total_dest_regs; 1414 dest_reg_idx++) 1415 { 1416 PhysRegIdPtr dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 1417 1418 // Some registers have fixed mapping, and there is no need to track 1419 // dependencies as these instructions must be executed at commit. 1420 if (dest_reg->isFixedMapping()) { 1421 continue; 1422 } 1423 1424 if (!dependGraph.empty(dest_reg->flatIndex())) { 1425 dependGraph.dump(); 1426 panic("Dependency graph %i (%s) (flat: %i) not empty!", 1427 dest_reg->index(), dest_reg->className(), 1428 dest_reg->flatIndex()); 1429 } 1430 1431 dependGraph.setInst(dest_reg->flatIndex(), new_inst); 1432 1433 // Mark the scoreboard to say it's not yet ready. 1434 regScoreboard[dest_reg->flatIndex()] = false; 1435 } 1436} 1437 1438template <class Impl> 1439void 1440InstructionQueue<Impl>::addIfReady(const DynInstPtr &inst) 1441{ 1442 // If the instruction now has all of its source registers 1443 // available, then add it to the list of ready instructions. 1444 if (inst->readyToIssue()) { 1445 1446 //Add the instruction to the proper ready list. 1447 if (inst->isMemRef()) { 1448 1449 DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 1450 1451 // Message to the mem dependence unit that this instruction has 1452 // its registers ready. 1453 memDepUnit[inst->threadNumber].regsReady(inst); 1454 1455 return; 1456 } 1457 1458 OpClass op_class = inst->opClass(); 1459 1460 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 1461 "the ready list, PC %s opclass:%i [sn:%lli].\n", 1462 inst->pcState(), op_class, inst->seqNum); 1463 1464 readyInsts[op_class].push(inst); 1465 1466 // Will need to reorder the list if either a queue is not on the list, 1467 // or it has an older instruction than last time. 1468 if (!queueOnList[op_class]) { 1469 addToOrderList(op_class); 1470 } else if (readyInsts[op_class].top()->seqNum < 1471 (*readyIt[op_class]).oldestInst) { 1472 listOrder.erase(readyIt[op_class]); 1473 addToOrderList(op_class); 1474 } 1475 } 1476} 1477 1478template <class Impl> 1479int 1480InstructionQueue<Impl>::countInsts() 1481{ 1482#if 0 1483 //ksewell:This works but definitely could use a cleaner write 1484 //with a more intuitive way of counting. Right now it's 1485 //just brute force .... 1486 // Change the #if if you want to use this method. 1487 int total_insts = 0; 1488 1489 for (ThreadID tid = 0; tid < numThreads; ++tid) { 1490 ListIt count_it = instList[tid].begin(); 1491 1492 while (count_it != instList[tid].end()) { 1493 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 1494 if (!(*count_it)->isIssued()) { 1495 ++total_insts; 1496 } else if ((*count_it)->isMemRef() && 1497 !(*count_it)->memOpDone) { 1498 // Loads that have not been marked as executed still count 1499 // towards the total instructions. 1500 ++total_insts; 1501 } 1502 } 1503 1504 ++count_it; 1505 } 1506 } 1507 1508 return total_insts; 1509#else 1510 return numEntries - freeEntries; 1511#endif 1512} 1513 1514template <class Impl> 1515void 1516InstructionQueue<Impl>::dumpLists() 1517{ 1518 for (int i = 0; i < Num_OpClasses; ++i) { 1519 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 1520 1521 cprintf("\n"); 1522 } 1523 1524 cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 1525 1526 NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 1527 NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 1528 1529 cprintf("Non speculative list: "); 1530 1531 while (non_spec_it != non_spec_end_it) { 1532 cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(), 1533 (*non_spec_it).second->seqNum); 1534 ++non_spec_it; 1535 } 1536 1537 cprintf("\n"); 1538 1539 ListOrderIt list_order_it = listOrder.begin(); 1540 ListOrderIt list_order_end_it = listOrder.end(); 1541 int i = 1; 1542 1543 cprintf("List order: "); 1544 1545 while (list_order_it != list_order_end_it) { 1546 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 1547 (*list_order_it).oldestInst); 1548 1549 ++list_order_it; 1550 ++i; 1551 } 1552 1553 cprintf("\n"); 1554} 1555 1556 1557template <class Impl> 1558void 1559InstructionQueue<Impl>::dumpInsts() 1560{ 1561 for (ThreadID tid = 0; tid < numThreads; ++tid) { 1562 int num = 0; 1563 int valid_num = 0; 1564 ListIt inst_list_it = instList[tid].begin(); 1565 1566 while (inst_list_it != instList[tid].end()) { 1567 cprintf("Instruction:%i\n", num); 1568 if (!(*inst_list_it)->isSquashed()) { 1569 if (!(*inst_list_it)->isIssued()) { 1570 ++valid_num; 1571 cprintf("Count:%i\n", valid_num); 1572 } else if ((*inst_list_it)->isMemRef() && 1573 !(*inst_list_it)->memOpDone()) { 1574 // Loads that have not been marked as executed 1575 // still count towards the total instructions. 1576 ++valid_num; 1577 cprintf("Count:%i\n", valid_num); 1578 } 1579 } 1580 1581 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 1582 "Issued:%i\nSquashed:%i\n", 1583 (*inst_list_it)->pcState(), 1584 (*inst_list_it)->seqNum, 1585 (*inst_list_it)->threadNumber, 1586 (*inst_list_it)->isIssued(), 1587 (*inst_list_it)->isSquashed()); 1588 1589 if ((*inst_list_it)->isMemRef()) { 1590 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 1591 } 1592 1593 cprintf("\n"); 1594 1595 inst_list_it++; 1596 ++num; 1597 } 1598 } 1599 1600 cprintf("Insts to Execute list:\n"); 1601 1602 int num = 0; 1603 int valid_num = 0; 1604 ListIt inst_list_it = instsToExecute.begin(); 1605 1606 while (inst_list_it != instsToExecute.end()) 1607 { 1608 cprintf("Instruction:%i\n", 1609 num); 1610 if (!(*inst_list_it)->isSquashed()) { 1611 if (!(*inst_list_it)->isIssued()) { 1612 ++valid_num; 1613 cprintf("Count:%i\n", valid_num); 1614 } else if ((*inst_list_it)->isMemRef() && 1615 !(*inst_list_it)->memOpDone()) { 1616 // Loads that have not been marked as executed 1617 // still count towards the total instructions. 1618 ++valid_num; 1619 cprintf("Count:%i\n", valid_num); 1620 } 1621 } 1622 1623 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 1624 "Issued:%i\nSquashed:%i\n", 1625 (*inst_list_it)->pcState(), 1626 (*inst_list_it)->seqNum, 1627 (*inst_list_it)->threadNumber, 1628 (*inst_list_it)->isIssued(), 1629 (*inst_list_it)->isSquashed()); 1630 1631 if ((*inst_list_it)->isMemRef()) { 1632 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 1633 } 1634 1635 cprintf("\n"); 1636 1637 inst_list_it++; 1638 ++num; 1639 } 1640} 1641 1642#endif//__CPU_O3_INST_QUEUE_IMPL_HH__ 1643