inst_queue_impl.hh revision 13561
11689SN/A/* 29783Sandreas.hansson@arm.com * Copyright (c) 2011-2014 ARM Limited 37598Sminkyu.jeong@arm.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47598Sminkyu.jeong@arm.com * All rights reserved. 57598Sminkyu.jeong@arm.com * 67598Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 77598Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 87598Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 97598Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 107598Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 117598Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 127598Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 137598Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 142326SN/A * 151689SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392665Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 411689SN/A * Authors: Kevin Lim 421689SN/A * Korey Sewell 439944Smatt.horsnell@ARM.com */ 449944Smatt.horsnell@ARM.com 459944Smatt.horsnell@ARM.com#ifndef __CPU_O3_INST_QUEUE_IMPL_HH__ 461060SN/A#define __CPU_O3_INST_QUEUE_IMPL_HH__ 471060SN/A 481689SN/A#include <limits> 491060SN/A#include <vector> 501060SN/A 511060SN/A#include "base/logging.hh" 528230Snate@binkert.org#include "cpu/o3/fu_pool.hh" 536658Snate@binkert.org#include "cpu/o3/inst_queue.hh" 548887Sgeoffrey.blake@arm.com#include "debug/IQ.hh" 552292SN/A#include "enums/OpClass.hh" 561717SN/A#include "params/DerivO3CPU.hh" 578229Snate@binkert.org#include "sim/core.hh" 588232Snate@binkert.org 599444SAndreas.Sandberg@ARM.com// clang complains about std::set being overloaded with Packet::set if 608232Snate@binkert.org// we open up the entire namespace std 619527SMatt.Horsnell@arm.comusing std::list; 625529Snate@binkert.org 631060SN/Atemplate <class Impl> 646221Snate@binkert.orgInstructionQueue<Impl>::FUCompletion::FUCompletion(const DynInstPtr &_inst, 656221Snate@binkert.org int fu_idx, InstructionQueue<Impl> *iq_ptr) 661681SN/A : Event(Stat_Event_Pri, AutoDelete), 675529Snate@binkert.org inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 682873Sktlim@umich.edu{ 694329Sktlim@umich.edu} 704329Sktlim@umich.edu 714329Sktlim@umich.edutemplate <class Impl> 722292SN/Avoid 732292SN/AInstructionQueue<Impl>::FUCompletion::process() 742292SN/A{ 752292SN/A iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 762820Sktlim@umich.edu inst = NULL; 772292SN/A} 782820Sktlim@umich.edu 792820Sktlim@umich.edu 809444SAndreas.Sandberg@ARM.comtemplate <class Impl> 811060SN/Aconst char * 822292SN/AInstructionQueue<Impl>::FUCompletion::description() const 832292SN/A{ 842292SN/A return "Functional unit completion"; 851060SN/A} 861060SN/A 871060SN/Atemplate <class Impl> 881060SN/AInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 891060SN/A DerivO3CPUParams *params) 901060SN/A : cpu(cpu_ptr), 911681SN/A iewStage(iew_ptr), 926221Snate@binkert.org fuPool(params->fuPool), 936221Snate@binkert.org iqPolicy(params->smtIQPolicy), 946221Snate@binkert.org numEntries(params->numIQEntries), 956221Snate@binkert.org totalWidth(params->issueWidth), 962292SN/A commitToIEWDelay(params->commitToIEWDelay) 972292SN/A{ 982820Sktlim@umich.edu assert(fuPool); 992820Sktlim@umich.edu 1002292SN/A numThreads = params->numThreads; 1012292SN/A 1022820Sktlim@umich.edu // Set the number of total physical registers 1032820Sktlim@umich.edu // As the vector registers have two addressing modes, they are added twice 1042292SN/A numPhysRegs = params->numPhysIntRegs + params->numPhysFloatRegs + 1052292SN/A params->numPhysVecRegs + 1062292SN/A params->numPhysVecRegs * TheISA::NumVecElemPerVecReg + 1072292SN/A params->numPhysCCRegs; 1082292SN/A 1092292SN/A //Create an entry for each physical register within the 1102292SN/A //dependency graph. 1112292SN/A dependGraph.resize(numPhysRegs); 1121060SN/A 1131060SN/A // Resize the register scoreboard. 1141681SN/A regScoreboard.resize(numPhysRegs); 1151062SN/A 1162292SN/A //Initialize Mem Dependence Units 1171062SN/A for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 1182301SN/A memDepUnit[tid].init(params, tid); 1192301SN/A memDepUnit[tid].setIQ(this); 1201062SN/A } 1212727Sktlim@umich.edu 1221062SN/A resetState(); 1231062SN/A 1241062SN/A //Figure out resource sharing policy 1251062SN/A if (iqPolicy == SMTQueuePolicy::Dynamic) { 1261062SN/A //Set Max Entries to Total ROB Capacity 1271062SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1281062SN/A maxEntries[tid] = numEntries; 1291062SN/A } 1301062SN/A 1311062SN/A } else if (iqPolicy == SMTQueuePolicy::Partitioned) { 1321062SN/A //@todo:make work if part_amt doesnt divide evenly. 1331062SN/A int part_amt = numEntries / numThreads; 1341062SN/A 1351062SN/A //Divide ROB up evenly 1361062SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1371062SN/A maxEntries[tid] = part_amt; 1381062SN/A } 1391062SN/A 1401062SN/A DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 1411062SN/A "%i entries per thread.\n",part_amt); 1421062SN/A } else if (iqPolicy == SMTQueuePolicy::Threshold) { 1431062SN/A double threshold = (double)params->smtIQThreshold / 100; 1441062SN/A 1451062SN/A int thresholdIQ = (int)((double)threshold * numEntries); 1461062SN/A 1471062SN/A //Divide up by threshold amount 1481062SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1491062SN/A maxEntries[tid] = thresholdIQ; 1501062SN/A } 1511062SN/A 1521062SN/A DPRINTF(IQ, "IQ sharing policy set to Threshold:" 1531062SN/A "%i entries per thread.\n",thresholdIQ); 1541062SN/A } 1551062SN/A for (ThreadID tid = numThreads; tid < Impl::MaxThreads; tid++) { 1561062SN/A maxEntries[tid] = 0; 1571062SN/A } 1581062SN/A} 1591062SN/A 1601062SN/Atemplate <class Impl> 1611062SN/AInstructionQueue<Impl>::~InstructionQueue() 1621062SN/A{ 1632292SN/A dependGraph.reset(); 1642292SN/A#ifdef DEBUG 1652292SN/A cprintf("Nodes traversed: %i, removed: %i\n", 1662292SN/A dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1671062SN/A#endif 1681062SN/A} 1691062SN/A 1701062SN/Atemplate <class Impl> 1711062SN/Astd::string 1721062SN/AInstructionQueue<Impl>::name() const 1731062SN/A{ 1742292SN/A return cpu->name() + ".iq"; 1752292SN/A} 1762292SN/A 1772292SN/Atemplate <class Impl> 1782292SN/Avoid 1792292SN/AInstructionQueue<Impl>::regStats() 1802292SN/A{ 1812292SN/A using namespace Stats; 1822292SN/A iqInstsAdded 1832292SN/A .name(name() + ".iqInstsAdded") 1842301SN/A .desc("Number of instructions added to the IQ (excludes non-spec)") 1852727Sktlim@umich.edu .prereq(iqInstsAdded); 1862353SN/A 1872727Sktlim@umich.edu iqNonSpecInstsAdded 1882727Sktlim@umich.edu .name(name() + ".iqNonSpecInstsAdded") 1892727Sktlim@umich.edu .desc("Number of non-speculative instructions added to the IQ") 1906221Snate@binkert.org .prereq(iqNonSpecInstsAdded); 1912353SN/A 1922727Sktlim@umich.edu iqInstsIssued 1932727Sktlim@umich.edu .name(name() + ".iqInstsIssued") 1942727Sktlim@umich.edu .desc("Number of instructions issued") 1952727Sktlim@umich.edu .prereq(iqInstsIssued); 1962353SN/A 1972727Sktlim@umich.edu iqIntInstsIssued 1982727Sktlim@umich.edu .name(name() + ".iqIntInstsIssued") 1992727Sktlim@umich.edu .desc("Number of integer instructions issued") 2006221Snate@binkert.org .prereq(iqIntInstsIssued); 2018240Snate@binkert.org 2022301SN/A iqFloatInstsIssued 2032727Sktlim@umich.edu .name(name() + ".iqFloatInstsIssued") 2042301SN/A .desc("Number of float instructions issued") 2052727Sktlim@umich.edu .prereq(iqFloatInstsIssued); 2066221Snate@binkert.org 2078240Snate@binkert.org iqBranchInstsIssued 2082301SN/A .name(name() + ".iqBranchInstsIssued") 2092727Sktlim@umich.edu .desc("Number of branch instructions issued") 2102301SN/A .prereq(iqBranchInstsIssued); 2112727Sktlim@umich.edu 2126221Snate@binkert.org iqMemInstsIssued 2138240Snate@binkert.org .name(name() + ".iqMemInstsIssued") 2142301SN/A .desc("Number of memory instructions issued") 2152727Sktlim@umich.edu .prereq(iqMemInstsIssued); 2162301SN/A 2172727Sktlim@umich.edu iqMiscInstsIssued 2186221Snate@binkert.org .name(name() + ".iqMiscInstsIssued") 2198240Snate@binkert.org .desc("Number of miscellaneous instructions issued") 2202301SN/A .prereq(iqMiscInstsIssued); 2212727Sktlim@umich.edu 2222301SN/A iqSquashedInstsIssued 2232301SN/A .name(name() + ".iqSquashedInstsIssued") 2248240Snate@binkert.org .desc("Number of squashed instructions issued") 2252301SN/A .prereq(iqSquashedInstsIssued); 2262727Sktlim@umich.edu 2272727Sktlim@umich.edu iqSquashedInstsExamined 2282727Sktlim@umich.edu .name(name() + ".iqSquashedInstsExamined") 2292727Sktlim@umich.edu .desc("Number of squashed instructions iterated over during squash;" 2308240Snate@binkert.org " mainly for profiling") 2312727Sktlim@umich.edu .prereq(iqSquashedInstsExamined); 2322727Sktlim@umich.edu 2332727Sktlim@umich.edu iqSquashedOperandsExamined 2342727Sktlim@umich.edu .name(name() + ".iqSquashedOperandsExamined") 2352301SN/A .desc("Number of squashed operands that are examined and possibly " 2362301SN/A "removed from graph") 2376221Snate@binkert.org .prereq(iqSquashedOperandsExamined); 2388240Snate@binkert.org 2392301SN/A iqSquashedNonSpecRemoved 2402727Sktlim@umich.edu .name(name() + ".iqSquashedNonSpecRemoved") 2412301SN/A .desc("Number of squashed non-spec instructions that were removed") 2422326SN/A .prereq(iqSquashedNonSpecRemoved); 2436221Snate@binkert.org/* 2448240Snate@binkert.org queueResDist 2452301SN/A .init(Num_OpClasses, 0, 99, 2) 2462727Sktlim@umich.edu .name(name() + ".IQ:residence:") 2472301SN/A .desc("cycles from dispatch to issue") 2482326SN/A .flags(total | pdf | cdf ) 2496221Snate@binkert.org ; 2508240Snate@binkert.org for (int i = 0; i < Num_OpClasses; ++i) { 2512301SN/A queueResDist.subname(i, opClassStrings[i]); 2522727Sktlim@umich.edu } 2532301SN/A*/ 2542326SN/A numIssuedDist 2556221Snate@binkert.org .init(0,totalWidth,1) 2568240Snate@binkert.org .name(name() + ".issued_per_cycle") 2572301SN/A .desc("Number of insts issued each cycle") 2582727Sktlim@umich.edu .flags(pdf) 2592301SN/A ; 2602326SN/A/* 2616221Snate@binkert.org dist_unissued 2628240Snate@binkert.org .init(Num_OpClasses+2) 2632301SN/A .name(name() + ".unissued_cause") 2642727Sktlim@umich.edu .desc("Reason ready instruction not issued") 2652301SN/A .flags(pdf | dist) 2662326SN/A ; 2678240Snate@binkert.org for (int i=0; i < (Num_OpClasses + 2); ++i) { 2682301SN/A dist_unissued.subname(i, unissued_names[i]); 2692727Sktlim@umich.edu } 2702301SN/A*/ 2712326SN/A statIssuedInstType 2722301SN/A .init(numThreads,Enums::Num_OpClass) 2732326SN/A .name(name() + ".FU_type") 2748240Snate@binkert.org .desc("Type of FU issued") 2752301SN/A .flags(total | pdf | dist) 2762727Sktlim@umich.edu ; 2772301SN/A statIssuedInstType.ysubnames(Enums::OpClassStrings); 2782326SN/A 2792301SN/A // 2802326SN/A // How long did instructions for a particular FU type wait prior to issue 2818240Snate@binkert.org // 2822301SN/A/* 2832727Sktlim@umich.edu issueDelayDist 2842326SN/A .init(Num_OpClasses,0,99,2) 2851062SN/A .name(name() + ".") 2861062SN/A .desc("cycles from operands ready to issue") 2871681SN/A .flags(pdf | cdf) 2881060SN/A ; 2899427SAndreas.Sandberg@ARM.com 2901060SN/A for (int i=0; i<Num_OpClasses; ++i) { 2916221Snate@binkert.org std::stringstream subname; 2922292SN/A subname << opClassStrings[i] << "_delay"; 2932292SN/A issueDelayDist.subname(i, subname.str()); 2942292SN/A } 2952292SN/A*/ 2962292SN/A issueRate 2972292SN/A .name(name() + ".rate") 2982292SN/A .desc("Inst issue rate") 2992292SN/A .flags(total) 3002292SN/A ; 3018887Sgeoffrey.blake@arm.com issueRate = iqInstsIssued / cpu->numCycles; 3028733Sgeoffrey.blake@arm.com 3038850Sandreas.hansson@arm.com statFuBusy 3048887Sgeoffrey.blake@arm.com .init(Num_OpClasses) 3058733Sgeoffrey.blake@arm.com .name(name() + ".fu_full") 3062733Sktlim@umich.edu .desc("attempts to use FU when none available") 3071060SN/A .flags(pdf | dist) 3081060SN/A ; 3091681SN/A for (int i=0; i < Num_OpClasses; ++i) { 3101060SN/A statFuBusy.subname(i, Enums::OpClassStrings[i]); 3112292SN/A } 3121060SN/A 3131060SN/A fuBusy 3141060SN/A .init(numThreads) 3151060SN/A .name(name() + ".fu_busy_cnt") 3161060SN/A .desc("FU busy when requested") 3171060SN/A .flags(total) 3181060SN/A ; 3191060SN/A 3201060SN/A fuBusyRate 3212292SN/A .name(name() + ".fu_busy_rate") 3222292SN/A .desc("FU busy rate (busy events/executed inst)") 3231060SN/A .flags(total) 3241060SN/A ; 3251060SN/A fuBusyRate = fuBusy / iqInstsIssued; 3261060SN/A 3271681SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 3281060SN/A // Tell mem dependence unit to reg stats as well. 3292292SN/A memDepUnit[tid].regStats(); 3301060SN/A } 3311060SN/A 3321060SN/A intInstQueueReads 3331060SN/A .name(name() + ".int_inst_queue_reads") 3341060SN/A .desc("Number of integer instruction queue reads") 3351060SN/A .flags(total); 3361060SN/A 3371681SN/A intInstQueueWrites 3381060SN/A .name(name() + ".int_inst_queue_writes") 3392292SN/A .desc("Number of integer instruction queue writes") 3401060SN/A .flags(total); 3411060SN/A 3421060SN/A intInstQueueWakeupAccesses 3431060SN/A .name(name() + ".int_inst_queue_wakeup_accesses") 3441060SN/A .desc("Number of integer instruction queue wakeup accesses") 3451060SN/A .flags(total); 3461060SN/A 3471681SN/A fpInstQueueReads 3481060SN/A .name(name() + ".fp_inst_queue_reads") 3496221Snate@binkert.org .desc("Number of floating instruction queue reads") 3501060SN/A .flags(total); 3512292SN/A 3522292SN/A fpInstQueueWrites 3532292SN/A .name(name() + ".fp_inst_queue_writes") 3542292SN/A .desc("Number of floating instruction queue writes") 3551060SN/A .flags(total); 3561060SN/A 3571681SN/A fpInstQueueWakeupAccesses 3581060SN/A .name(name() + ".fp_inst_queue_wakeup_accesses") 3592292SN/A .desc("Number of floating instruction queue wakeup accesses") 3601060SN/A .flags(total); 3612292SN/A 3621060SN/A vecInstQueueReads 3631060SN/A .name(name() + ".vec_inst_queue_reads") 3642307SN/A .desc("Number of vector instruction queue reads") 3652863Sktlim@umich.edu .flags(total); 3669444SAndreas.Sandberg@ARM.com 3672307SN/A vecInstQueueWrites 3689444SAndreas.Sandberg@ARM.com .name(name() + ".vec_inst_queue_writes") 3699444SAndreas.Sandberg@ARM.com .desc("Number of vector instruction queue writes") 3709444SAndreas.Sandberg@ARM.com .flags(total); 3719444SAndreas.Sandberg@ARM.com 3729444SAndreas.Sandberg@ARM.com vecInstQueueWakeupAccesses 3739444SAndreas.Sandberg@ARM.com .name(name() + ".vec_inst_queue_wakeup_accesses") 3749444SAndreas.Sandberg@ARM.com .desc("Number of vector instruction queue wakeup accesses") 3759444SAndreas.Sandberg@ARM.com .flags(total); 3769444SAndreas.Sandberg@ARM.com 3779444SAndreas.Sandberg@ARM.com intAluAccesses 3789444SAndreas.Sandberg@ARM.com .name(name() + ".int_alu_accesses") 3799444SAndreas.Sandberg@ARM.com .desc("Number of integer alu accesses") 3809444SAndreas.Sandberg@ARM.com .flags(total); 3819783Sandreas.hansson@arm.com 3829783Sandreas.hansson@arm.com fpAluAccesses 3839783Sandreas.hansson@arm.com .name(name() + ".fp_alu_accesses") 3849783Sandreas.hansson@arm.com .desc("Number of floating point alu accesses") 3859783Sandreas.hansson@arm.com .flags(total); 3869783Sandreas.hansson@arm.com 3879783Sandreas.hansson@arm.com vecAluAccesses 3889783Sandreas.hansson@arm.com .name(name() + ".vec_alu_accesses") 3899444SAndreas.Sandberg@ARM.com .desc("Number of vector alu accesses") 3901681SN/A .flags(total); 3911681SN/A 3922316SN/A} 3931681SN/A 3949444SAndreas.Sandberg@ARM.comtemplate <class Impl> 3952843Sktlim@umich.eduvoid 3969444SAndreas.Sandberg@ARM.comInstructionQueue<Impl>::resetState() 3972843Sktlim@umich.edu{ 3989444SAndreas.Sandberg@ARM.com //Initialize thread IQ counts 3999444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 4001681SN/A count[tid] = 0; 4011681SN/A instList[tid].clear(); 4022307SN/A } 4031681SN/A 4042307SN/A // Initialize the number of free IQ entries. 4051060SN/A freeEntries = numEntries; 4062348SN/A 4072307SN/A // Note that in actuality, the registers corresponding to the logical 4082307SN/A // registers start off as ready. However this doesn't matter for the 4092307SN/A // IQ as the instruction should have been correctly told if those 4101060SN/A // registers are ready in rename. Thus it can all be initialized as 4112307SN/A // unready. 4122307SN/A for (int i = 0; i < numPhysRegs; ++i) { 4139444SAndreas.Sandberg@ARM.com regScoreboard[i] = false; 4141060SN/A } 4159427SAndreas.Sandberg@ARM.com 4162307SN/A for (ThreadID tid = 0; tid < Impl::MaxThreads; ++tid) { 4171060SN/A squashedSeqNum[tid] = 0; 4186221Snate@binkert.org } 4196221Snate@binkert.org 4206221Snate@binkert.org for (int i = 0; i < Num_OpClasses; ++i) { 4216221Snate@binkert.org while (!readyInsts[i].empty()) 4222307SN/A readyInsts[i].pop(); 4231060SN/A queueOnList[i] = false; 4242307SN/A readyIt[i] = listOrder.end(); 4252307SN/A } 4262873Sktlim@umich.edu nonSpecInsts.clear(); 4272307SN/A listOrder.clear(); 4281060SN/A deferredMemInsts.clear(); 4291060SN/A blockedMemInsts.clear(); 4301060SN/A retryMemInsts.clear(); 4311681SN/A wbOutstanding = 0; 4321060SN/A} 4336221Snate@binkert.org 4342107SN/Atemplate <class Impl> 4356221Snate@binkert.orgvoid 4362107SN/AInstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 4372292SN/A{ 4382292SN/A activeThreads = at_ptr; 4392107SN/A} 4402292SN/A 4412326SN/Atemplate <class Impl> 4422292SN/Avoid 4432107SN/AInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 4442292SN/A{ 4452935Sksewell@umich.edu issueToExecuteQueue = i2e_ptr; 4464632Sgblack@eecs.umich.edu} 4472935Sksewell@umich.edu 4482292SN/Atemplate <class Impl> 4492292SN/Avoid 4502292SN/AInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 4512292SN/A{ 4522292SN/A timeBuffer = tb_ptr; 4532107SN/A 4542292SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 4552107SN/A} 4562292SN/A 4572292SN/Atemplate <class Impl> 4582107SN/Abool 4592702Sktlim@umich.eduInstructionQueue<Impl>::isDrained() const 4602107SN/A{ 4612107SN/A bool drained = dependGraph.empty() && 4622107SN/A instsToExecute.empty() && 4632107SN/A wbOutstanding == 0; 4646221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 4652292SN/A drained = drained && memDepUnit[tid].isDrained(); 4667720Sgblack@eecs.umich.edu 4677720Sgblack@eecs.umich.edu return drained; 4682292SN/A} 4697852SMatt.Horsnell@arm.com 4707852SMatt.Horsnell@arm.comtemplate <class Impl> 4717852SMatt.Horsnell@arm.comvoid 4727852SMatt.Horsnell@arm.comInstructionQueue<Impl>::drainSanityCheck() const 4737852SMatt.Horsnell@arm.com{ 4742935Sksewell@umich.edu assert(dependGraph.empty()); 4757852SMatt.Horsnell@arm.com assert(instsToExecute.empty()); 4767852SMatt.Horsnell@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) 4772292SN/A memDepUnit[tid].drainSanityCheck(); 4787852SMatt.Horsnell@arm.com} 4797852SMatt.Horsnell@arm.com 4807852SMatt.Horsnell@arm.comtemplate <class Impl> 4812292SN/Avoid 4827852SMatt.Horsnell@arm.comInstructionQueue<Impl>::takeOverFrom() 4837852SMatt.Horsnell@arm.com{ 4847852SMatt.Horsnell@arm.com resetState(); 4852292SN/A} 4862292SN/A 4872292SN/Atemplate <class Impl> 4882292SN/Aint 4896221Snate@binkert.orgInstructionQueue<Impl>::entryAmount(ThreadID num_threads) 4902292SN/A{ 4918513SGiacomo.Gabrielli@arm.com if (iqPolicy == SMTQueuePolicy::Partitioned) { 4928513SGiacomo.Gabrielli@arm.com return numEntries / num_threads; 4938513SGiacomo.Gabrielli@arm.com } else { 4948513SGiacomo.Gabrielli@arm.com return 0; 4958513SGiacomo.Gabrielli@arm.com } 4968513SGiacomo.Gabrielli@arm.com} 4978513SGiacomo.Gabrielli@arm.com 4988513SGiacomo.Gabrielli@arm.com 4998513SGiacomo.Gabrielli@arm.comtemplate <class Impl> 5008513SGiacomo.Gabrielli@arm.comvoid 5018513SGiacomo.Gabrielli@arm.comInstructionQueue<Impl>::resetEntries() 5022292SN/A{ 5037852SMatt.Horsnell@arm.com if (iqPolicy != SMTQueuePolicy::Dynamic || numThreads > 1) { 5048513SGiacomo.Gabrielli@arm.com int active_threads = activeThreads->size(); 5058137SAli.Saidi@ARM.com 5062292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 5078513SGiacomo.Gabrielli@arm.com list<ThreadID>::iterator end = activeThreads->end(); 5088513SGiacomo.Gabrielli@arm.com 5092292SN/A while (threads != end) { 5107852SMatt.Horsnell@arm.com ThreadID tid = *threads++; 5117852SMatt.Horsnell@arm.com 5122292SN/A if (iqPolicy == SMTQueuePolicy::Partitioned) { 5132292SN/A maxEntries[tid] = numEntries / active_threads; 5142292SN/A } else if (iqPolicy == SMTQueuePolicy::Threshold && 5152292SN/A active_threads == 1) { 5166221Snate@binkert.org maxEntries[tid] = numEntries; 5172292SN/A } 5182292SN/A } 5197720Sgblack@eecs.umich.edu } 5207852SMatt.Horsnell@arm.com} 5217852SMatt.Horsnell@arm.com 5227852SMatt.Horsnell@arm.comtemplate <class Impl> 5232292SN/Aunsigned 5247852SMatt.Horsnell@arm.comInstructionQueue<Impl>::numFreeEntries() 5257852SMatt.Horsnell@arm.com{ 5268137SAli.Saidi@ARM.com return freeEntries; 5272292SN/A} 5287852SMatt.Horsnell@arm.com 5297852SMatt.Horsnell@arm.comtemplate <class Impl> 5302292SN/Aunsigned 5317852SMatt.Horsnell@arm.comInstructionQueue<Impl>::numFreeEntries(ThreadID tid) 5322292SN/A{ 5337852SMatt.Horsnell@arm.com return maxEntries[tid] - count[tid]; 5347852SMatt.Horsnell@arm.com} 5352292SN/A 5362292SN/A// Might want to do something more complex if it knows how many instructions 5372292SN/A// will be issued this cycle. 5382292SN/Atemplate <class Impl> 5396221Snate@binkert.orgbool 5402292SN/AInstructionQueue<Impl>::isFull() 5412292SN/A{ 5422292SN/A if (freeEntries == 0) { 5432292SN/A return(true); 5442292SN/A } else { 5452292SN/A return(false); 5462292SN/A } 5472292SN/A} 5482292SN/A 5492292SN/Atemplate <class Impl> 5502292SN/Abool 5512292SN/AInstructionQueue<Impl>::isFull(ThreadID tid) 5522292SN/A{ 5532292SN/A if (numFreeEntries(tid) == 0) { 5542292SN/A return(true); 5552292SN/A } else { 5562292SN/A return(false); 5572292SN/A } 5586221Snate@binkert.org} 5592292SN/A 5602292SN/Atemplate <class Impl> 5612292SN/Abool 5622292SN/AInstructionQueue<Impl>::hasReadyInsts() 5632292SN/A{ 5642292SN/A if (!listOrder.empty()) { 5652292SN/A return true; 5662292SN/A } 5672292SN/A 5682292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 5692292SN/A if (!readyInsts[i].empty()) { 5702292SN/A return true; 5712292SN/A } 5722292SN/A } 5732292SN/A 5742292SN/A return false; 5752292SN/A} 5761060SN/A 5771681SN/Atemplate <class Impl> 5781060SN/Avoid 5791060SN/AInstructionQueue<Impl>::insert(const DynInstPtr &new_inst) 5802292SN/A{ 5812292SN/A if (new_inst->isFloating()) { 5822292SN/A fpInstQueueWrites++; 5832292SN/A } else if (new_inst->isVector()) { 5842292SN/A vecInstQueueWrites++; 5852292SN/A } else { 5861681SN/A intInstQueueWrites++; 5871681SN/A } 5881060SN/A // Make sure the instruction is valid 5892292SN/A assert(new_inst); 5901060SN/A 5912292SN/A DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n", 5922292SN/A new_inst->seqNum, new_inst->pcState()); 5931060SN/A 5942292SN/A assert(freeEntries != 0); 5952292SN/A 5962292SN/A instList[new_inst->threadNumber].push_back(new_inst); 5972292SN/A 5983221Sktlim@umich.edu --freeEntries; 5993221Sktlim@umich.edu 6003221Sktlim@umich.edu new_inst->setInIQ(); 6013221Sktlim@umich.edu 6023221Sktlim@umich.edu // Look through its source registers (physical regs), and mark any 6032292SN/A // dependencies. 6042292SN/A addToDependents(new_inst); 6052292SN/A 6062292SN/A // Have this instruction set itself as the producer of its destination 6072326SN/A // register(s). 6082292SN/A addToProducers(new_inst); 6092292SN/A 6102820Sktlim@umich.edu if (new_inst->isMemRef()) { 6112292SN/A memDepUnit[new_inst->threadNumber].insert(new_inst); 6122292SN/A } else { 6132292SN/A addIfReady(new_inst); 6142292SN/A } 6152353SN/A 6162292SN/A ++iqInstsAdded; 6172292SN/A 6182353SN/A count[new_inst->threadNumber]++; 6192353SN/A 6202292SN/A assert(freeEntries == (numEntries - countInsts())); 6212292SN/A} 6222292SN/A 6232292SN/Atemplate <class Impl> 6242292SN/Avoid 6252292SN/AInstructionQueue<Impl>::insertNonSpec(const DynInstPtr &new_inst) 6262292SN/A{ 6272292SN/A // @todo: Clean up this code; can do it by setting inst as unable 6282292SN/A // to issue, then calling normal insert on the inst. 6292292SN/A if (new_inst->isFloating()) { 6302292SN/A fpInstQueueWrites++; 6312292SN/A } else if (new_inst->isVector()) { 6322731Sktlim@umich.edu vecInstQueueWrites++; 6332292SN/A } else { 6342292SN/A intInstQueueWrites++; 6352292SN/A } 6362292SN/A 6372292SN/A assert(new_inst); 6382292SN/A 6392292SN/A nonSpecInsts[new_inst->seqNum] = new_inst; 6402292SN/A 6416221Snate@binkert.org DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s " 6422292SN/A "to the IQ.\n", 6432292SN/A new_inst->seqNum, new_inst->pcState()); 6442292SN/A 6452292SN/A assert(freeEntries != 0); 6462292SN/A 6472292SN/A instList[new_inst->threadNumber].push_back(new_inst); 6482292SN/A 6492292SN/A --freeEntries; 6509937SFaissal.Sleiman@arm.com 6512292SN/A new_inst->setInIQ(); 6527720Sgblack@eecs.umich.edu 6532292SN/A // Have this instruction set itself as the producer of its destination 6542292SN/A // register(s). 6552292SN/A addToProducers(new_inst); 6562292SN/A 6572292SN/A // If it's a memory instruction, add it to the memory dependency 6582292SN/A // unit. 6592292SN/A if (new_inst->isMemRef()) { 6602292SN/A memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 6612292SN/A } 6622292SN/A 6632292SN/A ++iqNonSpecInstsAdded; 6642292SN/A 6652292SN/A count[new_inst->threadNumber]++; 6662292SN/A 6676221Snate@binkert.org assert(freeEntries == (numEntries - countInsts())); 6686221Snate@binkert.org} 6692292SN/A 6703867Sbinkertn@umich.edutemplate <class Impl> 6716221Snate@binkert.orgvoid 6723867Sbinkertn@umich.eduInstructionQueue<Impl>::insertBarrier(const DynInstPtr &barr_inst) 6732292SN/A{ 6742292SN/A memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 6752292SN/A 6762292SN/A insertNonSpec(barr_inst); 6772292SN/A} 6782292SN/A 6792292SN/Atemplate <class Impl> 6802292SN/Atypename Impl::DynInstPtr 6812292SN/AInstructionQueue<Impl>::getInstToExecute() 6822292SN/A{ 6832292SN/A assert(!instsToExecute.empty()); 6846221Snate@binkert.org DynInstPtr inst = std::move(instsToExecute.front()); 6856221Snate@binkert.org instsToExecute.pop_front(); 6862292SN/A if (inst->isFloating()) { 6873867Sbinkertn@umich.edu fpInstQueueReads++; 6886221Snate@binkert.org } else if (inst->isVector()) { 6893867Sbinkertn@umich.edu vecInstQueueReads++; 6903867Sbinkertn@umich.edu } else { 6912292SN/A intInstQueueReads++; 6922292SN/A } 6932292SN/A return inst; 6942292SN/A} 6951062SN/A 6961062SN/Atemplate <class Impl> 6971681SN/Avoid 6981062SN/AInstructionQueue<Impl>::addToOrderList(OpClass op_class) 6992292SN/A{ 7001062SN/A assert(!readyInsts[op_class].empty()); 7012292SN/A 7021062SN/A ListOrderEntry queue_entry; 7036221Snate@binkert.org 7046221Snate@binkert.org queue_entry.queueType = op_class; 7051062SN/A 7063867Sbinkertn@umich.edu queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 7076221Snate@binkert.org 7081062SN/A ListOrderIt list_it = listOrder.begin(); 7092292SN/A ListOrderIt list_end_it = listOrder.end(); 7102292SN/A 7112292SN/A while (list_it != list_end_it) { 7122292SN/A if ((*list_it).oldestInst > queue_entry.oldestInst) { 7132292SN/A break; 7141062SN/A } 7152292SN/A 7162292SN/A list_it++; 7172292SN/A } 7187897Shestness@cs.utexas.edu 7192292SN/A readyIt[op_class] = listOrder.insert(list_it, queue_entry); 7202292SN/A queueOnList[op_class] = true; 7212292SN/A} 7221062SN/A 7232292SN/Atemplate <class Impl> 7241062SN/Avoid 7252292SN/AInstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 7262292SN/A{ 7272292SN/A // Get iterator of next item on the list 7282292SN/A // Delete the original iterator 7292292SN/A // Determine if the next item is either the end of the list or younger 7302292SN/A // than the new instruction. If so, then add in a new iterator right here. 7311062SN/A // If not, then move along. 7322292SN/A ListOrderEntry queue_entry; 7331062SN/A OpClass op_class = (*list_order_it).queueType; 7342292SN/A ListOrderIt next_it = list_order_it; 7351062SN/A 7361062SN/A ++next_it; 7371062SN/A 7381681SN/A queue_entry.queueType = op_class; 7391062SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 7402292SN/A 7411062SN/A while (next_it != listOrder.end() && 7422292SN/A (*next_it).oldestInst < queue_entry.oldestInst) { 7432292SN/A ++next_it; 7442292SN/A } 7451062SN/A 7462292SN/A readyIt[op_class] = listOrder.insert(next_it, queue_entry); 7472292SN/A} 7486221Snate@binkert.org 7492292SN/Atemplate <class Impl> 7502292SN/Avoid 7512292SN/AInstructionQueue<Impl>::processFUCompletion(const DynInstPtr &inst, int fu_idx) 7522292SN/A{ 7531062SN/A DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 7542292SN/A assert(!cpu->switchedOut()); 7552292SN/A // The CPU could have been sleeping until this op completed (*extremely* 7562292SN/A // long latency op). Wake it if it was. This may be overkill. 7572292SN/A --wbOutstanding; 7582292SN/A iewStage->wakeCPU(); 7592292SN/A 7602292SN/A if (fu_idx > -1) 7612292SN/A fuPool->freeUnitNextCycle(fu_idx); 7626221Snate@binkert.org 7632292SN/A // @todo: Ensure that these FU Completions happen at the beginning 7642292SN/A // of a cycle, otherwise they could add too many instructions to 7652292SN/A // the queue. 7662292SN/A issueToExecuteQueue->access(-1)->size++; 7672292SN/A instsToExecute.push_back(inst); 7682292SN/A} 7692292SN/A 7702292SN/A// @todo: Figure out a better way to remove the squashed items from the 7712292SN/A// lists. Checking the top item of each list to see if it's squashed 7722292SN/A// wastes time and forces jumps. 7732292SN/Atemplate <class Impl> 7742292SN/Avoid 7752292SN/AInstructionQueue<Impl>::scheduleReadyInsts() 7762292SN/A{ 7772292SN/A DPRINTF(IQ, "Attempting to schedule ready instructions from " 7782292SN/A "the IQ.\n"); 7792292SN/A 7802292SN/A IssueStruct *i2e_info = issueToExecuteQueue->access(0); 7812292SN/A 7822292SN/A DynInstPtr mem_inst; 7832292SN/A while (mem_inst = std::move(getDeferredMemInstToExecute())) { 7842292SN/A addReadyMemInst(mem_inst); 7852292SN/A } 7862292SN/A 7872292SN/A // See if any cache blocked instructions are able to be executed 7882292SN/A while (mem_inst = std::move(getBlockedMemInstToExecute())) { 7892292SN/A addReadyMemInst(mem_inst); 7902292SN/A } 7912292SN/A 7922292SN/A // Have iterator to head of the list 7932292SN/A // While I haven't exceeded bandwidth or reached the end of the list, 7942292SN/A // Try to get a FU that can do what this op needs. 7952292SN/A // If successful, change the oldestInst to the new top of the list, put 7962292SN/A // the queue in the proper place in the list. 7972292SN/A // Increment the iterator. 7986221Snate@binkert.org // This will avoid trying to schedule a certain op class if there are no 7992292SN/A // FUs that handle it. 8002292SN/A int total_issued = 0; 8012292SN/A ListOrderIt order_it = listOrder.begin(); 8022292SN/A ListOrderIt order_end_it = listOrder.end(); 8032292SN/A 8042292SN/A while (total_issued < totalWidth && order_it != order_end_it) { 8052292SN/A OpClass op_class = (*order_it).queueType; 8062292SN/A 8072292SN/A assert(!readyInsts[op_class].empty()); 8082292SN/A 8092292SN/A DynInstPtr issuing_inst = readyInsts[op_class].top(); 8102292SN/A 8112292SN/A if (issuing_inst->isFloating()) { 8122292SN/A fpInstQueueReads++; 8132292SN/A } else if (issuing_inst->isVector()) { 8142292SN/A vecInstQueueReads++; 8152292SN/A } else { 8162292SN/A intInstQueueReads++; 8172292SN/A } 8182292SN/A 8192292SN/A assert(issuing_inst->seqNum == (*order_it).oldestInst); 8202292SN/A 8212292SN/A if (issuing_inst->isSquashed()) { 8222292SN/A readyInsts[op_class].pop(); 8232292SN/A 8242702Sktlim@umich.edu if (!readyInsts[op_class].empty()) { 8252292SN/A moveToYoungerInst(order_it); 8262292SN/A } else { 8272702Sktlim@umich.edu readyIt[op_class] = listOrder.end(); 8282702Sktlim@umich.edu queueOnList[op_class] = false; 8292292SN/A } 8302292SN/A 8312292SN/A listOrder.erase(order_it++); 8322292SN/A 8332292SN/A ++iqSquashedInstsIssued; 8342292SN/A 8352292SN/A continue; 8362292SN/A } 8372292SN/A 8382292SN/A int idx = FUPool::NoCapableFU; 8392292SN/A Cycles op_latency = Cycles(1); 8402292SN/A ThreadID tid = issuing_inst->threadNumber; 8412292SN/A 8422292SN/A if (op_class != No_OpClass) { 8432292SN/A idx = fuPool->getUnit(op_class); 8442292SN/A if (issuing_inst->isFloating()) { 8452292SN/A fpAluAccesses++; 8462292SN/A } else if (issuing_inst->isVector()) { 8472292SN/A vecAluAccesses++; 8482292SN/A } else { 8492292SN/A intAluAccesses++; 8502292SN/A } 8512292SN/A if (idx > FUPool::NoFreeFU) { 8522292SN/A op_latency = fuPool->getOpLatency(op_class); 8532292SN/A } 8542292SN/A } 8552292SN/A 8562292SN/A // If we have an instruction that doesn't require a FU, or a 8572292SN/A // valid FU, then schedule for execution. 8582292SN/A if (idx != FUPool::NoFreeFU) { 8592292SN/A if (op_latency == Cycles(1)) { 8602292SN/A i2e_info->size++; 8612292SN/A instsToExecute.push_back(issuing_inst); 8622292SN/A 8632292SN/A // Add the FU onto the list of FU's to be freed next 8642292SN/A // cycle if we used one. 8652292SN/A if (idx >= 0) 8662292SN/A fuPool->freeUnitNextCycle(idx); 8672292SN/A } else { 8682326SN/A bool pipelined = fuPool->isPipelined(op_class); 8696221Snate@binkert.org // Generate completion event for the FU 8706221Snate@binkert.org ++wbOutstanding; 8712326SN/A FUCompletion *execution = new FUCompletion(issuing_inst, 8722292SN/A idx, this); 8732292SN/A 8742292SN/A cpu->schedule(execution, 8752292SN/A cpu->clockEdge(Cycles(op_latency - 1))); 8762292SN/A 8772292SN/A if (!pipelined) { 8782292SN/A // If FU isn't pipelined, then it must be freed 8796221Snate@binkert.org // upon the execution completing. 8802702Sktlim@umich.edu execution->setFreeFU(); 8814632Sgblack@eecs.umich.edu } else { 8822935Sksewell@umich.edu // Add the FU onto the list of FU's to be freed next cycle. 8832702Sktlim@umich.edu fuPool->freeUnitNextCycle(idx); 8842935Sksewell@umich.edu } 8852702Sktlim@umich.edu } 8862702Sktlim@umich.edu 8872702Sktlim@umich.edu DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 8882702Sktlim@umich.edu "[sn:%lli]\n", 8892702Sktlim@umich.edu tid, issuing_inst->pcState(), 8902702Sktlim@umich.edu issuing_inst->seqNum); 8912702Sktlim@umich.edu 8922702Sktlim@umich.edu readyInsts[op_class].pop(); 8932702Sktlim@umich.edu 8942702Sktlim@umich.edu if (!readyInsts[op_class].empty()) { 8952702Sktlim@umich.edu moveToYoungerInst(order_it); 8962702Sktlim@umich.edu } else { 8972702Sktlim@umich.edu readyIt[op_class] = listOrder.end(); 8982292SN/A queueOnList[op_class] = false; 8992292SN/A } 9002292SN/A 9012292SN/A issuing_inst->setIssued(); 9022292SN/A ++total_issued; 9032292SN/A 9042292SN/A#if TRACING_ON 9052292SN/A issuing_inst->issueTick = curTick() - issuing_inst->fetchTick; 9062292SN/A#endif 9072292SN/A 9082292SN/A if (!issuing_inst->isMemRef()) { 9092292SN/A // Memory instructions can not be freed from the IQ until they 9102292SN/A // complete. 9112292SN/A ++freeEntries; 9122292SN/A count[tid]--; 9132292SN/A issuing_inst->clearInIQ(); 9142292SN/A } else { 9152292SN/A memDepUnit[tid].issue(issuing_inst); 9162733Sktlim@umich.edu } 9172292SN/A 9182292SN/A listOrder.erase(order_it++); 9192292SN/A statIssuedInstType[tid][op_class]++; 9202292SN/A } else { 9212292SN/A statFuBusy[op_class]++; 9222292SN/A fuBusy[tid]++; 9232292SN/A ++order_it; 9242733Sktlim@umich.edu } 9252292SN/A } 9262292SN/A 9272292SN/A numIssuedDist.sample(total_issued); 9282292SN/A iqInstsIssued+= total_issued; 9296221Snate@binkert.org 9302292SN/A // If we issued any instructions, tell the CPU we had activity. 9312292SN/A // @todo If the way deferred memory instructions are handeled due to 9322292SN/A // translation changes then the deferredMemInsts condition should be removed 9332292SN/A // from the code below. 9342292SN/A if (total_issued || !retryMemInsts.empty() || !deferredMemInsts.empty()) { 9352292SN/A cpu->activityThisCycle(); 9362292SN/A } else { 9372292SN/A DPRINTF(IQ, "Not able to schedule any instructions.\n"); 9382292SN/A } 9392292SN/A} 9402292SN/A 9412292SN/Atemplate <class Impl> 9422292SN/Avoid 9432292SN/AInstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 9442292SN/A{ 9452292SN/A DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 9462292SN/A "to execute.\n", inst); 9472292SN/A 9482292SN/A NonSpecMapIt inst_it = nonSpecInsts.find(inst); 9492292SN/A 9502292SN/A assert(inst_it != nonSpecInsts.end()); 9512292SN/A 9522292SN/A ThreadID tid = (*inst_it).second->threadNumber; 9532292SN/A 9542292SN/A (*inst_it).second->setAtCommit(); 9552292SN/A 9562292SN/A (*inst_it).second->setCanIssue(); 9572292SN/A 9582292SN/A if (!(*inst_it).second->isMemRef()) { 9592292SN/A addIfReady((*inst_it).second); 9602292SN/A } else { 9612292SN/A memDepUnit[tid].nonSpecInstReady((*inst_it).second); 9622292SN/A } 9632292SN/A 9642292SN/A (*inst_it).second = NULL; 9655215Sgblack@eecs.umich.edu 9662292SN/A nonSpecInsts.erase(inst_it); 9672292SN/A} 9682292SN/A 9692292SN/Atemplate <class Impl> 9702292SN/Avoid 9712292SN/AInstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 9722292SN/A{ 9732292SN/A DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 9742292SN/A tid,inst); 9752292SN/A 9762292SN/A ListIt iq_it = instList[tid].begin(); 9776221Snate@binkert.org 9782292SN/A while (iq_it != instList[tid].end() && 9792292SN/A (*iq_it)->seqNum <= inst) { 9802292SN/A ++iq_it; 9812292SN/A instList[tid].pop_front(); 9822292SN/A } 9832292SN/A 9842292SN/A assert(freeEntries == (numEntries - countInsts())); 9852292SN/A} 9862292SN/A 9872292SN/Atemplate <class Impl> 9882292SN/Aint 9892292SN/AInstructionQueue<Impl>::wakeDependents(const DynInstPtr &completed_inst) 9902292SN/A{ 9912292SN/A int dependents = 0; 9922292SN/A 9932292SN/A // The instruction queue here takes care of both floating and int ops 9942820Sktlim@umich.edu if (completed_inst->isFloating()) { 9952292SN/A fpInstQueueWakeupAccesses++; 9962292SN/A } else if (completed_inst->isVector()) { 9972292SN/A vecInstQueueWakeupAccesses++; 9982292SN/A } else { 9992292SN/A intInstQueueWakeupAccesses++; 10002292SN/A } 10012292SN/A 10022292SN/A DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 10032292SN/A 10042292SN/A assert(!completed_inst->isSquashed()); 10052292SN/A 10062292SN/A // Tell the memory dependence unit to wake any dependents on this 10077720Sgblack@eecs.umich.edu // instruction if it is a memory instruction. Also complete the memory 10082292SN/A // instruction at this point since we know it executed without issues. 10097720Sgblack@eecs.umich.edu // @todo: Might want to rename "completeMemInst" to something that 10102292SN/A // indicates that it won't need to be replayed, and call this 10112292SN/A // earlier. Might not be a big deal. 10122292SN/A if (completed_inst->isMemRef()) { 10132292SN/A memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 10142292SN/A completeMemInst(completed_inst); 10152292SN/A } else if (completed_inst->isMemBarrier() || 10162292SN/A completed_inst->isWriteBarrier()) { 10172292SN/A memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 10182292SN/A } 10192292SN/A 10202292SN/A for (int dest_reg_idx = 0; 10212292SN/A dest_reg_idx < completed_inst->numDestRegs(); 10222292SN/A dest_reg_idx++) 10232292SN/A { 10242292SN/A PhysRegIdPtr dest_reg = 10252292SN/A completed_inst->renamedDestRegIdx(dest_reg_idx); 10262292SN/A 10272292SN/A // Special case of uniq or control registers. They are not 10282292SN/A // handled by the IQ and thus have no dependency graph entry. 10292292SN/A if (dest_reg->isFixedMapping()) { 10302292SN/A DPRINTF(IQ, "Reg %d [%s] is part of a fix mapping, skipping\n", 10312292SN/A dest_reg->index(), dest_reg->className()); 10322292SN/A continue; 10332292SN/A } 10342292SN/A 10352292SN/A DPRINTF(IQ, "Waking any dependents on register %i (%s).\n", 10362292SN/A dest_reg->index(), 10372292SN/A dest_reg->className()); 10382292SN/A 10392292SN/A //Go through the dependency chain, marking the registers as 10402292SN/A //ready within the waiting instructions. 10412292SN/A DynInstPtr dep_inst = dependGraph.pop(dest_reg->flatIndex()); 10422292SN/A 10432292SN/A while (dep_inst) { 10442292SN/A DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] " 10452292SN/A "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 10462292SN/A 10472292SN/A // Might want to give more information to the instruction 10482292SN/A // so that it knows which of its source registers is 10492292SN/A // ready. However that would mean that the dependency 10502292SN/A // graph entries would need to hold the src_reg_idx. 10512292SN/A dep_inst->markSrcRegReady(); 10522292SN/A 10532292SN/A addIfReady(dep_inst); 10542292SN/A 10552292SN/A dep_inst = dependGraph.pop(dest_reg->flatIndex()); 10562292SN/A 10572292SN/A ++dependents; 10582292SN/A } 10592292SN/A 10602292SN/A // Reset the head node now that all of its dependents have 10612292SN/A // been woken up. 10622292SN/A assert(dependGraph.empty(dest_reg->flatIndex())); 10632292SN/A dependGraph.clearInst(dest_reg->flatIndex()); 10642292SN/A 10652292SN/A // Mark the scoreboard as having that register ready. 10662292SN/A regScoreboard[dest_reg->flatIndex()] = true; 10672292SN/A } 10682292SN/A return dependents; 10692292SN/A} 10702292SN/A 10712292SN/Atemplate <class Impl> 10722292SN/Avoid 10732292SN/AInstructionQueue<Impl>::addReadyMemInst(const DynInstPtr &ready_inst) 10742292SN/A{ 10752292SN/A OpClass op_class = ready_inst->opClass(); 10762292SN/A 10772292SN/A readyInsts[op_class].push(ready_inst); 10782292SN/A 10792292SN/A // Will need to reorder the list if either a queue is not on the list, 10802292SN/A // or it has an older instruction than last time. 10812292SN/A if (!queueOnList[op_class]) { 10822292SN/A addToOrderList(op_class); 10832292SN/A } else if (readyInsts[op_class].top()->seqNum < 10842336SN/A (*readyIt[op_class]).oldestInst) { 10852336SN/A listOrder.erase(readyIt[op_class]); 10862336SN/A addToOrderList(op_class); 10872336SN/A } 10882348SN/A 10892292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 10902292SN/A "the ready list, PC %s opclass:%i [sn:%lli].\n", 10912292SN/A ready_inst->pcState(), op_class, ready_inst->seqNum); 10922292SN/A} 10932292SN/A 10942292SN/Atemplate <class Impl> 10952292SN/Avoid 10962292SN/AInstructionQueue<Impl>::rescheduleMemInst(const DynInstPtr &resched_inst) 10972292SN/A{ 10982292SN/A DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 10992292SN/A 11002326SN/A // Reset DTB translation state 11012292SN/A resched_inst->translationStarted(false); 11022292SN/A resched_inst->translationCompleted(false); 11032292SN/A 11042292SN/A resched_inst->clearCanIssue(); 11052292SN/A memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 11062292SN/A} 11072292SN/A 11082292SN/Atemplate <class Impl> 11092292SN/Avoid 11102292SN/AInstructionQueue<Impl>::replayMemInst(const DynInstPtr &replay_inst) 11112292SN/A{ 11122326SN/A memDepUnit[replay_inst->threadNumber].replay(); 11132292SN/A} 11142727Sktlim@umich.edu 11152301SN/Atemplate <class Impl> 11162292SN/Avoid 11172292SN/AInstructionQueue<Impl>::completeMemInst(const DynInstPtr &completed_inst) 11182292SN/A{ 11192292SN/A ThreadID tid = completed_inst->threadNumber; 11202292SN/A 11212292SN/A DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n", 11222292SN/A completed_inst->pcState(), completed_inst->seqNum); 11232292SN/A 11242292SN/A ++freeEntries; 11252326SN/A 11262292SN/A completed_inst->memOpDone(true); 11272292SN/A 11282292SN/A memDepUnit[tid].completed(completed_inst); 11292292SN/A count[tid]--; 11302292SN/A} 11314033Sktlim@umich.edu 11324033Sktlim@umich.edutemplate <class Impl> 11334033Sktlim@umich.eduvoid 11344033Sktlim@umich.eduInstructionQueue<Impl>::deferMemInst(const DynInstPtr &deferred_inst) 11354033Sktlim@umich.edu{ 11364033Sktlim@umich.edu deferredMemInsts.push_back(deferred_inst); 11374033Sktlim@umich.edu} 11384033Sktlim@umich.edu 11394033Sktlim@umich.edutemplate <class Impl> 11404033Sktlim@umich.eduvoid 11414033Sktlim@umich.eduInstructionQueue<Impl>::blockMemInst(const DynInstPtr &blocked_inst) 11424033Sktlim@umich.edu{ 11434033Sktlim@umich.edu blocked_inst->translationStarted(false); 11444033Sktlim@umich.edu blocked_inst->translationCompleted(false); 11452292SN/A 11462292SN/A blocked_inst->clearIssued(); 11472292SN/A blocked_inst->clearCanIssue(); 11482292SN/A blockedMemInsts.push_back(blocked_inst); 11492292SN/A} 11502292SN/A 11512292SN/Atemplate <class Impl> 11522292SN/Avoid 11532292SN/AInstructionQueue<Impl>::cacheUnblocked() 11542292SN/A{ 11552292SN/A retryMemInsts.splice(retryMemInsts.end(), blockedMemInsts); 11562292SN/A // Get the CPU ticking again 11578471SGiacomo.Gabrielli@arm.com cpu->wakeCPU(); 11588471SGiacomo.Gabrielli@arm.com} 11599046SAli.Saidi@ARM.com 11608471SGiacomo.Gabrielli@arm.comtemplate <class Impl> 11612292SN/Atypename Impl::DynInstPtr 11622292SN/AInstructionQueue<Impl>::getDeferredMemInstToExecute() 11632292SN/A{ 11642935Sksewell@umich.edu for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); 11652292SN/A ++it) { 11662292SN/A if ((*it)->translationCompleted() || (*it)->isSquashed()) { 11672292SN/A DynInstPtr mem_inst = std::move(*it); 11682292SN/A deferredMemInsts.erase(it); 11692292SN/A return mem_inst; 11702292SN/A } 11712292SN/A } 11722292SN/A return nullptr; 11732292SN/A} 11742292SN/A 11752292SN/Atemplate <class Impl> 11762292SN/Atypename Impl::DynInstPtr 11772292SN/AInstructionQueue<Impl>::getBlockedMemInstToExecute() 11782292SN/A{ 11792292SN/A if (retryMemInsts.empty()) { 11802292SN/A return nullptr; 11812292SN/A } else { 11822292SN/A DynInstPtr mem_inst = std::move(retryMemInsts.front()); 11832292SN/A retryMemInsts.pop_front(); 11842980Sgblack@eecs.umich.edu return mem_inst; 11852292SN/A } 11862292SN/A} 11872292SN/A 11882980Sgblack@eecs.umich.edutemplate <class Impl> 11892292SN/Avoid 11907720Sgblack@eecs.umich.eduInstructionQueue<Impl>::violation(const DynInstPtr &store, 11912292SN/A const DynInstPtr &faulting_load) 11922292SN/A{ 11932292SN/A intInstQueueWrites++; 11942292SN/A memDepUnit[store->threadNumber].violation(store, faulting_load); 11952292SN/A} 11962292SN/A 11972292SN/Atemplate <class Impl> 11982980Sgblack@eecs.umich.eduvoid 11992292SN/AInstructionQueue<Impl>::squash(ThreadID tid) 12002292SN/A{ 12012292SN/A DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 12022292SN/A "the IQ.\n", tid); 12032292SN/A 12042292SN/A // Read instruction sequence number of last instruction out of the 12052292SN/A // time buffer. 12062292SN/A squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 12072292SN/A 12086221Snate@binkert.org doSquash(tid); 12096221Snate@binkert.org 12102292SN/A // Also tell the memory dependence unit to squash. 12113867Sbinkertn@umich.edu memDepUnit[tid].squash(squashedSeqNum[tid], tid); 12126221Snate@binkert.org} 12132292SN/A 12142292SN/Atemplate <class Impl> 12152292SN/Avoid 12162698Sktlim@umich.eduInstructionQueue<Impl>::doSquash(ThreadID tid) 12177599Sminkyu.jeong@arm.com{ 12182698Sktlim@umich.edu // Start at the tail. 12191062SN/A ListIt squash_it = instList[tid].end(); 12201062SN/A --squash_it; 12212333SN/A 12222292SN/A DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 12232333SN/A tid, squashedSeqNum[tid]); 12242326SN/A 12251062SN/A // Squash any instructions younger than the squashed sequence number 12262292SN/A // given. 12271062SN/A while (squash_it != instList[tid].end() && 12282333SN/A (*squash_it)->seqNum > squashedSeqNum[tid]) { 12291062SN/A 12307720Sgblack@eecs.umich.edu DynInstPtr squashed_inst = (*squash_it); 12317720Sgblack@eecs.umich.edu if (squashed_inst->isFloating()) { 12321062SN/A fpInstQueueWrites++; 12331062SN/A } else if (squashed_inst->isVector()) { 12341062SN/A vecInstQueueWrites++; 12358315Sgeoffrey.blake@arm.com } else { 12368315Sgeoffrey.blake@arm.com intInstQueueWrites++; 12378315Sgeoffrey.blake@arm.com } 12381062SN/A 12391062SN/A // Only handle the instruction if it actually is in the IQ and 12401062SN/A // hasn't already been squashed in the IQ. 12411062SN/A if (squashed_inst->threadNumber != tid || 12421062SN/A squashed_inst->isSquashedInIQ()) { 12432292SN/A --squash_it; 12442292SN/A continue; 12452292SN/A } 12461062SN/A 12471062SN/A if (!squashed_inst->isIssued() || 12481062SN/A (squashed_inst->isMemRef() && 12492820Sktlim@umich.edu !squashed_inst->memOpDone())) { 12501062SN/A 12511062SN/A DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", 12521062SN/A tid, squashed_inst->seqNum, squashed_inst->pcState()); 12532292SN/A 12541062SN/A bool is_acq_rel = squashed_inst->isMemBarrier() && 12551062SN/A (squashed_inst->isLoad() || 12561062SN/A (squashed_inst->isStore() && 12571062SN/A !squashed_inst->isStoreConditional())); 12587850SMatt.Horsnell@arm.com 12592292SN/A // Remove the instruction from the dependency list. 12601062SN/A if (is_acq_rel || 12611062SN/A (!squashed_inst->isNonSpeculative() && 12621062SN/A !squashed_inst->isStoreConditional() && 12631062SN/A !squashed_inst->isMemBarrier() && 12642292SN/A !squashed_inst->isWriteBarrier())) { 12652292SN/A 12662292SN/A for (int src_reg_idx = 0; 12677944SGiacomo.Gabrielli@arm.com src_reg_idx < squashed_inst->numSrcRegs(); 12687944SGiacomo.Gabrielli@arm.com src_reg_idx++) 12697944SGiacomo.Gabrielli@arm.com { 12707944SGiacomo.Gabrielli@arm.com PhysRegIdPtr src_reg = 12717944SGiacomo.Gabrielli@arm.com squashed_inst->renamedSrcRegIdx(src_reg_idx); 12727944SGiacomo.Gabrielli@arm.com 12737944SGiacomo.Gabrielli@arm.com // Only remove it from the dependency graph if it 12747944SGiacomo.Gabrielli@arm.com // was placed there in the first place. 12757944SGiacomo.Gabrielli@arm.com 12767944SGiacomo.Gabrielli@arm.com // Instead of doing a linked list traversal, we 12777944SGiacomo.Gabrielli@arm.com // can just remove these squashed instructions 12787850SMatt.Horsnell@arm.com // either at issue time, or when the register is 12798073SAli.Saidi@ARM.com // overwritten. The only downside to this is it 12807850SMatt.Horsnell@arm.com // leaves more room for error. 12811062SN/A 12822367SN/A if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 12831062SN/A !src_reg->isFixedMapping()) { 12847944SGiacomo.Gabrielli@arm.com dependGraph.remove(src_reg->flatIndex(), 12857944SGiacomo.Gabrielli@arm.com squashed_inst); 12867944SGiacomo.Gabrielli@arm.com } 12877944SGiacomo.Gabrielli@arm.com 12887944SGiacomo.Gabrielli@arm.com 12897944SGiacomo.Gabrielli@arm.com ++iqSquashedOperandsExamined; 12907944SGiacomo.Gabrielli@arm.com } 12917944SGiacomo.Gabrielli@arm.com } else if (!squashed_inst->isStoreConditional() || 12927944SGiacomo.Gabrielli@arm.com !squashed_inst->isCompleted()) { 12937944SGiacomo.Gabrielli@arm.com NonSpecMapIt ns_inst_it = 12942292SN/A nonSpecInsts.find(squashed_inst->seqNum); 12957782Sminkyu.jeong@arm.com 12967782Sminkyu.jeong@arm.com // we remove non-speculative instructions from 12977782Sminkyu.jeong@arm.com // nonSpecInsts already when they are ready, and so we 12987782Sminkyu.jeong@arm.com // cannot always expect to find them 12992367SN/A if (ns_inst_it == nonSpecInsts.end()) { 13002367SN/A // loads that became ready but stalled on a 13012367SN/A // blocked cache are alreayd removed from 13022367SN/A // nonSpecInsts, and have not faulted 13032367SN/A assert(squashed_inst->getFault() != NoFault || 13042292SN/A squashed_inst->isMemRef()); 13052326SN/A } else { 13062326SN/A 13072326SN/A (*ns_inst_it).second = NULL; 13082326SN/A 13091062SN/A nonSpecInsts.erase(ns_inst_it); 13102292SN/A 13111062SN/A ++iqSquashedNonSpecRemoved; 13121062SN/A } 13131062SN/A } 13147847Sminkyu.jeong@arm.com 13157847Sminkyu.jeong@arm.com // Might want to also clear out the head of the dependency graph. 13167847Sminkyu.jeong@arm.com 13177847Sminkyu.jeong@arm.com // Mark it as squashed within the IQ. 13187847Sminkyu.jeong@arm.com squashed_inst->setSquashedInIQ(); 13197847Sminkyu.jeong@arm.com 13207848SAli.Saidi@ARM.com // @todo: Remove this hack where several statuses are set so the 13217848SAli.Saidi@ARM.com // inst will flow through the rest of the pipeline. 13227847Sminkyu.jeong@arm.com squashed_inst->setIssued(); 13231062SN/A squashed_inst->setCanCommit(); 13242292SN/A squashed_inst->clearInIQ(); 13252292SN/A 13262292SN/A //Update Thread IQ Count 13271062SN/A count[squashed_inst->threadNumber]--; 13281062SN/A 13292301SN/A ++freeEntries; 13301681SN/A } 13312326SN/A 13322326SN/A // IQ clears out the heads of the dependency graph only when 13332326SN/A // instructions reach writeback stage. If an instruction is squashed 13342107SN/A // before writeback stage, its head of dependency graph would not be 13351681SN/A // cleared out; it holds the instruction's DynInstPtr. This prevents 13362292SN/A // freeing the squashed instruction's DynInst. 13372292SN/A // Thus, we need to manually clear out the squashed instructions' heads 13382292SN/A // of dependency graph. 13396221Snate@binkert.org for (int dest_reg_idx = 0; 13401062SN/A dest_reg_idx < squashed_inst->numDestRegs(); 13413732Sktlim@umich.edu dest_reg_idx++) 13427852SMatt.Horsnell@arm.com { 13433732Sktlim@umich.edu PhysRegIdPtr dest_reg = 13441062SN/A squashed_inst->renamedDestRegIdx(dest_reg_idx); 13457856SMatt.Horsnell@arm.com if (dest_reg->isFixedMapping()){ 13467856SMatt.Horsnell@arm.com continue; 13477856SMatt.Horsnell@arm.com } 13487856SMatt.Horsnell@arm.com assert(dependGraph.empty(dest_reg->flatIndex())); 13497856SMatt.Horsnell@arm.com dependGraph.clearInst(dest_reg->flatIndex()); 13502292SN/A } 13511062SN/A instList[tid].erase(squash_it--); 13522292SN/A ++iqSquashedInstsExamined; 13538674Snilay@cs.wisc.edu } 13548674Snilay@cs.wisc.edu} 13557720Sgblack@eecs.umich.edu 13568674Snilay@cs.wisc.edutemplate <class Impl> 13571062SN/Abool 13582292SN/AInstructionQueue<Impl>::addToDependents(const DynInstPtr &new_inst) 13591062SN/A{ 13603795Sgblack@eecs.umich.edu // Loop through the instruction's source registers, adding 13611062SN/A // them to the dependency list if they are not ready. 13622292SN/A int8_t total_src_regs = new_inst->numSrcRegs(); 13632292SN/A bool return_val = false; 13641062SN/A 13652292SN/A for (int src_reg_idx = 0; 13664033Sktlim@umich.edu src_reg_idx < total_src_regs; 13672326SN/A src_reg_idx++) 13682326SN/A { 13692292SN/A // Only add it to the dependency graph if it's not ready. 13702292SN/A if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 13712292SN/A PhysRegIdPtr src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 13721062SN/A 13737720Sgblack@eecs.umich.edu // Check the IQ's scoreboard to make sure the register 13747720Sgblack@eecs.umich.edu // hasn't become ready while the instruction was in flight 13757720Sgblack@eecs.umich.edu // between stages. Only if it really isn't ready should 13767720Sgblack@eecs.umich.edu // it be added to the dependency graph. 13777720Sgblack@eecs.umich.edu if (src_reg->isFixedMapping()) { 13783732Sktlim@umich.edu continue; 13793732Sktlim@umich.edu } else if (!regScoreboard[src_reg->flatIndex()]) { 13801062SN/A DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that " 13811062SN/A "is being added to the dependency chain.\n", 13821062SN/A new_inst->pcState(), src_reg->index(), 13831062SN/A src_reg->className()); 13848513SGiacomo.Gabrielli@arm.com 13851062SN/A dependGraph.insert(src_reg->flatIndex(), new_inst); 13861062SN/A 13872292SN/A // Change the return value to indicate that something 13882292SN/A // was added to the dependency graph. 13892292SN/A return_val = true; 13902292SN/A } else { 13912292SN/A DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that " 13927720Sgblack@eecs.umich.edu "became ready before it reached the IQ.\n", 13937720Sgblack@eecs.umich.edu new_inst->pcState(), src_reg->index(), 13942292SN/A src_reg->className()); 13952292SN/A // Mark a register ready within the instruction. 13961062SN/A new_inst->markSrcRegReady(src_reg_idx); 13974033Sktlim@umich.edu } 13984033Sktlim@umich.edu } 13994033Sktlim@umich.edu } 14004033Sktlim@umich.edu 14014033Sktlim@umich.edu return return_val; 14024033Sktlim@umich.edu} 14034033Sktlim@umich.edu 14044033Sktlim@umich.edutemplate <class Impl> 14054033Sktlim@umich.eduvoid 14067720Sgblack@eecs.umich.eduInstructionQueue<Impl>::addToProducers(const DynInstPtr &new_inst) 14077720Sgblack@eecs.umich.edu{ 14087720Sgblack@eecs.umich.edu // Nothing really needs to be marked when an instruction becomes 14094033Sktlim@umich.edu // the producer of a register's value, but for convenience a ptr 14104033Sktlim@umich.edu // to the producing instruction will be placed in the head node of 14114033Sktlim@umich.edu // the dependency links. 14124033Sktlim@umich.edu int8_t total_dest_regs = new_inst->numDestRegs(); 14134033Sktlim@umich.edu 14144033Sktlim@umich.edu for (int dest_reg_idx = 0; 14154033Sktlim@umich.edu dest_reg_idx < total_dest_regs; 14164033Sktlim@umich.edu dest_reg_idx++) 14177720Sgblack@eecs.umich.edu { 14187720Sgblack@eecs.umich.edu PhysRegIdPtr dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 14194033Sktlim@umich.edu 14204033Sktlim@umich.edu // Some registers have fixed mapping, and there is no need to track 14214033Sktlim@umich.edu // dependencies as these instructions must be executed at commit. 14224033Sktlim@umich.edu if (dest_reg->isFixedMapping()) { 14234033Sktlim@umich.edu continue; 14244033Sktlim@umich.edu } 14251062SN/A 14261062SN/A if (!dependGraph.empty(dest_reg->flatIndex())) { 14272292SN/A dependGraph.dump(); 14282348SN/A panic("Dependency graph %i (%s) (flat: %i) not empty!", 14292292SN/A dest_reg->index(), dest_reg->className(), 14302292SN/A dest_reg->flatIndex()); 14312292SN/A } 14322292SN/A 14332292SN/A dependGraph.setInst(dest_reg->flatIndex(), new_inst); 14342292SN/A 14352292SN/A // Mark the scoreboard to say it's not yet ready. 14362292SN/A regScoreboard[dest_reg->flatIndex()] = false; 14372292SN/A } 14382292SN/A} 14392292SN/A 14402292SN/Atemplate <class Impl> 14412292SN/Avoid 14422292SN/AInstructionQueue<Impl>::addIfReady(const DynInstPtr &inst) 14437852SMatt.Horsnell@arm.com{ 14442107SN/A // If the instruction now has all of its source registers 14452107SN/A // available, then add it to the list of ready instructions. 14462292SN/A if (inst->readyToIssue()) { 14472107SN/A 14482292SN/A //Add the instruction to the proper ready list. 14492107SN/A if (inst->isMemRef()) { 14502326SN/A 14512326SN/A DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 14522326SN/A 14532326SN/A // Message to the mem dependence unit that this instruction has 14542326SN/A // its registers ready. 14553958Sgblack@eecs.umich.edu memDepUnit[inst->threadNumber].regsReady(inst); 14562292SN/A 14572107SN/A return; 14586221Snate@binkert.org } 14592107SN/A 14607720Sgblack@eecs.umich.edu OpClass op_class = inst->opClass(); 14617720Sgblack@eecs.umich.edu 14622107SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 14632301SN/A "the ready list, PC %s opclass:%i [sn:%lli].\n", 14642301SN/A inst->pcState(), op_class, inst->seqNum); 14652292SN/A 14662292SN/A readyInsts[op_class].push(inst); 14672292SN/A 14682292SN/A // Will need to reorder the list if either a queue is not on the list, 14692292SN/A // or it has an older instruction than last time. 14702367SN/A if (!queueOnList[op_class]) { 14712301SN/A addToOrderList(op_class); 14722107SN/A } else if (readyInsts[op_class].top()->seqNum < 14732292SN/A (*readyIt[op_class]).oldestInst) { 14742292SN/A listOrder.erase(readyIt[op_class]); 14752292SN/A addToOrderList(op_class); 14762292SN/A } 14772292SN/A } 14782107SN/A} 14792301SN/A 14802348SN/Atemplate <class Impl> 14812348SN/Aint 14822348SN/AInstructionQueue<Impl>::countInsts() 14832348SN/A{ 14842326SN/A#if 0 14852107SN/A //ksewell:This works but definitely could use a cleaner write 14862820Sktlim@umich.edu //with a more intuitive way of counting. Right now it's 14872820Sktlim@umich.edu //just brute force .... 14882107SN/A // Change the #if if you want to use this method. 14891060SN/A int total_insts = 0; 14901060SN/A 14911681SN/A for (ThreadID tid = 0; tid < numThreads; ++tid) { 14921060SN/A ListIt count_it = instList[tid].begin(); 14932292SN/A 14941060SN/A while (count_it != instList[tid].end()) { 14952292SN/A if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 14962292SN/A if (!(*count_it)->isIssued()) { 14971060SN/A ++total_insts; 14982292SN/A } else if ((*count_it)->isMemRef() && 14992292SN/A !(*count_it)->memOpDone) { 15001060SN/A // Loads that have not been marked as executed still count 15012292SN/A // towards the total instructions. 15021060SN/A ++total_insts; 15032326SN/A } 15042326SN/A } 15051062SN/A 15066221Snate@binkert.org ++count_it; 15076221Snate@binkert.org } 15081060SN/A } 15092326SN/A 15103867Sbinkertn@umich.edu return total_insts; 15116221Snate@binkert.org#else 15121060SN/A return numEntries - freeEntries; 15132292SN/A#endif 15141060SN/A} 15152292SN/A 15162292SN/Atemplate <class Impl> 15171060SN/Avoid 15181060SN/AInstructionQueue<Impl>::dumpLists() 15192292SN/A{ 15202292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 15211060SN/A cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 15222292SN/A 15232292SN/A cprintf("\n"); 15242292SN/A } 15252292SN/A 15262292SN/A cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 15272292SN/A 15282292SN/A NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 15292292SN/A NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 15302292SN/A 15312292SN/A cprintf("Non speculative list: "); 15322292SN/A 15332292SN/A while (non_spec_it != non_spec_end_it) { 15342292SN/A cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(), 15352292SN/A (*non_spec_it).second->seqNum); 15362292SN/A ++non_spec_it; 15372292SN/A } 15382292SN/A 15392292SN/A cprintf("\n"); 15402292SN/A 15412292SN/A ListOrderIt list_order_it = listOrder.begin(); 15422292SN/A ListOrderIt list_order_end_it = listOrder.end(); 15432292SN/A int i = 1; 15441681SN/A 15451681SN/A cprintf("List order: "); 15461061SN/A 15471061SN/A while (list_order_it != list_order_end_it) { 15481061SN/A cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 15491681SN/A (*list_order_it).oldestInst); 15502292SN/A 15513867Sbinkertn@umich.edu ++list_order_it; 15523867Sbinkertn@umich.edu ++i; 15536221Snate@binkert.org } 15542292SN/A 15552292SN/A cprintf("\n"); 15562292SN/A} 15572348SN/A 15582292SN/A 15592292SN/Atemplate <class Impl> 15602292SN/Avoid 15612292SN/AInstructionQueue<Impl>::dumpInsts() 15622292SN/A{ 15632292SN/A for (ThreadID tid = 0; tid < numThreads; ++tid) { 15642292SN/A int num = 0; 15652292SN/A int valid_num = 0; 15662292SN/A ListIt inst_list_it = instList[tid].begin(); 15672292SN/A 15682292SN/A while (inst_list_it != instList[tid].end()) { 15692292SN/A cprintf("Instruction:%i\n", num); 15702292SN/A if (!(*inst_list_it)->isSquashed()) { 15712292SN/A if (!(*inst_list_it)->isIssued()) { 15722292SN/A ++valid_num; 15732292SN/A cprintf("Count:%i\n", valid_num); 15742292SN/A } else if ((*inst_list_it)->isMemRef() && 15754033Sktlim@umich.edu !(*inst_list_it)->memOpDone()) { 15762292SN/A // Loads that have not been marked as executed 15772292SN/A // still count towards the total instructions. 15782292SN/A ++valid_num; 15792292SN/A cprintf("Count:%i\n", valid_num); 15802292SN/A } 15812292SN/A } 15822292SN/A 15832292SN/A cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 15842292SN/A "Issued:%i\nSquashed:%i\n", 15852292SN/A (*inst_list_it)->pcState(), 15862292SN/A (*inst_list_it)->seqNum, 15872292SN/A (*inst_list_it)->threadNumber, 15882292SN/A (*inst_list_it)->isIssued(), 15892292SN/A (*inst_list_it)->isSquashed()); 15902292SN/A 15912292SN/A if ((*inst_list_it)->isMemRef()) { 15922292SN/A cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 15932292SN/A } 15942292SN/A 15952292SN/A cprintf("\n"); 15962292SN/A 15972292SN/A inst_list_it++; 15982292SN/A ++num; 15992292SN/A } 16001061SN/A } 16011061SN/A 16022292SN/A cprintf("Insts to Execute list:\n"); 16032292SN/A 16042292SN/A int num = 0; 16052292SN/A int valid_num = 0; 16062292SN/A ListIt inst_list_it = instsToExecute.begin(); 16072292SN/A 16082292SN/A while (inst_list_it != instsToExecute.end()) 16092292SN/A { 16102292SN/A cprintf("Instruction:%i\n", 16112292SN/A num); 16121061SN/A if (!(*inst_list_it)->isSquashed()) { 16131060SN/A if (!(*inst_list_it)->isIssued()) { 16141060SN/A ++valid_num; 16152301SN/A cprintf("Count:%i\n", valid_num); 16161060SN/A } else if ((*inst_list_it)->isMemRef() && 16172301SN/A !(*inst_list_it)->memOpDone()) { 16181060SN/A // Loads that have not been marked as executed 16196221Snate@binkert.org // still count towards the total instructions. 16201060SN/A ++valid_num; 16212669Sktlim@umich.edu cprintf("Count:%i\n", valid_num); 16221060SN/A } 16238471SGiacomo.Gabrielli@arm.com } 16249527SMatt.Horsnell@arm.com 16259527SMatt.Horsnell@arm.com cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 16269527SMatt.Horsnell@arm.com "Issued:%i\nSquashed:%i\n", 16278471SGiacomo.Gabrielli@arm.com (*inst_list_it)->pcState(), 16288471SGiacomo.Gabrielli@arm.com (*inst_list_it)->seqNum, 16292301SN/A (*inst_list_it)->threadNumber, 16302301SN/A (*inst_list_it)->isIssued(), 16312301SN/A (*inst_list_it)->isSquashed()); 16322301SN/A 16336221Snate@binkert.org if ((*inst_list_it)->isMemRef()) { 16341060SN/A cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 16352301SN/A } 16362301SN/A 16372301SN/A cprintf("\n"); 16382301SN/A 16396221Snate@binkert.org inst_list_it++; 16401060SN/A ++num; 16412301SN/A } 16426221Snate@binkert.org} 16431060SN/A 16441060SN/A#endif//__CPU_O3_INST_QUEUE_IMPL_HH__ 16451060SN/A