inst_queue_impl.hh revision 13449
11689SN/A/* 29444SAndreas.Sandberg@ARM.com * Copyright (c) 2011-2014 ARM Limited 37944SGiacomo.Gabrielli@arm.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47944SGiacomo.Gabrielli@arm.com * All rights reserved. 57944SGiacomo.Gabrielli@arm.com * 67944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 77944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 87944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 97944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 107944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 117944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 127944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 137944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 142326SN/A * 151689SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392665Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412831Sksewell@umich.edu * Authors: Kevin Lim 421689SN/A * Korey Sewell 431689SN/A */ 442064SN/A 451060SN/A#ifndef __CPU_O3_INST_QUEUE_IMPL_HH__ 461060SN/A#define __CPU_O3_INST_QUEUE_IMPL_HH__ 472292SN/A 481717SN/A#include <limits> 498232Snate@binkert.org#include <vector> 504762Snate@binkert.org 516221Snate@binkert.org#include "base/logging.hh" 524762Snate@binkert.org#include "cpu/o3/fu_pool.hh" 531060SN/A#include "cpu/o3/inst_queue.hh" 548737Skoansin.tan@gmail.com#include "debug/IQ.hh" 558737Skoansin.tan@gmail.com#include "enums/OpClass.hh" 568737Skoansin.tan@gmail.com#include "params/DerivO3CPU.hh" 575529Snate@binkert.org#include "sim/core.hh" 581061SN/A 592292SN/A// clang complains about std::set being overloaded with Packet::set if 605606Snate@binkert.org// we open up the entire namespace std 618581Ssteve.reinhardt@amd.comusing std::list; 628581Ssteve.reinhardt@amd.com 631060SN/Atemplate <class Impl> 642292SN/AInstructionQueue<Impl>::FUCompletion::FUCompletion(const DynInstPtr &_inst, 652292SN/A int fu_idx, InstructionQueue<Impl> *iq_ptr) 662292SN/A : Event(Stat_Event_Pri, AutoDelete), 672292SN/A inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 682292SN/A{ 692292SN/A} 702326SN/A 712292SN/Atemplate <class Impl> 722292SN/Avoid 732292SN/AInstructionQueue<Impl>::FUCompletion::process() 742292SN/A{ 752292SN/A iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 762292SN/A inst = NULL; 775336Shines@cs.fsu.edu} 782292SN/A 794873Sstever@eecs.umich.edu 802292SN/Atemplate <class Impl> 812292SN/Aconst char * 822292SN/AInstructionQueue<Impl>::FUCompletion::description() const 834329Sktlim@umich.edu{ 845529Snate@binkert.org return "Functional unit completion"; 854329Sktlim@umich.edu} 864329Sktlim@umich.edu 874329Sktlim@umich.edutemplate <class Impl> 882292SN/AInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 892292SN/A DerivO3CPUParams *params) 902292SN/A : cpu(cpu_ptr), 912292SN/A iewStage(iew_ptr), 922292SN/A fuPool(params->fuPool), 932292SN/A numEntries(params->numIQEntries), 942292SN/A totalWidth(params->issueWidth), 952292SN/A commitToIEWDelay(params->commitToIEWDelay) 965529Snate@binkert.org{ 971060SN/A assert(fuPool); 981060SN/A 991060SN/A numThreads = params->numThreads; 1001060SN/A 1011060SN/A // Set the number of total physical registers 1021060SN/A // As the vector registers have two addressing modes, they are added twice 1032326SN/A numPhysRegs = params->numPhysIntRegs + params->numPhysFloatRegs + 1041060SN/A params->numPhysVecRegs + 1051060SN/A params->numPhysVecRegs * TheISA::NumVecElemPerVecReg + 1061060SN/A params->numPhysCCRegs; 1071060SN/A 1082292SN/A //Create an entry for each physical register within the 1096221Snate@binkert.org //dependency graph. 1106221Snate@binkert.org dependGraph.resize(numPhysRegs); 1116221Snate@binkert.org 1121060SN/A // Resize the register scoreboard. 1131060SN/A regScoreboard.resize(numPhysRegs); 1142307SN/A 1152292SN/A //Initialize Mem Dependence Units 1162980Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 1172292SN/A memDepUnit[tid].init(params, tid); 1182292SN/A memDepUnit[tid].setIQ(this); 1192292SN/A } 1202292SN/A 1212292SN/A resetState(); 1222292SN/A 1232292SN/A std::string policy = params->smtIQPolicy; 1242292SN/A 1252292SN/A //Convert string to lowercase 1262292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1276221Snate@binkert.org (int(*)(int)) tolower); 1286221Snate@binkert.org 1292292SN/A //Figure out resource sharing policy 1302292SN/A if (policy == "dynamic") { 1312292SN/A iqPolicy = Dynamic; 1322292SN/A 1332292SN/A //Set Max Entries to Total ROB Capacity 1342292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1352292SN/A maxEntries[tid] = numEntries; 1362292SN/A } 1372292SN/A 1386221Snate@binkert.org } else if (policy == "partitioned") { 1396221Snate@binkert.org iqPolicy = Partitioned; 1402292SN/A 1412292SN/A //@todo:make work if part_amt doesnt divide evenly. 1422831Sksewell@umich.edu int part_amt = numEntries / numThreads; 1432292SN/A 1442292SN/A //Divide ROB up evenly 1452292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1462292SN/A maxEntries[tid] = part_amt; 1472292SN/A } 1482292SN/A 1492292SN/A DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 1502292SN/A "%i entries per thread.\n",part_amt); 1512292SN/A } else if (policy == "threshold") { 1526221Snate@binkert.org iqPolicy = Threshold; 1536221Snate@binkert.org 1542292SN/A double threshold = (double)params->smtIQThreshold / 100; 1552292SN/A 1562831Sksewell@umich.edu int thresholdIQ = (int)((double)threshold * numEntries); 1572292SN/A 1582292SN/A //Divide up by threshold amount 1592292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1602292SN/A maxEntries[tid] = thresholdIQ; 1612292SN/A } 1622292SN/A 1632292SN/A DPRINTF(IQ, "IQ sharing policy set to Threshold:" 1642292SN/A "%i entries per thread.\n",thresholdIQ); 1652292SN/A } else { 1662292SN/A panic("Invalid IQ sharing policy. Options are: Dynamic, " 1672326SN/A "Partitioned, Threshold"); 1682348SN/A } 1692326SN/A} 1702326SN/A 1712348SN/Atemplate <class Impl> 1722292SN/AInstructionQueue<Impl>::~InstructionQueue() 1732292SN/A{ 1742292SN/A dependGraph.reset(); 1752292SN/A#ifdef DEBUG 1762292SN/A cprintf("Nodes traversed: %i, removed: %i\n", 1772292SN/A dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1782292SN/A#endif 1791060SN/A} 1801060SN/A 1811061SN/Atemplate <class Impl> 1821060SN/Astd::string 1831062SN/AInstructionQueue<Impl>::name() const 1841062SN/A{ 1852301SN/A return cpu->name() + ".iq"; 1861062SN/A} 1871062SN/A 1881062SN/Atemplate <class Impl> 1891062SN/Avoid 1901062SN/AInstructionQueue<Impl>::regStats() 1911062SN/A{ 1921062SN/A using namespace Stats; 1931062SN/A iqInstsAdded 1941062SN/A .name(name() + ".iqInstsAdded") 1951062SN/A .desc("Number of instructions added to the IQ (excludes non-spec)") 1962301SN/A .prereq(iqInstsAdded); 1972301SN/A 1982301SN/A iqNonSpecInstsAdded 1992301SN/A .name(name() + ".iqNonSpecInstsAdded") 2001062SN/A .desc("Number of non-speculative instructions added to the IQ") 2011062SN/A .prereq(iqNonSpecInstsAdded); 2021062SN/A 2031062SN/A iqInstsIssued 2041062SN/A .name(name() + ".iqInstsIssued") 2051062SN/A .desc("Number of instructions issued") 2061062SN/A .prereq(iqInstsIssued); 2071062SN/A 2081062SN/A iqIntInstsIssued 2091062SN/A .name(name() + ".iqIntInstsIssued") 2101062SN/A .desc("Number of integer instructions issued") 2111062SN/A .prereq(iqIntInstsIssued); 2121062SN/A 2131062SN/A iqFloatInstsIssued 2141062SN/A .name(name() + ".iqFloatInstsIssued") 2151062SN/A .desc("Number of float instructions issued") 2161062SN/A .prereq(iqFloatInstsIssued); 2171062SN/A 2181062SN/A iqBranchInstsIssued 2191062SN/A .name(name() + ".iqBranchInstsIssued") 2201062SN/A .desc("Number of branch instructions issued") 2211062SN/A .prereq(iqBranchInstsIssued); 2221062SN/A 2231062SN/A iqMemInstsIssued 2241062SN/A .name(name() + ".iqMemInstsIssued") 2251062SN/A .desc("Number of memory instructions issued") 2261062SN/A .prereq(iqMemInstsIssued); 2271062SN/A 2281062SN/A iqMiscInstsIssued 2291062SN/A .name(name() + ".iqMiscInstsIssued") 2301062SN/A .desc("Number of miscellaneous instructions issued") 2311062SN/A .prereq(iqMiscInstsIssued); 2321062SN/A 2331062SN/A iqSquashedInstsIssued 2341062SN/A .name(name() + ".iqSquashedInstsIssued") 2351062SN/A .desc("Number of squashed instructions issued") 2361062SN/A .prereq(iqSquashedInstsIssued); 2371062SN/A 2381062SN/A iqSquashedInstsExamined 2391062SN/A .name(name() + ".iqSquashedInstsExamined") 2401062SN/A .desc("Number of squashed instructions iterated over during squash;" 2411062SN/A " mainly for profiling") 2421062SN/A .prereq(iqSquashedInstsExamined); 2431062SN/A 2441062SN/A iqSquashedOperandsExamined 2451062SN/A .name(name() + ".iqSquashedOperandsExamined") 2461062SN/A .desc("Number of squashed operands that are examined and possibly " 2472361SN/A "removed from graph") 2482326SN/A .prereq(iqSquashedOperandsExamined); 2492301SN/A 2502301SN/A iqSquashedNonSpecRemoved 2512301SN/A .name(name() + ".iqSquashedNonSpecRemoved") 2522301SN/A .desc("Number of squashed non-spec instructions that were removed") 2532301SN/A .prereq(iqSquashedNonSpecRemoved); 2542301SN/A/* 2552326SN/A queueResDist 2562301SN/A .init(Num_OpClasses, 0, 99, 2) 2572361SN/A .name(name() + ".IQ:residence:") 2582326SN/A .desc("cycles from dispatch to issue") 2592307SN/A .flags(total | pdf | cdf ) 2608240Snate@binkert.org ; 2612301SN/A for (int i = 0; i < Num_OpClasses; ++i) { 2622307SN/A queueResDist.subname(i, opClassStrings[i]); 2632301SN/A } 2642301SN/A*/ 2652301SN/A numIssuedDist 2662301SN/A .init(0,totalWidth,1) 2678240Snate@binkert.org .name(name() + ".issued_per_cycle") 2682301SN/A .desc("Number of insts issued each cycle") 2692301SN/A .flags(pdf) 2702301SN/A ; 2712301SN/A/* 2722301SN/A dist_unissued 2732301SN/A .init(Num_OpClasses+2) 2742301SN/A .name(name() + ".unissued_cause") 2752326SN/A .desc("Reason ready instruction not issued") 2764762Snate@binkert.org .flags(pdf | dist) 2778240Snate@binkert.org ; 2782301SN/A for (int i=0; i < (Num_OpClasses + 2); ++i) { 2792301SN/A dist_unissued.subname(i, unissued_names[i]); 2802301SN/A } 2814762Snate@binkert.org*/ 2822301SN/A statIssuedInstType 2832301SN/A .init(numThreads,Enums::Num_OpClass) 2842301SN/A .name(name() + ".FU_type") 2852301SN/A .desc("Type of FU issued") 2862361SN/A .flags(total | pdf | dist) 2872326SN/A ; 2882301SN/A statIssuedInstType.ysubnames(Enums::OpClassStrings); 2898240Snate@binkert.org 2902301SN/A // 2912301SN/A // How long did instructions for a particular FU type wait prior to issue 2922301SN/A // 2932301SN/A/* 2942301SN/A issueDelayDist 2952980Sgblack@eecs.umich.edu .init(Num_OpClasses,0,99,2) 2962301SN/A .name(name() + ".") 2972326SN/A .desc("cycles from operands ready to issue") 2982301SN/A .flags(pdf | cdf) 2992361SN/A ; 3002326SN/A 3018240Snate@binkert.org for (int i=0; i<Num_OpClasses; ++i) { 3022301SN/A std::stringstream subname; 3032301SN/A subname << opClassStrings[i] << "_delay"; 3042301SN/A issueDelayDist.subname(i, subname.str()); 3052326SN/A } 3062727Sktlim@umich.edu*/ 3072326SN/A issueRate 3082301SN/A .name(name() + ".rate") 3098240Snate@binkert.org .desc("Inst issue rate") 3102301SN/A .flags(total) 3112301SN/A ; 3122301SN/A issueRate = iqInstsIssued / cpu->numCycles; 3132301SN/A 3144762Snate@binkert.org statFuBusy 3152301SN/A .init(Num_OpClasses) 3162301SN/A .name(name() + ".fu_full") 3172326SN/A .desc("attempts to use FU when none available") 3182301SN/A .flags(pdf | dist) 3198240Snate@binkert.org ; 3202301SN/A for (int i=0; i < Num_OpClasses; ++i) { 3212301SN/A statFuBusy.subname(i, Enums::OpClassStrings[i]); 3222301SN/A } 3232301SN/A 3242326SN/A fuBusy 3258240Snate@binkert.org .init(numThreads) 3262301SN/A .name(name() + ".fu_busy_cnt") 3272301SN/A .desc("FU busy when requested") 3282301SN/A .flags(total) 3292326SN/A ; 3302301SN/A 3316221Snate@binkert.org fuBusyRate 3322292SN/A .name(name() + ".fu_busy_rate") 3336221Snate@binkert.org .desc("FU busy rate (busy events/executed inst)") 3342292SN/A .flags(total) 3357897Shestness@cs.utexas.edu ; 3367897Shestness@cs.utexas.edu fuBusyRate = fuBusy / iqInstsIssued; 3377897Shestness@cs.utexas.edu 3387897Shestness@cs.utexas.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 3397897Shestness@cs.utexas.edu // Tell mem dependence unit to reg stats as well. 3407897Shestness@cs.utexas.edu memDepUnit[tid].regStats(); 3417897Shestness@cs.utexas.edu } 3427897Shestness@cs.utexas.edu 3437897Shestness@cs.utexas.edu intInstQueueReads 3447897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_reads") 3457897Shestness@cs.utexas.edu .desc("Number of integer instruction queue reads") 3467897Shestness@cs.utexas.edu .flags(total); 3477897Shestness@cs.utexas.edu 3487897Shestness@cs.utexas.edu intInstQueueWrites 3497897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_writes") 3507897Shestness@cs.utexas.edu .desc("Number of integer instruction queue writes") 3517897Shestness@cs.utexas.edu .flags(total); 3527897Shestness@cs.utexas.edu 3537897Shestness@cs.utexas.edu intInstQueueWakeupAccesses 3547897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_wakeup_accesses") 3557897Shestness@cs.utexas.edu .desc("Number of integer instruction queue wakeup accesses") 3567897Shestness@cs.utexas.edu .flags(total); 3577897Shestness@cs.utexas.edu 3587897Shestness@cs.utexas.edu fpInstQueueReads 3597897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_reads") 3607897Shestness@cs.utexas.edu .desc("Number of floating instruction queue reads") 3617897Shestness@cs.utexas.edu .flags(total); 3627897Shestness@cs.utexas.edu 3637897Shestness@cs.utexas.edu fpInstQueueWrites 3647897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_writes") 3657897Shestness@cs.utexas.edu .desc("Number of floating instruction queue writes") 3667897Shestness@cs.utexas.edu .flags(total); 3677897Shestness@cs.utexas.edu 3687897Shestness@cs.utexas.edu fpInstQueueWakeupAccesses 3697897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_wakeup_accesses") 3707897Shestness@cs.utexas.edu .desc("Number of floating instruction queue wakeup accesses") 3717897Shestness@cs.utexas.edu .flags(total); 3727897Shestness@cs.utexas.edu 3737897Shestness@cs.utexas.edu vecInstQueueReads 3747897Shestness@cs.utexas.edu .name(name() + ".vec_inst_queue_reads") 3757897Shestness@cs.utexas.edu .desc("Number of vector instruction queue reads") 3761062SN/A .flags(total); 3771062SN/A 3781062SN/A vecInstQueueWrites 3791062SN/A .name(name() + ".vec_inst_queue_writes") 3802307SN/A .desc("Number of vector instruction queue writes") 3811060SN/A .flags(total); 3822307SN/A 3836221Snate@binkert.org vecInstQueueWakeupAccesses 3846221Snate@binkert.org .name(name() + ".vec_inst_queue_wakeup_accesses") 3856221Snate@binkert.org .desc("Number of vector instruction queue wakeup accesses") 3862307SN/A .flags(total); 3871060SN/A 3882307SN/A intAluAccesses 3892307SN/A .name(name() + ".int_alu_accesses") 3902307SN/A .desc("Number of integer alu accesses") 3912307SN/A .flags(total); 3922307SN/A 3932307SN/A fpAluAccesses 3942307SN/A .name(name() + ".fp_alu_accesses") 3952307SN/A .desc("Number of floating point alu accesses") 3962307SN/A .flags(total); 3972307SN/A 3982307SN/A vecAluAccesses 3992307SN/A .name(name() + ".vec_alu_accesses") 4006221Snate@binkert.org .desc("Number of vector alu accesses") 4016221Snate@binkert.org .flags(total); 4022307SN/A 4032307SN/A} 4042307SN/A 4052307SN/Atemplate <class Impl> 4062307SN/Avoid 4072307SN/AInstructionQueue<Impl>::resetState() 4082307SN/A{ 4092307SN/A //Initialize thread IQ counts 4102307SN/A for (ThreadID tid = 0; tid <numThreads; tid++) { 4112307SN/A count[tid] = 0; 4127944SGiacomo.Gabrielli@arm.com instList[tid].clear(); 4131060SN/A } 4141060SN/A 4151061SN/A // Initialize the number of free IQ entries. 4161060SN/A freeEntries = numEntries; 4176221Snate@binkert.org 4181060SN/A // Note that in actuality, the registers corresponding to the logical 4192292SN/A // registers start off as ready. However this doesn't matter for the 4202064SN/A // IQ as the instruction should have been correctly told if those 4212064SN/A // registers are ready in rename. Thus it can all be initialized as 4222064SN/A // unready. 4232064SN/A for (int i = 0; i < numPhysRegs; ++i) { 4242292SN/A regScoreboard[i] = false; 4252064SN/A } 4264318Sktlim@umich.edu 4271060SN/A for (ThreadID tid = 0; tid < numThreads; ++tid) { 4281060SN/A squashedSeqNum[tid] = 0; 4291061SN/A } 4301060SN/A 4311060SN/A for (int i = 0; i < Num_OpClasses; ++i) { 4321060SN/A while (!readyInsts[i].empty()) 4331060SN/A readyInsts[i].pop(); 4341060SN/A queueOnList[i] = false; 4351060SN/A readyIt[i] = listOrder.end(); 4361060SN/A } 4371060SN/A nonSpecInsts.clear(); 4381684SN/A listOrder.clear(); 4392307SN/A deferredMemInsts.clear(); 4409444SAndreas.Sandberg@ARM.com blockedMemInsts.clear(); 4412307SN/A retryMemInsts.clear(); 4429444SAndreas.Sandberg@ARM.com wbOutstanding = 0; 4439444SAndreas.Sandberg@ARM.com} 4449444SAndreas.Sandberg@ARM.com 4459444SAndreas.Sandberg@ARM.comtemplate <class Impl> 4462307SN/Avoid 4472307SN/AInstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 4482307SN/A{ 4492307SN/A activeThreads = at_ptr; 4502307SN/A} 4512307SN/A 4529444SAndreas.Sandberg@ARM.comtemplate <class Impl> 4532307SN/Avoid 4542307SN/AInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 4552307SN/A{ 4562292SN/A issueToExecuteQueue = i2e_ptr; 4576221Snate@binkert.org} 4582292SN/A 4592292SN/Atemplate <class Impl> 4602292SN/Avoid 4612292SN/AInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 4622292SN/A{ 4632292SN/A timeBuffer = tb_ptr; 4642292SN/A 4652292SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 4662292SN/A} 4672292SN/A 4682292SN/Atemplate <class Impl> 4692292SN/Abool 4702292SN/AInstructionQueue<Impl>::isDrained() const 4712292SN/A{ 4723867Sbinkertn@umich.edu bool drained = dependGraph.empty() && 4732292SN/A instsToExecute.empty() && 4746221Snate@binkert.org wbOutstanding == 0; 4756221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 4762292SN/A drained = drained && memDepUnit[tid].isDrained(); 4773867Sbinkertn@umich.edu 4786221Snate@binkert.org return drained; 4793867Sbinkertn@umich.edu} 4802292SN/A 4813867Sbinkertn@umich.edutemplate <class Impl> 4822292SN/Avoid 4833867Sbinkertn@umich.eduInstructionQueue<Impl>::drainSanityCheck() const 4842292SN/A{ 4852292SN/A assert(dependGraph.empty()); 4862292SN/A assert(instsToExecute.empty()); 4872292SN/A for (ThreadID tid = 0; tid < numThreads; ++tid) 4882292SN/A memDepUnit[tid].drainSanityCheck(); 4892292SN/A} 4901684SN/A 4911684SN/Atemplate <class Impl> 4921684SN/Avoid 4931684SN/AInstructionQueue<Impl>::takeOverFrom() 4941684SN/A{ 4951684SN/A resetState(); 4962292SN/A} 4972292SN/A 4986221Snate@binkert.orgtemplate <class Impl> 4992292SN/Aint 5002292SN/AInstructionQueue<Impl>::entryAmount(ThreadID num_threads) 5012292SN/A{ 5022292SN/A if (iqPolicy == Partitioned) { 5031060SN/A return numEntries / num_threads; 5041060SN/A } else { 5051061SN/A return 0; 5061060SN/A } 5071060SN/A} 5081060SN/A 5091060SN/A 5101060SN/Atemplate <class Impl> 5111060SN/Avoid 5121060SN/AInstructionQueue<Impl>::resetEntries() 5131060SN/A{ 5141060SN/A if (iqPolicy != Dynamic || numThreads > 1) { 5151060SN/A int active_threads = activeThreads->size(); 5161061SN/A 5172292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 5186221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 5192292SN/A 5202292SN/A while (threads != end) { 5212292SN/A ThreadID tid = *threads++; 5222292SN/A 5232292SN/A if (iqPolicy == Partitioned) { 5242292SN/A maxEntries[tid] = numEntries / active_threads; 5252292SN/A } else if (iqPolicy == Threshold && active_threads == 1) { 5262292SN/A maxEntries[tid] = numEntries; 5272292SN/A } 5282292SN/A } 5292292SN/A } 5302292SN/A} 5312292SN/A 5322292SN/Atemplate <class Impl> 5332292SN/Aunsigned 5342292SN/AInstructionQueue<Impl>::numFreeEntries() 5352292SN/A{ 5362292SN/A return freeEntries; 5372292SN/A} 5382292SN/A 5392292SN/Atemplate <class Impl> 5402292SN/Aunsigned 5412292SN/AInstructionQueue<Impl>::numFreeEntries(ThreadID tid) 5422292SN/A{ 5432292SN/A return maxEntries[tid] - count[tid]; 5442292SN/A} 5451060SN/A 5461061SN/A// Might want to do something more complex if it knows how many instructions 5471060SN/A// will be issued this cycle. 5487897Shestness@cs.utexas.edutemplate <class Impl> 5491060SN/Abool 5501060SN/AInstructionQueue<Impl>::isFull() 5511060SN/A{ 5527720Sgblack@eecs.umich.edu if (freeEntries == 0) { 5537720Sgblack@eecs.umich.edu return(true); 5541060SN/A } else { 5551060SN/A return(false); 5561060SN/A } 5572292SN/A} 5581060SN/A 5592064SN/Atemplate <class Impl> 5601060SN/Abool 5612292SN/AInstructionQueue<Impl>::isFull(ThreadID tid) 5621060SN/A{ 5631060SN/A if (numFreeEntries(tid) == 0) { 5641060SN/A return(true); 5651060SN/A } else { 5661060SN/A return(false); 5671060SN/A } 5681060SN/A} 5692326SN/A 5701060SN/Atemplate <class Impl> 5711061SN/Abool 5722292SN/AInstructionQueue<Impl>::hasReadyInsts() 5731062SN/A{ 5741062SN/A if (!listOrder.empty()) { 5751061SN/A return true; 5761061SN/A } 5771062SN/A 5781060SN/A for (int i = 0; i < Num_OpClasses; ++i) { 5792292SN/A if (!readyInsts[i].empty()) { 5802292SN/A return true; 5811060SN/A } 5821060SN/A } 5831060SN/A 5841061SN/A return false; 5851061SN/A} 5862292SN/A 5871061SN/Atemplate <class Impl> 5881061SN/Avoid 5891061SN/AInstructionQueue<Impl>::insert(const DynInstPtr &new_inst) 5907897Shestness@cs.utexas.edu{ 5911061SN/A if (new_inst->isFloating()) { 5922292SN/A fpInstQueueWrites++; 5931061SN/A } else if (new_inst->isVector()) { 5942292SN/A vecInstQueueWrites++; 5951061SN/A } else { 5967720Sgblack@eecs.umich.edu intInstQueueWrites++; 5972326SN/A } 5987720Sgblack@eecs.umich.edu // Make sure the instruction is valid 5992064SN/A assert(new_inst); 6001061SN/A 6011061SN/A DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n", 6022292SN/A new_inst->seqNum, new_inst->pcState()); 6031061SN/A 6042064SN/A assert(freeEntries != 0); 6051061SN/A 6062292SN/A instList[new_inst->threadNumber].push_back(new_inst); 6071061SN/A 6081061SN/A --freeEntries; 6091061SN/A 6102326SN/A new_inst->setInIQ(); 6111061SN/A 6121061SN/A // Look through its source registers (physical regs), and mark any 6131061SN/A // dependencies. 6142292SN/A addToDependents(new_inst); 6152292SN/A 6161061SN/A // Have this instruction set itself as the producer of its destination 6171062SN/A // register(s). 6181062SN/A addToProducers(new_inst); 6192292SN/A 6202292SN/A if (new_inst->isMemRef()) { 6212292SN/A memDepUnit[new_inst->threadNumber].insert(new_inst); 6222292SN/A } else { 6231061SN/A addIfReady(new_inst); 6241061SN/A } 6251061SN/A 6261060SN/A ++iqInstsAdded; 6272292SN/A 6281060SN/A count[new_inst->threadNumber]++; 6292292SN/A 6301060SN/A assert(freeEntries == (numEntries - countInsts())); 6312292SN/A} 6322292SN/A 6331060SN/Atemplate <class Impl> 6342064SN/Avoid 6352333SN/AInstructionQueue<Impl>::insertNonSpec(const DynInstPtr &new_inst) 6362333SN/A{ 6372333SN/A // @todo: Clean up this code; can do it by setting inst as unable 6382333SN/A // to issue, then calling normal insert on the inst. 6392333SN/A if (new_inst->isFloating()) { 6402333SN/A fpInstQueueWrites++; 6417897Shestness@cs.utexas.edu } else if (new_inst->isVector()) { 6427897Shestness@cs.utexas.edu vecInstQueueWrites++; 6437897Shestness@cs.utexas.edu } else { 6447897Shestness@cs.utexas.edu intInstQueueWrites++; 6457897Shestness@cs.utexas.edu } 6462333SN/A 6472333SN/A assert(new_inst); 6481060SN/A 6492333SN/A nonSpecInsts[new_inst->seqNum] = new_inst; 6502064SN/A 6512292SN/A DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s " 6522292SN/A "to the IQ.\n", 6532292SN/A new_inst->seqNum, new_inst->pcState()); 6542292SN/A 6552292SN/A assert(freeEntries != 0); 6562292SN/A 6572292SN/A instList[new_inst->threadNumber].push_back(new_inst); 6582292SN/A 6592292SN/A --freeEntries; 6602292SN/A 6612292SN/A new_inst->setInIQ(); 6622292SN/A 6632292SN/A // Have this instruction set itself as the producer of its destination 6642292SN/A // register(s). 6652292SN/A addToProducers(new_inst); 6662292SN/A 6672292SN/A // If it's a memory instruction, add it to the memory dependency 6682292SN/A // unit. 6692292SN/A if (new_inst->isMemRef()) { 6701060SN/A memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 6711060SN/A } 6722292SN/A 6732292SN/A ++iqNonSpecInstsAdded; 6742292SN/A 6751060SN/A count[new_inst->threadNumber]++; 6762292SN/A 6772292SN/A assert(freeEntries == (numEntries - countInsts())); 6782292SN/A} 6792292SN/A 6802292SN/Atemplate <class Impl> 6812292SN/Avoid 6822292SN/AInstructionQueue<Impl>::insertBarrier(const DynInstPtr &barr_inst) 6832292SN/A{ 6842292SN/A memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 6852292SN/A 6862292SN/A insertNonSpec(barr_inst); 6872292SN/A} 6882292SN/A 6892292SN/Atemplate <class Impl> 6902292SN/Atypename Impl::DynInstPtr 6912292SN/AInstructionQueue<Impl>::getInstToExecute() 6922292SN/A{ 6932292SN/A assert(!instsToExecute.empty()); 6942292SN/A DynInstPtr inst = std::move(instsToExecute.front()); 6952292SN/A instsToExecute.pop_front(); 6962292SN/A if (inst->isFloating()) { 6971060SN/A fpInstQueueReads++; 6981060SN/A } else if (inst->isVector()) { 6992292SN/A vecInstQueueReads++; 7001060SN/A } else { 7011060SN/A intInstQueueReads++; 7022292SN/A } 7032292SN/A return inst; 7042292SN/A} 7052292SN/A 7062367SN/Atemplate <class Impl> 7079444SAndreas.Sandberg@ARM.comvoid 7082292SN/AInstructionQueue<Impl>::addToOrderList(OpClass op_class) 7092292SN/A{ 7102292SN/A assert(!readyInsts[op_class].empty()); 7112292SN/A 7122326SN/A ListOrderEntry queue_entry; 7132326SN/A 7142292SN/A queue_entry.queueType = op_class; 7152326SN/A 7162326SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 7172326SN/A 7185327Smengke97@hotmail.com ListOrderIt list_it = listOrder.begin(); 7192333SN/A ListOrderIt list_end_it = listOrder.end(); 7202292SN/A 7212292SN/A while (list_it != list_end_it) { 7221061SN/A if ((*list_it).oldestInst > queue_entry.oldestInst) { 7231061SN/A break; 7241061SN/A } 7251061SN/A 7261060SN/A list_it++; 7271060SN/A } 7281060SN/A 7292292SN/A readyIt[op_class] = listOrder.insert(list_it, queue_entry); 7302292SN/A queueOnList[op_class] = true; 7311060SN/A} 7321060SN/A 7331060SN/Atemplate <class Impl> 7347944SGiacomo.Gabrielli@arm.comvoid 7357944SGiacomo.Gabrielli@arm.comInstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 7367944SGiacomo.Gabrielli@arm.com{ 7377962Ssaidi@eecs.umich.edu // Get iterator of next item on the list 7387944SGiacomo.Gabrielli@arm.com // Delete the original iterator 7397944SGiacomo.Gabrielli@arm.com // Determine if the next item is either the end of the list or younger 7407944SGiacomo.Gabrielli@arm.com // than the new instruction. If so, then add in a new iterator right here. 7417944SGiacomo.Gabrielli@arm.com // If not, then move along. 7427944SGiacomo.Gabrielli@arm.com ListOrderEntry queue_entry; 7432292SN/A OpClass op_class = (*list_order_it).queueType; 7442292SN/A ListOrderIt next_it = list_order_it; 7452292SN/A 7462292SN/A ++next_it; 7472292SN/A 7482292SN/A queue_entry.queueType = op_class; 7492292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 7502292SN/A 7512292SN/A while (next_it != listOrder.end() && 7522292SN/A (*next_it).oldestInst < queue_entry.oldestInst) { 7532292SN/A ++next_it; 7541060SN/A } 7557944SGiacomo.Gabrielli@arm.com 7562820Sktlim@umich.edu readyIt[op_class] = listOrder.insert(next_it, queue_entry); 7572326SN/A} 7582292SN/A 7591060SN/Atemplate <class Impl> 7602292SN/Avoid 7611060SN/AInstructionQueue<Impl>::processFUCompletion(const DynInstPtr &inst, int fu_idx) 7622292SN/A{ 7631060SN/A DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 7647897Shestness@cs.utexas.edu assert(!cpu->switchedOut()); 7657897Shestness@cs.utexas.edu // The CPU could have been sleeping until this op completed (*extremely* 7662292SN/A // long latency op). Wake it if it was. This may be overkill. 7671060SN/A --wbOutstanding; 7682292SN/A iewStage->wakeCPU(); 7692292SN/A 7701060SN/A if (fu_idx > -1) 7712292SN/A fuPool->freeUnitNextCycle(fu_idx); 7722292SN/A 7732292SN/A // @todo: Ensure that these FU Completions happen at the beginning 7742292SN/A // of a cycle, otherwise they could add too many instructions to 7752292SN/A // the queue. 7761060SN/A issueToExecuteQueue->access(-1)->size++; 7771060SN/A instsToExecute.push_back(inst); 7782292SN/A} 7791060SN/A 7802292SN/A// @todo: Figure out a better way to remove the squashed items from the 7812292SN/A// lists. Checking the top item of each list to see if it's squashed 7822292SN/A// wastes time and forces jumps. 7831060SN/Atemplate <class Impl> 7841060SN/Avoid 7852326SN/AInstructionQueue<Impl>::scheduleReadyInsts() 7869184Sandreas.hansson@arm.com{ 7876221Snate@binkert.org DPRINTF(IQ, "Attempting to schedule ready instructions from " 7881060SN/A "the IQ.\n"); 7892326SN/A 7902326SN/A IssueStruct *i2e_info = issueToExecuteQueue->access(0); 7917897Shestness@cs.utexas.edu 7922326SN/A DynInstPtr mem_inst; 7932326SN/A while (mem_inst = std::move(getDeferredMemInstToExecute())) { 7941060SN/A addReadyMemInst(mem_inst); 7951060SN/A } 7961060SN/A 7972348SN/A // See if any cache blocked instructions are able to be executed 7982348SN/A while (mem_inst = std::move(getBlockedMemInstToExecute())) { 7992326SN/A addReadyMemInst(mem_inst); 8009184Sandreas.hansson@arm.com } 8012292SN/A 8022333SN/A // Have iterator to head of the list 8031060SN/A // While I haven't exceeded bandwidth or reached the end of the list, 8042326SN/A // Try to get a FU that can do what this op needs. 8052326SN/A // If successful, change the oldestInst to the new top of the list, put 8062326SN/A // the queue in the proper place in the list. 8072326SN/A // Increment the iterator. 8082292SN/A // This will avoid trying to schedule a certain op class if there are no 8099184Sandreas.hansson@arm.com // FUs that handle it. 8102326SN/A int total_issued = 0; 8112326SN/A ListOrderIt order_it = listOrder.begin(); 8122326SN/A ListOrderIt order_end_it = listOrder.end(); 8131060SN/A 8149180Sandreas.hansson@arm.com while (total_issued < totalWidth && order_it != order_end_it) { 8159180Sandreas.hansson@arm.com OpClass op_class = (*order_it).queueType; 8161060SN/A 8172326SN/A assert(!readyInsts[op_class].empty()); 8189184Sandreas.hansson@arm.com 8192348SN/A DynInstPtr issuing_inst = readyInsts[op_class].top(); 8202348SN/A 8212326SN/A if (issuing_inst->isFloating()) { 8222292SN/A fpInstQueueReads++; 8232292SN/A } else if (issuing_inst->isVector()) { 8242326SN/A vecInstQueueReads++; 8252292SN/A } else { 8261060SN/A intInstQueueReads++; 8271060SN/A } 8287720Sgblack@eecs.umich.edu 8292292SN/A assert(issuing_inst->seqNum == (*order_it).oldestInst); 8307720Sgblack@eecs.umich.edu 8312292SN/A if (issuing_inst->isSquashed()) { 8321060SN/A readyInsts[op_class].pop(); 8332292SN/A 8341061SN/A if (!readyInsts[op_class].empty()) { 8352292SN/A moveToYoungerInst(order_it); 8362292SN/A } else { 8372292SN/A readyIt[op_class] = listOrder.end(); 8382292SN/A queueOnList[op_class] = false; 8392292SN/A } 8401060SN/A 8411060SN/A listOrder.erase(order_it++); 8422064SN/A 8432292SN/A ++iqSquashedInstsIssued; 8442064SN/A 8458471SGiacomo.Gabrielli@arm.com continue; 8469046SAli.Saidi@ARM.com } 8478471SGiacomo.Gabrielli@arm.com 8488471SGiacomo.Gabrielli@arm.com int idx = FUPool::NoCapableFU; 8492292SN/A Cycles op_latency = Cycles(1); 8502292SN/A ThreadID tid = issuing_inst->threadNumber; 8512292SN/A 8522292SN/A if (op_class != No_OpClass) { 8532301SN/A idx = fuPool->getUnit(op_class); 8542731Sktlim@umich.edu if (issuing_inst->isFloating()) { 8552292SN/A fpAluAccesses++; 8562301SN/A } else if (issuing_inst->isVector()) { 8572292SN/A vecAluAccesses++; 8582292SN/A } else { 8592292SN/A intAluAccesses++; 8602326SN/A } 8612820Sktlim@umich.edu if (idx > FUPool::NoFreeFU) { 8622292SN/A op_latency = fuPool->getOpLatency(op_class); 8632326SN/A } 8642326SN/A } 8652292SN/A 8661060SN/A // If we have an instruction that doesn't require a FU, or a 8671060SN/A // valid FU, then schedule for execution. 8681062SN/A if (idx != FUPool::NoFreeFU) { 8692326SN/A if (op_latency == Cycles(1)) { 8702326SN/A i2e_info->size++; 8712307SN/A instsToExecute.push_back(issuing_inst); 8722348SN/A 8738071SAli.Saidi@ARM.com // Add the FU onto the list of FU's to be freed next 8748071SAli.Saidi@ARM.com // cycle if we used one. 8758071SAli.Saidi@ARM.com if (idx >= 0) 8768071SAli.Saidi@ARM.com fuPool->freeUnitNextCycle(idx); 8772292SN/A } else { 8782292SN/A bool pipelined = fuPool->isPipelined(op_class); 8792292SN/A // Generate completion event for the FU 8802292SN/A ++wbOutstanding; 8811060SN/A FUCompletion *execution = new FUCompletion(issuing_inst, 8821060SN/A idx, this); 8831061SN/A 8841060SN/A cpu->schedule(execution, 8851061SN/A cpu->clockEdge(Cycles(op_latency - 1))); 8861060SN/A 8872292SN/A if (!pipelined) { 8882292SN/A // If FU isn't pipelined, then it must be freed 8891062SN/A // upon the execution completing. 8902292SN/A execution->setFreeFU(); 8911060SN/A } else { 8921061SN/A // Add the FU onto the list of FU's to be freed next cycle. 8931060SN/A fuPool->freeUnitNextCycle(idx); 8946221Snate@binkert.org } 8952292SN/A } 8964033Sktlim@umich.edu 8974033Sktlim@umich.edu DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 8981061SN/A "[sn:%lli]\n", 8991060SN/A tid, issuing_inst->pcState(), 9001062SN/A issuing_inst->seqNum); 9011062SN/A 9021062SN/A readyInsts[op_class].pop(); 9032292SN/A 9041062SN/A if (!readyInsts[op_class].empty()) { 9051060SN/A moveToYoungerInst(order_it); 9062292SN/A } else { 9072292SN/A readyIt[op_class] = listOrder.end(); 9081061SN/A queueOnList[op_class] = false; 9091060SN/A } 9101060SN/A 9111061SN/A issuing_inst->setIssued(); 9121061SN/A ++total_issued; 9136221Snate@binkert.org 9142292SN/A#if TRACING_ON 9152292SN/A issuing_inst->issueTick = curTick() - issuing_inst->fetchTick; 9162292SN/A#endif 9172292SN/A 9182292SN/A if (!issuing_inst->isMemRef()) { 9192292SN/A // Memory instructions can not be freed from the IQ until they 9202292SN/A // complete. 9212292SN/A ++freeEntries; 9222292SN/A count[tid]--; 9232292SN/A issuing_inst->clearInIQ(); 9242292SN/A } else { 9252292SN/A memDepUnit[tid].issue(issuing_inst); 9262292SN/A } 9272292SN/A 9282292SN/A listOrder.erase(order_it++); 9292292SN/A statIssuedInstType[tid][op_class]++; 9302301SN/A } else { 9311684SN/A statFuBusy[op_class]++; 9321684SN/A fuBusy[tid]++; 9332301SN/A ++order_it; 9342301SN/A } 9357897Shestness@cs.utexas.edu } 9367897Shestness@cs.utexas.edu 9377897Shestness@cs.utexas.edu numIssuedDist.sample(total_issued); 9387897Shestness@cs.utexas.edu iqInstsIssued+= total_issued; 9397897Shestness@cs.utexas.edu 9407897Shestness@cs.utexas.edu // If we issued any instructions, tell the CPU we had activity. 9417897Shestness@cs.utexas.edu // @todo If the way deferred memory instructions are handeled due to 9422292SN/A // translation changes then the deferredMemInsts condition should be removed 9432292SN/A // from the code below. 9442292SN/A if (total_issued || !retryMemInsts.empty() || !deferredMemInsts.empty()) { 9451684SN/A cpu->activityThisCycle(); 9461684SN/A } else { 9472292SN/A DPRINTF(IQ, "Not able to schedule any instructions.\n"); 9482326SN/A } 9492326SN/A} 9502326SN/A 9512326SN/Atemplate <class Impl> 9521684SN/Avoid 9532292SN/AInstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 9542292SN/A{ 9552292SN/A DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 9562292SN/A "to execute.\n", inst); 9572292SN/A 9581684SN/A NonSpecMapIt inst_it = nonSpecInsts.find(inst); 9591684SN/A 9601684SN/A assert(inst_it != nonSpecInsts.end()); 9611684SN/A 9621684SN/A ThreadID tid = (*inst_it).second->threadNumber; 9631684SN/A 9641684SN/A (*inst_it).second->setAtCommit(); 9651684SN/A 9661684SN/A (*inst_it).second->setCanIssue(); 9671684SN/A 9681684SN/A if (!(*inst_it).second->isMemRef()) { 9691684SN/A addIfReady((*inst_it).second); 9701684SN/A } else { 9717599Sminkyu.jeong@arm.com memDepUnit[tid].nonSpecInstReady((*inst_it).second); 9727599Sminkyu.jeong@arm.com } 9731684SN/A 9741684SN/A (*inst_it).second = NULL; 9751684SN/A 9762292SN/A nonSpecInsts.erase(inst_it); 9771684SN/A} 9781684SN/A 9792326SN/Atemplate <class Impl> 9802326SN/Avoid 9812326SN/AInstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 9821684SN/A{ 9832326SN/A DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 9847599Sminkyu.jeong@arm.com tid,inst); 9857720Sgblack@eecs.umich.edu 9861684SN/A ListIt iq_it = instList[tid].begin(); 9871684SN/A 9882326SN/A while (iq_it != instList[tid].end() && 9892326SN/A (*iq_it)->seqNum <= inst) { 9902326SN/A ++iq_it; 9912326SN/A instList[tid].pop_front(); 9921684SN/A } 9932326SN/A 9941684SN/A assert(freeEntries == (numEntries - countInsts())); 9952326SN/A} 9961684SN/A 9972301SN/Atemplate <class Impl> 9981684SN/Aint 9991684SN/AInstructionQueue<Impl>::wakeDependents(const DynInstPtr &completed_inst) 10002326SN/A{ 10012326SN/A int dependents = 0; 10022326SN/A 10032326SN/A // The instruction queue here takes care of both floating and int ops 10041684SN/A if (completed_inst->isFloating()) { 10051684SN/A fpInstQueueWakeupAccesses++; 10061684SN/A } else if (completed_inst->isVector()) { 10071684SN/A vecInstQueueWakeupAccesses++; 10082301SN/A } else { 10092064SN/A intInstQueueWakeupAccesses++; 10102064SN/A } 10112064SN/A 10122064SN/A DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 10132292SN/A 10142064SN/A assert(!completed_inst->isSquashed()); 10152292SN/A 10162292SN/A // Tell the memory dependence unit to wake any dependents on this 10172292SN/A // instruction if it is a memory instruction. Also complete the memory 10182292SN/A // instruction at this point since we know it executed without issues. 10192326SN/A // @todo: Might want to rename "completeMemInst" to something that 10202326SN/A // indicates that it won't need to be replayed, and call this 10212326SN/A // earlier. Might not be a big deal. 10222326SN/A if (completed_inst->isMemRef()) { 10232326SN/A memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 10242326SN/A completeMemInst(completed_inst); 10252326SN/A } else if (completed_inst->isMemBarrier() || 10262326SN/A completed_inst->isWriteBarrier()) { 10272326SN/A memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 10282326SN/A } 10292292SN/A 10307720Sgblack@eecs.umich.edu for (int dest_reg_idx = 0; 10317720Sgblack@eecs.umich.edu dest_reg_idx < completed_inst->numDestRegs(); 10322064SN/A dest_reg_idx++) 10332064SN/A { 10342064SN/A PhysRegIdPtr dest_reg = 10352064SN/A completed_inst->renamedDestRegIdx(dest_reg_idx); 10362292SN/A 10372064SN/A // Special case of uniq or control registers. They are not 10384033Sktlim@umich.edu // handled by the IQ and thus have no dependency graph entry. 10397944SGiacomo.Gabrielli@arm.com if (dest_reg->isFixedMapping()) { 10407944SGiacomo.Gabrielli@arm.com DPRINTF(IQ, "Reg %d [%s] is part of a fix mapping, skipping\n", 10419046SAli.Saidi@ARM.com dest_reg->index(), dest_reg->className()); 10429046SAli.Saidi@ARM.com continue; 10437944SGiacomo.Gabrielli@arm.com } 10444033Sktlim@umich.edu 10452292SN/A DPRINTF(IQ, "Waking any dependents on register %i (%s).\n", 10462064SN/A dest_reg->index(), 10472064SN/A dest_reg->className()); 10482064SN/A 10492064SN/A //Go through the dependency chain, marking the registers as 10502292SN/A //ready within the waiting instructions. 10512064SN/A DynInstPtr dep_inst = dependGraph.pop(dest_reg->flatIndex()); 10522292SN/A 10532292SN/A while (dep_inst) { 10542292SN/A DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] " 10552292SN/A "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 10562292SN/A 10572292SN/A // Might want to give more information to the instruction 10582292SN/A // so that it knows which of its source registers is 10596221Snate@binkert.org // ready. However that would mean that the dependency 10602292SN/A // graph entries would need to hold the src_reg_idx. 10617720Sgblack@eecs.umich.edu dep_inst->markSrcRegReady(); 10627720Sgblack@eecs.umich.edu 10632292SN/A addIfReady(dep_inst); 10642292SN/A 10652292SN/A dep_inst = dependGraph.pop(dest_reg->flatIndex()); 10669046SAli.Saidi@ARM.com 10672292SN/A ++dependents; 10682292SN/A } 10692292SN/A 10701684SN/A // Reset the head node now that all of its dependents have 10711684SN/A // been woken up. 10721684SN/A assert(dependGraph.empty(dest_reg->flatIndex())); 10731684SN/A dependGraph.clearInst(dest_reg->flatIndex()); 10747944SGiacomo.Gabrielli@arm.com 10757944SGiacomo.Gabrielli@arm.com // Mark the scoreboard as having that register ready. 10767944SGiacomo.Gabrielli@arm.com regScoreboard[dest_reg->flatIndex()] = true; 10777944SGiacomo.Gabrielli@arm.com } 10787944SGiacomo.Gabrielli@arm.com return dependents; 10797944SGiacomo.Gabrielli@arm.com} 10807944SGiacomo.Gabrielli@arm.com 10817944SGiacomo.Gabrielli@arm.comtemplate <class Impl> 10827944SGiacomo.Gabrielli@arm.comvoid 10837944SGiacomo.Gabrielli@arm.comInstructionQueue<Impl>::addReadyMemInst(const DynInstPtr &ready_inst) 10847944SGiacomo.Gabrielli@arm.com{ 10859046SAli.Saidi@ARM.com OpClass op_class = ready_inst->opClass(); 10867944SGiacomo.Gabrielli@arm.com 10877944SGiacomo.Gabrielli@arm.com readyInsts[op_class].push(ready_inst); 10887944SGiacomo.Gabrielli@arm.com 10897944SGiacomo.Gabrielli@arm.com // Will need to reorder the list if either a queue is not on the list, 10907944SGiacomo.Gabrielli@arm.com // or it has an older instruction than last time. 10917944SGiacomo.Gabrielli@arm.com if (!queueOnList[op_class]) { 10927944SGiacomo.Gabrielli@arm.com addToOrderList(op_class); 10937944SGiacomo.Gabrielli@arm.com } else if (readyInsts[op_class].top()->seqNum < 10947944SGiacomo.Gabrielli@arm.com (*readyIt[op_class]).oldestInst) { 10957944SGiacomo.Gabrielli@arm.com listOrder.erase(readyIt[op_class]); 10961061SN/A addToOrderList(op_class); 10971061SN/A } 10981061SN/A 10997897Shestness@cs.utexas.edu DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 11002292SN/A "the ready list, PC %s opclass:%i [sn:%lli].\n", 11011061SN/A ready_inst->pcState(), op_class, ready_inst->seqNum); 11021061SN/A} 11031061SN/A 11041060SN/Atemplate <class Impl> 11056221Snate@binkert.orgvoid 11061060SN/AInstructionQueue<Impl>::rescheduleMemInst(const DynInstPtr &resched_inst) 11072292SN/A{ 11082292SN/A DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 11091060SN/A 11101060SN/A // Reset DTB translation state 11111060SN/A resched_inst->translationStarted(false); 11122292SN/A resched_inst->translationCompleted(false); 11131060SN/A 11141681SN/A resched_inst->clearCanIssue(); 11152292SN/A memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 11162292SN/A} 11171681SN/A 11181061SN/Atemplate <class Impl> 11191061SN/Avoid 11202292SN/AInstructionQueue<Impl>::replayMemInst(const DynInstPtr &replay_inst) 11211060SN/A{ 11221060SN/A memDepUnit[replay_inst->threadNumber].replay(); 11231061SN/A} 11241061SN/A 11256221Snate@binkert.orgtemplate <class Impl> 11261061SN/Avoid 11272326SN/AInstructionQueue<Impl>::completeMemInst(const DynInstPtr &completed_inst) 11282326SN/A{ 11292326SN/A ThreadID tid = completed_inst->threadNumber; 11301061SN/A 11312292SN/A DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n", 11322292SN/A completed_inst->pcState(), completed_inst->seqNum); 11331061SN/A 11341061SN/A ++freeEntries; 11351061SN/A 11362326SN/A completed_inst->memOpDone(true); 11372326SN/A 11382292SN/A memDepUnit[tid].completed(completed_inst); 11392326SN/A count[tid]--; 11407897Shestness@cs.utexas.edu} 11411061SN/A 11421061SN/Atemplate <class Impl> 11431061SN/Avoid 11442292SN/AInstructionQueue<Impl>::deferMemInst(const DynInstPtr &deferred_inst) 11452292SN/A{ 11462326SN/A deferredMemInsts.push_back(deferred_inst); 11472292SN/A} 11482292SN/A 11492292SN/Atemplate <class Impl> 11502292SN/Avoid 11512292SN/AInstructionQueue<Impl>::blockMemInst(const DynInstPtr &blocked_inst) 11529046SAli.Saidi@ARM.com{ 11531062SN/A blocked_inst->translationStarted(false); 11547720Sgblack@eecs.umich.edu blocked_inst->translationCompleted(false); 11557720Sgblack@eecs.umich.edu 11562367SN/A blocked_inst->clearIssued(); 11571061SN/A blocked_inst->clearCanIssue(); 11582292SN/A blockedMemInsts.push_back(blocked_inst); 11592336SN/A} 11602292SN/A 11612292SN/Atemplate <class Impl> 11621061SN/Avoid 11631061SN/AInstructionQueue<Impl>::cacheUnblocked() 11641681SN/A{ 11651061SN/A retryMemInsts.splice(retryMemInsts.end(), blockedMemInsts); 11661061SN/A // Get the CPU ticking again 11671061SN/A cpu->wakeCPU(); 11681061SN/A} 11691061SN/A 11702326SN/Atemplate <class Impl> 11712326SN/Atypename Impl::DynInstPtr 11722326SN/AInstructionQueue<Impl>::getDeferredMemInstToExecute() 11732326SN/A{ 11742326SN/A for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); 11752326SN/A ++it) { 11762326SN/A if ((*it)->translationCompleted() || (*it)->isSquashed()) { 11772326SN/A DynInstPtr mem_inst = std::move(*it); 11782292SN/A deferredMemInsts.erase(it); 11791061SN/A return mem_inst; 11801061SN/A } 11812326SN/A } 11821061SN/A return nullptr; 11831062SN/A} 11842292SN/A 11851062SN/Atemplate <class Impl> 11861061SN/Atypename Impl::DynInstPtr 11874033Sktlim@umich.eduInstructionQueue<Impl>::getBlockedMemInstToExecute() 11884033Sktlim@umich.edu{ 11892292SN/A if (retryMemInsts.empty()) { 11902292SN/A return nullptr; 11918275SAli.Saidi@ARM.com } else { 11924033Sktlim@umich.edu DynInstPtr mem_inst = std::move(retryMemInsts.front()); 11934033Sktlim@umich.edu retryMemInsts.pop_front(); 11944033Sktlim@umich.edu return mem_inst; 11951062SN/A } 11964033Sktlim@umich.edu} 11971681SN/A 11984033Sktlim@umich.edutemplate <class Impl> 11991062SN/Avoid 12004033Sktlim@umich.eduInstructionQueue<Impl>::violation(const DynInstPtr &store, 12014033Sktlim@umich.edu const DynInstPtr &faulting_load) 12021061SN/A{ 12031061SN/A intInstQueueWrites++; 12041061SN/A memDepUnit[store->threadNumber].violation(store, faulting_load); 12051061SN/A} 12061061SN/A 12071061SN/Atemplate <class Impl> 12081061SN/Avoid 12092292SN/AInstructionQueue<Impl>::squash(ThreadID tid) 12102292SN/A{ 12111681SN/A DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 12121681SN/A "the IQ.\n", tid); 12132731Sktlim@umich.edu 12142292SN/A // Read instruction sequence number of last instruction out of the 12152292SN/A // time buffer. 12162292SN/A squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 12171681SN/A 12181681SN/A doSquash(tid); 12191061SN/A 12201061SN/A // Also tell the memory dependence unit to squash. 12212326SN/A memDepUnit[tid].squash(squashedSeqNum[tid], tid); 12221062SN/A} 12231061SN/A 12241060SN/Atemplate <class Impl> 12251060SN/Avoid 12261061SN/AInstructionQueue<Impl>::doSquash(ThreadID tid) 12271060SN/A{ 12281061SN/A // Start at the tail. 12291060SN/A ListIt squash_it = instList[tid].end(); 12301060SN/A --squash_it; 12311060SN/A 12321060SN/A DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 12331060SN/A tid, squashedSeqNum[tid]); 12341060SN/A 12351060SN/A // Squash any instructions younger than the squashed sequence number 12361060SN/A // given. 12371060SN/A while (squash_it != instList[tid].end() && 12381060SN/A (*squash_it)->seqNum > squashedSeqNum[tid]) { 12391060SN/A 12401060SN/A DynInstPtr squashed_inst = (*squash_it); 12411060SN/A if (squashed_inst->isFloating()) { 12421060SN/A fpInstQueueWrites++; 12431060SN/A } else if (squashed_inst->isVector()) { 12441060SN/A vecInstQueueWrites++; 12451060SN/A } else { 12461060SN/A intInstQueueWrites++; 12471061SN/A } 12481061SN/A 12491061SN/A // Only handle the instruction if it actually is in the IQ and 12507720Sgblack@eecs.umich.edu // hasn't already been squashed in the IQ. 12511060SN/A if (squashed_inst->threadNumber != tid || 12527720Sgblack@eecs.umich.edu squashed_inst->isSquashedInIQ()) { 12531060SN/A --squash_it; 12542326SN/A continue; 12551060SN/A } 12561060SN/A 12571060SN/A if (!squashed_inst->isIssued() || 12581060SN/A (squashed_inst->isMemRef() && 12591060SN/A !squashed_inst->memOpDone())) { 12607720Sgblack@eecs.umich.edu 12611060SN/A DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", 12627720Sgblack@eecs.umich.edu tid, squashed_inst->seqNum, squashed_inst->pcState()); 12631060SN/A 12642326SN/A bool is_acq_rel = squashed_inst->isMemBarrier() && 12651060SN/A (squashed_inst->isLoad() || 12661060SN/A (squashed_inst->isStore() && 12671060SN/A !squashed_inst->isStoreConditional())); 12681060SN/A 12691060SN/A // Remove the instruction from the dependency list. 12701060SN/A if (is_acq_rel || 12711060SN/A (!squashed_inst->isNonSpeculative() && 12721061SN/A !squashed_inst->isStoreConditional() && 12731060SN/A !squashed_inst->isMemBarrier() && 12742326SN/A !squashed_inst->isWriteBarrier())) { 12751060SN/A 12762326SN/A for (int src_reg_idx = 0; 12772326SN/A src_reg_idx < squashed_inst->numSrcRegs(); 12782326SN/A src_reg_idx++) 12792326SN/A { 12801060SN/A PhysRegIdPtr src_reg = 12811060SN/A squashed_inst->renamedSrcRegIdx(src_reg_idx); 12821060SN/A 12831060SN/A // Only remove it from the dependency graph if it 12841060SN/A // was placed there in the first place. 12851060SN/A 12861061SN/A // Instead of doing a linked list traversal, we 12871061SN/A // can just remove these squashed instructions 12881061SN/A // either at issue time, or when the register is 12891061SN/A // overwritten. The only downside to this is it 12901061SN/A // leaves more room for error. 12911061SN/A 12921061SN/A if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 12931061SN/A !src_reg->isFixedMapping()) { 12941060SN/A dependGraph.remove(src_reg->flatIndex(), 12951060SN/A squashed_inst); 12962326SN/A } 12972326SN/A 12982292SN/A 12992064SN/A ++iqSquashedOperandsExamined; 13001062SN/A } 13012326SN/A } else if (!squashed_inst->isStoreConditional() || 13021062SN/A !squashed_inst->isCompleted()) { 13031060SN/A NonSpecMapIt ns_inst_it = 13041060SN/A nonSpecInsts.find(squashed_inst->seqNum); 13051060SN/A 13061060SN/A // we remove non-speculative instructions from 13071060SN/A // nonSpecInsts already when they are ready, and so we 13081061SN/A // cannot always expect to find them 13091060SN/A if (ns_inst_it == nonSpecInsts.end()) { 13101061SN/A // loads that became ready but stalled on a 13111060SN/A // blocked cache are alreayd removed from 13122326SN/A // nonSpecInsts, and have not faulted 13131060SN/A assert(squashed_inst->getFault() != NoFault || 13141060SN/A squashed_inst->isMemRef()); 13151061SN/A } else { 13161060SN/A 13172292SN/A (*ns_inst_it).second = NULL; 13181061SN/A 13192292SN/A nonSpecInsts.erase(ns_inst_it); 13201061SN/A 13211062SN/A ++iqSquashedNonSpecRemoved; 13221062SN/A } 13232292SN/A } 13241062SN/A 13252292SN/A // Might want to also clear out the head of the dependency graph. 13262292SN/A 13271062SN/A // Mark it as squashed within the IQ. 13282292SN/A squashed_inst->setSquashedInIQ(); 13291061SN/A 13302292SN/A // @todo: Remove this hack where several statuses are set so the 13317720Sgblack@eecs.umich.edu // inst will flow through the rest of the pipeline. 13327720Sgblack@eecs.umich.edu squashed_inst->setIssued(); 13331061SN/A squashed_inst->setCanCommit(); 13342292SN/A squashed_inst->clearInIQ(); 13351061SN/A 13362326SN/A //Update Thread IQ Count 13372326SN/A count[squashed_inst->threadNumber]--; 13382326SN/A 13392326SN/A ++freeEntries; 13402326SN/A } 13412326SN/A 13422326SN/A // IQ clears out the heads of the dependency graph only when 13432326SN/A // instructions reach writeback stage. If an instruction is squashed 13441060SN/A // before writeback stage, its head of dependency graph would not be 13451060SN/A // cleared out; it holds the instruction's DynInstPtr. This prevents 13461060SN/A // freeing the squashed instruction's DynInst. 13471060SN/A // Thus, we need to manually clear out the squashed instructions' heads 13481061SN/A // of dependency graph. 13491061SN/A for (int dest_reg_idx = 0; 13501061SN/A dest_reg_idx < squashed_inst->numDestRegs(); 13511061SN/A dest_reg_idx++) 13522698Sktlim@umich.edu { 13532292SN/A PhysRegIdPtr dest_reg = 13542292SN/A squashed_inst->renamedDestRegIdx(dest_reg_idx); 13552292SN/A if (dest_reg->isFixedMapping()){ 13562698Sktlim@umich.edu continue; 13571061SN/A } 13581061SN/A assert(dependGraph.empty(dest_reg->flatIndex())); 13596221Snate@binkert.org dependGraph.clearInst(dest_reg->flatIndex()); 13606221Snate@binkert.org } 13611681SN/A instList[tid].erase(squash_it--); 13626221Snate@binkert.org ++iqSquashedInstsExamined; 13632292SN/A } 13642292SN/A} 13652292SN/A 13662292SN/Atemplate <class Impl> 13672292SN/Abool 13682292SN/AInstructionQueue<Impl>::addToDependents(const DynInstPtr &new_inst) 13692292SN/A{ 13702292SN/A // Loop through the instruction's source registers, adding 13712292SN/A // them to the dependency list if they are not ready. 13722292SN/A int8_t total_src_regs = new_inst->numSrcRegs(); 13732292SN/A bool return_val = false; 13742292SN/A 13751061SN/A for (int src_reg_idx = 0; 13761061SN/A src_reg_idx < total_src_regs; 13771061SN/A src_reg_idx++) 13781061SN/A { 13792292SN/A // Only add it to the dependency graph if it's not ready. 13802292SN/A if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 13812292SN/A PhysRegIdPtr src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 13821681SN/A 13831681SN/A // Check the IQ's scoreboard to make sure the register 13841681SN/A // hasn't become ready while the instruction was in flight 13851681SN/A // between stages. Only if it really isn't ready should 13861061SN/A // it be added to the dependency graph. 13871061SN/A if (src_reg->isFixedMapping()) { 13882292SN/A continue; 13892292SN/A } else if (!regScoreboard[src_reg->flatIndex()]) { 13901061SN/A DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that " 13912292SN/A "is being added to the dependency chain.\n", 13922292SN/A new_inst->pcState(), src_reg->index(), 13931061SN/A src_reg->className()); 13941061SN/A 13951061SN/A dependGraph.insert(src_reg->flatIndex(), new_inst); 13962292SN/A 13972292SN/A // Change the return value to indicate that something 13981061SN/A // was added to the dependency graph. 13991061SN/A return_val = true; 14001061SN/A } else { 14012292SN/A DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that " 14027720Sgblack@eecs.umich.edu "became ready before it reached the IQ.\n", 14032292SN/A new_inst->pcState(), src_reg->index(), 14041061SN/A src_reg->className()); 14051061SN/A // Mark a register ready within the instruction. 14061061SN/A new_inst->markSrcRegReady(src_reg_idx); 14071061SN/A } 14081061SN/A } 14092292SN/A } 14102292SN/A 14112292SN/A return return_val; 14122292SN/A} 14132292SN/A 14142292SN/Atemplate <class Impl> 14152292SN/Avoid 14162292SN/AInstructionQueue<Impl>::addToProducers(const DynInstPtr &new_inst) 14172292SN/A{ 14182292SN/A // Nothing really needs to be marked when an instruction becomes 14192292SN/A // the producer of a register's value, but for convenience a ptr 14202292SN/A // to the producing instruction will be placed in the head node of 14212292SN/A // the dependency links. 14222292SN/A int8_t total_dest_regs = new_inst->numDestRegs(); 14232292SN/A 14241061SN/A for (int dest_reg_idx = 0; 14252292SN/A dest_reg_idx < total_dest_regs; 14262292SN/A dest_reg_idx++) 14272292SN/A { 14282292SN/A PhysRegIdPtr dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 14292292SN/A 14302292SN/A // Some registers have fixed mapping, and there is no need to track 14316221Snate@binkert.org // dependencies as these instructions must be executed at commit. 14322292SN/A if (dest_reg->isFixedMapping()) { 14332292SN/A continue; 14346221Snate@binkert.org } 14352292SN/A 14366221Snate@binkert.org if (!dependGraph.empty(dest_reg->flatIndex())) { 14376221Snate@binkert.org dependGraph.dump(); 14382292SN/A panic("Dependency graph %i (%s) (flat: %i) not empty!", 14392292SN/A dest_reg->index(), dest_reg->className(), 14402292SN/A dest_reg->flatIndex()); 14412292SN/A } 14422292SN/A 14439046SAli.Saidi@ARM.com dependGraph.setInst(dest_reg->flatIndex(), new_inst); 14442326SN/A 14452326SN/A // Mark the scoreboard to say it's not yet ready. 14462292SN/A regScoreboard[dest_reg->flatIndex()] = false; 14472292SN/A } 14482292SN/A} 14492292SN/A 14502292SN/Atemplate <class Impl> 14517720Sgblack@eecs.umich.eduvoid 14522292SN/AInstructionQueue<Impl>::addIfReady(const DynInstPtr &inst) 14537720Sgblack@eecs.umich.edu{ 14542292SN/A // If the instruction now has all of its source registers 14552292SN/A // available, then add it to the list of ready instructions. 14562292SN/A if (inst->readyToIssue()) { 14572292SN/A 14582292SN/A //Add the instruction to the proper ready list. 14592292SN/A if (inst->isMemRef()) { 14609046SAli.Saidi@ARM.com 14612292SN/A DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 14622292SN/A 14632292SN/A // Message to the mem dependence unit that this instruction has 14642292SN/A // its registers ready. 14652292SN/A memDepUnit[inst->threadNumber].regsReady(inst); 14662292SN/A 14672292SN/A return; 14682292SN/A } 14692348SN/A 14702348SN/A OpClass op_class = inst->opClass(); 14712348SN/A 14722348SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 14732348SN/A "the ready list, PC %s opclass:%i [sn:%lli].\n", 14742348SN/A inst->pcState(), op_class, inst->seqNum); 14752348SN/A 14762348SN/A readyInsts[op_class].push(inst); 14772348SN/A 14782348SN/A // Will need to reorder the list if either a queue is not on the list, 14792348SN/A // or it has an older instruction than last time. 14802348SN/A if (!queueOnList[op_class]) { 14812348SN/A addToOrderList(op_class); 14822348SN/A } else if (readyInsts[op_class].top()->seqNum < 14832348SN/A (*readyIt[op_class]).oldestInst) { 14842348SN/A listOrder.erase(readyIt[op_class]); 14859046SAli.Saidi@ARM.com addToOrderList(op_class); 14862348SN/A } 14872348SN/A } 14882348SN/A} 14892348SN/A 14902348SN/Atemplate <class Impl> 14912348SN/Aint 14922348SN/AInstructionQueue<Impl>::countInsts() 14937720Sgblack@eecs.umich.edu{ 14942348SN/A#if 0 14957720Sgblack@eecs.umich.edu //ksewell:This works but definitely could use a cleaner write 14962348SN/A //with a more intuitive way of counting. Right now it's 14972348SN/A //just brute force .... 14982348SN/A // Change the #if if you want to use this method. 14992348SN/A int total_insts = 0; 15002348SN/A 15012348SN/A for (ThreadID tid = 0; tid < numThreads; ++tid) { 15029046SAli.Saidi@ARM.com ListIt count_it = instList[tid].begin(); 15032348SN/A 15042348SN/A while (count_it != instList[tid].end()) { 15052348SN/A if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 15062348SN/A if (!(*count_it)->isIssued()) { 15072348SN/A ++total_insts; 15082348SN/A } else if ((*count_it)->isMemRef() && 15092348SN/A !(*count_it)->memOpDone) { 15102292SN/A // Loads that have not been marked as executed still count 1511 // towards the total instructions. 1512 ++total_insts; 1513 } 1514 } 1515 1516 ++count_it; 1517 } 1518 } 1519 1520 return total_insts; 1521#else 1522 return numEntries - freeEntries; 1523#endif 1524} 1525 1526template <class Impl> 1527void 1528InstructionQueue<Impl>::dumpLists() 1529{ 1530 for (int i = 0; i < Num_OpClasses; ++i) { 1531 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 1532 1533 cprintf("\n"); 1534 } 1535 1536 cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 1537 1538 NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 1539 NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 1540 1541 cprintf("Non speculative list: "); 1542 1543 while (non_spec_it != non_spec_end_it) { 1544 cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(), 1545 (*non_spec_it).second->seqNum); 1546 ++non_spec_it; 1547 } 1548 1549 cprintf("\n"); 1550 1551 ListOrderIt list_order_it = listOrder.begin(); 1552 ListOrderIt list_order_end_it = listOrder.end(); 1553 int i = 1; 1554 1555 cprintf("List order: "); 1556 1557 while (list_order_it != list_order_end_it) { 1558 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 1559 (*list_order_it).oldestInst); 1560 1561 ++list_order_it; 1562 ++i; 1563 } 1564 1565 cprintf("\n"); 1566} 1567 1568 1569template <class Impl> 1570void 1571InstructionQueue<Impl>::dumpInsts() 1572{ 1573 for (ThreadID tid = 0; tid < numThreads; ++tid) { 1574 int num = 0; 1575 int valid_num = 0; 1576 ListIt inst_list_it = instList[tid].begin(); 1577 1578 while (inst_list_it != instList[tid].end()) { 1579 cprintf("Instruction:%i\n", num); 1580 if (!(*inst_list_it)->isSquashed()) { 1581 if (!(*inst_list_it)->isIssued()) { 1582 ++valid_num; 1583 cprintf("Count:%i\n", valid_num); 1584 } else if ((*inst_list_it)->isMemRef() && 1585 !(*inst_list_it)->memOpDone()) { 1586 // Loads that have not been marked as executed 1587 // still count towards the total instructions. 1588 ++valid_num; 1589 cprintf("Count:%i\n", valid_num); 1590 } 1591 } 1592 1593 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 1594 "Issued:%i\nSquashed:%i\n", 1595 (*inst_list_it)->pcState(), 1596 (*inst_list_it)->seqNum, 1597 (*inst_list_it)->threadNumber, 1598 (*inst_list_it)->isIssued(), 1599 (*inst_list_it)->isSquashed()); 1600 1601 if ((*inst_list_it)->isMemRef()) { 1602 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 1603 } 1604 1605 cprintf("\n"); 1606 1607 inst_list_it++; 1608 ++num; 1609 } 1610 } 1611 1612 cprintf("Insts to Execute list:\n"); 1613 1614 int num = 0; 1615 int valid_num = 0; 1616 ListIt inst_list_it = instsToExecute.begin(); 1617 1618 while (inst_list_it != instsToExecute.end()) 1619 { 1620 cprintf("Instruction:%i\n", 1621 num); 1622 if (!(*inst_list_it)->isSquashed()) { 1623 if (!(*inst_list_it)->isIssued()) { 1624 ++valid_num; 1625 cprintf("Count:%i\n", valid_num); 1626 } else if ((*inst_list_it)->isMemRef() && 1627 !(*inst_list_it)->memOpDone()) { 1628 // Loads that have not been marked as executed 1629 // still count towards the total instructions. 1630 ++valid_num; 1631 cprintf("Count:%i\n", valid_num); 1632 } 1633 } 1634 1635 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 1636 "Issued:%i\nSquashed:%i\n", 1637 (*inst_list_it)->pcState(), 1638 (*inst_list_it)->seqNum, 1639 (*inst_list_it)->threadNumber, 1640 (*inst_list_it)->isIssued(), 1641 (*inst_list_it)->isSquashed()); 1642 1643 if ((*inst_list_it)->isMemRef()) { 1644 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 1645 } 1646 1647 cprintf("\n"); 1648 1649 inst_list_it++; 1650 ++num; 1651 } 1652} 1653 1654#endif//__CPU_O3_INST_QUEUE_IMPL_HH__ 1655