inst_queue_impl.hh revision 13429
11689SN/A/* 210333Smitch.hayenga@arm.com * Copyright (c) 2011-2014 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47944SGiacomo.Gabrielli@arm.com * All rights reserved. 57944SGiacomo.Gabrielli@arm.com * 67944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 77944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 87944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 97944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 107944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 117944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 127944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 137944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 147944SGiacomo.Gabrielli@arm.com * 152326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422831Sksewell@umich.edu * Korey Sewell 431689SN/A */ 441689SN/A 459944Smatt.horsnell@ARM.com#ifndef __CPU_O3_INST_QUEUE_IMPL_HH__ 469944Smatt.horsnell@ARM.com#define __CPU_O3_INST_QUEUE_IMPL_HH__ 479944Smatt.horsnell@ARM.com 482064SN/A#include <limits> 491060SN/A#include <vector> 501060SN/A 512292SN/A#include "cpu/o3/fu_pool.hh" 521717SN/A#include "cpu/o3/inst_queue.hh" 538232Snate@binkert.org#include "debug/IQ.hh" 544762Snate@binkert.org#include "enums/OpClass.hh" 556221Snate@binkert.org#include "params/DerivO3CPU.hh" 564762Snate@binkert.org#include "sim/core.hh" 571060SN/A 588737Skoansin.tan@gmail.com// clang complains about std::set being overloaded with Packet::set if 598737Skoansin.tan@gmail.com// we open up the entire namespace std 608737Skoansin.tan@gmail.comusing std::list; 615529Snate@binkert.org 621061SN/Atemplate <class Impl> 6313429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::FUCompletion::FUCompletion(const DynInstPtr &_inst, 645606Snate@binkert.org int fu_idx, InstructionQueue<Impl> *iq_ptr) 658581Ssteve.reinhardt@amd.com : Event(Stat_Event_Pri, AutoDelete), 668581Ssteve.reinhardt@amd.com inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 671060SN/A{ 682292SN/A} 692292SN/A 702292SN/Atemplate <class Impl> 712292SN/Avoid 722292SN/AInstructionQueue<Impl>::FUCompletion::process() 732292SN/A{ 742326SN/A iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 752292SN/A inst = NULL; 762292SN/A} 772292SN/A 782292SN/A 792292SN/Atemplate <class Impl> 802292SN/Aconst char * 815336Shines@cs.fsu.eduInstructionQueue<Impl>::FUCompletion::description() const 822292SN/A{ 834873Sstever@eecs.umich.edu return "Functional unit completion"; 842292SN/A} 852292SN/A 862292SN/Atemplate <class Impl> 874329Sktlim@umich.eduInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 885529Snate@binkert.org DerivO3CPUParams *params) 894329Sktlim@umich.edu : cpu(cpu_ptr), 904329Sktlim@umich.edu iewStage(iew_ptr), 914329Sktlim@umich.edu fuPool(params->fuPool), 922292SN/A numEntries(params->numIQEntries), 932292SN/A totalWidth(params->issueWidth), 942292SN/A commitToIEWDelay(params->commitToIEWDelay) 952292SN/A{ 962292SN/A assert(fuPool); 972292SN/A 985529Snate@binkert.org numThreads = params->numThreads; 991060SN/A 1009920Syasuko.eckert@amd.com // Set the number of total physical registers 10112109SRekai.GonzalezAlberquilla@arm.com // As the vector registers have two addressing modes, they are added twice 1029920Syasuko.eckert@amd.com numPhysRegs = params->numPhysIntRegs + params->numPhysFloatRegs + 10312109SRekai.GonzalezAlberquilla@arm.com params->numPhysVecRegs + 10412109SRekai.GonzalezAlberquilla@arm.com params->numPhysVecRegs * TheISA::NumVecElemPerVecReg + 10512109SRekai.GonzalezAlberquilla@arm.com params->numPhysCCRegs; 1061060SN/A 1071060SN/A //Create an entry for each physical register within the 1081060SN/A //dependency graph. 1092326SN/A dependGraph.resize(numPhysRegs); 1101060SN/A 1111060SN/A // Resize the register scoreboard. 1121060SN/A regScoreboard.resize(numPhysRegs); 1131060SN/A 1142292SN/A //Initialize Mem Dependence Units 1156221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1166221Snate@binkert.org memDepUnit[tid].init(params, tid); 1176221Snate@binkert.org memDepUnit[tid].setIQ(this); 1181060SN/A } 1191060SN/A 1202307SN/A resetState(); 1212292SN/A 1222980Sgblack@eecs.umich.edu std::string policy = params->smtIQPolicy; 1232292SN/A 1242292SN/A //Convert string to lowercase 1252292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1262292SN/A (int(*)(int)) tolower); 1272292SN/A 1282292SN/A //Figure out resource sharing policy 1292292SN/A if (policy == "dynamic") { 1302292SN/A iqPolicy = Dynamic; 1312292SN/A 1322292SN/A //Set Max Entries to Total ROB Capacity 1336221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1346221Snate@binkert.org maxEntries[tid] = numEntries; 1352292SN/A } 1362292SN/A 1372292SN/A } else if (policy == "partitioned") { 1382292SN/A iqPolicy = Partitioned; 1392292SN/A 1402292SN/A //@todo:make work if part_amt doesnt divide evenly. 1412292SN/A int part_amt = numEntries / numThreads; 1422292SN/A 1432292SN/A //Divide ROB up evenly 1446221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1456221Snate@binkert.org maxEntries[tid] = part_amt; 1462292SN/A } 1472292SN/A 1482831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 1492292SN/A "%i entries per thread.\n",part_amt); 1502292SN/A } else if (policy == "threshold") { 1512292SN/A iqPolicy = Threshold; 1522292SN/A 1532292SN/A double threshold = (double)params->smtIQThreshold / 100; 1542292SN/A 1552292SN/A int thresholdIQ = (int)((double)threshold * numEntries); 1562292SN/A 1572292SN/A //Divide up by threshold amount 1586221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1596221Snate@binkert.org maxEntries[tid] = thresholdIQ; 1602292SN/A } 1612292SN/A 1622831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Threshold:" 1632292SN/A "%i entries per thread.\n",thresholdIQ); 1642292SN/A } else { 1652292SN/A assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 1662292SN/A "Partitioned, Threshold}"); 1672292SN/A } 1682292SN/A} 1692292SN/A 1702292SN/Atemplate <class Impl> 1712292SN/AInstructionQueue<Impl>::~InstructionQueue() 1722292SN/A{ 1732326SN/A dependGraph.reset(); 1742348SN/A#ifdef DEBUG 1752326SN/A cprintf("Nodes traversed: %i, removed: %i\n", 1762326SN/A dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1772348SN/A#endif 1782292SN/A} 1792292SN/A 1802292SN/Atemplate <class Impl> 1812292SN/Astd::string 1822292SN/AInstructionQueue<Impl>::name() const 1832292SN/A{ 1842292SN/A return cpu->name() + ".iq"; 1851060SN/A} 1861060SN/A 1871061SN/Atemplate <class Impl> 1881060SN/Avoid 1891062SN/AInstructionQueue<Impl>::regStats() 1901062SN/A{ 1912301SN/A using namespace Stats; 1921062SN/A iqInstsAdded 1931062SN/A .name(name() + ".iqInstsAdded") 1941062SN/A .desc("Number of instructions added to the IQ (excludes non-spec)") 1951062SN/A .prereq(iqInstsAdded); 1961062SN/A 1971062SN/A iqNonSpecInstsAdded 1981062SN/A .name(name() + ".iqNonSpecInstsAdded") 1991062SN/A .desc("Number of non-speculative instructions added to the IQ") 2001062SN/A .prereq(iqNonSpecInstsAdded); 2011062SN/A 2022301SN/A iqInstsIssued 2032301SN/A .name(name() + ".iqInstsIssued") 2042301SN/A .desc("Number of instructions issued") 2052301SN/A .prereq(iqInstsIssued); 2061062SN/A 2071062SN/A iqIntInstsIssued 2081062SN/A .name(name() + ".iqIntInstsIssued") 2091062SN/A .desc("Number of integer instructions issued") 2101062SN/A .prereq(iqIntInstsIssued); 2111062SN/A 2121062SN/A iqFloatInstsIssued 2131062SN/A .name(name() + ".iqFloatInstsIssued") 2141062SN/A .desc("Number of float instructions issued") 2151062SN/A .prereq(iqFloatInstsIssued); 2161062SN/A 2171062SN/A iqBranchInstsIssued 2181062SN/A .name(name() + ".iqBranchInstsIssued") 2191062SN/A .desc("Number of branch instructions issued") 2201062SN/A .prereq(iqBranchInstsIssued); 2211062SN/A 2221062SN/A iqMemInstsIssued 2231062SN/A .name(name() + ".iqMemInstsIssued") 2241062SN/A .desc("Number of memory instructions issued") 2251062SN/A .prereq(iqMemInstsIssued); 2261062SN/A 2271062SN/A iqMiscInstsIssued 2281062SN/A .name(name() + ".iqMiscInstsIssued") 2291062SN/A .desc("Number of miscellaneous instructions issued") 2301062SN/A .prereq(iqMiscInstsIssued); 2311062SN/A 2321062SN/A iqSquashedInstsIssued 2331062SN/A .name(name() + ".iqSquashedInstsIssued") 2341062SN/A .desc("Number of squashed instructions issued") 2351062SN/A .prereq(iqSquashedInstsIssued); 2361062SN/A 2371062SN/A iqSquashedInstsExamined 2381062SN/A .name(name() + ".iqSquashedInstsExamined") 2391062SN/A .desc("Number of squashed instructions iterated over during squash;" 2401062SN/A " mainly for profiling") 2411062SN/A .prereq(iqSquashedInstsExamined); 2421062SN/A 2431062SN/A iqSquashedOperandsExamined 2441062SN/A .name(name() + ".iqSquashedOperandsExamined") 2451062SN/A .desc("Number of squashed operands that are examined and possibly " 2461062SN/A "removed from graph") 2471062SN/A .prereq(iqSquashedOperandsExamined); 2481062SN/A 2491062SN/A iqSquashedNonSpecRemoved 2501062SN/A .name(name() + ".iqSquashedNonSpecRemoved") 2511062SN/A .desc("Number of squashed non-spec instructions that were removed") 2521062SN/A .prereq(iqSquashedNonSpecRemoved); 2532361SN/A/* 2542326SN/A queueResDist 2552301SN/A .init(Num_OpClasses, 0, 99, 2) 2562301SN/A .name(name() + ".IQ:residence:") 2572301SN/A .desc("cycles from dispatch to issue") 2582301SN/A .flags(total | pdf | cdf ) 2592301SN/A ; 2602301SN/A for (int i = 0; i < Num_OpClasses; ++i) { 2612326SN/A queueResDist.subname(i, opClassStrings[i]); 2622301SN/A } 2632361SN/A*/ 2642326SN/A numIssuedDist 2652307SN/A .init(0,totalWidth,1) 2668240Snate@binkert.org .name(name() + ".issued_per_cycle") 2672301SN/A .desc("Number of insts issued each cycle") 2682307SN/A .flags(pdf) 2692301SN/A ; 2702301SN/A/* 2712301SN/A dist_unissued 2722301SN/A .init(Num_OpClasses+2) 2738240Snate@binkert.org .name(name() + ".unissued_cause") 2742301SN/A .desc("Reason ready instruction not issued") 2752301SN/A .flags(pdf | dist) 2762301SN/A ; 2772301SN/A for (int i=0; i < (Num_OpClasses + 2); ++i) { 2782301SN/A dist_unissued.subname(i, unissued_names[i]); 2792301SN/A } 2802301SN/A*/ 2812326SN/A statIssuedInstType 2824762Snate@binkert.org .init(numThreads,Enums::Num_OpClass) 2838240Snate@binkert.org .name(name() + ".FU_type") 2842301SN/A .desc("Type of FU issued") 2852301SN/A .flags(total | pdf | dist) 2862301SN/A ; 2874762Snate@binkert.org statIssuedInstType.ysubnames(Enums::OpClassStrings); 2882301SN/A 2892301SN/A // 2902301SN/A // How long did instructions for a particular FU type wait prior to issue 2912301SN/A // 2922361SN/A/* 2932326SN/A issueDelayDist 2942301SN/A .init(Num_OpClasses,0,99,2) 2958240Snate@binkert.org .name(name() + ".") 2962301SN/A .desc("cycles from operands ready to issue") 2972301SN/A .flags(pdf | cdf) 2982301SN/A ; 2992301SN/A 3002301SN/A for (int i=0; i<Num_OpClasses; ++i) { 3012980Sgblack@eecs.umich.edu std::stringstream subname; 3022301SN/A subname << opClassStrings[i] << "_delay"; 3032326SN/A issueDelayDist.subname(i, subname.str()); 3042301SN/A } 3052361SN/A*/ 3062326SN/A issueRate 3078240Snate@binkert.org .name(name() + ".rate") 3082301SN/A .desc("Inst issue rate") 3092301SN/A .flags(total) 3102301SN/A ; 3112326SN/A issueRate = iqInstsIssued / cpu->numCycles; 3122727Sktlim@umich.edu 3132326SN/A statFuBusy 3142301SN/A .init(Num_OpClasses) 3158240Snate@binkert.org .name(name() + ".fu_full") 3162301SN/A .desc("attempts to use FU when none available") 3172301SN/A .flags(pdf | dist) 3182301SN/A ; 3192301SN/A for (int i=0; i < Num_OpClasses; ++i) { 3204762Snate@binkert.org statFuBusy.subname(i, Enums::OpClassStrings[i]); 3212301SN/A } 3222301SN/A 3232326SN/A fuBusy 3242301SN/A .init(numThreads) 3258240Snate@binkert.org .name(name() + ".fu_busy_cnt") 3262301SN/A .desc("FU busy when requested") 3272301SN/A .flags(total) 3282301SN/A ; 3292301SN/A 3302326SN/A fuBusyRate 3318240Snate@binkert.org .name(name() + ".fu_busy_rate") 3322301SN/A .desc("FU busy rate (busy events/executed inst)") 3332301SN/A .flags(total) 3342301SN/A ; 3352326SN/A fuBusyRate = fuBusy / iqInstsIssued; 3362301SN/A 3376221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3382292SN/A // Tell mem dependence unit to reg stats as well. 3396221Snate@binkert.org memDepUnit[tid].regStats(); 3402292SN/A } 3417897Shestness@cs.utexas.edu 3427897Shestness@cs.utexas.edu intInstQueueReads 3437897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_reads") 3447897Shestness@cs.utexas.edu .desc("Number of integer instruction queue reads") 3457897Shestness@cs.utexas.edu .flags(total); 3467897Shestness@cs.utexas.edu 3477897Shestness@cs.utexas.edu intInstQueueWrites 3487897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_writes") 3497897Shestness@cs.utexas.edu .desc("Number of integer instruction queue writes") 3507897Shestness@cs.utexas.edu .flags(total); 3517897Shestness@cs.utexas.edu 3527897Shestness@cs.utexas.edu intInstQueueWakeupAccesses 3537897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_wakeup_accesses") 3547897Shestness@cs.utexas.edu .desc("Number of integer instruction queue wakeup accesses") 3557897Shestness@cs.utexas.edu .flags(total); 3567897Shestness@cs.utexas.edu 3577897Shestness@cs.utexas.edu fpInstQueueReads 3587897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_reads") 3597897Shestness@cs.utexas.edu .desc("Number of floating instruction queue reads") 3607897Shestness@cs.utexas.edu .flags(total); 3617897Shestness@cs.utexas.edu 3627897Shestness@cs.utexas.edu fpInstQueueWrites 3637897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_writes") 3647897Shestness@cs.utexas.edu .desc("Number of floating instruction queue writes") 3657897Shestness@cs.utexas.edu .flags(total); 3667897Shestness@cs.utexas.edu 36712110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWakeupAccesses 3687897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_wakeup_accesses") 3697897Shestness@cs.utexas.edu .desc("Number of floating instruction queue wakeup accesses") 3707897Shestness@cs.utexas.edu .flags(total); 3717897Shestness@cs.utexas.edu 37212319Sandreas.sandberg@arm.com vecInstQueueReads 37312319Sandreas.sandberg@arm.com .name(name() + ".vec_inst_queue_reads") 37412319Sandreas.sandberg@arm.com .desc("Number of vector instruction queue reads") 37512319Sandreas.sandberg@arm.com .flags(total); 37612319Sandreas.sandberg@arm.com 37712319Sandreas.sandberg@arm.com vecInstQueueWrites 37812319Sandreas.sandberg@arm.com .name(name() + ".vec_inst_queue_writes") 37912319Sandreas.sandberg@arm.com .desc("Number of vector instruction queue writes") 38012319Sandreas.sandberg@arm.com .flags(total); 38112319Sandreas.sandberg@arm.com 38212319Sandreas.sandberg@arm.com vecInstQueueWakeupAccesses 38312319Sandreas.sandberg@arm.com .name(name() + ".vec_inst_queue_wakeup_accesses") 38412319Sandreas.sandberg@arm.com .desc("Number of vector instruction queue wakeup accesses") 38512319Sandreas.sandberg@arm.com .flags(total); 38612319Sandreas.sandberg@arm.com 3877897Shestness@cs.utexas.edu intAluAccesses 3887897Shestness@cs.utexas.edu .name(name() + ".int_alu_accesses") 3897897Shestness@cs.utexas.edu .desc("Number of integer alu accesses") 3907897Shestness@cs.utexas.edu .flags(total); 3917897Shestness@cs.utexas.edu 3927897Shestness@cs.utexas.edu fpAluAccesses 3937897Shestness@cs.utexas.edu .name(name() + ".fp_alu_accesses") 3947897Shestness@cs.utexas.edu .desc("Number of floating point alu accesses") 3957897Shestness@cs.utexas.edu .flags(total); 3967897Shestness@cs.utexas.edu 39712319Sandreas.sandberg@arm.com vecAluAccesses 39812319Sandreas.sandberg@arm.com .name(name() + ".vec_alu_accesses") 39912319Sandreas.sandberg@arm.com .desc("Number of vector alu accesses") 40012319Sandreas.sandberg@arm.com .flags(total); 40112319Sandreas.sandberg@arm.com 4021062SN/A} 4031062SN/A 4041062SN/Atemplate <class Impl> 4051062SN/Avoid 4062307SN/AInstructionQueue<Impl>::resetState() 4071060SN/A{ 4082307SN/A //Initialize thread IQ counts 4096221Snate@binkert.org for (ThreadID tid = 0; tid <numThreads; tid++) { 4106221Snate@binkert.org count[tid] = 0; 4116221Snate@binkert.org instList[tid].clear(); 4122307SN/A } 4131060SN/A 4142307SN/A // Initialize the number of free IQ entries. 4152307SN/A freeEntries = numEntries; 4162307SN/A 4172307SN/A // Note that in actuality, the registers corresponding to the logical 4182307SN/A // registers start off as ready. However this doesn't matter for the 4192307SN/A // IQ as the instruction should have been correctly told if those 4202307SN/A // registers are ready in rename. Thus it can all be initialized as 4212307SN/A // unready. 4222307SN/A for (int i = 0; i < numPhysRegs; ++i) { 4232307SN/A regScoreboard[i] = false; 4242307SN/A } 4252307SN/A 4266221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 4276221Snate@binkert.org squashedSeqNum[tid] = 0; 4282307SN/A } 4292307SN/A 4302307SN/A for (int i = 0; i < Num_OpClasses; ++i) { 4312307SN/A while (!readyInsts[i].empty()) 4322307SN/A readyInsts[i].pop(); 4332307SN/A queueOnList[i] = false; 4342307SN/A readyIt[i] = listOrder.end(); 4352307SN/A } 4362307SN/A nonSpecInsts.clear(); 4372307SN/A listOrder.clear(); 4387944SGiacomo.Gabrielli@arm.com deferredMemInsts.clear(); 43910333Smitch.hayenga@arm.com blockedMemInsts.clear(); 44010333Smitch.hayenga@arm.com retryMemInsts.clear(); 44110511Smitch.hayenga@arm.com wbOutstanding = 0; 4421060SN/A} 4431060SN/A 4441061SN/Atemplate <class Impl> 4451060SN/Avoid 4466221Snate@binkert.orgInstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 4471060SN/A{ 4482292SN/A activeThreads = at_ptr; 4492064SN/A} 4502064SN/A 4512064SN/Atemplate <class Impl> 4522064SN/Avoid 4532292SN/AInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 4542064SN/A{ 4554318Sktlim@umich.edu issueToExecuteQueue = i2e_ptr; 4561060SN/A} 4571060SN/A 4581061SN/Atemplate <class Impl> 4591060SN/Avoid 4601060SN/AInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 4611060SN/A{ 4621060SN/A timeBuffer = tb_ptr; 4631060SN/A 4641060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 4651060SN/A} 4661060SN/A 4671684SN/Atemplate <class Impl> 46810510Smitch.hayenga@arm.combool 46910510Smitch.hayenga@arm.comInstructionQueue<Impl>::isDrained() const 47010510Smitch.hayenga@arm.com{ 47110511Smitch.hayenga@arm.com bool drained = dependGraph.empty() && 47210511Smitch.hayenga@arm.com instsToExecute.empty() && 47310511Smitch.hayenga@arm.com wbOutstanding == 0; 47410510Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) 47510510Smitch.hayenga@arm.com drained = drained && memDepUnit[tid].isDrained(); 47610510Smitch.hayenga@arm.com 47710510Smitch.hayenga@arm.com return drained; 47810510Smitch.hayenga@arm.com} 47910510Smitch.hayenga@arm.com 48010510Smitch.hayenga@arm.comtemplate <class Impl> 4812307SN/Avoid 4829444SAndreas.Sandberg@ARM.comInstructionQueue<Impl>::drainSanityCheck() const 4832307SN/A{ 4849444SAndreas.Sandberg@ARM.com assert(dependGraph.empty()); 4859444SAndreas.Sandberg@ARM.com assert(instsToExecute.empty()); 4869444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; ++tid) 4879444SAndreas.Sandberg@ARM.com memDepUnit[tid].drainSanityCheck(); 4882307SN/A} 4892307SN/A 4902307SN/Atemplate <class Impl> 4912307SN/Avoid 4922307SN/AInstructionQueue<Impl>::takeOverFrom() 4932307SN/A{ 4949444SAndreas.Sandberg@ARM.com resetState(); 4952307SN/A} 4962307SN/A 4972307SN/Atemplate <class Impl> 4982292SN/Aint 4996221Snate@binkert.orgInstructionQueue<Impl>::entryAmount(ThreadID num_threads) 5002292SN/A{ 5012292SN/A if (iqPolicy == Partitioned) { 5022292SN/A return numEntries / num_threads; 5032292SN/A } else { 5042292SN/A return 0; 5052292SN/A } 5062292SN/A} 5072292SN/A 5082292SN/A 5092292SN/Atemplate <class Impl> 5102292SN/Avoid 5112292SN/AInstructionQueue<Impl>::resetEntries() 5122292SN/A{ 5132292SN/A if (iqPolicy != Dynamic || numThreads > 1) { 5143867Sbinkertn@umich.edu int active_threads = activeThreads->size(); 5152292SN/A 5166221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 5176221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 5182292SN/A 5193867Sbinkertn@umich.edu while (threads != end) { 5206221Snate@binkert.org ThreadID tid = *threads++; 5213867Sbinkertn@umich.edu 5222292SN/A if (iqPolicy == Partitioned) { 5233867Sbinkertn@umich.edu maxEntries[tid] = numEntries / active_threads; 52411321Ssteve.reinhardt@amd.com } else if (iqPolicy == Threshold && active_threads == 1) { 5253867Sbinkertn@umich.edu maxEntries[tid] = numEntries; 5262292SN/A } 5272292SN/A } 5282292SN/A } 5292292SN/A} 5302292SN/A 5312292SN/Atemplate <class Impl> 5321684SN/Aunsigned 5331684SN/AInstructionQueue<Impl>::numFreeEntries() 5341684SN/A{ 5351684SN/A return freeEntries; 5361684SN/A} 5371684SN/A 5382292SN/Atemplate <class Impl> 5392292SN/Aunsigned 5406221Snate@binkert.orgInstructionQueue<Impl>::numFreeEntries(ThreadID tid) 5412292SN/A{ 5422292SN/A return maxEntries[tid] - count[tid]; 5432292SN/A} 5442292SN/A 5451060SN/A// Might want to do something more complex if it knows how many instructions 5461060SN/A// will be issued this cycle. 5471061SN/Atemplate <class Impl> 5481060SN/Abool 5491060SN/AInstructionQueue<Impl>::isFull() 5501060SN/A{ 5511060SN/A if (freeEntries == 0) { 5521060SN/A return(true); 5531060SN/A } else { 5541060SN/A return(false); 5551060SN/A } 5561060SN/A} 5571060SN/A 5581061SN/Atemplate <class Impl> 5592292SN/Abool 5606221Snate@binkert.orgInstructionQueue<Impl>::isFull(ThreadID tid) 5612292SN/A{ 5622292SN/A if (numFreeEntries(tid) == 0) { 5632292SN/A return(true); 5642292SN/A } else { 5652292SN/A return(false); 5662292SN/A } 5672292SN/A} 5682292SN/A 5692292SN/Atemplate <class Impl> 5702292SN/Abool 5712292SN/AInstructionQueue<Impl>::hasReadyInsts() 5722292SN/A{ 5732292SN/A if (!listOrder.empty()) { 5742292SN/A return true; 5752292SN/A } 5762292SN/A 5772292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 5782292SN/A if (!readyInsts[i].empty()) { 5792292SN/A return true; 5802292SN/A } 5812292SN/A } 5822292SN/A 5832292SN/A return false; 5842292SN/A} 5852292SN/A 5862292SN/Atemplate <class Impl> 5871060SN/Avoid 58813429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::insert(const DynInstPtr &new_inst) 5891060SN/A{ 59012110SRekai.GonzalezAlberquilla@arm.com if (new_inst->isFloating()) { 59112110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWrites++; 59212110SRekai.GonzalezAlberquilla@arm.com } else if (new_inst->isVector()) { 59312110SRekai.GonzalezAlberquilla@arm.com vecInstQueueWrites++; 59412110SRekai.GonzalezAlberquilla@arm.com } else { 59512110SRekai.GonzalezAlberquilla@arm.com intInstQueueWrites++; 59612110SRekai.GonzalezAlberquilla@arm.com } 5971060SN/A // Make sure the instruction is valid 5981060SN/A assert(new_inst); 5991060SN/A 6007720Sgblack@eecs.umich.edu DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n", 6017720Sgblack@eecs.umich.edu new_inst->seqNum, new_inst->pcState()); 6021060SN/A 6031060SN/A assert(freeEntries != 0); 6041060SN/A 6052292SN/A instList[new_inst->threadNumber].push_back(new_inst); 6061060SN/A 6072064SN/A --freeEntries; 6081060SN/A 6092292SN/A new_inst->setInIQ(); 6101060SN/A 6111060SN/A // Look through its source registers (physical regs), and mark any 6121060SN/A // dependencies. 6131060SN/A addToDependents(new_inst); 6141060SN/A 6151060SN/A // Have this instruction set itself as the producer of its destination 6161060SN/A // register(s). 6172326SN/A addToProducers(new_inst); 6181060SN/A 6191061SN/A if (new_inst->isMemRef()) { 6202292SN/A memDepUnit[new_inst->threadNumber].insert(new_inst); 6211062SN/A } else { 6221062SN/A addIfReady(new_inst); 6231061SN/A } 6241061SN/A 6251062SN/A ++iqInstsAdded; 6261060SN/A 6272292SN/A count[new_inst->threadNumber]++; 6282292SN/A 6291060SN/A assert(freeEntries == (numEntries - countInsts())); 6301060SN/A} 6311060SN/A 6321061SN/Atemplate <class Impl> 6331061SN/Avoid 63413429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::insertNonSpec(const DynInstPtr &new_inst) 6351061SN/A{ 6361061SN/A // @todo: Clean up this code; can do it by setting inst as unable 6371061SN/A // to issue, then calling normal insert on the inst. 63812110SRekai.GonzalezAlberquilla@arm.com if (new_inst->isFloating()) { 63912110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWrites++; 64012110SRekai.GonzalezAlberquilla@arm.com } else if (new_inst->isVector()) { 64112110SRekai.GonzalezAlberquilla@arm.com vecInstQueueWrites++; 64212110SRekai.GonzalezAlberquilla@arm.com } else { 64312110SRekai.GonzalezAlberquilla@arm.com intInstQueueWrites++; 64412110SRekai.GonzalezAlberquilla@arm.com } 6451061SN/A 6462292SN/A assert(new_inst); 6471061SN/A 6482292SN/A nonSpecInsts[new_inst->seqNum] = new_inst; 6491061SN/A 6507720Sgblack@eecs.umich.edu DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s " 6512326SN/A "to the IQ.\n", 6527720Sgblack@eecs.umich.edu new_inst->seqNum, new_inst->pcState()); 6532064SN/A 6541061SN/A assert(freeEntries != 0); 6551061SN/A 6562292SN/A instList[new_inst->threadNumber].push_back(new_inst); 6571061SN/A 6582064SN/A --freeEntries; 6591061SN/A 6602292SN/A new_inst->setInIQ(); 6611061SN/A 6621061SN/A // Have this instruction set itself as the producer of its destination 6631061SN/A // register(s). 6642326SN/A addToProducers(new_inst); 6651061SN/A 6661061SN/A // If it's a memory instruction, add it to the memory dependency 6671061SN/A // unit. 6682292SN/A if (new_inst->isMemRef()) { 6692292SN/A memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 6701061SN/A } 6711062SN/A 6721062SN/A ++iqNonSpecInstsAdded; 6732292SN/A 6742292SN/A count[new_inst->threadNumber]++; 6752292SN/A 6762292SN/A assert(freeEntries == (numEntries - countInsts())); 6771061SN/A} 6781061SN/A 6791061SN/Atemplate <class Impl> 6801060SN/Avoid 68113429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::insertBarrier(const DynInstPtr &barr_inst) 6821060SN/A{ 6832292SN/A memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 6841060SN/A 6852292SN/A insertNonSpec(barr_inst); 6862292SN/A} 6871060SN/A 6882064SN/Atemplate <class Impl> 6892333SN/Atypename Impl::DynInstPtr 6902333SN/AInstructionQueue<Impl>::getInstToExecute() 6912333SN/A{ 6922333SN/A assert(!instsToExecute.empty()); 69313429Srekai.gonzalezalberquilla@arm.com DynInstPtr inst = std::move(instsToExecute.front()); 6942333SN/A instsToExecute.pop_front(); 69512110SRekai.GonzalezAlberquilla@arm.com if (inst->isFloating()) { 6967897Shestness@cs.utexas.edu fpInstQueueReads++; 69712110SRekai.GonzalezAlberquilla@arm.com } else if (inst->isVector()) { 69812110SRekai.GonzalezAlberquilla@arm.com vecInstQueueReads++; 6997897Shestness@cs.utexas.edu } else { 7007897Shestness@cs.utexas.edu intInstQueueReads++; 7017897Shestness@cs.utexas.edu } 7022333SN/A return inst; 7032333SN/A} 7041060SN/A 7052333SN/Atemplate <class Impl> 7062064SN/Avoid 7072292SN/AInstructionQueue<Impl>::addToOrderList(OpClass op_class) 7082292SN/A{ 7092292SN/A assert(!readyInsts[op_class].empty()); 7102292SN/A 7112292SN/A ListOrderEntry queue_entry; 7122292SN/A 7132292SN/A queue_entry.queueType = op_class; 7142292SN/A 7152292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 7162292SN/A 7172292SN/A ListOrderIt list_it = listOrder.begin(); 7182292SN/A ListOrderIt list_end_it = listOrder.end(); 7192292SN/A 7202292SN/A while (list_it != list_end_it) { 7212292SN/A if ((*list_it).oldestInst > queue_entry.oldestInst) { 7222292SN/A break; 7232292SN/A } 7242292SN/A 7252292SN/A list_it++; 7261060SN/A } 7271060SN/A 7282292SN/A readyIt[op_class] = listOrder.insert(list_it, queue_entry); 7292292SN/A queueOnList[op_class] = true; 7302292SN/A} 7311060SN/A 7322292SN/Atemplate <class Impl> 7332292SN/Avoid 7342292SN/AInstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 7352292SN/A{ 7362292SN/A // Get iterator of next item on the list 7372292SN/A // Delete the original iterator 7382292SN/A // Determine if the next item is either the end of the list or younger 7392292SN/A // than the new instruction. If so, then add in a new iterator right here. 7402292SN/A // If not, then move along. 7412292SN/A ListOrderEntry queue_entry; 7422292SN/A OpClass op_class = (*list_order_it).queueType; 7432292SN/A ListOrderIt next_it = list_order_it; 7442292SN/A 7452292SN/A ++next_it; 7462292SN/A 7472292SN/A queue_entry.queueType = op_class; 7482292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 7492292SN/A 7502292SN/A while (next_it != listOrder.end() && 7512292SN/A (*next_it).oldestInst < queue_entry.oldestInst) { 7522292SN/A ++next_it; 7531060SN/A } 7541060SN/A 7552292SN/A readyIt[op_class] = listOrder.insert(next_it, queue_entry); 7561060SN/A} 7571060SN/A 7582292SN/Atemplate <class Impl> 7592292SN/Avoid 76013429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::processFUCompletion(const DynInstPtr &inst, int fu_idx) 7612292SN/A{ 7622367SN/A DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 7639444SAndreas.Sandberg@ARM.com assert(!cpu->switchedOut()); 7642292SN/A // The CPU could have been sleeping until this op completed (*extremely* 7652292SN/A // long latency op). Wake it if it was. This may be overkill. 76610511Smitch.hayenga@arm.com --wbOutstanding; 7672292SN/A iewStage->wakeCPU(); 7682292SN/A 7692326SN/A if (fu_idx > -1) 7702326SN/A fuPool->freeUnitNextCycle(fu_idx); 7712292SN/A 7722326SN/A // @todo: Ensure that these FU Completions happen at the beginning 7732326SN/A // of a cycle, otherwise they could add too many instructions to 7742326SN/A // the queue. 7755327Smengke97@hotmail.com issueToExecuteQueue->access(-1)->size++; 7762333SN/A instsToExecute.push_back(inst); 7772292SN/A} 7782292SN/A 7791061SN/A// @todo: Figure out a better way to remove the squashed items from the 7801061SN/A// lists. Checking the top item of each list to see if it's squashed 7811061SN/A// wastes time and forces jumps. 7821061SN/Atemplate <class Impl> 7831060SN/Avoid 7841060SN/AInstructionQueue<Impl>::scheduleReadyInsts() 7851060SN/A{ 7862292SN/A DPRINTF(IQ, "Attempting to schedule ready instructions from " 7872292SN/A "the IQ.\n"); 7881060SN/A 7891060SN/A IssueStruct *i2e_info = issueToExecuteQueue->access(0); 7901060SN/A 79110333Smitch.hayenga@arm.com DynInstPtr mem_inst; 79213429Srekai.gonzalezalberquilla@arm.com while (mem_inst = std::move(getDeferredMemInstToExecute())) { 79310333Smitch.hayenga@arm.com addReadyMemInst(mem_inst); 79410333Smitch.hayenga@arm.com } 79510333Smitch.hayenga@arm.com 79610333Smitch.hayenga@arm.com // See if any cache blocked instructions are able to be executed 79713429Srekai.gonzalezalberquilla@arm.com while (mem_inst = std::move(getBlockedMemInstToExecute())) { 79810333Smitch.hayenga@arm.com addReadyMemInst(mem_inst); 7997944SGiacomo.Gabrielli@arm.com } 8007944SGiacomo.Gabrielli@arm.com 8012292SN/A // Have iterator to head of the list 8022292SN/A // While I haven't exceeded bandwidth or reached the end of the list, 8032292SN/A // Try to get a FU that can do what this op needs. 8042292SN/A // If successful, change the oldestInst to the new top of the list, put 8052292SN/A // the queue in the proper place in the list. 8062292SN/A // Increment the iterator. 8072292SN/A // This will avoid trying to schedule a certain op class if there are no 8082292SN/A // FUs that handle it. 80910333Smitch.hayenga@arm.com int total_issued = 0; 8102292SN/A ListOrderIt order_it = listOrder.begin(); 8112292SN/A ListOrderIt order_end_it = listOrder.end(); 8121060SN/A 81310333Smitch.hayenga@arm.com while (total_issued < totalWidth && order_it != order_end_it) { 8142292SN/A OpClass op_class = (*order_it).queueType; 8151060SN/A 8162292SN/A assert(!readyInsts[op_class].empty()); 8171060SN/A 8182292SN/A DynInstPtr issuing_inst = readyInsts[op_class].top(); 8191060SN/A 82012110SRekai.GonzalezAlberquilla@arm.com if (issuing_inst->isFloating()) { 82112110SRekai.GonzalezAlberquilla@arm.com fpInstQueueReads++; 82212110SRekai.GonzalezAlberquilla@arm.com } else if (issuing_inst->isVector()) { 82312110SRekai.GonzalezAlberquilla@arm.com vecInstQueueReads++; 82412110SRekai.GonzalezAlberquilla@arm.com } else { 82512110SRekai.GonzalezAlberquilla@arm.com intInstQueueReads++; 82612110SRekai.GonzalezAlberquilla@arm.com } 8277897Shestness@cs.utexas.edu 8282292SN/A assert(issuing_inst->seqNum == (*order_it).oldestInst); 8291060SN/A 8302292SN/A if (issuing_inst->isSquashed()) { 8312292SN/A readyInsts[op_class].pop(); 8321060SN/A 8332292SN/A if (!readyInsts[op_class].empty()) { 8342292SN/A moveToYoungerInst(order_it); 8352292SN/A } else { 8362292SN/A readyIt[op_class] = listOrder.end(); 8372292SN/A queueOnList[op_class] = false; 8381060SN/A } 8391060SN/A 8402292SN/A listOrder.erase(order_it++); 8411060SN/A 8422292SN/A ++iqSquashedInstsIssued; 8432292SN/A 8442292SN/A continue; 8451060SN/A } 8461060SN/A 84711365SRekai.GonzalezAlberquilla@arm.com int idx = FUPool::NoCapableFU; 8489184Sandreas.hansson@arm.com Cycles op_latency = Cycles(1); 8496221Snate@binkert.org ThreadID tid = issuing_inst->threadNumber; 8501060SN/A 8512326SN/A if (op_class != No_OpClass) { 8522326SN/A idx = fuPool->getUnit(op_class); 85312110SRekai.GonzalezAlberquilla@arm.com if (issuing_inst->isFloating()) { 85412110SRekai.GonzalezAlberquilla@arm.com fpAluAccesses++; 85512110SRekai.GonzalezAlberquilla@arm.com } else if (issuing_inst->isVector()) { 85612110SRekai.GonzalezAlberquilla@arm.com vecAluAccesses++; 85712110SRekai.GonzalezAlberquilla@arm.com } else { 85812110SRekai.GonzalezAlberquilla@arm.com intAluAccesses++; 85912110SRekai.GonzalezAlberquilla@arm.com } 86011365SRekai.GonzalezAlberquilla@arm.com if (idx > FUPool::NoFreeFU) { 8612326SN/A op_latency = fuPool->getOpLatency(op_class); 8621060SN/A } 8631060SN/A } 8641060SN/A 8652348SN/A // If we have an instruction that doesn't require a FU, or a 8662348SN/A // valid FU, then schedule for execution. 86711365SRekai.GonzalezAlberquilla@arm.com if (idx != FUPool::NoFreeFU) { 8689184Sandreas.hansson@arm.com if (op_latency == Cycles(1)) { 8692292SN/A i2e_info->size++; 8702333SN/A instsToExecute.push_back(issuing_inst); 8711060SN/A 8722326SN/A // Add the FU onto the list of FU's to be freed next 8732326SN/A // cycle if we used one. 8742326SN/A if (idx >= 0) 8752326SN/A fuPool->freeUnitNextCycle(idx); 8762292SN/A } else { 87710807Snilay@cs.wisc.edu bool pipelined = fuPool->isPipelined(op_class); 8782326SN/A // Generate completion event for the FU 87910511Smitch.hayenga@arm.com ++wbOutstanding; 8802326SN/A FUCompletion *execution = new FUCompletion(issuing_inst, 8812326SN/A idx, this); 8821060SN/A 8839180Sandreas.hansson@arm.com cpu->schedule(execution, 8849180Sandreas.hansson@arm.com cpu->clockEdge(Cycles(op_latency - 1))); 8851060SN/A 88610807Snilay@cs.wisc.edu if (!pipelined) { 8872348SN/A // If FU isn't pipelined, then it must be freed 8882348SN/A // upon the execution completing. 8892326SN/A execution->setFreeFU(); 8902292SN/A } else { 8912292SN/A // Add the FU onto the list of FU's to be freed next cycle. 8922326SN/A fuPool->freeUnitNextCycle(idx); 8932292SN/A } 8941060SN/A } 8951060SN/A 8967720Sgblack@eecs.umich.edu DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 8972292SN/A "[sn:%lli]\n", 8987720Sgblack@eecs.umich.edu tid, issuing_inst->pcState(), 8992292SN/A issuing_inst->seqNum); 9001060SN/A 9012292SN/A readyInsts[op_class].pop(); 9021061SN/A 9032292SN/A if (!readyInsts[op_class].empty()) { 9042292SN/A moveToYoungerInst(order_it); 9052292SN/A } else { 9062292SN/A readyIt[op_class] = listOrder.end(); 9072292SN/A queueOnList[op_class] = false; 9081060SN/A } 9091060SN/A 9102064SN/A issuing_inst->setIssued(); 9112292SN/A ++total_issued; 9122064SN/A 9138471SGiacomo.Gabrielli@arm.com#if TRACING_ON 9149046SAli.Saidi@ARM.com issuing_inst->issueTick = curTick() - issuing_inst->fetchTick; 9158471SGiacomo.Gabrielli@arm.com#endif 9168471SGiacomo.Gabrielli@arm.com 9172292SN/A if (!issuing_inst->isMemRef()) { 9182292SN/A // Memory instructions can not be freed from the IQ until they 9192292SN/A // complete. 9202292SN/A ++freeEntries; 9212301SN/A count[tid]--; 9222731Sktlim@umich.edu issuing_inst->clearInIQ(); 9232292SN/A } else { 9242301SN/A memDepUnit[tid].issue(issuing_inst); 9252292SN/A } 9262292SN/A 9272292SN/A listOrder.erase(order_it++); 9282326SN/A statIssuedInstType[tid][op_class]++; 9292292SN/A } else { 9302326SN/A statFuBusy[op_class]++; 9312326SN/A fuBusy[tid]++; 9322292SN/A ++order_it; 9331060SN/A } 9341060SN/A } 9351062SN/A 9362326SN/A numIssuedDist.sample(total_issued); 9372326SN/A iqInstsIssued+= total_issued; 9382307SN/A 9392348SN/A // If we issued any instructions, tell the CPU we had activity. 9408071SAli.Saidi@ARM.com // @todo If the way deferred memory instructions are handeled due to 9418071SAli.Saidi@ARM.com // translation changes then the deferredMemInsts condition should be removed 9428071SAli.Saidi@ARM.com // from the code below. 94310333Smitch.hayenga@arm.com if (total_issued || !retryMemInsts.empty() || !deferredMemInsts.empty()) { 9442292SN/A cpu->activityThisCycle(); 9452292SN/A } else { 9462292SN/A DPRINTF(IQ, "Not able to schedule any instructions.\n"); 9472292SN/A } 9481060SN/A} 9491060SN/A 9501061SN/Atemplate <class Impl> 9511060SN/Avoid 9521061SN/AInstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 9531060SN/A{ 9542292SN/A DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 9552292SN/A "to execute.\n", inst); 9561062SN/A 9572292SN/A NonSpecMapIt inst_it = nonSpecInsts.find(inst); 9581060SN/A 9591061SN/A assert(inst_it != nonSpecInsts.end()); 9601060SN/A 9616221Snate@binkert.org ThreadID tid = (*inst_it).second->threadNumber; 9622292SN/A 9634033Sktlim@umich.edu (*inst_it).second->setAtCommit(); 9644033Sktlim@umich.edu 9651061SN/A (*inst_it).second->setCanIssue(); 9661060SN/A 9671062SN/A if (!(*inst_it).second->isMemRef()) { 9681062SN/A addIfReady((*inst_it).second); 9691062SN/A } else { 9702292SN/A memDepUnit[tid].nonSpecInstReady((*inst_it).second); 9711062SN/A } 9721060SN/A 9732292SN/A (*inst_it).second = NULL; 9742292SN/A 9751061SN/A nonSpecInsts.erase(inst_it); 9761060SN/A} 9771060SN/A 9781061SN/Atemplate <class Impl> 9791061SN/Avoid 9806221Snate@binkert.orgInstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 9812292SN/A{ 9822292SN/A DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 9832292SN/A tid,inst); 9842292SN/A 9852292SN/A ListIt iq_it = instList[tid].begin(); 9862292SN/A 9872292SN/A while (iq_it != instList[tid].end() && 9882292SN/A (*iq_it)->seqNum <= inst) { 9892292SN/A ++iq_it; 9902292SN/A instList[tid].pop_front(); 9912292SN/A } 9922292SN/A 9932292SN/A assert(freeEntries == (numEntries - countInsts())); 9942292SN/A} 9952292SN/A 9962292SN/Atemplate <class Impl> 9972301SN/Aint 99813429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::wakeDependents(const DynInstPtr &completed_inst) 9991684SN/A{ 10002301SN/A int dependents = 0; 10012301SN/A 10027897Shestness@cs.utexas.edu // The instruction queue here takes care of both floating and int ops 10037897Shestness@cs.utexas.edu if (completed_inst->isFloating()) { 100412110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWakeupAccesses++; 100512110SRekai.GonzalezAlberquilla@arm.com } else if (completed_inst->isVector()) { 100612110SRekai.GonzalezAlberquilla@arm.com vecInstQueueWakeupAccesses++; 10077897Shestness@cs.utexas.edu } else { 10087897Shestness@cs.utexas.edu intInstQueueWakeupAccesses++; 10097897Shestness@cs.utexas.edu } 10107897Shestness@cs.utexas.edu 10112292SN/A DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 10122292SN/A 10132292SN/A assert(!completed_inst->isSquashed()); 10141684SN/A 10151684SN/A // Tell the memory dependence unit to wake any dependents on this 10162292SN/A // instruction if it is a memory instruction. Also complete the memory 10172326SN/A // instruction at this point since we know it executed without issues. 10182326SN/A // @todo: Might want to rename "completeMemInst" to something that 10192326SN/A // indicates that it won't need to be replayed, and call this 10202326SN/A // earlier. Might not be a big deal. 10211684SN/A if (completed_inst->isMemRef()) { 10222292SN/A memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 10232292SN/A completeMemInst(completed_inst); 10242292SN/A } else if (completed_inst->isMemBarrier() || 10252292SN/A completed_inst->isWriteBarrier()) { 10262292SN/A memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 10271684SN/A } 10281684SN/A 10291684SN/A for (int dest_reg_idx = 0; 10301684SN/A dest_reg_idx < completed_inst->numDestRegs(); 10311684SN/A dest_reg_idx++) 10321684SN/A { 103312105Snathanael.premillieu@arm.com PhysRegIdPtr dest_reg = 10341684SN/A completed_inst->renamedDestRegIdx(dest_reg_idx); 10351684SN/A 10361684SN/A // Special case of uniq or control registers. They are not 10371684SN/A // handled by the IQ and thus have no dependency graph entry. 103812105Snathanael.premillieu@arm.com if (dest_reg->isFixedMapping()) { 103912105Snathanael.premillieu@arm.com DPRINTF(IQ, "Reg %d [%s] is part of a fix mapping, skipping\n", 104012106SRekai.GonzalezAlberquilla@arm.com dest_reg->index(), dest_reg->className()); 10411684SN/A continue; 10421684SN/A } 10431684SN/A 104412105Snathanael.premillieu@arm.com DPRINTF(IQ, "Waking any dependents on register %i (%s).\n", 104512106SRekai.GonzalezAlberquilla@arm.com dest_reg->index(), 104612106SRekai.GonzalezAlberquilla@arm.com dest_reg->className()); 10471684SN/A 10482326SN/A //Go through the dependency chain, marking the registers as 10492326SN/A //ready within the waiting instructions. 105012106SRekai.GonzalezAlberquilla@arm.com DynInstPtr dep_inst = dependGraph.pop(dest_reg->flatIndex()); 10511684SN/A 10522326SN/A while (dep_inst) { 10537599Sminkyu.jeong@arm.com DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] " 10547720Sgblack@eecs.umich.edu "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 10551684SN/A 10561684SN/A // Might want to give more information to the instruction 10572326SN/A // so that it knows which of its source registers is 10582326SN/A // ready. However that would mean that the dependency 10592326SN/A // graph entries would need to hold the src_reg_idx. 10602326SN/A dep_inst->markSrcRegReady(); 10611684SN/A 10622326SN/A addIfReady(dep_inst); 10631684SN/A 106412106SRekai.GonzalezAlberquilla@arm.com dep_inst = dependGraph.pop(dest_reg->flatIndex()); 10651684SN/A 10662301SN/A ++dependents; 10671684SN/A } 10681684SN/A 10692326SN/A // Reset the head node now that all of its dependents have 10702326SN/A // been woken up. 107112106SRekai.GonzalezAlberquilla@arm.com assert(dependGraph.empty(dest_reg->flatIndex())); 107212106SRekai.GonzalezAlberquilla@arm.com dependGraph.clearInst(dest_reg->flatIndex()); 10731684SN/A 10741684SN/A // Mark the scoreboard as having that register ready. 107512106SRekai.GonzalezAlberquilla@arm.com regScoreboard[dest_reg->flatIndex()] = true; 10761684SN/A } 10772301SN/A return dependents; 10782064SN/A} 10792064SN/A 10802064SN/Atemplate <class Impl> 10812064SN/Avoid 108213429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::addReadyMemInst(const DynInstPtr &ready_inst) 10832064SN/A{ 10842292SN/A OpClass op_class = ready_inst->opClass(); 10852292SN/A 10862292SN/A readyInsts[op_class].push(ready_inst); 10872292SN/A 10882326SN/A // Will need to reorder the list if either a queue is not on the list, 10892326SN/A // or it has an older instruction than last time. 10902326SN/A if (!queueOnList[op_class]) { 10912326SN/A addToOrderList(op_class); 10922326SN/A } else if (readyInsts[op_class].top()->seqNum < 10932326SN/A (*readyIt[op_class]).oldestInst) { 10942326SN/A listOrder.erase(readyIt[op_class]); 10952326SN/A addToOrderList(op_class); 10962326SN/A } 10972326SN/A 10982292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 10997720Sgblack@eecs.umich.edu "the ready list, PC %s opclass:%i [sn:%lli].\n", 11007720Sgblack@eecs.umich.edu ready_inst->pcState(), op_class, ready_inst->seqNum); 11012064SN/A} 11022064SN/A 11032064SN/Atemplate <class Impl> 11042064SN/Avoid 110513429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::rescheduleMemInst(const DynInstPtr &resched_inst) 11062064SN/A{ 11074033Sktlim@umich.edu DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 11087944SGiacomo.Gabrielli@arm.com 11097944SGiacomo.Gabrielli@arm.com // Reset DTB translation state 11109046SAli.Saidi@ARM.com resched_inst->translationStarted(false); 11119046SAli.Saidi@ARM.com resched_inst->translationCompleted(false); 11127944SGiacomo.Gabrielli@arm.com 11134033Sktlim@umich.edu resched_inst->clearCanIssue(); 11142292SN/A memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 11152064SN/A} 11162064SN/A 11172064SN/Atemplate <class Impl> 11182064SN/Avoid 111913429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::replayMemInst(const DynInstPtr &replay_inst) 11202064SN/A{ 112110333Smitch.hayenga@arm.com memDepUnit[replay_inst->threadNumber].replay(); 11222292SN/A} 11232292SN/A 11242292SN/Atemplate <class Impl> 11252292SN/Avoid 112613429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::completeMemInst(const DynInstPtr &completed_inst) 11272292SN/A{ 11286221Snate@binkert.org ThreadID tid = completed_inst->threadNumber; 11292292SN/A 11307720Sgblack@eecs.umich.edu DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n", 11317720Sgblack@eecs.umich.edu completed_inst->pcState(), completed_inst->seqNum); 11322292SN/A 11332292SN/A ++freeEntries; 11342292SN/A 11359046SAli.Saidi@ARM.com completed_inst->memOpDone(true); 11362292SN/A 11372292SN/A memDepUnit[tid].completed(completed_inst); 11382292SN/A count[tid]--; 11391684SN/A} 11401684SN/A 11411684SN/Atemplate <class Impl> 11421684SN/Avoid 114313429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::deferMemInst(const DynInstPtr &deferred_inst) 11447944SGiacomo.Gabrielli@arm.com{ 11457944SGiacomo.Gabrielli@arm.com deferredMemInsts.push_back(deferred_inst); 11467944SGiacomo.Gabrielli@arm.com} 11477944SGiacomo.Gabrielli@arm.com 11487944SGiacomo.Gabrielli@arm.comtemplate <class Impl> 114910333Smitch.hayenga@arm.comvoid 115013429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::blockMemInst(const DynInstPtr &blocked_inst) 115110333Smitch.hayenga@arm.com{ 115210333Smitch.hayenga@arm.com blocked_inst->translationStarted(false); 115310333Smitch.hayenga@arm.com blocked_inst->translationCompleted(false); 115410333Smitch.hayenga@arm.com 115510333Smitch.hayenga@arm.com blocked_inst->clearIssued(); 115610333Smitch.hayenga@arm.com blocked_inst->clearCanIssue(); 115710333Smitch.hayenga@arm.com blockedMemInsts.push_back(blocked_inst); 115810333Smitch.hayenga@arm.com} 115910333Smitch.hayenga@arm.com 116010333Smitch.hayenga@arm.comtemplate <class Impl> 116110333Smitch.hayenga@arm.comvoid 116210333Smitch.hayenga@arm.comInstructionQueue<Impl>::cacheUnblocked() 116310333Smitch.hayenga@arm.com{ 116410333Smitch.hayenga@arm.com retryMemInsts.splice(retryMemInsts.end(), blockedMemInsts); 116510333Smitch.hayenga@arm.com // Get the CPU ticking again 116610333Smitch.hayenga@arm.com cpu->wakeCPU(); 116710333Smitch.hayenga@arm.com} 116810333Smitch.hayenga@arm.com 116910333Smitch.hayenga@arm.comtemplate <class Impl> 11707944SGiacomo.Gabrielli@arm.comtypename Impl::DynInstPtr 11717944SGiacomo.Gabrielli@arm.comInstructionQueue<Impl>::getDeferredMemInstToExecute() 11727944SGiacomo.Gabrielli@arm.com{ 11737944SGiacomo.Gabrielli@arm.com for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); 11747944SGiacomo.Gabrielli@arm.com ++it) { 11759046SAli.Saidi@ARM.com if ((*it)->translationCompleted() || (*it)->isSquashed()) { 117613429Srekai.gonzalezalberquilla@arm.com DynInstPtr mem_inst = std::move(*it); 11777944SGiacomo.Gabrielli@arm.com deferredMemInsts.erase(it); 117810333Smitch.hayenga@arm.com return mem_inst; 11797944SGiacomo.Gabrielli@arm.com } 11807944SGiacomo.Gabrielli@arm.com } 118110333Smitch.hayenga@arm.com return nullptr; 118210333Smitch.hayenga@arm.com} 118310333Smitch.hayenga@arm.com 118410333Smitch.hayenga@arm.comtemplate <class Impl> 118510333Smitch.hayenga@arm.comtypename Impl::DynInstPtr 118610333Smitch.hayenga@arm.comInstructionQueue<Impl>::getBlockedMemInstToExecute() 118710333Smitch.hayenga@arm.com{ 118810333Smitch.hayenga@arm.com if (retryMemInsts.empty()) { 118910333Smitch.hayenga@arm.com return nullptr; 119010333Smitch.hayenga@arm.com } else { 119113429Srekai.gonzalezalberquilla@arm.com DynInstPtr mem_inst = std::move(retryMemInsts.front()); 119210333Smitch.hayenga@arm.com retryMemInsts.pop_front(); 119310333Smitch.hayenga@arm.com return mem_inst; 119410333Smitch.hayenga@arm.com } 11957944SGiacomo.Gabrielli@arm.com} 11967944SGiacomo.Gabrielli@arm.com 11977944SGiacomo.Gabrielli@arm.comtemplate <class Impl> 11987944SGiacomo.Gabrielli@arm.comvoid 119913429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::violation(const DynInstPtr &store, 120013429Srekai.gonzalezalberquilla@arm.com const DynInstPtr &faulting_load) 12011061SN/A{ 12027897Shestness@cs.utexas.edu intInstQueueWrites++; 12032292SN/A memDepUnit[store->threadNumber].violation(store, faulting_load); 12041061SN/A} 12051061SN/A 12061061SN/Atemplate <class Impl> 12071060SN/Avoid 12086221Snate@binkert.orgInstructionQueue<Impl>::squash(ThreadID tid) 12091060SN/A{ 12102292SN/A DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 12112292SN/A "the IQ.\n", tid); 12121060SN/A 12131060SN/A // Read instruction sequence number of last instruction out of the 12141060SN/A // time buffer. 12152292SN/A squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 12161060SN/A 121710797Sbrandon.potter@amd.com doSquash(tid); 12181061SN/A 12191061SN/A // Also tell the memory dependence unit to squash. 12202292SN/A memDepUnit[tid].squash(squashedSeqNum[tid], tid); 12211060SN/A} 12221060SN/A 12231061SN/Atemplate <class Impl> 12241061SN/Avoid 12256221Snate@binkert.orgInstructionQueue<Impl>::doSquash(ThreadID tid) 12261061SN/A{ 12272326SN/A // Start at the tail. 12282326SN/A ListIt squash_it = instList[tid].end(); 12292326SN/A --squash_it; 12301061SN/A 12312292SN/A DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 12322292SN/A tid, squashedSeqNum[tid]); 12331061SN/A 12341061SN/A // Squash any instructions younger than the squashed sequence number 12351061SN/A // given. 12362326SN/A while (squash_it != instList[tid].end() && 12372326SN/A (*squash_it)->seqNum > squashedSeqNum[tid]) { 12382292SN/A 12392326SN/A DynInstPtr squashed_inst = (*squash_it); 124012110SRekai.GonzalezAlberquilla@arm.com if (squashed_inst->isFloating()) { 124112110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWrites++; 124212110SRekai.GonzalezAlberquilla@arm.com } else if (squashed_inst->isVector()) { 124312110SRekai.GonzalezAlberquilla@arm.com vecInstQueueWrites++; 124412110SRekai.GonzalezAlberquilla@arm.com } else { 124512110SRekai.GonzalezAlberquilla@arm.com intInstQueueWrites++; 124612110SRekai.GonzalezAlberquilla@arm.com } 12471061SN/A 12481061SN/A // Only handle the instruction if it actually is in the IQ and 12491061SN/A // hasn't already been squashed in the IQ. 12502292SN/A if (squashed_inst->threadNumber != tid || 12512292SN/A squashed_inst->isSquashedInIQ()) { 12522326SN/A --squash_it; 12532292SN/A continue; 12542292SN/A } 12552292SN/A 12562292SN/A if (!squashed_inst->isIssued() || 12572292SN/A (squashed_inst->isMemRef() && 12589046SAli.Saidi@ARM.com !squashed_inst->memOpDone())) { 12591062SN/A 12607720Sgblack@eecs.umich.edu DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", 12617720Sgblack@eecs.umich.edu tid, squashed_inst->seqNum, squashed_inst->pcState()); 12622367SN/A 126310032SGiacomo.Gabrielli@arm.com bool is_acq_rel = squashed_inst->isMemBarrier() && 126410032SGiacomo.Gabrielli@arm.com (squashed_inst->isLoad() || 126510032SGiacomo.Gabrielli@arm.com (squashed_inst->isStore() && 126610032SGiacomo.Gabrielli@arm.com !squashed_inst->isStoreConditional())); 126710032SGiacomo.Gabrielli@arm.com 12681061SN/A // Remove the instruction from the dependency list. 126910032SGiacomo.Gabrielli@arm.com if (is_acq_rel || 127010032SGiacomo.Gabrielli@arm.com (!squashed_inst->isNonSpeculative() && 127110032SGiacomo.Gabrielli@arm.com !squashed_inst->isStoreConditional() && 127210032SGiacomo.Gabrielli@arm.com !squashed_inst->isMemBarrier() && 127310032SGiacomo.Gabrielli@arm.com !squashed_inst->isWriteBarrier())) { 12741061SN/A 12751061SN/A for (int src_reg_idx = 0; 12761681SN/A src_reg_idx < squashed_inst->numSrcRegs(); 12771061SN/A src_reg_idx++) 12781061SN/A { 127912105Snathanael.premillieu@arm.com PhysRegIdPtr src_reg = 12801061SN/A squashed_inst->renamedSrcRegIdx(src_reg_idx); 12811061SN/A 12822326SN/A // Only remove it from the dependency graph if it 12832326SN/A // was placed there in the first place. 12842326SN/A 12852326SN/A // Instead of doing a linked list traversal, we 12862326SN/A // can just remove these squashed instructions 12872326SN/A // either at issue time, or when the register is 12882326SN/A // overwritten. The only downside to this is it 12892326SN/A // leaves more room for error. 12902292SN/A 12911061SN/A if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 129212105Snathanael.premillieu@arm.com !src_reg->isFixedMapping()) { 129312106SRekai.GonzalezAlberquilla@arm.com dependGraph.remove(src_reg->flatIndex(), 129412106SRekai.GonzalezAlberquilla@arm.com squashed_inst); 12951061SN/A } 12961062SN/A 12972292SN/A 12981062SN/A ++iqSquashedOperandsExamined; 12991061SN/A } 13004033Sktlim@umich.edu } else if (!squashed_inst->isStoreConditional() || 13014033Sktlim@umich.edu !squashed_inst->isCompleted()) { 13022292SN/A NonSpecMapIt ns_inst_it = 13032292SN/A nonSpecInsts.find(squashed_inst->seqNum); 13048275SAli.Saidi@ARM.com 130510017Sandreas.hansson@arm.com // we remove non-speculative instructions from 130610017Sandreas.hansson@arm.com // nonSpecInsts already when they are ready, and so we 130710017Sandreas.hansson@arm.com // cannot always expect to find them 13084033Sktlim@umich.edu if (ns_inst_it == nonSpecInsts.end()) { 130910017Sandreas.hansson@arm.com // loads that became ready but stalled on a 131010017Sandreas.hansson@arm.com // blocked cache are alreayd removed from 131110017Sandreas.hansson@arm.com // nonSpecInsts, and have not faulted 131210017Sandreas.hansson@arm.com assert(squashed_inst->getFault() != NoFault || 131310017Sandreas.hansson@arm.com squashed_inst->isMemRef()); 13144033Sktlim@umich.edu } else { 13151062SN/A 13164033Sktlim@umich.edu (*ns_inst_it).second = NULL; 13171681SN/A 13184033Sktlim@umich.edu nonSpecInsts.erase(ns_inst_it); 13191062SN/A 13204033Sktlim@umich.edu ++iqSquashedNonSpecRemoved; 13214033Sktlim@umich.edu } 13221061SN/A } 13231061SN/A 13241061SN/A // Might want to also clear out the head of the dependency graph. 13251061SN/A 13261061SN/A // Mark it as squashed within the IQ. 13271061SN/A squashed_inst->setSquashedInIQ(); 13281061SN/A 13292292SN/A // @todo: Remove this hack where several statuses are set so the 13302292SN/A // inst will flow through the rest of the pipeline. 13311681SN/A squashed_inst->setIssued(); 13321681SN/A squashed_inst->setCanCommit(); 13332731Sktlim@umich.edu squashed_inst->clearInIQ(); 13342292SN/A 13352292SN/A //Update Thread IQ Count 13362292SN/A count[squashed_inst->threadNumber]--; 13371681SN/A 13381681SN/A ++freeEntries; 13391061SN/A } 13401061SN/A 134112833Sjang.hanhwi@gmail.com // IQ clears out the heads of the dependency graph only when 134212833Sjang.hanhwi@gmail.com // instructions reach writeback stage. If an instruction is squashed 134312833Sjang.hanhwi@gmail.com // before writeback stage, its head of dependency graph would not be 134412833Sjang.hanhwi@gmail.com // cleared out; it holds the instruction's DynInstPtr. This prevents 134512833Sjang.hanhwi@gmail.com // freeing the squashed instruction's DynInst. 134612833Sjang.hanhwi@gmail.com // Thus, we need to manually clear out the squashed instructions' heads 134712833Sjang.hanhwi@gmail.com // of dependency graph. 134812833Sjang.hanhwi@gmail.com for (int dest_reg_idx = 0; 134912833Sjang.hanhwi@gmail.com dest_reg_idx < squashed_inst->numDestRegs(); 135012833Sjang.hanhwi@gmail.com dest_reg_idx++) 135112833Sjang.hanhwi@gmail.com { 135212833Sjang.hanhwi@gmail.com PhysRegIdPtr dest_reg = 135312833Sjang.hanhwi@gmail.com squashed_inst->renamedDestRegIdx(dest_reg_idx); 135412833Sjang.hanhwi@gmail.com if (dest_reg->isFixedMapping()){ 135512833Sjang.hanhwi@gmail.com continue; 135612833Sjang.hanhwi@gmail.com } 135712833Sjang.hanhwi@gmail.com assert(dependGraph.empty(dest_reg->flatIndex())); 135812833Sjang.hanhwi@gmail.com dependGraph.clearInst(dest_reg->flatIndex()); 135912833Sjang.hanhwi@gmail.com } 13602326SN/A instList[tid].erase(squash_it--); 13611062SN/A ++iqSquashedInstsExamined; 13621061SN/A } 13631060SN/A} 13641060SN/A 13651061SN/Atemplate <class Impl> 13661060SN/Abool 136713429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::addToDependents(const DynInstPtr &new_inst) 13681060SN/A{ 13691060SN/A // Loop through the instruction's source registers, adding 13701060SN/A // them to the dependency list if they are not ready. 13711060SN/A int8_t total_src_regs = new_inst->numSrcRegs(); 13721060SN/A bool return_val = false; 13731060SN/A 13741060SN/A for (int src_reg_idx = 0; 13751060SN/A src_reg_idx < total_src_regs; 13761060SN/A src_reg_idx++) 13771060SN/A { 13781060SN/A // Only add it to the dependency graph if it's not ready. 13791060SN/A if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 138012105Snathanael.premillieu@arm.com PhysRegIdPtr src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 13811060SN/A 13821060SN/A // Check the IQ's scoreboard to make sure the register 13831060SN/A // hasn't become ready while the instruction was in flight 13841060SN/A // between stages. Only if it really isn't ready should 13851060SN/A // it be added to the dependency graph. 138612105Snathanael.premillieu@arm.com if (src_reg->isFixedMapping()) { 13871061SN/A continue; 138812106SRekai.GonzalezAlberquilla@arm.com } else if (!regScoreboard[src_reg->flatIndex()]) { 138912105Snathanael.premillieu@arm.com DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that " 13901060SN/A "is being added to the dependency chain.\n", 139112106SRekai.GonzalezAlberquilla@arm.com new_inst->pcState(), src_reg->index(), 139212106SRekai.GonzalezAlberquilla@arm.com src_reg->className()); 13931060SN/A 139412106SRekai.GonzalezAlberquilla@arm.com dependGraph.insert(src_reg->flatIndex(), new_inst); 13951060SN/A 13961060SN/A // Change the return value to indicate that something 13971060SN/A // was added to the dependency graph. 13981060SN/A return_val = true; 13991060SN/A } else { 140012105Snathanael.premillieu@arm.com DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that " 14011060SN/A "became ready before it reached the IQ.\n", 140212106SRekai.GonzalezAlberquilla@arm.com new_inst->pcState(), src_reg->index(), 140312106SRekai.GonzalezAlberquilla@arm.com src_reg->className()); 14041060SN/A // Mark a register ready within the instruction. 14052326SN/A new_inst->markSrcRegReady(src_reg_idx); 14061060SN/A } 14071060SN/A } 14081060SN/A } 14091060SN/A 14101060SN/A return return_val; 14111060SN/A} 14121060SN/A 14131061SN/Atemplate <class Impl> 14141060SN/Avoid 141513429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::addToProducers(const DynInstPtr &new_inst) 14161060SN/A{ 14172326SN/A // Nothing really needs to be marked when an instruction becomes 14182326SN/A // the producer of a register's value, but for convenience a ptr 14192326SN/A // to the producing instruction will be placed in the head node of 14202326SN/A // the dependency links. 14211060SN/A int8_t total_dest_regs = new_inst->numDestRegs(); 14221060SN/A 14231060SN/A for (int dest_reg_idx = 0; 14241060SN/A dest_reg_idx < total_dest_regs; 14251060SN/A dest_reg_idx++) 14261060SN/A { 142712105Snathanael.premillieu@arm.com PhysRegIdPtr dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 14281061SN/A 142912105Snathanael.premillieu@arm.com // Some registers have fixed mapping, and there is no need to track 14301061SN/A // dependencies as these instructions must be executed at commit. 143112105Snathanael.premillieu@arm.com if (dest_reg->isFixedMapping()) { 14321061SN/A continue; 14331060SN/A } 14341060SN/A 143512106SRekai.GonzalezAlberquilla@arm.com if (!dependGraph.empty(dest_reg->flatIndex())) { 14362326SN/A dependGraph.dump(); 143712105Snathanael.premillieu@arm.com panic("Dependency graph %i (%s) (flat: %i) not empty!", 143812106SRekai.GonzalezAlberquilla@arm.com dest_reg->index(), dest_reg->className(), 143912106SRekai.GonzalezAlberquilla@arm.com dest_reg->flatIndex()); 14402064SN/A } 14411062SN/A 144212106SRekai.GonzalezAlberquilla@arm.com dependGraph.setInst(dest_reg->flatIndex(), new_inst); 14431062SN/A 14441060SN/A // Mark the scoreboard to say it's not yet ready. 144512106SRekai.GonzalezAlberquilla@arm.com regScoreboard[dest_reg->flatIndex()] = false; 14461060SN/A } 14471060SN/A} 14481060SN/A 14491061SN/Atemplate <class Impl> 14501060SN/Avoid 145113429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::addIfReady(const DynInstPtr &inst) 14521060SN/A{ 14532326SN/A // If the instruction now has all of its source registers 14541060SN/A // available, then add it to the list of ready instructions. 14551060SN/A if (inst->readyToIssue()) { 14561061SN/A 14571060SN/A //Add the instruction to the proper ready list. 14582292SN/A if (inst->isMemRef()) { 14591061SN/A 14602292SN/A DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 14611061SN/A 14621062SN/A // Message to the mem dependence unit that this instruction has 14631062SN/A // its registers ready. 14642292SN/A memDepUnit[inst->threadNumber].regsReady(inst); 14651062SN/A 14662292SN/A return; 14672292SN/A } 14681062SN/A 14692292SN/A OpClass op_class = inst->opClass(); 14701061SN/A 14712292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 14727720Sgblack@eecs.umich.edu "the ready list, PC %s opclass:%i [sn:%lli].\n", 14737720Sgblack@eecs.umich.edu inst->pcState(), op_class, inst->seqNum); 14741061SN/A 14752292SN/A readyInsts[op_class].push(inst); 14761061SN/A 14772326SN/A // Will need to reorder the list if either a queue is not on the list, 14782326SN/A // or it has an older instruction than last time. 14792326SN/A if (!queueOnList[op_class]) { 14802326SN/A addToOrderList(op_class); 14812326SN/A } else if (readyInsts[op_class].top()->seqNum < 14822326SN/A (*readyIt[op_class]).oldestInst) { 14832326SN/A listOrder.erase(readyIt[op_class]); 14842326SN/A addToOrderList(op_class); 14851060SN/A } 14861060SN/A } 14871060SN/A} 14881060SN/A 14891061SN/Atemplate <class Impl> 14901061SN/Aint 14911061SN/AInstructionQueue<Impl>::countInsts() 14921061SN/A{ 14932698Sktlim@umich.edu#if 0 14942292SN/A //ksewell:This works but definitely could use a cleaner write 14952292SN/A //with a more intuitive way of counting. Right now it's 14962292SN/A //just brute force .... 14972698Sktlim@umich.edu // Change the #if if you want to use this method. 14981061SN/A int total_insts = 0; 14991061SN/A 15006221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 15016221Snate@binkert.org ListIt count_it = instList[tid].begin(); 15021681SN/A 15036221Snate@binkert.org while (count_it != instList[tid].end()) { 15042292SN/A if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 15052292SN/A if (!(*count_it)->isIssued()) { 15062292SN/A ++total_insts; 15072292SN/A } else if ((*count_it)->isMemRef() && 15082292SN/A !(*count_it)->memOpDone) { 15092292SN/A // Loads that have not been marked as executed still count 15102292SN/A // towards the total instructions. 15112292SN/A ++total_insts; 15122292SN/A } 15132292SN/A } 15142292SN/A 15152292SN/A ++count_it; 15161061SN/A } 15171061SN/A } 15181061SN/A 15191061SN/A return total_insts; 15202292SN/A#else 15212292SN/A return numEntries - freeEntries; 15222292SN/A#endif 15231681SN/A} 15241681SN/A 15251681SN/Atemplate <class Impl> 15261681SN/Avoid 15271061SN/AInstructionQueue<Impl>::dumpLists() 15281061SN/A{ 15292292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 15302292SN/A cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 15311061SN/A 15322292SN/A cprintf("\n"); 15332292SN/A } 15341061SN/A 15351061SN/A cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 15361061SN/A 15372292SN/A NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 15382292SN/A NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 15391061SN/A 15401061SN/A cprintf("Non speculative list: "); 15411061SN/A 15422292SN/A while (non_spec_it != non_spec_end_it) { 15437720Sgblack@eecs.umich.edu cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(), 15442292SN/A (*non_spec_it).second->seqNum); 15451061SN/A ++non_spec_it; 15461061SN/A } 15471061SN/A 15481061SN/A cprintf("\n"); 15491061SN/A 15502292SN/A ListOrderIt list_order_it = listOrder.begin(); 15512292SN/A ListOrderIt list_order_end_it = listOrder.end(); 15522292SN/A int i = 1; 15532292SN/A 15542292SN/A cprintf("List order: "); 15552292SN/A 15562292SN/A while (list_order_it != list_order_end_it) { 15572292SN/A cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 15582292SN/A (*list_order_it).oldestInst); 15592292SN/A 15602292SN/A ++list_order_it; 15612292SN/A ++i; 15622292SN/A } 15632292SN/A 15642292SN/A cprintf("\n"); 15651061SN/A} 15662292SN/A 15672292SN/A 15682292SN/Atemplate <class Impl> 15692292SN/Avoid 15702292SN/AInstructionQueue<Impl>::dumpInsts() 15712292SN/A{ 15726221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 15732292SN/A int num = 0; 15742292SN/A int valid_num = 0; 15756221Snate@binkert.org ListIt inst_list_it = instList[tid].begin(); 15762292SN/A 15776221Snate@binkert.org while (inst_list_it != instList[tid].end()) { 15786221Snate@binkert.org cprintf("Instruction:%i\n", num); 15792292SN/A if (!(*inst_list_it)->isSquashed()) { 15802292SN/A if (!(*inst_list_it)->isIssued()) { 15812292SN/A ++valid_num; 15822292SN/A cprintf("Count:%i\n", valid_num); 15832292SN/A } else if ((*inst_list_it)->isMemRef() && 15849046SAli.Saidi@ARM.com !(*inst_list_it)->memOpDone()) { 15852326SN/A // Loads that have not been marked as executed 15862326SN/A // still count towards the total instructions. 15872292SN/A ++valid_num; 15882292SN/A cprintf("Count:%i\n", valid_num); 15892292SN/A } 15902292SN/A } 15912292SN/A 15927720Sgblack@eecs.umich.edu cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 15932292SN/A "Issued:%i\nSquashed:%i\n", 15947720Sgblack@eecs.umich.edu (*inst_list_it)->pcState(), 15952292SN/A (*inst_list_it)->seqNum, 15962292SN/A (*inst_list_it)->threadNumber, 15972292SN/A (*inst_list_it)->isIssued(), 15982292SN/A (*inst_list_it)->isSquashed()); 15992292SN/A 16002292SN/A if ((*inst_list_it)->isMemRef()) { 16019046SAli.Saidi@ARM.com cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 16022292SN/A } 16032292SN/A 16042292SN/A cprintf("\n"); 16052292SN/A 16062292SN/A inst_list_it++; 16072292SN/A ++num; 16082292SN/A } 16092292SN/A } 16102348SN/A 16112348SN/A cprintf("Insts to Execute list:\n"); 16122348SN/A 16132348SN/A int num = 0; 16142348SN/A int valid_num = 0; 16152348SN/A ListIt inst_list_it = instsToExecute.begin(); 16162348SN/A 16172348SN/A while (inst_list_it != instsToExecute.end()) 16182348SN/A { 16192348SN/A cprintf("Instruction:%i\n", 16202348SN/A num); 16212348SN/A if (!(*inst_list_it)->isSquashed()) { 16222348SN/A if (!(*inst_list_it)->isIssued()) { 16232348SN/A ++valid_num; 16242348SN/A cprintf("Count:%i\n", valid_num); 16252348SN/A } else if ((*inst_list_it)->isMemRef() && 16269046SAli.Saidi@ARM.com !(*inst_list_it)->memOpDone()) { 16272348SN/A // Loads that have not been marked as executed 16282348SN/A // still count towards the total instructions. 16292348SN/A ++valid_num; 16302348SN/A cprintf("Count:%i\n", valid_num); 16312348SN/A } 16322348SN/A } 16332348SN/A 16347720Sgblack@eecs.umich.edu cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 16352348SN/A "Issued:%i\nSquashed:%i\n", 16367720Sgblack@eecs.umich.edu (*inst_list_it)->pcState(), 16372348SN/A (*inst_list_it)->seqNum, 16382348SN/A (*inst_list_it)->threadNumber, 16392348SN/A (*inst_list_it)->isIssued(), 16402348SN/A (*inst_list_it)->isSquashed()); 16412348SN/A 16422348SN/A if ((*inst_list_it)->isMemRef()) { 16439046SAli.Saidi@ARM.com cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 16442348SN/A } 16452348SN/A 16462348SN/A cprintf("\n"); 16472348SN/A 16482348SN/A inst_list_it++; 16492348SN/A ++num; 16502348SN/A } 16512292SN/A} 16529944Smatt.horsnell@ARM.com 16539944Smatt.horsnell@ARM.com#endif//__CPU_O3_INST_QUEUE_IMPL_HH__ 1654