inst_queue_impl.hh revision 12833
15132Sgblack@eecs.umich.edu/* 25132Sgblack@eecs.umich.edu * Copyright (c) 2011-2014 ARM Limited 35132Sgblack@eecs.umich.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 45132Sgblack@eecs.umich.edu * All rights reserved. 55132Sgblack@eecs.umich.edu * 65132Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 75132Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 85132Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 95132Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 105132Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 115132Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 125132Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 135132Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 145132Sgblack@eecs.umich.edu * 155132Sgblack@eecs.umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 165132Sgblack@eecs.umich.edu * All rights reserved. 175132Sgblack@eecs.umich.edu * 185132Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 195132Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 205132Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 215132Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 225132Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 235132Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 245132Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 255132Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 265132Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 275132Sgblack@eecs.umich.edu * this software without specific prior written permission. 285132Sgblack@eecs.umich.edu * 295132Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 305132Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 315132Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 325132Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 335132Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 345132Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 355132Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 365132Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 375132Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 385132Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 395132Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 405132Sgblack@eecs.umich.edu * 415132Sgblack@eecs.umich.edu * Authors: Kevin Lim 425132Sgblack@eecs.umich.edu * Korey Sewell 435132Sgblack@eecs.umich.edu */ 445132Sgblack@eecs.umich.edu 455132Sgblack@eecs.umich.edu#ifndef __CPU_O3_INST_QUEUE_IMPL_HH__ 465132Sgblack@eecs.umich.edu#define __CPU_O3_INST_QUEUE_IMPL_HH__ 475132Sgblack@eecs.umich.edu 485132Sgblack@eecs.umich.edu#include <limits> 495132Sgblack@eecs.umich.edu#include <vector> 505132Sgblack@eecs.umich.edu 515132Sgblack@eecs.umich.edu#include "cpu/o3/fu_pool.hh" 525132Sgblack@eecs.umich.edu#include "cpu/o3/inst_queue.hh" 535132Sgblack@eecs.umich.edu#include "debug/IQ.hh" 545132Sgblack@eecs.umich.edu#include "enums/OpClass.hh" 555132Sgblack@eecs.umich.edu#include "params/DerivO3CPU.hh" 565132Sgblack@eecs.umich.edu#include "sim/core.hh" 575132Sgblack@eecs.umich.edu 585612Sgblack@eecs.umich.edu// clang complains about std::set being overloaded with Packet::set if 595625Sgblack@eecs.umich.edu// we open up the entire namespace std 605299Sgblack@eecs.umich.eduusing std::list; 615132Sgblack@eecs.umich.edu 625132Sgblack@eecs.umich.edutemplate <class Impl> 635625Sgblack@eecs.umich.eduInstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 645132Sgblack@eecs.umich.edu int fu_idx, InstructionQueue<Impl> *iq_ptr) 655132Sgblack@eecs.umich.edu : Event(Stat_Event_Pri, AutoDelete), 665625Sgblack@eecs.umich.edu inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 675132Sgblack@eecs.umich.edu{ 685299Sgblack@eecs.umich.edu} 695132Sgblack@eecs.umich.edu 705132Sgblack@eecs.umich.edutemplate <class Impl> 715132Sgblack@eecs.umich.eduvoid 725132Sgblack@eecs.umich.eduInstructionQueue<Impl>::FUCompletion::process() 735132Sgblack@eecs.umich.edu{ 745299Sgblack@eecs.umich.edu iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 755299Sgblack@eecs.umich.edu inst = NULL; 765132Sgblack@eecs.umich.edu} 775625Sgblack@eecs.umich.edu 785625Sgblack@eecs.umich.edu 795625Sgblack@eecs.umich.edutemplate <class Impl> 805627Sgblack@eecs.umich.educonst char * 815627Sgblack@eecs.umich.eduInstructionQueue<Impl>::FUCompletion::description() const 825615Sgblack@eecs.umich.edu{ 835132Sgblack@eecs.umich.edu return "Functional unit completion"; 846220Sgblack@eecs.umich.edu} 856220Sgblack@eecs.umich.edu 866220Sgblack@eecs.umich.edutemplate <class Impl> 876220Sgblack@eecs.umich.eduInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 886220Sgblack@eecs.umich.edu DerivO3CPUParams *params) 896220Sgblack@eecs.umich.edu : cpu(cpu_ptr), 906220Sgblack@eecs.umich.edu iewStage(iew_ptr), 916220Sgblack@eecs.umich.edu fuPool(params->fuPool), 926220Sgblack@eecs.umich.edu numEntries(params->numIQEntries), 936220Sgblack@eecs.umich.edu totalWidth(params->issueWidth), 946220Sgblack@eecs.umich.edu commitToIEWDelay(params->commitToIEWDelay) 956220Sgblack@eecs.umich.edu{ 966222Sgblack@eecs.umich.edu assert(fuPool); 976222Sgblack@eecs.umich.edu 986222Sgblack@eecs.umich.edu numThreads = params->numThreads; 996222Sgblack@eecs.umich.edu 1006222Sgblack@eecs.umich.edu // Set the number of total physical registers 1016222Sgblack@eecs.umich.edu // As the vector registers have two addressing modes, they are added twice 1026222Sgblack@eecs.umich.edu numPhysRegs = params->numPhysIntRegs + params->numPhysFloatRegs + 1036222Sgblack@eecs.umich.edu params->numPhysVecRegs + 1046222Sgblack@eecs.umich.edu params->numPhysVecRegs * TheISA::NumVecElemPerVecReg + 1056222Sgblack@eecs.umich.edu params->numPhysCCRegs; 1066220Sgblack@eecs.umich.edu 1076220Sgblack@eecs.umich.edu //Create an entry for each physical register within the 1086220Sgblack@eecs.umich.edu //dependency graph. 1096222Sgblack@eecs.umich.edu dependGraph.resize(numPhysRegs); 1106220Sgblack@eecs.umich.edu 1116222Sgblack@eecs.umich.edu // Resize the register scoreboard. 1126220Sgblack@eecs.umich.edu regScoreboard.resize(numPhysRegs); 1136220Sgblack@eecs.umich.edu 1146222Sgblack@eecs.umich.edu //Initialize Mem Dependence Units 1156220Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 1166220Sgblack@eecs.umich.edu memDepUnit[tid].init(params, tid); 1176220Sgblack@eecs.umich.edu memDepUnit[tid].setIQ(this); 1186220Sgblack@eecs.umich.edu } 1196222Sgblack@eecs.umich.edu 1206220Sgblack@eecs.umich.edu resetState(); 1216220Sgblack@eecs.umich.edu 1226220Sgblack@eecs.umich.edu std::string policy = params->smtIQPolicy; 1236220Sgblack@eecs.umich.edu 1246220Sgblack@eecs.umich.edu //Convert string to lowercase 1256220Sgblack@eecs.umich.edu std::transform(policy.begin(), policy.end(), policy.begin(), 1266220Sgblack@eecs.umich.edu (int(*)(int)) tolower); 1276220Sgblack@eecs.umich.edu 1286220Sgblack@eecs.umich.edu //Figure out resource sharing policy 1296220Sgblack@eecs.umich.edu if (policy == "dynamic") { 1305299Sgblack@eecs.umich.edu iqPolicy = Dynamic; 1315299Sgblack@eecs.umich.edu 1325299Sgblack@eecs.umich.edu //Set Max Entries to Total ROB Capacity 1335299Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 1346220Sgblack@eecs.umich.edu maxEntries[tid] = numEntries; 1355299Sgblack@eecs.umich.edu } 1365299Sgblack@eecs.umich.edu 1375299Sgblack@eecs.umich.edu } else if (policy == "partitioned") { 1385299Sgblack@eecs.umich.edu iqPolicy = Partitioned; 1395299Sgblack@eecs.umich.edu 1405299Sgblack@eecs.umich.edu //@todo:make work if part_amt doesnt divide evenly. 1415299Sgblack@eecs.umich.edu int part_amt = numEntries / numThreads; 1425299Sgblack@eecs.umich.edu 1435299Sgblack@eecs.umich.edu //Divide ROB up evenly 1445299Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 1455299Sgblack@eecs.umich.edu maxEntries[tid] = part_amt; 1465299Sgblack@eecs.umich.edu } 1475299Sgblack@eecs.umich.edu 1485299Sgblack@eecs.umich.edu DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 1495299Sgblack@eecs.umich.edu "%i entries per thread.\n",part_amt); 1505299Sgblack@eecs.umich.edu } else if (policy == "threshold") { 1515299Sgblack@eecs.umich.edu iqPolicy = Threshold; 1525299Sgblack@eecs.umich.edu 1535299Sgblack@eecs.umich.edu double threshold = (double)params->smtIQThreshold / 100; 1545299Sgblack@eecs.umich.edu 1555299Sgblack@eecs.umich.edu int thresholdIQ = (int)((double)threshold * numEntries); 1566220Sgblack@eecs.umich.edu 1575299Sgblack@eecs.umich.edu //Divide up by threshold amount 1585299Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 1595299Sgblack@eecs.umich.edu maxEntries[tid] = thresholdIQ; 1605299Sgblack@eecs.umich.edu } 1616220Sgblack@eecs.umich.edu 1625299Sgblack@eecs.umich.edu DPRINTF(IQ, "IQ sharing policy set to Threshold:" 1635299Sgblack@eecs.umich.edu "%i entries per thread.\n",thresholdIQ); 1646220Sgblack@eecs.umich.edu } else { 1656220Sgblack@eecs.umich.edu assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 1666220Sgblack@eecs.umich.edu "Partitioned, Threshold}"); 1675299Sgblack@eecs.umich.edu } 1685299Sgblack@eecs.umich.edu} 1695299Sgblack@eecs.umich.edu 1706220Sgblack@eecs.umich.edutemplate <class Impl> 1715299Sgblack@eecs.umich.eduInstructionQueue<Impl>::~InstructionQueue() 1726220Sgblack@eecs.umich.edu{ 1735299Sgblack@eecs.umich.edu dependGraph.reset(); 1745299Sgblack@eecs.umich.edu#ifdef DEBUG 1755299Sgblack@eecs.umich.edu cprintf("Nodes traversed: %i, removed: %i\n", 1765299Sgblack@eecs.umich.edu dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1776220Sgblack@eecs.umich.edu#endif 1786220Sgblack@eecs.umich.edu} 1796220Sgblack@eecs.umich.edu 1806220Sgblack@eecs.umich.edutemplate <class Impl> 1815299Sgblack@eecs.umich.edustd::string 1825299Sgblack@eecs.umich.eduInstructionQueue<Impl>::name() const 1835299Sgblack@eecs.umich.edu{ 1845299Sgblack@eecs.umich.edu return cpu->name() + ".iq"; 1855299Sgblack@eecs.umich.edu} 1866220Sgblack@eecs.umich.edu 1876220Sgblack@eecs.umich.edutemplate <class Impl> 1885299Sgblack@eecs.umich.eduvoid 1896220Sgblack@eecs.umich.eduInstructionQueue<Impl>::regStats() 1906220Sgblack@eecs.umich.edu{ 1916220Sgblack@eecs.umich.edu using namespace Stats; 1926220Sgblack@eecs.umich.edu iqInstsAdded 1936220Sgblack@eecs.umich.edu .name(name() + ".iqInstsAdded") 1946220Sgblack@eecs.umich.edu .desc("Number of instructions added to the IQ (excludes non-spec)") 1956220Sgblack@eecs.umich.edu .prereq(iqInstsAdded); 1966220Sgblack@eecs.umich.edu 1976220Sgblack@eecs.umich.edu iqNonSpecInstsAdded 1986220Sgblack@eecs.umich.edu .name(name() + ".iqNonSpecInstsAdded") 1996220Sgblack@eecs.umich.edu .desc("Number of non-speculative instructions added to the IQ") 2006220Sgblack@eecs.umich.edu .prereq(iqNonSpecInstsAdded); 2016220Sgblack@eecs.umich.edu 2026220Sgblack@eecs.umich.edu iqInstsIssued 2036220Sgblack@eecs.umich.edu .name(name() + ".iqInstsIssued") 2046220Sgblack@eecs.umich.edu .desc("Number of instructions issued") 2056220Sgblack@eecs.umich.edu .prereq(iqInstsIssued); 2066220Sgblack@eecs.umich.edu 2076220Sgblack@eecs.umich.edu iqIntInstsIssued 2086220Sgblack@eecs.umich.edu .name(name() + ".iqIntInstsIssued") 2096220Sgblack@eecs.umich.edu .desc("Number of integer instructions issued") 2106220Sgblack@eecs.umich.edu .prereq(iqIntInstsIssued); 2116220Sgblack@eecs.umich.edu 2126220Sgblack@eecs.umich.edu iqFloatInstsIssued 2136220Sgblack@eecs.umich.edu .name(name() + ".iqFloatInstsIssued") 2146712Snate@binkert.org .desc("Number of float instructions issued") 2156220Sgblack@eecs.umich.edu .prereq(iqFloatInstsIssued); 2166220Sgblack@eecs.umich.edu 2176220Sgblack@eecs.umich.edu iqBranchInstsIssued 2186220Sgblack@eecs.umich.edu .name(name() + ".iqBranchInstsIssued") 2196220Sgblack@eecs.umich.edu .desc("Number of branch instructions issued") 2206220Sgblack@eecs.umich.edu .prereq(iqBranchInstsIssued); 2216220Sgblack@eecs.umich.edu 2226220Sgblack@eecs.umich.edu iqMemInstsIssued 2236220Sgblack@eecs.umich.edu .name(name() + ".iqMemInstsIssued") 2246220Sgblack@eecs.umich.edu .desc("Number of memory instructions issued") 2256220Sgblack@eecs.umich.edu .prereq(iqMemInstsIssued); 2266220Sgblack@eecs.umich.edu 2276220Sgblack@eecs.umich.edu iqMiscInstsIssued 2286220Sgblack@eecs.umich.edu .name(name() + ".iqMiscInstsIssued") 2296220Sgblack@eecs.umich.edu .desc("Number of miscellaneous instructions issued") 2306220Sgblack@eecs.umich.edu .prereq(iqMiscInstsIssued); 2316220Sgblack@eecs.umich.edu 2326220Sgblack@eecs.umich.edu iqSquashedInstsIssued 2336220Sgblack@eecs.umich.edu .name(name() + ".iqSquashedInstsIssued") 2346220Sgblack@eecs.umich.edu .desc("Number of squashed instructions issued") 2356220Sgblack@eecs.umich.edu .prereq(iqSquashedInstsIssued); 2366220Sgblack@eecs.umich.edu 2376220Sgblack@eecs.umich.edu iqSquashedInstsExamined 2386220Sgblack@eecs.umich.edu .name(name() + ".iqSquashedInstsExamined") 2396220Sgblack@eecs.umich.edu .desc("Number of squashed instructions iterated over during squash;" 2406220Sgblack@eecs.umich.edu " mainly for profiling") 2416220Sgblack@eecs.umich.edu .prereq(iqSquashedInstsExamined); 2426220Sgblack@eecs.umich.edu 2436220Sgblack@eecs.umich.edu iqSquashedOperandsExamined 2446220Sgblack@eecs.umich.edu .name(name() + ".iqSquashedOperandsExamined") 2456220Sgblack@eecs.umich.edu .desc("Number of squashed operands that are examined and possibly " 2466220Sgblack@eecs.umich.edu "removed from graph") 2475299Sgblack@eecs.umich.edu .prereq(iqSquashedOperandsExamined); 2485299Sgblack@eecs.umich.edu 2495299Sgblack@eecs.umich.edu iqSquashedNonSpecRemoved 2505299Sgblack@eecs.umich.edu .name(name() + ".iqSquashedNonSpecRemoved") 2515299Sgblack@eecs.umich.edu .desc("Number of squashed non-spec instructions that were removed") 2525299Sgblack@eecs.umich.edu .prereq(iqSquashedNonSpecRemoved); 2535299Sgblack@eecs.umich.edu/* 2545299Sgblack@eecs.umich.edu queueResDist 2555299Sgblack@eecs.umich.edu .init(Num_OpClasses, 0, 99, 2) 2565299Sgblack@eecs.umich.edu .name(name() + ".IQ:residence:") 2575299Sgblack@eecs.umich.edu .desc("cycles from dispatch to issue") 2585299Sgblack@eecs.umich.edu .flags(total | pdf | cdf ) 2595299Sgblack@eecs.umich.edu ; 2605299Sgblack@eecs.umich.edu for (int i = 0; i < Num_OpClasses; ++i) { 2615299Sgblack@eecs.umich.edu queueResDist.subname(i, opClassStrings[i]); 2625299Sgblack@eecs.umich.edu } 2635299Sgblack@eecs.umich.edu*/ 2645299Sgblack@eecs.umich.edu numIssuedDist 2655299Sgblack@eecs.umich.edu .init(0,totalWidth,1) 2665299Sgblack@eecs.umich.edu .name(name() + ".issued_per_cycle") 2675299Sgblack@eecs.umich.edu .desc("Number of insts issued each cycle") 2685299Sgblack@eecs.umich.edu .flags(pdf) 2695299Sgblack@eecs.umich.edu ; 2705299Sgblack@eecs.umich.edu/* 2715299Sgblack@eecs.umich.edu dist_unissued 2725299Sgblack@eecs.umich.edu .init(Num_OpClasses+2) 2735299Sgblack@eecs.umich.edu .name(name() + ".unissued_cause") 2745299Sgblack@eecs.umich.edu .desc("Reason ready instruction not issued") 2755299Sgblack@eecs.umich.edu .flags(pdf | dist) 2765299Sgblack@eecs.umich.edu ; 2775299Sgblack@eecs.umich.edu for (int i=0; i < (Num_OpClasses + 2); ++i) { 2785299Sgblack@eecs.umich.edu dist_unissued.subname(i, unissued_names[i]); 2795299Sgblack@eecs.umich.edu } 2805299Sgblack@eecs.umich.edu*/ 2815299Sgblack@eecs.umich.edu statIssuedInstType 2825299Sgblack@eecs.umich.edu .init(numThreads,Enums::Num_OpClass) 2835299Sgblack@eecs.umich.edu .name(name() + ".FU_type") 2845299Sgblack@eecs.umich.edu .desc("Type of FU issued") 2855299Sgblack@eecs.umich.edu .flags(total | pdf | dist) 2865299Sgblack@eecs.umich.edu ; 2875299Sgblack@eecs.umich.edu statIssuedInstType.ysubnames(Enums::OpClassStrings); 2885299Sgblack@eecs.umich.edu 2895299Sgblack@eecs.umich.edu // 2905299Sgblack@eecs.umich.edu // How long did instructions for a particular FU type wait prior to issue 2915299Sgblack@eecs.umich.edu // 2925299Sgblack@eecs.umich.edu/* 2935299Sgblack@eecs.umich.edu issueDelayDist 2945299Sgblack@eecs.umich.edu .init(Num_OpClasses,0,99,2) 2955299Sgblack@eecs.umich.edu .name(name() + ".") 2965299Sgblack@eecs.umich.edu .desc("cycles from operands ready to issue") 2975299Sgblack@eecs.umich.edu .flags(pdf | cdf) 2985299Sgblack@eecs.umich.edu ; 2995299Sgblack@eecs.umich.edu 3005299Sgblack@eecs.umich.edu for (int i=0; i<Num_OpClasses; ++i) { 3015299Sgblack@eecs.umich.edu std::stringstream subname; 3025299Sgblack@eecs.umich.edu subname << opClassStrings[i] << "_delay"; 3035299Sgblack@eecs.umich.edu issueDelayDist.subname(i, subname.str()); 3045299Sgblack@eecs.umich.edu } 3056220Sgblack@eecs.umich.edu*/ 3065299Sgblack@eecs.umich.edu issueRate 3075299Sgblack@eecs.umich.edu .name(name() + ".rate") 3086220Sgblack@eecs.umich.edu .desc("Inst issue rate") 3095299Sgblack@eecs.umich.edu .flags(total) 3105299Sgblack@eecs.umich.edu ; 3116220Sgblack@eecs.umich.edu issueRate = iqInstsIssued / cpu->numCycles; 3125299Sgblack@eecs.umich.edu 3136220Sgblack@eecs.umich.edu statFuBusy 3145299Sgblack@eecs.umich.edu .init(Num_OpClasses) 3155299Sgblack@eecs.umich.edu .name(name() + ".fu_full") 3166220Sgblack@eecs.umich.edu .desc("attempts to use FU when none available") 3175299Sgblack@eecs.umich.edu .flags(pdf | dist) 3185299Sgblack@eecs.umich.edu ; 3196220Sgblack@eecs.umich.edu for (int i=0; i < Num_OpClasses; ++i) { 3205299Sgblack@eecs.umich.edu statFuBusy.subname(i, Enums::OpClassStrings[i]); 3216220Sgblack@eecs.umich.edu } 3225299Sgblack@eecs.umich.edu 3235299Sgblack@eecs.umich.edu fuBusy 3246220Sgblack@eecs.umich.edu .init(numThreads) 3256220Sgblack@eecs.umich.edu .name(name() + ".fu_busy_cnt") 3266220Sgblack@eecs.umich.edu .desc("FU busy when requested") 3276220Sgblack@eecs.umich.edu .flags(total) 3286220Sgblack@eecs.umich.edu ; 3296220Sgblack@eecs.umich.edu 3306220Sgblack@eecs.umich.edu fuBusyRate 3316220Sgblack@eecs.umich.edu .name(name() + ".fu_busy_rate") 3326220Sgblack@eecs.umich.edu .desc("FU busy rate (busy events/executed inst)") 3335299Sgblack@eecs.umich.edu .flags(total) 3345299Sgblack@eecs.umich.edu ; 3355299Sgblack@eecs.umich.edu fuBusyRate = fuBusy / iqInstsIssued; 3366220Sgblack@eecs.umich.edu 3375299Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 3386220Sgblack@eecs.umich.edu // Tell mem dependence unit to reg stats as well. 3396220Sgblack@eecs.umich.edu memDepUnit[tid].regStats(); 3405299Sgblack@eecs.umich.edu } 3415299Sgblack@eecs.umich.edu 3425334Sgblack@eecs.umich.edu intInstQueueReads 3435615Sgblack@eecs.umich.edu .name(name() + ".int_inst_queue_reads") 3445625Sgblack@eecs.umich.edu .desc("Number of integer instruction queue reads") 3455615Sgblack@eecs.umich.edu .flags(total); 3465334Sgblack@eecs.umich.edu 3475625Sgblack@eecs.umich.edu intInstQueueWrites 3485625Sgblack@eecs.umich.edu .name(name() + ".int_inst_queue_writes") 3495625Sgblack@eecs.umich.edu .desc("Number of integer instruction queue writes") 3505625Sgblack@eecs.umich.edu .flags(total); 3515625Sgblack@eecs.umich.edu 3525625Sgblack@eecs.umich.edu intInstQueueWakeupAccesses 3535625Sgblack@eecs.umich.edu .name(name() + ".int_inst_queue_wakeup_accesses") 3545299Sgblack@eecs.umich.edu .desc("Number of integer instruction queue wakeup accesses") 3555299Sgblack@eecs.umich.edu .flags(total); 3565334Sgblack@eecs.umich.edu 3575615Sgblack@eecs.umich.edu fpInstQueueReads 3585615Sgblack@eecs.umich.edu .name(name() + ".fp_inst_queue_reads") 3595334Sgblack@eecs.umich.edu .desc("Number of floating instruction queue reads") 3605334Sgblack@eecs.umich.edu .flags(total); 3615334Sgblack@eecs.umich.edu 3625334Sgblack@eecs.umich.edu fpInstQueueWrites 3635334Sgblack@eecs.umich.edu .name(name() + ".fp_inst_queue_writes") 3645334Sgblack@eecs.umich.edu .desc("Number of floating instruction queue writes") 3655615Sgblack@eecs.umich.edu .flags(total); 3665615Sgblack@eecs.umich.edu 3675615Sgblack@eecs.umich.edu fpInstQueueWakeupAccesses 3685334Sgblack@eecs.umich.edu .name(name() + ".fp_inst_queue_wakeup_accesses") 3695615Sgblack@eecs.umich.edu .desc("Number of floating instruction queue wakeup accesses") 3705615Sgblack@eecs.umich.edu .flags(total); 3715615Sgblack@eecs.umich.edu 3725615Sgblack@eecs.umich.edu vecInstQueueReads 3735615Sgblack@eecs.umich.edu .name(name() + ".vec_inst_queue_reads") 3745615Sgblack@eecs.umich.edu .desc("Number of vector instruction queue reads") 3755334Sgblack@eecs.umich.edu .flags(total); 3765334Sgblack@eecs.umich.edu 3775625Sgblack@eecs.umich.edu vecInstQueueWrites 3785625Sgblack@eecs.umich.edu .name(name() + ".vec_inst_queue_writes") 3795625Sgblack@eecs.umich.edu .desc("Number of vector instruction queue writes") 3805625Sgblack@eecs.umich.edu .flags(total); 3815625Sgblack@eecs.umich.edu 3825625Sgblack@eecs.umich.edu vecInstQueueWakeupAccesses 3835625Sgblack@eecs.umich.edu .name(name() + ".vec_inst_queue_wakeup_accesses") 3845625Sgblack@eecs.umich.edu .desc("Number of vector instruction queue wakeup accesses") 3855625Sgblack@eecs.umich.edu .flags(total); 3865625Sgblack@eecs.umich.edu 3875625Sgblack@eecs.umich.edu intAluAccesses 3885625Sgblack@eecs.umich.edu .name(name() + ".int_alu_accesses") 3895625Sgblack@eecs.umich.edu .desc("Number of integer alu accesses") 3905625Sgblack@eecs.umich.edu .flags(total); 3915625Sgblack@eecs.umich.edu 3925625Sgblack@eecs.umich.edu fpAluAccesses 3935625Sgblack@eecs.umich.edu .name(name() + ".fp_alu_accesses") 3945625Sgblack@eecs.umich.edu .desc("Number of floating point alu accesses") 3955625Sgblack@eecs.umich.edu .flags(total); 3965625Sgblack@eecs.umich.edu 3975625Sgblack@eecs.umich.edu vecAluAccesses 3985625Sgblack@eecs.umich.edu .name(name() + ".vec_alu_accesses") 3995625Sgblack@eecs.umich.edu .desc("Number of vector alu accesses") 4005625Sgblack@eecs.umich.edu .flags(total); 4015625Sgblack@eecs.umich.edu 4025625Sgblack@eecs.umich.edu} 4035625Sgblack@eecs.umich.edu 4045625Sgblack@eecs.umich.edutemplate <class Impl> 4055625Sgblack@eecs.umich.eduvoid 4065334Sgblack@eecs.umich.eduInstructionQueue<Impl>::resetState() 4075132Sgblack@eecs.umich.edu{ 4085132Sgblack@eecs.umich.edu //Initialize thread IQ counts 4095334Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid <numThreads; tid++) { 4105132Sgblack@eecs.umich.edu count[tid] = 0; 4115132Sgblack@eecs.umich.edu instList[tid].clear(); 4125132Sgblack@eecs.umich.edu } 4135132Sgblack@eecs.umich.edu 4145132Sgblack@eecs.umich.edu // Initialize the number of free IQ entries. 4155132Sgblack@eecs.umich.edu freeEntries = numEntries; 4165132Sgblack@eecs.umich.edu 4175132Sgblack@eecs.umich.edu // Note that in actuality, the registers corresponding to the logical 4185132Sgblack@eecs.umich.edu // registers start off as ready. However this doesn't matter for the 4195132Sgblack@eecs.umich.edu // IQ as the instruction should have been correctly told if those 4205132Sgblack@eecs.umich.edu // registers are ready in rename. Thus it can all be initialized as 4215132Sgblack@eecs.umich.edu // unready. 4225132Sgblack@eecs.umich.edu for (int i = 0; i < numPhysRegs; ++i) { 4235132Sgblack@eecs.umich.edu regScoreboard[i] = false; 4245132Sgblack@eecs.umich.edu } 4255132Sgblack@eecs.umich.edu 4265132Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; ++tid) { 4275132Sgblack@eecs.umich.edu squashedSeqNum[tid] = 0; 4285132Sgblack@eecs.umich.edu } 4295132Sgblack@eecs.umich.edu 430 for (int i = 0; i < Num_OpClasses; ++i) { 431 while (!readyInsts[i].empty()) 432 readyInsts[i].pop(); 433 queueOnList[i] = false; 434 readyIt[i] = listOrder.end(); 435 } 436 nonSpecInsts.clear(); 437 listOrder.clear(); 438 deferredMemInsts.clear(); 439 blockedMemInsts.clear(); 440 retryMemInsts.clear(); 441 wbOutstanding = 0; 442} 443 444template <class Impl> 445void 446InstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 447{ 448 activeThreads = at_ptr; 449} 450 451template <class Impl> 452void 453InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 454{ 455 issueToExecuteQueue = i2e_ptr; 456} 457 458template <class Impl> 459void 460InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 461{ 462 timeBuffer = tb_ptr; 463 464 fromCommit = timeBuffer->getWire(-commitToIEWDelay); 465} 466 467template <class Impl> 468bool 469InstructionQueue<Impl>::isDrained() const 470{ 471 bool drained = dependGraph.empty() && 472 instsToExecute.empty() && 473 wbOutstanding == 0; 474 for (ThreadID tid = 0; tid < numThreads; ++tid) 475 drained = drained && memDepUnit[tid].isDrained(); 476 477 return drained; 478} 479 480template <class Impl> 481void 482InstructionQueue<Impl>::drainSanityCheck() const 483{ 484 assert(dependGraph.empty()); 485 assert(instsToExecute.empty()); 486 for (ThreadID tid = 0; tid < numThreads; ++tid) 487 memDepUnit[tid].drainSanityCheck(); 488} 489 490template <class Impl> 491void 492InstructionQueue<Impl>::takeOverFrom() 493{ 494 resetState(); 495} 496 497template <class Impl> 498int 499InstructionQueue<Impl>::entryAmount(ThreadID num_threads) 500{ 501 if (iqPolicy == Partitioned) { 502 return numEntries / num_threads; 503 } else { 504 return 0; 505 } 506} 507 508 509template <class Impl> 510void 511InstructionQueue<Impl>::resetEntries() 512{ 513 if (iqPolicy != Dynamic || numThreads > 1) { 514 int active_threads = activeThreads->size(); 515 516 list<ThreadID>::iterator threads = activeThreads->begin(); 517 list<ThreadID>::iterator end = activeThreads->end(); 518 519 while (threads != end) { 520 ThreadID tid = *threads++; 521 522 if (iqPolicy == Partitioned) { 523 maxEntries[tid] = numEntries / active_threads; 524 } else if (iqPolicy == Threshold && active_threads == 1) { 525 maxEntries[tid] = numEntries; 526 } 527 } 528 } 529} 530 531template <class Impl> 532unsigned 533InstructionQueue<Impl>::numFreeEntries() 534{ 535 return freeEntries; 536} 537 538template <class Impl> 539unsigned 540InstructionQueue<Impl>::numFreeEntries(ThreadID tid) 541{ 542 return maxEntries[tid] - count[tid]; 543} 544 545// Might want to do something more complex if it knows how many instructions 546// will be issued this cycle. 547template <class Impl> 548bool 549InstructionQueue<Impl>::isFull() 550{ 551 if (freeEntries == 0) { 552 return(true); 553 } else { 554 return(false); 555 } 556} 557 558template <class Impl> 559bool 560InstructionQueue<Impl>::isFull(ThreadID tid) 561{ 562 if (numFreeEntries(tid) == 0) { 563 return(true); 564 } else { 565 return(false); 566 } 567} 568 569template <class Impl> 570bool 571InstructionQueue<Impl>::hasReadyInsts() 572{ 573 if (!listOrder.empty()) { 574 return true; 575 } 576 577 for (int i = 0; i < Num_OpClasses; ++i) { 578 if (!readyInsts[i].empty()) { 579 return true; 580 } 581 } 582 583 return false; 584} 585 586template <class Impl> 587void 588InstructionQueue<Impl>::insert(DynInstPtr &new_inst) 589{ 590 if (new_inst->isFloating()) { 591 fpInstQueueWrites++; 592 } else if (new_inst->isVector()) { 593 vecInstQueueWrites++; 594 } else { 595 intInstQueueWrites++; 596 } 597 // Make sure the instruction is valid 598 assert(new_inst); 599 600 DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n", 601 new_inst->seqNum, new_inst->pcState()); 602 603 assert(freeEntries != 0); 604 605 instList[new_inst->threadNumber].push_back(new_inst); 606 607 --freeEntries; 608 609 new_inst->setInIQ(); 610 611 // Look through its source registers (physical regs), and mark any 612 // dependencies. 613 addToDependents(new_inst); 614 615 // Have this instruction set itself as the producer of its destination 616 // register(s). 617 addToProducers(new_inst); 618 619 if (new_inst->isMemRef()) { 620 memDepUnit[new_inst->threadNumber].insert(new_inst); 621 } else { 622 addIfReady(new_inst); 623 } 624 625 ++iqInstsAdded; 626 627 count[new_inst->threadNumber]++; 628 629 assert(freeEntries == (numEntries - countInsts())); 630} 631 632template <class Impl> 633void 634InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) 635{ 636 // @todo: Clean up this code; can do it by setting inst as unable 637 // to issue, then calling normal insert on the inst. 638 if (new_inst->isFloating()) { 639 fpInstQueueWrites++; 640 } else if (new_inst->isVector()) { 641 vecInstQueueWrites++; 642 } else { 643 intInstQueueWrites++; 644 } 645 646 assert(new_inst); 647 648 nonSpecInsts[new_inst->seqNum] = new_inst; 649 650 DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s " 651 "to the IQ.\n", 652 new_inst->seqNum, new_inst->pcState()); 653 654 assert(freeEntries != 0); 655 656 instList[new_inst->threadNumber].push_back(new_inst); 657 658 --freeEntries; 659 660 new_inst->setInIQ(); 661 662 // Have this instruction set itself as the producer of its destination 663 // register(s). 664 addToProducers(new_inst); 665 666 // If it's a memory instruction, add it to the memory dependency 667 // unit. 668 if (new_inst->isMemRef()) { 669 memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 670 } 671 672 ++iqNonSpecInstsAdded; 673 674 count[new_inst->threadNumber]++; 675 676 assert(freeEntries == (numEntries - countInsts())); 677} 678 679template <class Impl> 680void 681InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) 682{ 683 memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 684 685 insertNonSpec(barr_inst); 686} 687 688template <class Impl> 689typename Impl::DynInstPtr 690InstructionQueue<Impl>::getInstToExecute() 691{ 692 assert(!instsToExecute.empty()); 693 DynInstPtr inst = instsToExecute.front(); 694 instsToExecute.pop_front(); 695 if (inst->isFloating()) { 696 fpInstQueueReads++; 697 } else if (inst->isVector()) { 698 vecInstQueueReads++; 699 } else { 700 intInstQueueReads++; 701 } 702 return inst; 703} 704 705template <class Impl> 706void 707InstructionQueue<Impl>::addToOrderList(OpClass op_class) 708{ 709 assert(!readyInsts[op_class].empty()); 710 711 ListOrderEntry queue_entry; 712 713 queue_entry.queueType = op_class; 714 715 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 716 717 ListOrderIt list_it = listOrder.begin(); 718 ListOrderIt list_end_it = listOrder.end(); 719 720 while (list_it != list_end_it) { 721 if ((*list_it).oldestInst > queue_entry.oldestInst) { 722 break; 723 } 724 725 list_it++; 726 } 727 728 readyIt[op_class] = listOrder.insert(list_it, queue_entry); 729 queueOnList[op_class] = true; 730} 731 732template <class Impl> 733void 734InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 735{ 736 // Get iterator of next item on the list 737 // Delete the original iterator 738 // Determine if the next item is either the end of the list or younger 739 // than the new instruction. If so, then add in a new iterator right here. 740 // If not, then move along. 741 ListOrderEntry queue_entry; 742 OpClass op_class = (*list_order_it).queueType; 743 ListOrderIt next_it = list_order_it; 744 745 ++next_it; 746 747 queue_entry.queueType = op_class; 748 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 749 750 while (next_it != listOrder.end() && 751 (*next_it).oldestInst < queue_entry.oldestInst) { 752 ++next_it; 753 } 754 755 readyIt[op_class] = listOrder.insert(next_it, queue_entry); 756} 757 758template <class Impl> 759void 760InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 761{ 762 DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 763 assert(!cpu->switchedOut()); 764 // The CPU could have been sleeping until this op completed (*extremely* 765 // long latency op). Wake it if it was. This may be overkill. 766 --wbOutstanding; 767 iewStage->wakeCPU(); 768 769 if (fu_idx > -1) 770 fuPool->freeUnitNextCycle(fu_idx); 771 772 // @todo: Ensure that these FU Completions happen at the beginning 773 // of a cycle, otherwise they could add too many instructions to 774 // the queue. 775 issueToExecuteQueue->access(-1)->size++; 776 instsToExecute.push_back(inst); 777} 778 779// @todo: Figure out a better way to remove the squashed items from the 780// lists. Checking the top item of each list to see if it's squashed 781// wastes time and forces jumps. 782template <class Impl> 783void 784InstructionQueue<Impl>::scheduleReadyInsts() 785{ 786 DPRINTF(IQ, "Attempting to schedule ready instructions from " 787 "the IQ.\n"); 788 789 IssueStruct *i2e_info = issueToExecuteQueue->access(0); 790 791 DynInstPtr mem_inst; 792 while (mem_inst = getDeferredMemInstToExecute()) { 793 addReadyMemInst(mem_inst); 794 } 795 796 // See if any cache blocked instructions are able to be executed 797 while (mem_inst = getBlockedMemInstToExecute()) { 798 addReadyMemInst(mem_inst); 799 } 800 801 // Have iterator to head of the list 802 // While I haven't exceeded bandwidth or reached the end of the list, 803 // Try to get a FU that can do what this op needs. 804 // If successful, change the oldestInst to the new top of the list, put 805 // the queue in the proper place in the list. 806 // Increment the iterator. 807 // This will avoid trying to schedule a certain op class if there are no 808 // FUs that handle it. 809 int total_issued = 0; 810 ListOrderIt order_it = listOrder.begin(); 811 ListOrderIt order_end_it = listOrder.end(); 812 813 while (total_issued < totalWidth && order_it != order_end_it) { 814 OpClass op_class = (*order_it).queueType; 815 816 assert(!readyInsts[op_class].empty()); 817 818 DynInstPtr issuing_inst = readyInsts[op_class].top(); 819 820 if (issuing_inst->isFloating()) { 821 fpInstQueueReads++; 822 } else if (issuing_inst->isVector()) { 823 vecInstQueueReads++; 824 } else { 825 intInstQueueReads++; 826 } 827 828 assert(issuing_inst->seqNum == (*order_it).oldestInst); 829 830 if (issuing_inst->isSquashed()) { 831 readyInsts[op_class].pop(); 832 833 if (!readyInsts[op_class].empty()) { 834 moveToYoungerInst(order_it); 835 } else { 836 readyIt[op_class] = listOrder.end(); 837 queueOnList[op_class] = false; 838 } 839 840 listOrder.erase(order_it++); 841 842 ++iqSquashedInstsIssued; 843 844 continue; 845 } 846 847 int idx = FUPool::NoCapableFU; 848 Cycles op_latency = Cycles(1); 849 ThreadID tid = issuing_inst->threadNumber; 850 851 if (op_class != No_OpClass) { 852 idx = fuPool->getUnit(op_class); 853 if (issuing_inst->isFloating()) { 854 fpAluAccesses++; 855 } else if (issuing_inst->isVector()) { 856 vecAluAccesses++; 857 } else { 858 intAluAccesses++; 859 } 860 if (idx > FUPool::NoFreeFU) { 861 op_latency = fuPool->getOpLatency(op_class); 862 } 863 } 864 865 // If we have an instruction that doesn't require a FU, or a 866 // valid FU, then schedule for execution. 867 if (idx != FUPool::NoFreeFU) { 868 if (op_latency == Cycles(1)) { 869 i2e_info->size++; 870 instsToExecute.push_back(issuing_inst); 871 872 // Add the FU onto the list of FU's to be freed next 873 // cycle if we used one. 874 if (idx >= 0) 875 fuPool->freeUnitNextCycle(idx); 876 } else { 877 bool pipelined = fuPool->isPipelined(op_class); 878 // Generate completion event for the FU 879 ++wbOutstanding; 880 FUCompletion *execution = new FUCompletion(issuing_inst, 881 idx, this); 882 883 cpu->schedule(execution, 884 cpu->clockEdge(Cycles(op_latency - 1))); 885 886 if (!pipelined) { 887 // If FU isn't pipelined, then it must be freed 888 // upon the execution completing. 889 execution->setFreeFU(); 890 } else { 891 // Add the FU onto the list of FU's to be freed next cycle. 892 fuPool->freeUnitNextCycle(idx); 893 } 894 } 895 896 DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 897 "[sn:%lli]\n", 898 tid, issuing_inst->pcState(), 899 issuing_inst->seqNum); 900 901 readyInsts[op_class].pop(); 902 903 if (!readyInsts[op_class].empty()) { 904 moveToYoungerInst(order_it); 905 } else { 906 readyIt[op_class] = listOrder.end(); 907 queueOnList[op_class] = false; 908 } 909 910 issuing_inst->setIssued(); 911 ++total_issued; 912 913#if TRACING_ON 914 issuing_inst->issueTick = curTick() - issuing_inst->fetchTick; 915#endif 916 917 if (!issuing_inst->isMemRef()) { 918 // Memory instructions can not be freed from the IQ until they 919 // complete. 920 ++freeEntries; 921 count[tid]--; 922 issuing_inst->clearInIQ(); 923 } else { 924 memDepUnit[tid].issue(issuing_inst); 925 } 926 927 listOrder.erase(order_it++); 928 statIssuedInstType[tid][op_class]++; 929 } else { 930 statFuBusy[op_class]++; 931 fuBusy[tid]++; 932 ++order_it; 933 } 934 } 935 936 numIssuedDist.sample(total_issued); 937 iqInstsIssued+= total_issued; 938 939 // If we issued any instructions, tell the CPU we had activity. 940 // @todo If the way deferred memory instructions are handeled due to 941 // translation changes then the deferredMemInsts condition should be removed 942 // from the code below. 943 if (total_issued || !retryMemInsts.empty() || !deferredMemInsts.empty()) { 944 cpu->activityThisCycle(); 945 } else { 946 DPRINTF(IQ, "Not able to schedule any instructions.\n"); 947 } 948} 949 950template <class Impl> 951void 952InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 953{ 954 DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 955 "to execute.\n", inst); 956 957 NonSpecMapIt inst_it = nonSpecInsts.find(inst); 958 959 assert(inst_it != nonSpecInsts.end()); 960 961 ThreadID tid = (*inst_it).second->threadNumber; 962 963 (*inst_it).second->setAtCommit(); 964 965 (*inst_it).second->setCanIssue(); 966 967 if (!(*inst_it).second->isMemRef()) { 968 addIfReady((*inst_it).second); 969 } else { 970 memDepUnit[tid].nonSpecInstReady((*inst_it).second); 971 } 972 973 (*inst_it).second = NULL; 974 975 nonSpecInsts.erase(inst_it); 976} 977 978template <class Impl> 979void 980InstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 981{ 982 DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 983 tid,inst); 984 985 ListIt iq_it = instList[tid].begin(); 986 987 while (iq_it != instList[tid].end() && 988 (*iq_it)->seqNum <= inst) { 989 ++iq_it; 990 instList[tid].pop_front(); 991 } 992 993 assert(freeEntries == (numEntries - countInsts())); 994} 995 996template <class Impl> 997int 998InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 999{ 1000 int dependents = 0; 1001 1002 // The instruction queue here takes care of both floating and int ops 1003 if (completed_inst->isFloating()) { 1004 fpInstQueueWakeupAccesses++; 1005 } else if (completed_inst->isVector()) { 1006 vecInstQueueWakeupAccesses++; 1007 } else { 1008 intInstQueueWakeupAccesses++; 1009 } 1010 1011 DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 1012 1013 assert(!completed_inst->isSquashed()); 1014 1015 // Tell the memory dependence unit to wake any dependents on this 1016 // instruction if it is a memory instruction. Also complete the memory 1017 // instruction at this point since we know it executed without issues. 1018 // @todo: Might want to rename "completeMemInst" to something that 1019 // indicates that it won't need to be replayed, and call this 1020 // earlier. Might not be a big deal. 1021 if (completed_inst->isMemRef()) { 1022 memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 1023 completeMemInst(completed_inst); 1024 } else if (completed_inst->isMemBarrier() || 1025 completed_inst->isWriteBarrier()) { 1026 memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 1027 } 1028 1029 for (int dest_reg_idx = 0; 1030 dest_reg_idx < completed_inst->numDestRegs(); 1031 dest_reg_idx++) 1032 { 1033 PhysRegIdPtr dest_reg = 1034 completed_inst->renamedDestRegIdx(dest_reg_idx); 1035 1036 // Special case of uniq or control registers. They are not 1037 // handled by the IQ and thus have no dependency graph entry. 1038 if (dest_reg->isFixedMapping()) { 1039 DPRINTF(IQ, "Reg %d [%s] is part of a fix mapping, skipping\n", 1040 dest_reg->index(), dest_reg->className()); 1041 continue; 1042 } 1043 1044 DPRINTF(IQ, "Waking any dependents on register %i (%s).\n", 1045 dest_reg->index(), 1046 dest_reg->className()); 1047 1048 //Go through the dependency chain, marking the registers as 1049 //ready within the waiting instructions. 1050 DynInstPtr dep_inst = dependGraph.pop(dest_reg->flatIndex()); 1051 1052 while (dep_inst) { 1053 DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] " 1054 "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 1055 1056 // Might want to give more information to the instruction 1057 // so that it knows which of its source registers is 1058 // ready. However that would mean that the dependency 1059 // graph entries would need to hold the src_reg_idx. 1060 dep_inst->markSrcRegReady(); 1061 1062 addIfReady(dep_inst); 1063 1064 dep_inst = dependGraph.pop(dest_reg->flatIndex()); 1065 1066 ++dependents; 1067 } 1068 1069 // Reset the head node now that all of its dependents have 1070 // been woken up. 1071 assert(dependGraph.empty(dest_reg->flatIndex())); 1072 dependGraph.clearInst(dest_reg->flatIndex()); 1073 1074 // Mark the scoreboard as having that register ready. 1075 regScoreboard[dest_reg->flatIndex()] = true; 1076 } 1077 return dependents; 1078} 1079 1080template <class Impl> 1081void 1082InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 1083{ 1084 OpClass op_class = ready_inst->opClass(); 1085 1086 readyInsts[op_class].push(ready_inst); 1087 1088 // Will need to reorder the list if either a queue is not on the list, 1089 // or it has an older instruction than last time. 1090 if (!queueOnList[op_class]) { 1091 addToOrderList(op_class); 1092 } else if (readyInsts[op_class].top()->seqNum < 1093 (*readyIt[op_class]).oldestInst) { 1094 listOrder.erase(readyIt[op_class]); 1095 addToOrderList(op_class); 1096 } 1097 1098 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 1099 "the ready list, PC %s opclass:%i [sn:%lli].\n", 1100 ready_inst->pcState(), op_class, ready_inst->seqNum); 1101} 1102 1103template <class Impl> 1104void 1105InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 1106{ 1107 DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 1108 1109 // Reset DTB translation state 1110 resched_inst->translationStarted(false); 1111 resched_inst->translationCompleted(false); 1112 1113 resched_inst->clearCanIssue(); 1114 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 1115} 1116 1117template <class Impl> 1118void 1119InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 1120{ 1121 memDepUnit[replay_inst->threadNumber].replay(); 1122} 1123 1124template <class Impl> 1125void 1126InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 1127{ 1128 ThreadID tid = completed_inst->threadNumber; 1129 1130 DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n", 1131 completed_inst->pcState(), completed_inst->seqNum); 1132 1133 ++freeEntries; 1134 1135 completed_inst->memOpDone(true); 1136 1137 memDepUnit[tid].completed(completed_inst); 1138 count[tid]--; 1139} 1140 1141template <class Impl> 1142void 1143InstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst) 1144{ 1145 deferredMemInsts.push_back(deferred_inst); 1146} 1147 1148template <class Impl> 1149void 1150InstructionQueue<Impl>::blockMemInst(DynInstPtr &blocked_inst) 1151{ 1152 blocked_inst->translationStarted(false); 1153 blocked_inst->translationCompleted(false); 1154 1155 blocked_inst->clearIssued(); 1156 blocked_inst->clearCanIssue(); 1157 blockedMemInsts.push_back(blocked_inst); 1158} 1159 1160template <class Impl> 1161void 1162InstructionQueue<Impl>::cacheUnblocked() 1163{ 1164 retryMemInsts.splice(retryMemInsts.end(), blockedMemInsts); 1165 // Get the CPU ticking again 1166 cpu->wakeCPU(); 1167} 1168 1169template <class Impl> 1170typename Impl::DynInstPtr 1171InstructionQueue<Impl>::getDeferredMemInstToExecute() 1172{ 1173 for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); 1174 ++it) { 1175 if ((*it)->translationCompleted() || (*it)->isSquashed()) { 1176 DynInstPtr mem_inst = *it; 1177 deferredMemInsts.erase(it); 1178 return mem_inst; 1179 } 1180 } 1181 return nullptr; 1182} 1183 1184template <class Impl> 1185typename Impl::DynInstPtr 1186InstructionQueue<Impl>::getBlockedMemInstToExecute() 1187{ 1188 if (retryMemInsts.empty()) { 1189 return nullptr; 1190 } else { 1191 DynInstPtr mem_inst = retryMemInsts.front(); 1192 retryMemInsts.pop_front(); 1193 return mem_inst; 1194 } 1195} 1196 1197template <class Impl> 1198void 1199InstructionQueue<Impl>::violation(DynInstPtr &store, 1200 DynInstPtr &faulting_load) 1201{ 1202 intInstQueueWrites++; 1203 memDepUnit[store->threadNumber].violation(store, faulting_load); 1204} 1205 1206template <class Impl> 1207void 1208InstructionQueue<Impl>::squash(ThreadID tid) 1209{ 1210 DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 1211 "the IQ.\n", tid); 1212 1213 // Read instruction sequence number of last instruction out of the 1214 // time buffer. 1215 squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 1216 1217 doSquash(tid); 1218 1219 // Also tell the memory dependence unit to squash. 1220 memDepUnit[tid].squash(squashedSeqNum[tid], tid); 1221} 1222 1223template <class Impl> 1224void 1225InstructionQueue<Impl>::doSquash(ThreadID tid) 1226{ 1227 // Start at the tail. 1228 ListIt squash_it = instList[tid].end(); 1229 --squash_it; 1230 1231 DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 1232 tid, squashedSeqNum[tid]); 1233 1234 // Squash any instructions younger than the squashed sequence number 1235 // given. 1236 while (squash_it != instList[tid].end() && 1237 (*squash_it)->seqNum > squashedSeqNum[tid]) { 1238 1239 DynInstPtr squashed_inst = (*squash_it); 1240 if (squashed_inst->isFloating()) { 1241 fpInstQueueWrites++; 1242 } else if (squashed_inst->isVector()) { 1243 vecInstQueueWrites++; 1244 } else { 1245 intInstQueueWrites++; 1246 } 1247 1248 // Only handle the instruction if it actually is in the IQ and 1249 // hasn't already been squashed in the IQ. 1250 if (squashed_inst->threadNumber != tid || 1251 squashed_inst->isSquashedInIQ()) { 1252 --squash_it; 1253 continue; 1254 } 1255 1256 if (!squashed_inst->isIssued() || 1257 (squashed_inst->isMemRef() && 1258 !squashed_inst->memOpDone())) { 1259 1260 DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", 1261 tid, squashed_inst->seqNum, squashed_inst->pcState()); 1262 1263 bool is_acq_rel = squashed_inst->isMemBarrier() && 1264 (squashed_inst->isLoad() || 1265 (squashed_inst->isStore() && 1266 !squashed_inst->isStoreConditional())); 1267 1268 // Remove the instruction from the dependency list. 1269 if (is_acq_rel || 1270 (!squashed_inst->isNonSpeculative() && 1271 !squashed_inst->isStoreConditional() && 1272 !squashed_inst->isMemBarrier() && 1273 !squashed_inst->isWriteBarrier())) { 1274 1275 for (int src_reg_idx = 0; 1276 src_reg_idx < squashed_inst->numSrcRegs(); 1277 src_reg_idx++) 1278 { 1279 PhysRegIdPtr src_reg = 1280 squashed_inst->renamedSrcRegIdx(src_reg_idx); 1281 1282 // Only remove it from the dependency graph if it 1283 // was placed there in the first place. 1284 1285 // Instead of doing a linked list traversal, we 1286 // can just remove these squashed instructions 1287 // either at issue time, or when the register is 1288 // overwritten. The only downside to this is it 1289 // leaves more room for error. 1290 1291 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 1292 !src_reg->isFixedMapping()) { 1293 dependGraph.remove(src_reg->flatIndex(), 1294 squashed_inst); 1295 } 1296 1297 1298 ++iqSquashedOperandsExamined; 1299 } 1300 } else if (!squashed_inst->isStoreConditional() || 1301 !squashed_inst->isCompleted()) { 1302 NonSpecMapIt ns_inst_it = 1303 nonSpecInsts.find(squashed_inst->seqNum); 1304 1305 // we remove non-speculative instructions from 1306 // nonSpecInsts already when they are ready, and so we 1307 // cannot always expect to find them 1308 if (ns_inst_it == nonSpecInsts.end()) { 1309 // loads that became ready but stalled on a 1310 // blocked cache are alreayd removed from 1311 // nonSpecInsts, and have not faulted 1312 assert(squashed_inst->getFault() != NoFault || 1313 squashed_inst->isMemRef()); 1314 } else { 1315 1316 (*ns_inst_it).second = NULL; 1317 1318 nonSpecInsts.erase(ns_inst_it); 1319 1320 ++iqSquashedNonSpecRemoved; 1321 } 1322 } 1323 1324 // Might want to also clear out the head of the dependency graph. 1325 1326 // Mark it as squashed within the IQ. 1327 squashed_inst->setSquashedInIQ(); 1328 1329 // @todo: Remove this hack where several statuses are set so the 1330 // inst will flow through the rest of the pipeline. 1331 squashed_inst->setIssued(); 1332 squashed_inst->setCanCommit(); 1333 squashed_inst->clearInIQ(); 1334 1335 //Update Thread IQ Count 1336 count[squashed_inst->threadNumber]--; 1337 1338 ++freeEntries; 1339 } 1340 1341 // IQ clears out the heads of the dependency graph only when 1342 // instructions reach writeback stage. If an instruction is squashed 1343 // before writeback stage, its head of dependency graph would not be 1344 // cleared out; it holds the instruction's DynInstPtr. This prevents 1345 // freeing the squashed instruction's DynInst. 1346 // Thus, we need to manually clear out the squashed instructions' heads 1347 // of dependency graph. 1348 for (int dest_reg_idx = 0; 1349 dest_reg_idx < squashed_inst->numDestRegs(); 1350 dest_reg_idx++) 1351 { 1352 PhysRegIdPtr dest_reg = 1353 squashed_inst->renamedDestRegIdx(dest_reg_idx); 1354 if (dest_reg->isFixedMapping()){ 1355 continue; 1356 } 1357 assert(dependGraph.empty(dest_reg->flatIndex())); 1358 dependGraph.clearInst(dest_reg->flatIndex()); 1359 } 1360 instList[tid].erase(squash_it--); 1361 ++iqSquashedInstsExamined; 1362 } 1363} 1364 1365template <class Impl> 1366bool 1367InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 1368{ 1369 // Loop through the instruction's source registers, adding 1370 // them to the dependency list if they are not ready. 1371 int8_t total_src_regs = new_inst->numSrcRegs(); 1372 bool return_val = false; 1373 1374 for (int src_reg_idx = 0; 1375 src_reg_idx < total_src_regs; 1376 src_reg_idx++) 1377 { 1378 // Only add it to the dependency graph if it's not ready. 1379 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 1380 PhysRegIdPtr src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 1381 1382 // Check the IQ's scoreboard to make sure the register 1383 // hasn't become ready while the instruction was in flight 1384 // between stages. Only if it really isn't ready should 1385 // it be added to the dependency graph. 1386 if (src_reg->isFixedMapping()) { 1387 continue; 1388 } else if (!regScoreboard[src_reg->flatIndex()]) { 1389 DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that " 1390 "is being added to the dependency chain.\n", 1391 new_inst->pcState(), src_reg->index(), 1392 src_reg->className()); 1393 1394 dependGraph.insert(src_reg->flatIndex(), new_inst); 1395 1396 // Change the return value to indicate that something 1397 // was added to the dependency graph. 1398 return_val = true; 1399 } else { 1400 DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that " 1401 "became ready before it reached the IQ.\n", 1402 new_inst->pcState(), src_reg->index(), 1403 src_reg->className()); 1404 // Mark a register ready within the instruction. 1405 new_inst->markSrcRegReady(src_reg_idx); 1406 } 1407 } 1408 } 1409 1410 return return_val; 1411} 1412 1413template <class Impl> 1414void 1415InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) 1416{ 1417 // Nothing really needs to be marked when an instruction becomes 1418 // the producer of a register's value, but for convenience a ptr 1419 // to the producing instruction will be placed in the head node of 1420 // the dependency links. 1421 int8_t total_dest_regs = new_inst->numDestRegs(); 1422 1423 for (int dest_reg_idx = 0; 1424 dest_reg_idx < total_dest_regs; 1425 dest_reg_idx++) 1426 { 1427 PhysRegIdPtr dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 1428 1429 // Some registers have fixed mapping, and there is no need to track 1430 // dependencies as these instructions must be executed at commit. 1431 if (dest_reg->isFixedMapping()) { 1432 continue; 1433 } 1434 1435 if (!dependGraph.empty(dest_reg->flatIndex())) { 1436 dependGraph.dump(); 1437 panic("Dependency graph %i (%s) (flat: %i) not empty!", 1438 dest_reg->index(), dest_reg->className(), 1439 dest_reg->flatIndex()); 1440 } 1441 1442 dependGraph.setInst(dest_reg->flatIndex(), new_inst); 1443 1444 // Mark the scoreboard to say it's not yet ready. 1445 regScoreboard[dest_reg->flatIndex()] = false; 1446 } 1447} 1448 1449template <class Impl> 1450void 1451InstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 1452{ 1453 // If the instruction now has all of its source registers 1454 // available, then add it to the list of ready instructions. 1455 if (inst->readyToIssue()) { 1456 1457 //Add the instruction to the proper ready list. 1458 if (inst->isMemRef()) { 1459 1460 DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 1461 1462 // Message to the mem dependence unit that this instruction has 1463 // its registers ready. 1464 memDepUnit[inst->threadNumber].regsReady(inst); 1465 1466 return; 1467 } 1468 1469 OpClass op_class = inst->opClass(); 1470 1471 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 1472 "the ready list, PC %s opclass:%i [sn:%lli].\n", 1473 inst->pcState(), op_class, inst->seqNum); 1474 1475 readyInsts[op_class].push(inst); 1476 1477 // Will need to reorder the list if either a queue is not on the list, 1478 // or it has an older instruction than last time. 1479 if (!queueOnList[op_class]) { 1480 addToOrderList(op_class); 1481 } else if (readyInsts[op_class].top()->seqNum < 1482 (*readyIt[op_class]).oldestInst) { 1483 listOrder.erase(readyIt[op_class]); 1484 addToOrderList(op_class); 1485 } 1486 } 1487} 1488 1489template <class Impl> 1490int 1491InstructionQueue<Impl>::countInsts() 1492{ 1493#if 0 1494 //ksewell:This works but definitely could use a cleaner write 1495 //with a more intuitive way of counting. Right now it's 1496 //just brute force .... 1497 // Change the #if if you want to use this method. 1498 int total_insts = 0; 1499 1500 for (ThreadID tid = 0; tid < numThreads; ++tid) { 1501 ListIt count_it = instList[tid].begin(); 1502 1503 while (count_it != instList[tid].end()) { 1504 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 1505 if (!(*count_it)->isIssued()) { 1506 ++total_insts; 1507 } else if ((*count_it)->isMemRef() && 1508 !(*count_it)->memOpDone) { 1509 // Loads that have not been marked as executed still count 1510 // towards the total instructions. 1511 ++total_insts; 1512 } 1513 } 1514 1515 ++count_it; 1516 } 1517 } 1518 1519 return total_insts; 1520#else 1521 return numEntries - freeEntries; 1522#endif 1523} 1524 1525template <class Impl> 1526void 1527InstructionQueue<Impl>::dumpLists() 1528{ 1529 for (int i = 0; i < Num_OpClasses; ++i) { 1530 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 1531 1532 cprintf("\n"); 1533 } 1534 1535 cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 1536 1537 NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 1538 NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 1539 1540 cprintf("Non speculative list: "); 1541 1542 while (non_spec_it != non_spec_end_it) { 1543 cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(), 1544 (*non_spec_it).second->seqNum); 1545 ++non_spec_it; 1546 } 1547 1548 cprintf("\n"); 1549 1550 ListOrderIt list_order_it = listOrder.begin(); 1551 ListOrderIt list_order_end_it = listOrder.end(); 1552 int i = 1; 1553 1554 cprintf("List order: "); 1555 1556 while (list_order_it != list_order_end_it) { 1557 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 1558 (*list_order_it).oldestInst); 1559 1560 ++list_order_it; 1561 ++i; 1562 } 1563 1564 cprintf("\n"); 1565} 1566 1567 1568template <class Impl> 1569void 1570InstructionQueue<Impl>::dumpInsts() 1571{ 1572 for (ThreadID tid = 0; tid < numThreads; ++tid) { 1573 int num = 0; 1574 int valid_num = 0; 1575 ListIt inst_list_it = instList[tid].begin(); 1576 1577 while (inst_list_it != instList[tid].end()) { 1578 cprintf("Instruction:%i\n", num); 1579 if (!(*inst_list_it)->isSquashed()) { 1580 if (!(*inst_list_it)->isIssued()) { 1581 ++valid_num; 1582 cprintf("Count:%i\n", valid_num); 1583 } else if ((*inst_list_it)->isMemRef() && 1584 !(*inst_list_it)->memOpDone()) { 1585 // Loads that have not been marked as executed 1586 // still count towards the total instructions. 1587 ++valid_num; 1588 cprintf("Count:%i\n", valid_num); 1589 } 1590 } 1591 1592 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 1593 "Issued:%i\nSquashed:%i\n", 1594 (*inst_list_it)->pcState(), 1595 (*inst_list_it)->seqNum, 1596 (*inst_list_it)->threadNumber, 1597 (*inst_list_it)->isIssued(), 1598 (*inst_list_it)->isSquashed()); 1599 1600 if ((*inst_list_it)->isMemRef()) { 1601 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 1602 } 1603 1604 cprintf("\n"); 1605 1606 inst_list_it++; 1607 ++num; 1608 } 1609 } 1610 1611 cprintf("Insts to Execute list:\n"); 1612 1613 int num = 0; 1614 int valid_num = 0; 1615 ListIt inst_list_it = instsToExecute.begin(); 1616 1617 while (inst_list_it != instsToExecute.end()) 1618 { 1619 cprintf("Instruction:%i\n", 1620 num); 1621 if (!(*inst_list_it)->isSquashed()) { 1622 if (!(*inst_list_it)->isIssued()) { 1623 ++valid_num; 1624 cprintf("Count:%i\n", valid_num); 1625 } else if ((*inst_list_it)->isMemRef() && 1626 !(*inst_list_it)->memOpDone()) { 1627 // Loads that have not been marked as executed 1628 // still count towards the total instructions. 1629 ++valid_num; 1630 cprintf("Count:%i\n", valid_num); 1631 } 1632 } 1633 1634 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 1635 "Issued:%i\nSquashed:%i\n", 1636 (*inst_list_it)->pcState(), 1637 (*inst_list_it)->seqNum, 1638 (*inst_list_it)->threadNumber, 1639 (*inst_list_it)->isIssued(), 1640 (*inst_list_it)->isSquashed()); 1641 1642 if ((*inst_list_it)->isMemRef()) { 1643 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 1644 } 1645 1646 cprintf("\n"); 1647 1648 inst_list_it++; 1649 ++num; 1650 } 1651} 1652 1653#endif//__CPU_O3_INST_QUEUE_IMPL_HH__ 1654