inst_queue_impl.hh revision 12106
11689SN/A/* 210333Smitch.hayenga@arm.com * Copyright (c) 2011-2014 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47944SGiacomo.Gabrielli@arm.com * All rights reserved. 57944SGiacomo.Gabrielli@arm.com * 67944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 77944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 87944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 97944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 107944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 117944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 127944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 137944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 147944SGiacomo.Gabrielli@arm.com * 152326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422831Sksewell@umich.edu * Korey Sewell 431689SN/A */ 441689SN/A 459944Smatt.horsnell@ARM.com#ifndef __CPU_O3_INST_QUEUE_IMPL_HH__ 469944Smatt.horsnell@ARM.com#define __CPU_O3_INST_QUEUE_IMPL_HH__ 479944Smatt.horsnell@ARM.com 482064SN/A#include <limits> 491060SN/A#include <vector> 501060SN/A 512292SN/A#include "cpu/o3/fu_pool.hh" 521717SN/A#include "cpu/o3/inst_queue.hh" 538232Snate@binkert.org#include "debug/IQ.hh" 544762Snate@binkert.org#include "enums/OpClass.hh" 556221Snate@binkert.org#include "params/DerivO3CPU.hh" 564762Snate@binkert.org#include "sim/core.hh" 571060SN/A 588737Skoansin.tan@gmail.com// clang complains about std::set being overloaded with Packet::set if 598737Skoansin.tan@gmail.com// we open up the entire namespace std 608737Skoansin.tan@gmail.comusing std::list; 615529Snate@binkert.org 621061SN/Atemplate <class Impl> 632292SN/AInstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 645606Snate@binkert.org int fu_idx, InstructionQueue<Impl> *iq_ptr) 658581Ssteve.reinhardt@amd.com : Event(Stat_Event_Pri, AutoDelete), 668581Ssteve.reinhardt@amd.com inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 671060SN/A{ 682292SN/A} 692292SN/A 702292SN/Atemplate <class Impl> 712292SN/Avoid 722292SN/AInstructionQueue<Impl>::FUCompletion::process() 732292SN/A{ 742326SN/A iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 752292SN/A inst = NULL; 762292SN/A} 772292SN/A 782292SN/A 792292SN/Atemplate <class Impl> 802292SN/Aconst char * 815336Shines@cs.fsu.eduInstructionQueue<Impl>::FUCompletion::description() const 822292SN/A{ 834873Sstever@eecs.umich.edu return "Functional unit completion"; 842292SN/A} 852292SN/A 862292SN/Atemplate <class Impl> 874329Sktlim@umich.eduInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 885529Snate@binkert.org DerivO3CPUParams *params) 894329Sktlim@umich.edu : cpu(cpu_ptr), 904329Sktlim@umich.edu iewStage(iew_ptr), 914329Sktlim@umich.edu fuPool(params->fuPool), 922292SN/A numEntries(params->numIQEntries), 932292SN/A totalWidth(params->issueWidth), 942292SN/A commitToIEWDelay(params->commitToIEWDelay) 952292SN/A{ 962292SN/A assert(fuPool); 972292SN/A 985529Snate@binkert.org numThreads = params->numThreads; 991060SN/A 1009920Syasuko.eckert@amd.com // Set the number of total physical registers 1019920Syasuko.eckert@amd.com numPhysRegs = params->numPhysIntRegs + params->numPhysFloatRegs + 10210935Snilay@cs.wisc.edu params->numPhysCCRegs; 1031060SN/A 1041060SN/A //Create an entry for each physical register within the 1051060SN/A //dependency graph. 1062326SN/A dependGraph.resize(numPhysRegs); 1071060SN/A 1081060SN/A // Resize the register scoreboard. 1091060SN/A regScoreboard.resize(numPhysRegs); 1101060SN/A 1112292SN/A //Initialize Mem Dependence Units 1126221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1136221Snate@binkert.org memDepUnit[tid].init(params, tid); 1146221Snate@binkert.org memDepUnit[tid].setIQ(this); 1151060SN/A } 1161060SN/A 1172307SN/A resetState(); 1182292SN/A 1192980Sgblack@eecs.umich.edu std::string policy = params->smtIQPolicy; 1202292SN/A 1212292SN/A //Convert string to lowercase 1222292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1232292SN/A (int(*)(int)) tolower); 1242292SN/A 1252292SN/A //Figure out resource sharing policy 1262292SN/A if (policy == "dynamic") { 1272292SN/A iqPolicy = Dynamic; 1282292SN/A 1292292SN/A //Set Max Entries to Total ROB Capacity 1306221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1316221Snate@binkert.org maxEntries[tid] = numEntries; 1322292SN/A } 1332292SN/A 1342292SN/A } else if (policy == "partitioned") { 1352292SN/A iqPolicy = Partitioned; 1362292SN/A 1372292SN/A //@todo:make work if part_amt doesnt divide evenly. 1382292SN/A int part_amt = numEntries / numThreads; 1392292SN/A 1402292SN/A //Divide ROB up evenly 1416221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1426221Snate@binkert.org maxEntries[tid] = part_amt; 1432292SN/A } 1442292SN/A 1452831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 1462292SN/A "%i entries per thread.\n",part_amt); 1472292SN/A } else if (policy == "threshold") { 1482292SN/A iqPolicy = Threshold; 1492292SN/A 1502292SN/A double threshold = (double)params->smtIQThreshold / 100; 1512292SN/A 1522292SN/A int thresholdIQ = (int)((double)threshold * numEntries); 1532292SN/A 1542292SN/A //Divide up by threshold amount 1556221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1566221Snate@binkert.org maxEntries[tid] = thresholdIQ; 1572292SN/A } 1582292SN/A 1592831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Threshold:" 1602292SN/A "%i entries per thread.\n",thresholdIQ); 1612292SN/A } else { 1622292SN/A assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 1632292SN/A "Partitioned, Threshold}"); 1642292SN/A } 1652292SN/A} 1662292SN/A 1672292SN/Atemplate <class Impl> 1682292SN/AInstructionQueue<Impl>::~InstructionQueue() 1692292SN/A{ 1702326SN/A dependGraph.reset(); 1712348SN/A#ifdef DEBUG 1722326SN/A cprintf("Nodes traversed: %i, removed: %i\n", 1732326SN/A dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1742348SN/A#endif 1752292SN/A} 1762292SN/A 1772292SN/Atemplate <class Impl> 1782292SN/Astd::string 1792292SN/AInstructionQueue<Impl>::name() const 1802292SN/A{ 1812292SN/A return cpu->name() + ".iq"; 1821060SN/A} 1831060SN/A 1841061SN/Atemplate <class Impl> 1851060SN/Avoid 1861062SN/AInstructionQueue<Impl>::regStats() 1871062SN/A{ 1882301SN/A using namespace Stats; 1891062SN/A iqInstsAdded 1901062SN/A .name(name() + ".iqInstsAdded") 1911062SN/A .desc("Number of instructions added to the IQ (excludes non-spec)") 1921062SN/A .prereq(iqInstsAdded); 1931062SN/A 1941062SN/A iqNonSpecInstsAdded 1951062SN/A .name(name() + ".iqNonSpecInstsAdded") 1961062SN/A .desc("Number of non-speculative instructions added to the IQ") 1971062SN/A .prereq(iqNonSpecInstsAdded); 1981062SN/A 1992301SN/A iqInstsIssued 2002301SN/A .name(name() + ".iqInstsIssued") 2012301SN/A .desc("Number of instructions issued") 2022301SN/A .prereq(iqInstsIssued); 2031062SN/A 2041062SN/A iqIntInstsIssued 2051062SN/A .name(name() + ".iqIntInstsIssued") 2061062SN/A .desc("Number of integer instructions issued") 2071062SN/A .prereq(iqIntInstsIssued); 2081062SN/A 2091062SN/A iqFloatInstsIssued 2101062SN/A .name(name() + ".iqFloatInstsIssued") 2111062SN/A .desc("Number of float instructions issued") 2121062SN/A .prereq(iqFloatInstsIssued); 2131062SN/A 2141062SN/A iqBranchInstsIssued 2151062SN/A .name(name() + ".iqBranchInstsIssued") 2161062SN/A .desc("Number of branch instructions issued") 2171062SN/A .prereq(iqBranchInstsIssued); 2181062SN/A 2191062SN/A iqMemInstsIssued 2201062SN/A .name(name() + ".iqMemInstsIssued") 2211062SN/A .desc("Number of memory instructions issued") 2221062SN/A .prereq(iqMemInstsIssued); 2231062SN/A 2241062SN/A iqMiscInstsIssued 2251062SN/A .name(name() + ".iqMiscInstsIssued") 2261062SN/A .desc("Number of miscellaneous instructions issued") 2271062SN/A .prereq(iqMiscInstsIssued); 2281062SN/A 2291062SN/A iqSquashedInstsIssued 2301062SN/A .name(name() + ".iqSquashedInstsIssued") 2311062SN/A .desc("Number of squashed instructions issued") 2321062SN/A .prereq(iqSquashedInstsIssued); 2331062SN/A 2341062SN/A iqSquashedInstsExamined 2351062SN/A .name(name() + ".iqSquashedInstsExamined") 2361062SN/A .desc("Number of squashed instructions iterated over during squash;" 2371062SN/A " mainly for profiling") 2381062SN/A .prereq(iqSquashedInstsExamined); 2391062SN/A 2401062SN/A iqSquashedOperandsExamined 2411062SN/A .name(name() + ".iqSquashedOperandsExamined") 2421062SN/A .desc("Number of squashed operands that are examined and possibly " 2431062SN/A "removed from graph") 2441062SN/A .prereq(iqSquashedOperandsExamined); 2451062SN/A 2461062SN/A iqSquashedNonSpecRemoved 2471062SN/A .name(name() + ".iqSquashedNonSpecRemoved") 2481062SN/A .desc("Number of squashed non-spec instructions that were removed") 2491062SN/A .prereq(iqSquashedNonSpecRemoved); 2502361SN/A/* 2512326SN/A queueResDist 2522301SN/A .init(Num_OpClasses, 0, 99, 2) 2532301SN/A .name(name() + ".IQ:residence:") 2542301SN/A .desc("cycles from dispatch to issue") 2552301SN/A .flags(total | pdf | cdf ) 2562301SN/A ; 2572301SN/A for (int i = 0; i < Num_OpClasses; ++i) { 2582326SN/A queueResDist.subname(i, opClassStrings[i]); 2592301SN/A } 2602361SN/A*/ 2612326SN/A numIssuedDist 2622307SN/A .init(0,totalWidth,1) 2638240Snate@binkert.org .name(name() + ".issued_per_cycle") 2642301SN/A .desc("Number of insts issued each cycle") 2652307SN/A .flags(pdf) 2662301SN/A ; 2672301SN/A/* 2682301SN/A dist_unissued 2692301SN/A .init(Num_OpClasses+2) 2708240Snate@binkert.org .name(name() + ".unissued_cause") 2712301SN/A .desc("Reason ready instruction not issued") 2722301SN/A .flags(pdf | dist) 2732301SN/A ; 2742301SN/A for (int i=0; i < (Num_OpClasses + 2); ++i) { 2752301SN/A dist_unissued.subname(i, unissued_names[i]); 2762301SN/A } 2772301SN/A*/ 2782326SN/A statIssuedInstType 2794762Snate@binkert.org .init(numThreads,Enums::Num_OpClass) 2808240Snate@binkert.org .name(name() + ".FU_type") 2812301SN/A .desc("Type of FU issued") 2822301SN/A .flags(total | pdf | dist) 2832301SN/A ; 2844762Snate@binkert.org statIssuedInstType.ysubnames(Enums::OpClassStrings); 2852301SN/A 2862301SN/A // 2872301SN/A // How long did instructions for a particular FU type wait prior to issue 2882301SN/A // 2892361SN/A/* 2902326SN/A issueDelayDist 2912301SN/A .init(Num_OpClasses,0,99,2) 2928240Snate@binkert.org .name(name() + ".") 2932301SN/A .desc("cycles from operands ready to issue") 2942301SN/A .flags(pdf | cdf) 2952301SN/A ; 2962301SN/A 2972301SN/A for (int i=0; i<Num_OpClasses; ++i) { 2982980Sgblack@eecs.umich.edu std::stringstream subname; 2992301SN/A subname << opClassStrings[i] << "_delay"; 3002326SN/A issueDelayDist.subname(i, subname.str()); 3012301SN/A } 3022361SN/A*/ 3032326SN/A issueRate 3048240Snate@binkert.org .name(name() + ".rate") 3052301SN/A .desc("Inst issue rate") 3062301SN/A .flags(total) 3072301SN/A ; 3082326SN/A issueRate = iqInstsIssued / cpu->numCycles; 3092727Sktlim@umich.edu 3102326SN/A statFuBusy 3112301SN/A .init(Num_OpClasses) 3128240Snate@binkert.org .name(name() + ".fu_full") 3132301SN/A .desc("attempts to use FU when none available") 3142301SN/A .flags(pdf | dist) 3152301SN/A ; 3162301SN/A for (int i=0; i < Num_OpClasses; ++i) { 3174762Snate@binkert.org statFuBusy.subname(i, Enums::OpClassStrings[i]); 3182301SN/A } 3192301SN/A 3202326SN/A fuBusy 3212301SN/A .init(numThreads) 3228240Snate@binkert.org .name(name() + ".fu_busy_cnt") 3232301SN/A .desc("FU busy when requested") 3242301SN/A .flags(total) 3252301SN/A ; 3262301SN/A 3272326SN/A fuBusyRate 3288240Snate@binkert.org .name(name() + ".fu_busy_rate") 3292301SN/A .desc("FU busy rate (busy events/executed inst)") 3302301SN/A .flags(total) 3312301SN/A ; 3322326SN/A fuBusyRate = fuBusy / iqInstsIssued; 3332301SN/A 3346221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3352292SN/A // Tell mem dependence unit to reg stats as well. 3366221Snate@binkert.org memDepUnit[tid].regStats(); 3372292SN/A } 3387897Shestness@cs.utexas.edu 3397897Shestness@cs.utexas.edu intInstQueueReads 3407897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_reads") 3417897Shestness@cs.utexas.edu .desc("Number of integer instruction queue reads") 3427897Shestness@cs.utexas.edu .flags(total); 3437897Shestness@cs.utexas.edu 3447897Shestness@cs.utexas.edu intInstQueueWrites 3457897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_writes") 3467897Shestness@cs.utexas.edu .desc("Number of integer instruction queue writes") 3477897Shestness@cs.utexas.edu .flags(total); 3487897Shestness@cs.utexas.edu 3497897Shestness@cs.utexas.edu intInstQueueWakeupAccesses 3507897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_wakeup_accesses") 3517897Shestness@cs.utexas.edu .desc("Number of integer instruction queue wakeup accesses") 3527897Shestness@cs.utexas.edu .flags(total); 3537897Shestness@cs.utexas.edu 3547897Shestness@cs.utexas.edu fpInstQueueReads 3557897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_reads") 3567897Shestness@cs.utexas.edu .desc("Number of floating instruction queue reads") 3577897Shestness@cs.utexas.edu .flags(total); 3587897Shestness@cs.utexas.edu 3597897Shestness@cs.utexas.edu fpInstQueueWrites 3607897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_writes") 3617897Shestness@cs.utexas.edu .desc("Number of floating instruction queue writes") 3627897Shestness@cs.utexas.edu .flags(total); 3637897Shestness@cs.utexas.edu 3647897Shestness@cs.utexas.edu fpInstQueueWakeupQccesses 3657897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_wakeup_accesses") 3667897Shestness@cs.utexas.edu .desc("Number of floating instruction queue wakeup accesses") 3677897Shestness@cs.utexas.edu .flags(total); 3687897Shestness@cs.utexas.edu 3697897Shestness@cs.utexas.edu intAluAccesses 3707897Shestness@cs.utexas.edu .name(name() + ".int_alu_accesses") 3717897Shestness@cs.utexas.edu .desc("Number of integer alu accesses") 3727897Shestness@cs.utexas.edu .flags(total); 3737897Shestness@cs.utexas.edu 3747897Shestness@cs.utexas.edu fpAluAccesses 3757897Shestness@cs.utexas.edu .name(name() + ".fp_alu_accesses") 3767897Shestness@cs.utexas.edu .desc("Number of floating point alu accesses") 3777897Shestness@cs.utexas.edu .flags(total); 3787897Shestness@cs.utexas.edu 3791062SN/A} 3801062SN/A 3811062SN/Atemplate <class Impl> 3821062SN/Avoid 3832307SN/AInstructionQueue<Impl>::resetState() 3841060SN/A{ 3852307SN/A //Initialize thread IQ counts 3866221Snate@binkert.org for (ThreadID tid = 0; tid <numThreads; tid++) { 3876221Snate@binkert.org count[tid] = 0; 3886221Snate@binkert.org instList[tid].clear(); 3892307SN/A } 3901060SN/A 3912307SN/A // Initialize the number of free IQ entries. 3922307SN/A freeEntries = numEntries; 3932307SN/A 3942307SN/A // Note that in actuality, the registers corresponding to the logical 3952307SN/A // registers start off as ready. However this doesn't matter for the 3962307SN/A // IQ as the instruction should have been correctly told if those 3972307SN/A // registers are ready in rename. Thus it can all be initialized as 3982307SN/A // unready. 3992307SN/A for (int i = 0; i < numPhysRegs; ++i) { 4002307SN/A regScoreboard[i] = false; 4012307SN/A } 4022307SN/A 4036221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 4046221Snate@binkert.org squashedSeqNum[tid] = 0; 4052307SN/A } 4062307SN/A 4072307SN/A for (int i = 0; i < Num_OpClasses; ++i) { 4082307SN/A while (!readyInsts[i].empty()) 4092307SN/A readyInsts[i].pop(); 4102307SN/A queueOnList[i] = false; 4112307SN/A readyIt[i] = listOrder.end(); 4122307SN/A } 4132307SN/A nonSpecInsts.clear(); 4142307SN/A listOrder.clear(); 4157944SGiacomo.Gabrielli@arm.com deferredMemInsts.clear(); 41610333Smitch.hayenga@arm.com blockedMemInsts.clear(); 41710333Smitch.hayenga@arm.com retryMemInsts.clear(); 41810511Smitch.hayenga@arm.com wbOutstanding = 0; 4191060SN/A} 4201060SN/A 4211061SN/Atemplate <class Impl> 4221060SN/Avoid 4236221Snate@binkert.orgInstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 4241060SN/A{ 4252292SN/A activeThreads = at_ptr; 4262064SN/A} 4272064SN/A 4282064SN/Atemplate <class Impl> 4292064SN/Avoid 4302292SN/AInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 4312064SN/A{ 4324318Sktlim@umich.edu issueToExecuteQueue = i2e_ptr; 4331060SN/A} 4341060SN/A 4351061SN/Atemplate <class Impl> 4361060SN/Avoid 4371060SN/AInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 4381060SN/A{ 4391060SN/A timeBuffer = tb_ptr; 4401060SN/A 4411060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 4421060SN/A} 4431060SN/A 4441684SN/Atemplate <class Impl> 44510510Smitch.hayenga@arm.combool 44610510Smitch.hayenga@arm.comInstructionQueue<Impl>::isDrained() const 44710510Smitch.hayenga@arm.com{ 44810511Smitch.hayenga@arm.com bool drained = dependGraph.empty() && 44910511Smitch.hayenga@arm.com instsToExecute.empty() && 45010511Smitch.hayenga@arm.com wbOutstanding == 0; 45110510Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) 45210510Smitch.hayenga@arm.com drained = drained && memDepUnit[tid].isDrained(); 45310510Smitch.hayenga@arm.com 45410510Smitch.hayenga@arm.com return drained; 45510510Smitch.hayenga@arm.com} 45610510Smitch.hayenga@arm.com 45710510Smitch.hayenga@arm.comtemplate <class Impl> 4582307SN/Avoid 4599444SAndreas.Sandberg@ARM.comInstructionQueue<Impl>::drainSanityCheck() const 4602307SN/A{ 4619444SAndreas.Sandberg@ARM.com assert(dependGraph.empty()); 4629444SAndreas.Sandberg@ARM.com assert(instsToExecute.empty()); 4639444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; ++tid) 4649444SAndreas.Sandberg@ARM.com memDepUnit[tid].drainSanityCheck(); 4652307SN/A} 4662307SN/A 4672307SN/Atemplate <class Impl> 4682307SN/Avoid 4692307SN/AInstructionQueue<Impl>::takeOverFrom() 4702307SN/A{ 4719444SAndreas.Sandberg@ARM.com resetState(); 4722307SN/A} 4732307SN/A 4742307SN/Atemplate <class Impl> 4752292SN/Aint 4766221Snate@binkert.orgInstructionQueue<Impl>::entryAmount(ThreadID num_threads) 4772292SN/A{ 4782292SN/A if (iqPolicy == Partitioned) { 4792292SN/A return numEntries / num_threads; 4802292SN/A } else { 4812292SN/A return 0; 4822292SN/A } 4832292SN/A} 4842292SN/A 4852292SN/A 4862292SN/Atemplate <class Impl> 4872292SN/Avoid 4882292SN/AInstructionQueue<Impl>::resetEntries() 4892292SN/A{ 4902292SN/A if (iqPolicy != Dynamic || numThreads > 1) { 4913867Sbinkertn@umich.edu int active_threads = activeThreads->size(); 4922292SN/A 4936221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4946221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4952292SN/A 4963867Sbinkertn@umich.edu while (threads != end) { 4976221Snate@binkert.org ThreadID tid = *threads++; 4983867Sbinkertn@umich.edu 4992292SN/A if (iqPolicy == Partitioned) { 5003867Sbinkertn@umich.edu maxEntries[tid] = numEntries / active_threads; 50111321Ssteve.reinhardt@amd.com } else if (iqPolicy == Threshold && active_threads == 1) { 5023867Sbinkertn@umich.edu maxEntries[tid] = numEntries; 5032292SN/A } 5042292SN/A } 5052292SN/A } 5062292SN/A} 5072292SN/A 5082292SN/Atemplate <class Impl> 5091684SN/Aunsigned 5101684SN/AInstructionQueue<Impl>::numFreeEntries() 5111684SN/A{ 5121684SN/A return freeEntries; 5131684SN/A} 5141684SN/A 5152292SN/Atemplate <class Impl> 5162292SN/Aunsigned 5176221Snate@binkert.orgInstructionQueue<Impl>::numFreeEntries(ThreadID tid) 5182292SN/A{ 5192292SN/A return maxEntries[tid] - count[tid]; 5202292SN/A} 5212292SN/A 5221060SN/A// Might want to do something more complex if it knows how many instructions 5231060SN/A// will be issued this cycle. 5241061SN/Atemplate <class Impl> 5251060SN/Abool 5261060SN/AInstructionQueue<Impl>::isFull() 5271060SN/A{ 5281060SN/A if (freeEntries == 0) { 5291060SN/A return(true); 5301060SN/A } else { 5311060SN/A return(false); 5321060SN/A } 5331060SN/A} 5341060SN/A 5351061SN/Atemplate <class Impl> 5362292SN/Abool 5376221Snate@binkert.orgInstructionQueue<Impl>::isFull(ThreadID tid) 5382292SN/A{ 5392292SN/A if (numFreeEntries(tid) == 0) { 5402292SN/A return(true); 5412292SN/A } else { 5422292SN/A return(false); 5432292SN/A } 5442292SN/A} 5452292SN/A 5462292SN/Atemplate <class Impl> 5472292SN/Abool 5482292SN/AInstructionQueue<Impl>::hasReadyInsts() 5492292SN/A{ 5502292SN/A if (!listOrder.empty()) { 5512292SN/A return true; 5522292SN/A } 5532292SN/A 5542292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 5552292SN/A if (!readyInsts[i].empty()) { 5562292SN/A return true; 5572292SN/A } 5582292SN/A } 5592292SN/A 5602292SN/A return false; 5612292SN/A} 5622292SN/A 5632292SN/Atemplate <class Impl> 5641060SN/Avoid 5651061SN/AInstructionQueue<Impl>::insert(DynInstPtr &new_inst) 5661060SN/A{ 5677897Shestness@cs.utexas.edu new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 5681060SN/A // Make sure the instruction is valid 5691060SN/A assert(new_inst); 5701060SN/A 5717720Sgblack@eecs.umich.edu DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n", 5727720Sgblack@eecs.umich.edu new_inst->seqNum, new_inst->pcState()); 5731060SN/A 5741060SN/A assert(freeEntries != 0); 5751060SN/A 5762292SN/A instList[new_inst->threadNumber].push_back(new_inst); 5771060SN/A 5782064SN/A --freeEntries; 5791060SN/A 5802292SN/A new_inst->setInIQ(); 5811060SN/A 5821060SN/A // Look through its source registers (physical regs), and mark any 5831060SN/A // dependencies. 5841060SN/A addToDependents(new_inst); 5851060SN/A 5861060SN/A // Have this instruction set itself as the producer of its destination 5871060SN/A // register(s). 5882326SN/A addToProducers(new_inst); 5891060SN/A 5901061SN/A if (new_inst->isMemRef()) { 5912292SN/A memDepUnit[new_inst->threadNumber].insert(new_inst); 5921062SN/A } else { 5931062SN/A addIfReady(new_inst); 5941061SN/A } 5951061SN/A 5961062SN/A ++iqInstsAdded; 5971060SN/A 5982292SN/A count[new_inst->threadNumber]++; 5992292SN/A 6001060SN/A assert(freeEntries == (numEntries - countInsts())); 6011060SN/A} 6021060SN/A 6031061SN/Atemplate <class Impl> 6041061SN/Avoid 6052292SN/AInstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) 6061061SN/A{ 6071061SN/A // @todo: Clean up this code; can do it by setting inst as unable 6081061SN/A // to issue, then calling normal insert on the inst. 6097897Shestness@cs.utexas.edu new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 6101061SN/A 6112292SN/A assert(new_inst); 6121061SN/A 6132292SN/A nonSpecInsts[new_inst->seqNum] = new_inst; 6141061SN/A 6157720Sgblack@eecs.umich.edu DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s " 6162326SN/A "to the IQ.\n", 6177720Sgblack@eecs.umich.edu new_inst->seqNum, new_inst->pcState()); 6182064SN/A 6191061SN/A assert(freeEntries != 0); 6201061SN/A 6212292SN/A instList[new_inst->threadNumber].push_back(new_inst); 6221061SN/A 6232064SN/A --freeEntries; 6241061SN/A 6252292SN/A new_inst->setInIQ(); 6261061SN/A 6271061SN/A // Have this instruction set itself as the producer of its destination 6281061SN/A // register(s). 6292326SN/A addToProducers(new_inst); 6301061SN/A 6311061SN/A // If it's a memory instruction, add it to the memory dependency 6321061SN/A // unit. 6332292SN/A if (new_inst->isMemRef()) { 6342292SN/A memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 6351061SN/A } 6361062SN/A 6371062SN/A ++iqNonSpecInstsAdded; 6382292SN/A 6392292SN/A count[new_inst->threadNumber]++; 6402292SN/A 6412292SN/A assert(freeEntries == (numEntries - countInsts())); 6421061SN/A} 6431061SN/A 6441061SN/Atemplate <class Impl> 6451060SN/Avoid 6462292SN/AInstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) 6471060SN/A{ 6482292SN/A memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 6491060SN/A 6502292SN/A insertNonSpec(barr_inst); 6512292SN/A} 6521060SN/A 6532064SN/Atemplate <class Impl> 6542333SN/Atypename Impl::DynInstPtr 6552333SN/AInstructionQueue<Impl>::getInstToExecute() 6562333SN/A{ 6572333SN/A assert(!instsToExecute.empty()); 6582333SN/A DynInstPtr inst = instsToExecute.front(); 6592333SN/A instsToExecute.pop_front(); 6607897Shestness@cs.utexas.edu if (inst->isFloating()){ 6617897Shestness@cs.utexas.edu fpInstQueueReads++; 6627897Shestness@cs.utexas.edu } else { 6637897Shestness@cs.utexas.edu intInstQueueReads++; 6647897Shestness@cs.utexas.edu } 6652333SN/A return inst; 6662333SN/A} 6671060SN/A 6682333SN/Atemplate <class Impl> 6692064SN/Avoid 6702292SN/AInstructionQueue<Impl>::addToOrderList(OpClass op_class) 6712292SN/A{ 6722292SN/A assert(!readyInsts[op_class].empty()); 6732292SN/A 6742292SN/A ListOrderEntry queue_entry; 6752292SN/A 6762292SN/A queue_entry.queueType = op_class; 6772292SN/A 6782292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 6792292SN/A 6802292SN/A ListOrderIt list_it = listOrder.begin(); 6812292SN/A ListOrderIt list_end_it = listOrder.end(); 6822292SN/A 6832292SN/A while (list_it != list_end_it) { 6842292SN/A if ((*list_it).oldestInst > queue_entry.oldestInst) { 6852292SN/A break; 6862292SN/A } 6872292SN/A 6882292SN/A list_it++; 6891060SN/A } 6901060SN/A 6912292SN/A readyIt[op_class] = listOrder.insert(list_it, queue_entry); 6922292SN/A queueOnList[op_class] = true; 6932292SN/A} 6941060SN/A 6952292SN/Atemplate <class Impl> 6962292SN/Avoid 6972292SN/AInstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 6982292SN/A{ 6992292SN/A // Get iterator of next item on the list 7002292SN/A // Delete the original iterator 7012292SN/A // Determine if the next item is either the end of the list or younger 7022292SN/A // than the new instruction. If so, then add in a new iterator right here. 7032292SN/A // If not, then move along. 7042292SN/A ListOrderEntry queue_entry; 7052292SN/A OpClass op_class = (*list_order_it).queueType; 7062292SN/A ListOrderIt next_it = list_order_it; 7072292SN/A 7082292SN/A ++next_it; 7092292SN/A 7102292SN/A queue_entry.queueType = op_class; 7112292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 7122292SN/A 7132292SN/A while (next_it != listOrder.end() && 7142292SN/A (*next_it).oldestInst < queue_entry.oldestInst) { 7152292SN/A ++next_it; 7161060SN/A } 7171060SN/A 7182292SN/A readyIt[op_class] = listOrder.insert(next_it, queue_entry); 7191060SN/A} 7201060SN/A 7212292SN/Atemplate <class Impl> 7222292SN/Avoid 7232292SN/AInstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 7242292SN/A{ 7252367SN/A DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 7269444SAndreas.Sandberg@ARM.com assert(!cpu->switchedOut()); 7272292SN/A // The CPU could have been sleeping until this op completed (*extremely* 7282292SN/A // long latency op). Wake it if it was. This may be overkill. 72910511Smitch.hayenga@arm.com --wbOutstanding; 7302292SN/A iewStage->wakeCPU(); 7312292SN/A 7322326SN/A if (fu_idx > -1) 7332326SN/A fuPool->freeUnitNextCycle(fu_idx); 7342292SN/A 7352326SN/A // @todo: Ensure that these FU Completions happen at the beginning 7362326SN/A // of a cycle, otherwise they could add too many instructions to 7372326SN/A // the queue. 7385327Smengke97@hotmail.com issueToExecuteQueue->access(-1)->size++; 7392333SN/A instsToExecute.push_back(inst); 7402292SN/A} 7412292SN/A 7421061SN/A// @todo: Figure out a better way to remove the squashed items from the 7431061SN/A// lists. Checking the top item of each list to see if it's squashed 7441061SN/A// wastes time and forces jumps. 7451061SN/Atemplate <class Impl> 7461060SN/Avoid 7471060SN/AInstructionQueue<Impl>::scheduleReadyInsts() 7481060SN/A{ 7492292SN/A DPRINTF(IQ, "Attempting to schedule ready instructions from " 7502292SN/A "the IQ.\n"); 7511060SN/A 7521060SN/A IssueStruct *i2e_info = issueToExecuteQueue->access(0); 7531060SN/A 75410333Smitch.hayenga@arm.com DynInstPtr mem_inst; 75510333Smitch.hayenga@arm.com while (mem_inst = getDeferredMemInstToExecute()) { 75610333Smitch.hayenga@arm.com addReadyMemInst(mem_inst); 75710333Smitch.hayenga@arm.com } 75810333Smitch.hayenga@arm.com 75910333Smitch.hayenga@arm.com // See if any cache blocked instructions are able to be executed 76010333Smitch.hayenga@arm.com while (mem_inst = getBlockedMemInstToExecute()) { 76110333Smitch.hayenga@arm.com addReadyMemInst(mem_inst); 7627944SGiacomo.Gabrielli@arm.com } 7637944SGiacomo.Gabrielli@arm.com 7642292SN/A // Have iterator to head of the list 7652292SN/A // While I haven't exceeded bandwidth or reached the end of the list, 7662292SN/A // Try to get a FU that can do what this op needs. 7672292SN/A // If successful, change the oldestInst to the new top of the list, put 7682292SN/A // the queue in the proper place in the list. 7692292SN/A // Increment the iterator. 7702292SN/A // This will avoid trying to schedule a certain op class if there are no 7712292SN/A // FUs that handle it. 77210333Smitch.hayenga@arm.com int total_issued = 0; 7732292SN/A ListOrderIt order_it = listOrder.begin(); 7742292SN/A ListOrderIt order_end_it = listOrder.end(); 7751060SN/A 77610333Smitch.hayenga@arm.com while (total_issued < totalWidth && order_it != order_end_it) { 7772292SN/A OpClass op_class = (*order_it).queueType; 7781060SN/A 7792292SN/A assert(!readyInsts[op_class].empty()); 7801060SN/A 7812292SN/A DynInstPtr issuing_inst = readyInsts[op_class].top(); 7821060SN/A 7837897Shestness@cs.utexas.edu issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++; 7847897Shestness@cs.utexas.edu 7852292SN/A assert(issuing_inst->seqNum == (*order_it).oldestInst); 7861060SN/A 7872292SN/A if (issuing_inst->isSquashed()) { 7882292SN/A readyInsts[op_class].pop(); 7891060SN/A 7902292SN/A if (!readyInsts[op_class].empty()) { 7912292SN/A moveToYoungerInst(order_it); 7922292SN/A } else { 7932292SN/A readyIt[op_class] = listOrder.end(); 7942292SN/A queueOnList[op_class] = false; 7951060SN/A } 7961060SN/A 7972292SN/A listOrder.erase(order_it++); 7981060SN/A 7992292SN/A ++iqSquashedInstsIssued; 8002292SN/A 8012292SN/A continue; 8021060SN/A } 8031060SN/A 80411365SRekai.GonzalezAlberquilla@arm.com int idx = FUPool::NoCapableFU; 8059184Sandreas.hansson@arm.com Cycles op_latency = Cycles(1); 8066221Snate@binkert.org ThreadID tid = issuing_inst->threadNumber; 8071060SN/A 8082326SN/A if (op_class != No_OpClass) { 8092326SN/A idx = fuPool->getUnit(op_class); 8107897Shestness@cs.utexas.edu issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++; 81111365SRekai.GonzalezAlberquilla@arm.com if (idx > FUPool::NoFreeFU) { 8122326SN/A op_latency = fuPool->getOpLatency(op_class); 8131060SN/A } 8141060SN/A } 8151060SN/A 8162348SN/A // If we have an instruction that doesn't require a FU, or a 8172348SN/A // valid FU, then schedule for execution. 81811365SRekai.GonzalezAlberquilla@arm.com if (idx != FUPool::NoFreeFU) { 8199184Sandreas.hansson@arm.com if (op_latency == Cycles(1)) { 8202292SN/A i2e_info->size++; 8212333SN/A instsToExecute.push_back(issuing_inst); 8221060SN/A 8232326SN/A // Add the FU onto the list of FU's to be freed next 8242326SN/A // cycle if we used one. 8252326SN/A if (idx >= 0) 8262326SN/A fuPool->freeUnitNextCycle(idx); 8272292SN/A } else { 82810807Snilay@cs.wisc.edu bool pipelined = fuPool->isPipelined(op_class); 8292326SN/A // Generate completion event for the FU 83010511Smitch.hayenga@arm.com ++wbOutstanding; 8312326SN/A FUCompletion *execution = new FUCompletion(issuing_inst, 8322326SN/A idx, this); 8331060SN/A 8349180Sandreas.hansson@arm.com cpu->schedule(execution, 8359180Sandreas.hansson@arm.com cpu->clockEdge(Cycles(op_latency - 1))); 8361060SN/A 83710807Snilay@cs.wisc.edu if (!pipelined) { 8382348SN/A // If FU isn't pipelined, then it must be freed 8392348SN/A // upon the execution completing. 8402326SN/A execution->setFreeFU(); 8412292SN/A } else { 8422292SN/A // Add the FU onto the list of FU's to be freed next cycle. 8432326SN/A fuPool->freeUnitNextCycle(idx); 8442292SN/A } 8451060SN/A } 8461060SN/A 8477720Sgblack@eecs.umich.edu DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 8482292SN/A "[sn:%lli]\n", 8497720Sgblack@eecs.umich.edu tid, issuing_inst->pcState(), 8502292SN/A issuing_inst->seqNum); 8511060SN/A 8522292SN/A readyInsts[op_class].pop(); 8531061SN/A 8542292SN/A if (!readyInsts[op_class].empty()) { 8552292SN/A moveToYoungerInst(order_it); 8562292SN/A } else { 8572292SN/A readyIt[op_class] = listOrder.end(); 8582292SN/A queueOnList[op_class] = false; 8591060SN/A } 8601060SN/A 8612064SN/A issuing_inst->setIssued(); 8622292SN/A ++total_issued; 8632064SN/A 8648471SGiacomo.Gabrielli@arm.com#if TRACING_ON 8659046SAli.Saidi@ARM.com issuing_inst->issueTick = curTick() - issuing_inst->fetchTick; 8668471SGiacomo.Gabrielli@arm.com#endif 8678471SGiacomo.Gabrielli@arm.com 8682292SN/A if (!issuing_inst->isMemRef()) { 8692292SN/A // Memory instructions can not be freed from the IQ until they 8702292SN/A // complete. 8712292SN/A ++freeEntries; 8722301SN/A count[tid]--; 8732731Sktlim@umich.edu issuing_inst->clearInIQ(); 8742292SN/A } else { 8752301SN/A memDepUnit[tid].issue(issuing_inst); 8762292SN/A } 8772292SN/A 8782292SN/A listOrder.erase(order_it++); 8792326SN/A statIssuedInstType[tid][op_class]++; 8802292SN/A } else { 8812326SN/A statFuBusy[op_class]++; 8822326SN/A fuBusy[tid]++; 8832292SN/A ++order_it; 8841060SN/A } 8851060SN/A } 8861062SN/A 8872326SN/A numIssuedDist.sample(total_issued); 8882326SN/A iqInstsIssued+= total_issued; 8892307SN/A 8902348SN/A // If we issued any instructions, tell the CPU we had activity. 8918071SAli.Saidi@ARM.com // @todo If the way deferred memory instructions are handeled due to 8928071SAli.Saidi@ARM.com // translation changes then the deferredMemInsts condition should be removed 8938071SAli.Saidi@ARM.com // from the code below. 89410333Smitch.hayenga@arm.com if (total_issued || !retryMemInsts.empty() || !deferredMemInsts.empty()) { 8952292SN/A cpu->activityThisCycle(); 8962292SN/A } else { 8972292SN/A DPRINTF(IQ, "Not able to schedule any instructions.\n"); 8982292SN/A } 8991060SN/A} 9001060SN/A 9011061SN/Atemplate <class Impl> 9021060SN/Avoid 9031061SN/AInstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 9041060SN/A{ 9052292SN/A DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 9062292SN/A "to execute.\n", inst); 9071062SN/A 9082292SN/A NonSpecMapIt inst_it = nonSpecInsts.find(inst); 9091060SN/A 9101061SN/A assert(inst_it != nonSpecInsts.end()); 9111060SN/A 9126221Snate@binkert.org ThreadID tid = (*inst_it).second->threadNumber; 9132292SN/A 9144033Sktlim@umich.edu (*inst_it).second->setAtCommit(); 9154033Sktlim@umich.edu 9161061SN/A (*inst_it).second->setCanIssue(); 9171060SN/A 9181062SN/A if (!(*inst_it).second->isMemRef()) { 9191062SN/A addIfReady((*inst_it).second); 9201062SN/A } else { 9212292SN/A memDepUnit[tid].nonSpecInstReady((*inst_it).second); 9221062SN/A } 9231060SN/A 9242292SN/A (*inst_it).second = NULL; 9252292SN/A 9261061SN/A nonSpecInsts.erase(inst_it); 9271060SN/A} 9281060SN/A 9291061SN/Atemplate <class Impl> 9301061SN/Avoid 9316221Snate@binkert.orgInstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 9322292SN/A{ 9332292SN/A DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 9342292SN/A tid,inst); 9352292SN/A 9362292SN/A ListIt iq_it = instList[tid].begin(); 9372292SN/A 9382292SN/A while (iq_it != instList[tid].end() && 9392292SN/A (*iq_it)->seqNum <= inst) { 9402292SN/A ++iq_it; 9412292SN/A instList[tid].pop_front(); 9422292SN/A } 9432292SN/A 9442292SN/A assert(freeEntries == (numEntries - countInsts())); 9452292SN/A} 9462292SN/A 9472292SN/Atemplate <class Impl> 9482301SN/Aint 9491684SN/AInstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 9501684SN/A{ 9512301SN/A int dependents = 0; 9522301SN/A 9537897Shestness@cs.utexas.edu // The instruction queue here takes care of both floating and int ops 9547897Shestness@cs.utexas.edu if (completed_inst->isFloating()) { 9557897Shestness@cs.utexas.edu fpInstQueueWakeupQccesses++; 9567897Shestness@cs.utexas.edu } else { 9577897Shestness@cs.utexas.edu intInstQueueWakeupAccesses++; 9587897Shestness@cs.utexas.edu } 9597897Shestness@cs.utexas.edu 9602292SN/A DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 9612292SN/A 9622292SN/A assert(!completed_inst->isSquashed()); 9631684SN/A 9641684SN/A // Tell the memory dependence unit to wake any dependents on this 9652292SN/A // instruction if it is a memory instruction. Also complete the memory 9662326SN/A // instruction at this point since we know it executed without issues. 9672326SN/A // @todo: Might want to rename "completeMemInst" to something that 9682326SN/A // indicates that it won't need to be replayed, and call this 9692326SN/A // earlier. Might not be a big deal. 9701684SN/A if (completed_inst->isMemRef()) { 9712292SN/A memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 9722292SN/A completeMemInst(completed_inst); 9732292SN/A } else if (completed_inst->isMemBarrier() || 9742292SN/A completed_inst->isWriteBarrier()) { 9752292SN/A memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 9761684SN/A } 9771684SN/A 9781684SN/A for (int dest_reg_idx = 0; 9791684SN/A dest_reg_idx < completed_inst->numDestRegs(); 9801684SN/A dest_reg_idx++) 9811684SN/A { 98212105Snathanael.premillieu@arm.com PhysRegIdPtr dest_reg = 9831684SN/A completed_inst->renamedDestRegIdx(dest_reg_idx); 9841684SN/A 9851684SN/A // Special case of uniq or control registers. They are not 9861684SN/A // handled by the IQ and thus have no dependency graph entry. 98712105Snathanael.premillieu@arm.com if (dest_reg->isFixedMapping()) { 98812105Snathanael.premillieu@arm.com DPRINTF(IQ, "Reg %d [%s] is part of a fix mapping, skipping\n", 98912106SRekai.GonzalezAlberquilla@arm.com dest_reg->index(), dest_reg->className()); 9901684SN/A continue; 9911684SN/A } 9921684SN/A 99312105Snathanael.premillieu@arm.com DPRINTF(IQ, "Waking any dependents on register %i (%s).\n", 99412106SRekai.GonzalezAlberquilla@arm.com dest_reg->index(), 99512106SRekai.GonzalezAlberquilla@arm.com dest_reg->className()); 9961684SN/A 9972326SN/A //Go through the dependency chain, marking the registers as 9982326SN/A //ready within the waiting instructions. 99912106SRekai.GonzalezAlberquilla@arm.com DynInstPtr dep_inst = dependGraph.pop(dest_reg->flatIndex()); 10001684SN/A 10012326SN/A while (dep_inst) { 10027599Sminkyu.jeong@arm.com DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] " 10037720Sgblack@eecs.umich.edu "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 10041684SN/A 10051684SN/A // Might want to give more information to the instruction 10062326SN/A // so that it knows which of its source registers is 10072326SN/A // ready. However that would mean that the dependency 10082326SN/A // graph entries would need to hold the src_reg_idx. 10092326SN/A dep_inst->markSrcRegReady(); 10101684SN/A 10112326SN/A addIfReady(dep_inst); 10121684SN/A 101312106SRekai.GonzalezAlberquilla@arm.com dep_inst = dependGraph.pop(dest_reg->flatIndex()); 10141684SN/A 10152301SN/A ++dependents; 10161684SN/A } 10171684SN/A 10182326SN/A // Reset the head node now that all of its dependents have 10192326SN/A // been woken up. 102012106SRekai.GonzalezAlberquilla@arm.com assert(dependGraph.empty(dest_reg->flatIndex())); 102112106SRekai.GonzalezAlberquilla@arm.com dependGraph.clearInst(dest_reg->flatIndex()); 10221684SN/A 10231684SN/A // Mark the scoreboard as having that register ready. 102412106SRekai.GonzalezAlberquilla@arm.com regScoreboard[dest_reg->flatIndex()] = true; 10251684SN/A } 10262301SN/A return dependents; 10272064SN/A} 10282064SN/A 10292064SN/Atemplate <class Impl> 10302064SN/Avoid 10312292SN/AInstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 10322064SN/A{ 10332292SN/A OpClass op_class = ready_inst->opClass(); 10342292SN/A 10352292SN/A readyInsts[op_class].push(ready_inst); 10362292SN/A 10372326SN/A // Will need to reorder the list if either a queue is not on the list, 10382326SN/A // or it has an older instruction than last time. 10392326SN/A if (!queueOnList[op_class]) { 10402326SN/A addToOrderList(op_class); 10412326SN/A } else if (readyInsts[op_class].top()->seqNum < 10422326SN/A (*readyIt[op_class]).oldestInst) { 10432326SN/A listOrder.erase(readyIt[op_class]); 10442326SN/A addToOrderList(op_class); 10452326SN/A } 10462326SN/A 10472292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 10487720Sgblack@eecs.umich.edu "the ready list, PC %s opclass:%i [sn:%lli].\n", 10497720Sgblack@eecs.umich.edu ready_inst->pcState(), op_class, ready_inst->seqNum); 10502064SN/A} 10512064SN/A 10522064SN/Atemplate <class Impl> 10532064SN/Avoid 10542292SN/AInstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 10552064SN/A{ 10564033Sktlim@umich.edu DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 10577944SGiacomo.Gabrielli@arm.com 10587944SGiacomo.Gabrielli@arm.com // Reset DTB translation state 10599046SAli.Saidi@ARM.com resched_inst->translationStarted(false); 10609046SAli.Saidi@ARM.com resched_inst->translationCompleted(false); 10617944SGiacomo.Gabrielli@arm.com 10624033Sktlim@umich.edu resched_inst->clearCanIssue(); 10632292SN/A memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 10642064SN/A} 10652064SN/A 10662064SN/Atemplate <class Impl> 10672064SN/Avoid 10682292SN/AInstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 10692064SN/A{ 107010333Smitch.hayenga@arm.com memDepUnit[replay_inst->threadNumber].replay(); 10712292SN/A} 10722292SN/A 10732292SN/Atemplate <class Impl> 10742292SN/Avoid 10752292SN/AInstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 10762292SN/A{ 10776221Snate@binkert.org ThreadID tid = completed_inst->threadNumber; 10782292SN/A 10797720Sgblack@eecs.umich.edu DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n", 10807720Sgblack@eecs.umich.edu completed_inst->pcState(), completed_inst->seqNum); 10812292SN/A 10822292SN/A ++freeEntries; 10832292SN/A 10849046SAli.Saidi@ARM.com completed_inst->memOpDone(true); 10852292SN/A 10862292SN/A memDepUnit[tid].completed(completed_inst); 10872292SN/A count[tid]--; 10881684SN/A} 10891684SN/A 10901684SN/Atemplate <class Impl> 10911684SN/Avoid 10927944SGiacomo.Gabrielli@arm.comInstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst) 10937944SGiacomo.Gabrielli@arm.com{ 10947944SGiacomo.Gabrielli@arm.com deferredMemInsts.push_back(deferred_inst); 10957944SGiacomo.Gabrielli@arm.com} 10967944SGiacomo.Gabrielli@arm.com 10977944SGiacomo.Gabrielli@arm.comtemplate <class Impl> 109810333Smitch.hayenga@arm.comvoid 109910333Smitch.hayenga@arm.comInstructionQueue<Impl>::blockMemInst(DynInstPtr &blocked_inst) 110010333Smitch.hayenga@arm.com{ 110110333Smitch.hayenga@arm.com blocked_inst->translationStarted(false); 110210333Smitch.hayenga@arm.com blocked_inst->translationCompleted(false); 110310333Smitch.hayenga@arm.com 110410333Smitch.hayenga@arm.com blocked_inst->clearIssued(); 110510333Smitch.hayenga@arm.com blocked_inst->clearCanIssue(); 110610333Smitch.hayenga@arm.com blockedMemInsts.push_back(blocked_inst); 110710333Smitch.hayenga@arm.com} 110810333Smitch.hayenga@arm.com 110910333Smitch.hayenga@arm.comtemplate <class Impl> 111010333Smitch.hayenga@arm.comvoid 111110333Smitch.hayenga@arm.comInstructionQueue<Impl>::cacheUnblocked() 111210333Smitch.hayenga@arm.com{ 111310333Smitch.hayenga@arm.com retryMemInsts.splice(retryMemInsts.end(), blockedMemInsts); 111410333Smitch.hayenga@arm.com // Get the CPU ticking again 111510333Smitch.hayenga@arm.com cpu->wakeCPU(); 111610333Smitch.hayenga@arm.com} 111710333Smitch.hayenga@arm.com 111810333Smitch.hayenga@arm.comtemplate <class Impl> 11197944SGiacomo.Gabrielli@arm.comtypename Impl::DynInstPtr 11207944SGiacomo.Gabrielli@arm.comInstructionQueue<Impl>::getDeferredMemInstToExecute() 11217944SGiacomo.Gabrielli@arm.com{ 11227944SGiacomo.Gabrielli@arm.com for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); 11237944SGiacomo.Gabrielli@arm.com ++it) { 11249046SAli.Saidi@ARM.com if ((*it)->translationCompleted() || (*it)->isSquashed()) { 112510333Smitch.hayenga@arm.com DynInstPtr mem_inst = *it; 11267944SGiacomo.Gabrielli@arm.com deferredMemInsts.erase(it); 112710333Smitch.hayenga@arm.com return mem_inst; 11287944SGiacomo.Gabrielli@arm.com } 11297944SGiacomo.Gabrielli@arm.com } 113010333Smitch.hayenga@arm.com return nullptr; 113110333Smitch.hayenga@arm.com} 113210333Smitch.hayenga@arm.com 113310333Smitch.hayenga@arm.comtemplate <class Impl> 113410333Smitch.hayenga@arm.comtypename Impl::DynInstPtr 113510333Smitch.hayenga@arm.comInstructionQueue<Impl>::getBlockedMemInstToExecute() 113610333Smitch.hayenga@arm.com{ 113710333Smitch.hayenga@arm.com if (retryMemInsts.empty()) { 113810333Smitch.hayenga@arm.com return nullptr; 113910333Smitch.hayenga@arm.com } else { 114010333Smitch.hayenga@arm.com DynInstPtr mem_inst = retryMemInsts.front(); 114110333Smitch.hayenga@arm.com retryMemInsts.pop_front(); 114210333Smitch.hayenga@arm.com return mem_inst; 114310333Smitch.hayenga@arm.com } 11447944SGiacomo.Gabrielli@arm.com} 11457944SGiacomo.Gabrielli@arm.com 11467944SGiacomo.Gabrielli@arm.comtemplate <class Impl> 11477944SGiacomo.Gabrielli@arm.comvoid 11481061SN/AInstructionQueue<Impl>::violation(DynInstPtr &store, 11491061SN/A DynInstPtr &faulting_load) 11501061SN/A{ 11517897Shestness@cs.utexas.edu intInstQueueWrites++; 11522292SN/A memDepUnit[store->threadNumber].violation(store, faulting_load); 11531061SN/A} 11541061SN/A 11551061SN/Atemplate <class Impl> 11561060SN/Avoid 11576221Snate@binkert.orgInstructionQueue<Impl>::squash(ThreadID tid) 11581060SN/A{ 11592292SN/A DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 11602292SN/A "the IQ.\n", tid); 11611060SN/A 11621060SN/A // Read instruction sequence number of last instruction out of the 11631060SN/A // time buffer. 11642292SN/A squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 11651060SN/A 116610797Sbrandon.potter@amd.com doSquash(tid); 11671061SN/A 11681061SN/A // Also tell the memory dependence unit to squash. 11692292SN/A memDepUnit[tid].squash(squashedSeqNum[tid], tid); 11701060SN/A} 11711060SN/A 11721061SN/Atemplate <class Impl> 11731061SN/Avoid 11746221Snate@binkert.orgInstructionQueue<Impl>::doSquash(ThreadID tid) 11751061SN/A{ 11762326SN/A // Start at the tail. 11772326SN/A ListIt squash_it = instList[tid].end(); 11782326SN/A --squash_it; 11791061SN/A 11802292SN/A DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 11812292SN/A tid, squashedSeqNum[tid]); 11821061SN/A 11831061SN/A // Squash any instructions younger than the squashed sequence number 11841061SN/A // given. 11852326SN/A while (squash_it != instList[tid].end() && 11862326SN/A (*squash_it)->seqNum > squashedSeqNum[tid]) { 11872292SN/A 11882326SN/A DynInstPtr squashed_inst = (*squash_it); 11897897Shestness@cs.utexas.edu squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 11901061SN/A 11911061SN/A // Only handle the instruction if it actually is in the IQ and 11921061SN/A // hasn't already been squashed in the IQ. 11932292SN/A if (squashed_inst->threadNumber != tid || 11942292SN/A squashed_inst->isSquashedInIQ()) { 11952326SN/A --squash_it; 11962292SN/A continue; 11972292SN/A } 11982292SN/A 11992292SN/A if (!squashed_inst->isIssued() || 12002292SN/A (squashed_inst->isMemRef() && 12019046SAli.Saidi@ARM.com !squashed_inst->memOpDone())) { 12021062SN/A 12037720Sgblack@eecs.umich.edu DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", 12047720Sgblack@eecs.umich.edu tid, squashed_inst->seqNum, squashed_inst->pcState()); 12052367SN/A 120610032SGiacomo.Gabrielli@arm.com bool is_acq_rel = squashed_inst->isMemBarrier() && 120710032SGiacomo.Gabrielli@arm.com (squashed_inst->isLoad() || 120810032SGiacomo.Gabrielli@arm.com (squashed_inst->isStore() && 120910032SGiacomo.Gabrielli@arm.com !squashed_inst->isStoreConditional())); 121010032SGiacomo.Gabrielli@arm.com 12111061SN/A // Remove the instruction from the dependency list. 121210032SGiacomo.Gabrielli@arm.com if (is_acq_rel || 121310032SGiacomo.Gabrielli@arm.com (!squashed_inst->isNonSpeculative() && 121410032SGiacomo.Gabrielli@arm.com !squashed_inst->isStoreConditional() && 121510032SGiacomo.Gabrielli@arm.com !squashed_inst->isMemBarrier() && 121610032SGiacomo.Gabrielli@arm.com !squashed_inst->isWriteBarrier())) { 12171061SN/A 12181061SN/A for (int src_reg_idx = 0; 12191681SN/A src_reg_idx < squashed_inst->numSrcRegs(); 12201061SN/A src_reg_idx++) 12211061SN/A { 122212105Snathanael.premillieu@arm.com PhysRegIdPtr src_reg = 12231061SN/A squashed_inst->renamedSrcRegIdx(src_reg_idx); 12241061SN/A 12252326SN/A // Only remove it from the dependency graph if it 12262326SN/A // was placed there in the first place. 12272326SN/A 12282326SN/A // Instead of doing a linked list traversal, we 12292326SN/A // can just remove these squashed instructions 12302326SN/A // either at issue time, or when the register is 12312326SN/A // overwritten. The only downside to this is it 12322326SN/A // leaves more room for error. 12332292SN/A 12341061SN/A if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 123512105Snathanael.premillieu@arm.com !src_reg->isFixedMapping()) { 123612106SRekai.GonzalezAlberquilla@arm.com dependGraph.remove(src_reg->flatIndex(), 123712106SRekai.GonzalezAlberquilla@arm.com squashed_inst); 12381061SN/A } 12391062SN/A 12402292SN/A 12411062SN/A ++iqSquashedOperandsExamined; 12421061SN/A } 12434033Sktlim@umich.edu } else if (!squashed_inst->isStoreConditional() || 12444033Sktlim@umich.edu !squashed_inst->isCompleted()) { 12452292SN/A NonSpecMapIt ns_inst_it = 12462292SN/A nonSpecInsts.find(squashed_inst->seqNum); 12478275SAli.Saidi@ARM.com 124810017Sandreas.hansson@arm.com // we remove non-speculative instructions from 124910017Sandreas.hansson@arm.com // nonSpecInsts already when they are ready, and so we 125010017Sandreas.hansson@arm.com // cannot always expect to find them 12514033Sktlim@umich.edu if (ns_inst_it == nonSpecInsts.end()) { 125210017Sandreas.hansson@arm.com // loads that became ready but stalled on a 125310017Sandreas.hansson@arm.com // blocked cache are alreayd removed from 125410017Sandreas.hansson@arm.com // nonSpecInsts, and have not faulted 125510017Sandreas.hansson@arm.com assert(squashed_inst->getFault() != NoFault || 125610017Sandreas.hansson@arm.com squashed_inst->isMemRef()); 12574033Sktlim@umich.edu } else { 12581062SN/A 12594033Sktlim@umich.edu (*ns_inst_it).second = NULL; 12601681SN/A 12614033Sktlim@umich.edu nonSpecInsts.erase(ns_inst_it); 12621062SN/A 12634033Sktlim@umich.edu ++iqSquashedNonSpecRemoved; 12644033Sktlim@umich.edu } 12651061SN/A } 12661061SN/A 12671061SN/A // Might want to also clear out the head of the dependency graph. 12681061SN/A 12691061SN/A // Mark it as squashed within the IQ. 12701061SN/A squashed_inst->setSquashedInIQ(); 12711061SN/A 12722292SN/A // @todo: Remove this hack where several statuses are set so the 12732292SN/A // inst will flow through the rest of the pipeline. 12741681SN/A squashed_inst->setIssued(); 12751681SN/A squashed_inst->setCanCommit(); 12762731Sktlim@umich.edu squashed_inst->clearInIQ(); 12772292SN/A 12782292SN/A //Update Thread IQ Count 12792292SN/A count[squashed_inst->threadNumber]--; 12801681SN/A 12811681SN/A ++freeEntries; 12821061SN/A } 12831061SN/A 12842326SN/A instList[tid].erase(squash_it--); 12851062SN/A ++iqSquashedInstsExamined; 12861061SN/A } 12871060SN/A} 12881060SN/A 12891061SN/Atemplate <class Impl> 12901060SN/Abool 12911061SN/AInstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 12921060SN/A{ 12931060SN/A // Loop through the instruction's source registers, adding 12941060SN/A // them to the dependency list if they are not ready. 12951060SN/A int8_t total_src_regs = new_inst->numSrcRegs(); 12961060SN/A bool return_val = false; 12971060SN/A 12981060SN/A for (int src_reg_idx = 0; 12991060SN/A src_reg_idx < total_src_regs; 13001060SN/A src_reg_idx++) 13011060SN/A { 13021060SN/A // Only add it to the dependency graph if it's not ready. 13031060SN/A if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 130412105Snathanael.premillieu@arm.com PhysRegIdPtr src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 13051060SN/A 13061060SN/A // Check the IQ's scoreboard to make sure the register 13071060SN/A // hasn't become ready while the instruction was in flight 13081060SN/A // between stages. Only if it really isn't ready should 13091060SN/A // it be added to the dependency graph. 131012105Snathanael.premillieu@arm.com if (src_reg->isFixedMapping()) { 13111061SN/A continue; 131212106SRekai.GonzalezAlberquilla@arm.com } else if (!regScoreboard[src_reg->flatIndex()]) { 131312105Snathanael.premillieu@arm.com DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that " 13141060SN/A "is being added to the dependency chain.\n", 131512106SRekai.GonzalezAlberquilla@arm.com new_inst->pcState(), src_reg->index(), 131612106SRekai.GonzalezAlberquilla@arm.com src_reg->className()); 13171060SN/A 131812106SRekai.GonzalezAlberquilla@arm.com dependGraph.insert(src_reg->flatIndex(), new_inst); 13191060SN/A 13201060SN/A // Change the return value to indicate that something 13211060SN/A // was added to the dependency graph. 13221060SN/A return_val = true; 13231060SN/A } else { 132412105Snathanael.premillieu@arm.com DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that " 13251060SN/A "became ready before it reached the IQ.\n", 132612106SRekai.GonzalezAlberquilla@arm.com new_inst->pcState(), src_reg->index(), 132712106SRekai.GonzalezAlberquilla@arm.com src_reg->className()); 13281060SN/A // Mark a register ready within the instruction. 13292326SN/A new_inst->markSrcRegReady(src_reg_idx); 13301060SN/A } 13311060SN/A } 13321060SN/A } 13331060SN/A 13341060SN/A return return_val; 13351060SN/A} 13361060SN/A 13371061SN/Atemplate <class Impl> 13381060SN/Avoid 13392326SN/AInstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) 13401060SN/A{ 13412326SN/A // Nothing really needs to be marked when an instruction becomes 13422326SN/A // the producer of a register's value, but for convenience a ptr 13432326SN/A // to the producing instruction will be placed in the head node of 13442326SN/A // the dependency links. 13451060SN/A int8_t total_dest_regs = new_inst->numDestRegs(); 13461060SN/A 13471060SN/A for (int dest_reg_idx = 0; 13481060SN/A dest_reg_idx < total_dest_regs; 13491060SN/A dest_reg_idx++) 13501060SN/A { 135112105Snathanael.premillieu@arm.com PhysRegIdPtr dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 13521061SN/A 135312105Snathanael.premillieu@arm.com // Some registers have fixed mapping, and there is no need to track 13541061SN/A // dependencies as these instructions must be executed at commit. 135512105Snathanael.premillieu@arm.com if (dest_reg->isFixedMapping()) { 13561061SN/A continue; 13571060SN/A } 13581060SN/A 135912106SRekai.GonzalezAlberquilla@arm.com if (!dependGraph.empty(dest_reg->flatIndex())) { 13602326SN/A dependGraph.dump(); 136112105Snathanael.premillieu@arm.com panic("Dependency graph %i (%s) (flat: %i) not empty!", 136212106SRekai.GonzalezAlberquilla@arm.com dest_reg->index(), dest_reg->className(), 136312106SRekai.GonzalezAlberquilla@arm.com dest_reg->flatIndex()); 13642064SN/A } 13651062SN/A 136612106SRekai.GonzalezAlberquilla@arm.com dependGraph.setInst(dest_reg->flatIndex(), new_inst); 13671062SN/A 13681060SN/A // Mark the scoreboard to say it's not yet ready. 136912106SRekai.GonzalezAlberquilla@arm.com regScoreboard[dest_reg->flatIndex()] = false; 13701060SN/A } 13711060SN/A} 13721060SN/A 13731061SN/Atemplate <class Impl> 13741060SN/Avoid 13751061SN/AInstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 13761060SN/A{ 13772326SN/A // If the instruction now has all of its source registers 13781060SN/A // available, then add it to the list of ready instructions. 13791060SN/A if (inst->readyToIssue()) { 13801061SN/A 13811060SN/A //Add the instruction to the proper ready list. 13822292SN/A if (inst->isMemRef()) { 13831061SN/A 13842292SN/A DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 13851061SN/A 13861062SN/A // Message to the mem dependence unit that this instruction has 13871062SN/A // its registers ready. 13882292SN/A memDepUnit[inst->threadNumber].regsReady(inst); 13891062SN/A 13902292SN/A return; 13912292SN/A } 13921062SN/A 13932292SN/A OpClass op_class = inst->opClass(); 13941061SN/A 13952292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 13967720Sgblack@eecs.umich.edu "the ready list, PC %s opclass:%i [sn:%lli].\n", 13977720Sgblack@eecs.umich.edu inst->pcState(), op_class, inst->seqNum); 13981061SN/A 13992292SN/A readyInsts[op_class].push(inst); 14001061SN/A 14012326SN/A // Will need to reorder the list if either a queue is not on the list, 14022326SN/A // or it has an older instruction than last time. 14032326SN/A if (!queueOnList[op_class]) { 14042326SN/A addToOrderList(op_class); 14052326SN/A } else if (readyInsts[op_class].top()->seqNum < 14062326SN/A (*readyIt[op_class]).oldestInst) { 14072326SN/A listOrder.erase(readyIt[op_class]); 14082326SN/A addToOrderList(op_class); 14091060SN/A } 14101060SN/A } 14111060SN/A} 14121060SN/A 14131061SN/Atemplate <class Impl> 14141061SN/Aint 14151061SN/AInstructionQueue<Impl>::countInsts() 14161061SN/A{ 14172698Sktlim@umich.edu#if 0 14182292SN/A //ksewell:This works but definitely could use a cleaner write 14192292SN/A //with a more intuitive way of counting. Right now it's 14202292SN/A //just brute force .... 14212698Sktlim@umich.edu // Change the #if if you want to use this method. 14221061SN/A int total_insts = 0; 14231061SN/A 14246221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 14256221Snate@binkert.org ListIt count_it = instList[tid].begin(); 14261681SN/A 14276221Snate@binkert.org while (count_it != instList[tid].end()) { 14282292SN/A if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 14292292SN/A if (!(*count_it)->isIssued()) { 14302292SN/A ++total_insts; 14312292SN/A } else if ((*count_it)->isMemRef() && 14322292SN/A !(*count_it)->memOpDone) { 14332292SN/A // Loads that have not been marked as executed still count 14342292SN/A // towards the total instructions. 14352292SN/A ++total_insts; 14362292SN/A } 14372292SN/A } 14382292SN/A 14392292SN/A ++count_it; 14401061SN/A } 14411061SN/A } 14421061SN/A 14431061SN/A return total_insts; 14442292SN/A#else 14452292SN/A return numEntries - freeEntries; 14462292SN/A#endif 14471681SN/A} 14481681SN/A 14491681SN/Atemplate <class Impl> 14501681SN/Avoid 14511061SN/AInstructionQueue<Impl>::dumpLists() 14521061SN/A{ 14532292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 14542292SN/A cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 14551061SN/A 14562292SN/A cprintf("\n"); 14572292SN/A } 14581061SN/A 14591061SN/A cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 14601061SN/A 14612292SN/A NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 14622292SN/A NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 14631061SN/A 14641061SN/A cprintf("Non speculative list: "); 14651061SN/A 14662292SN/A while (non_spec_it != non_spec_end_it) { 14677720Sgblack@eecs.umich.edu cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(), 14682292SN/A (*non_spec_it).second->seqNum); 14691061SN/A ++non_spec_it; 14701061SN/A } 14711061SN/A 14721061SN/A cprintf("\n"); 14731061SN/A 14742292SN/A ListOrderIt list_order_it = listOrder.begin(); 14752292SN/A ListOrderIt list_order_end_it = listOrder.end(); 14762292SN/A int i = 1; 14772292SN/A 14782292SN/A cprintf("List order: "); 14792292SN/A 14802292SN/A while (list_order_it != list_order_end_it) { 14812292SN/A cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 14822292SN/A (*list_order_it).oldestInst); 14832292SN/A 14842292SN/A ++list_order_it; 14852292SN/A ++i; 14862292SN/A } 14872292SN/A 14882292SN/A cprintf("\n"); 14891061SN/A} 14902292SN/A 14912292SN/A 14922292SN/Atemplate <class Impl> 14932292SN/Avoid 14942292SN/AInstructionQueue<Impl>::dumpInsts() 14952292SN/A{ 14966221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 14972292SN/A int num = 0; 14982292SN/A int valid_num = 0; 14996221Snate@binkert.org ListIt inst_list_it = instList[tid].begin(); 15002292SN/A 15016221Snate@binkert.org while (inst_list_it != instList[tid].end()) { 15026221Snate@binkert.org cprintf("Instruction:%i\n", num); 15032292SN/A if (!(*inst_list_it)->isSquashed()) { 15042292SN/A if (!(*inst_list_it)->isIssued()) { 15052292SN/A ++valid_num; 15062292SN/A cprintf("Count:%i\n", valid_num); 15072292SN/A } else if ((*inst_list_it)->isMemRef() && 15089046SAli.Saidi@ARM.com !(*inst_list_it)->memOpDone()) { 15092326SN/A // Loads that have not been marked as executed 15102326SN/A // still count towards the total instructions. 15112292SN/A ++valid_num; 15122292SN/A cprintf("Count:%i\n", valid_num); 15132292SN/A } 15142292SN/A } 15152292SN/A 15167720Sgblack@eecs.umich.edu cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 15172292SN/A "Issued:%i\nSquashed:%i\n", 15187720Sgblack@eecs.umich.edu (*inst_list_it)->pcState(), 15192292SN/A (*inst_list_it)->seqNum, 15202292SN/A (*inst_list_it)->threadNumber, 15212292SN/A (*inst_list_it)->isIssued(), 15222292SN/A (*inst_list_it)->isSquashed()); 15232292SN/A 15242292SN/A if ((*inst_list_it)->isMemRef()) { 15259046SAli.Saidi@ARM.com cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 15262292SN/A } 15272292SN/A 15282292SN/A cprintf("\n"); 15292292SN/A 15302292SN/A inst_list_it++; 15312292SN/A ++num; 15322292SN/A } 15332292SN/A } 15342348SN/A 15352348SN/A cprintf("Insts to Execute list:\n"); 15362348SN/A 15372348SN/A int num = 0; 15382348SN/A int valid_num = 0; 15392348SN/A ListIt inst_list_it = instsToExecute.begin(); 15402348SN/A 15412348SN/A while (inst_list_it != instsToExecute.end()) 15422348SN/A { 15432348SN/A cprintf("Instruction:%i\n", 15442348SN/A num); 15452348SN/A if (!(*inst_list_it)->isSquashed()) { 15462348SN/A if (!(*inst_list_it)->isIssued()) { 15472348SN/A ++valid_num; 15482348SN/A cprintf("Count:%i\n", valid_num); 15492348SN/A } else if ((*inst_list_it)->isMemRef() && 15509046SAli.Saidi@ARM.com !(*inst_list_it)->memOpDone()) { 15512348SN/A // Loads that have not been marked as executed 15522348SN/A // still count towards the total instructions. 15532348SN/A ++valid_num; 15542348SN/A cprintf("Count:%i\n", valid_num); 15552348SN/A } 15562348SN/A } 15572348SN/A 15587720Sgblack@eecs.umich.edu cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 15592348SN/A "Issued:%i\nSquashed:%i\n", 15607720Sgblack@eecs.umich.edu (*inst_list_it)->pcState(), 15612348SN/A (*inst_list_it)->seqNum, 15622348SN/A (*inst_list_it)->threadNumber, 15632348SN/A (*inst_list_it)->isIssued(), 15642348SN/A (*inst_list_it)->isSquashed()); 15652348SN/A 15662348SN/A if ((*inst_list_it)->isMemRef()) { 15679046SAli.Saidi@ARM.com cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 15682348SN/A } 15692348SN/A 15702348SN/A cprintf("\n"); 15712348SN/A 15722348SN/A inst_list_it++; 15732348SN/A ++num; 15742348SN/A } 15752292SN/A} 15769944Smatt.horsnell@ARM.com 15779944Smatt.horsnell@ARM.com#endif//__CPU_O3_INST_QUEUE_IMPL_HH__ 1578