inst_queue_impl.hh revision 10510
12068SN/A/* 22068SN/A * Copyright (c) 2011-2014 ARM Limited 32068SN/A * Copyright (c) 2013 Advanced Micro Devices, Inc. 42068SN/A * All rights reserved. 52068SN/A * 62068SN/A * The license below extends only to copyright in the software and shall 72068SN/A * not be construed as granting a license to any other intellectual 82068SN/A * property including but not limited to intellectual property relating 92068SN/A * to a hardware implementation of the functionality of the software 102068SN/A * licensed hereunder. You may use the software subject to the license 112068SN/A * terms below provided that you ensure that this notice is replicated 122068SN/A * unmodified and in its entirety in all distributions of the software, 132068SN/A * modified or unmodified, in source code or in binary form. 142068SN/A * 152068SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 162068SN/A * All rights reserved. 172068SN/A * 182068SN/A * Redistribution and use in source and binary forms, with or without 192068SN/A * modification, are permitted provided that the following conditions are 202068SN/A * met: redistributions of source code must retain the above copyright 212068SN/A * notice, this list of conditions and the following disclaimer; 222068SN/A * redistributions in binary form must reproduce the above copyright 232068SN/A * notice, this list of conditions and the following disclaimer in the 242068SN/A * documentation and/or other materials provided with the distribution; 252068SN/A * neither the name of the copyright holders nor the names of its 262068SN/A * contributors may be used to endorse or promote products derived from 272068SN/A * this software without specific prior written permission. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302665Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312068SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322649Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332649Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342649Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352649Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362649Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372068SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382068SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392068SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402068SN/A * 412068SN/A * Authors: Kevin Lim 422068SN/A * Korey Sewell 432068SN/A */ 442068SN/A 452068SN/A#ifndef __CPU_O3_INST_QUEUE_IMPL_HH__ 465736Snate@binkert.org#define __CPU_O3_INST_QUEUE_IMPL_HH__ 472068SN/A 482068SN/A#include <limits> 496181Sksewell@umich.edu#include <vector> 506181Sksewell@umich.edu 512068SN/A#include "cpu/o3/fu_pool.hh" 522068SN/A#include "cpu/o3/inst_queue.hh" 532068SN/A#include "debug/IQ.hh" 5412616Sgabeblack@google.com#include "enums/OpClass.hh" 5512616Sgabeblack@google.com#include "params/DerivO3CPU.hh" 562068SN/A#include "sim/core.hh" 572068SN/A 582068SN/A// clang complains about std::set being overloaded with Packet::set if 592068SN/A// we open up the entire namespace std 602068SN/Ausing std::list; 612068SN/A 622068SN/Atemplate <class Impl> 632068SN/AInstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 642068SN/A int fu_idx, InstructionQueue<Impl> *iq_ptr) 652068SN/A : Event(Stat_Event_Pri, AutoDelete), 662068SN/A inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 672068SN/A{ 682068SN/A} 696181Sksewell@umich.edu 706181Sksewell@umich.edutemplate <class Impl> 712068SN/Avoid 722068SN/AInstructionQueue<Impl>::FUCompletion::process() 732068SN/A{ 742068SN/A iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 752068SN/A inst = NULL; 762068SN/A} 772068SN/A 782068SN/A 792068SN/Atemplate <class Impl> 802068SN/Aconst char * 812068SN/AInstructionQueue<Impl>::FUCompletion::description() const 822068SN/A{ 832068SN/A return "Functional unit completion"; 842068SN/A} 852068SN/A 866181Sksewell@umich.edutemplate <class Impl> 876181Sksewell@umich.eduInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 882068SN/A DerivO3CPUParams *params) 892068SN/A : cpu(cpu_ptr), 902068SN/A iewStage(iew_ptr), 9112616Sgabeblack@google.com fuPool(params->fuPool), 9212616Sgabeblack@google.com numEntries(params->numIQEntries), 932068SN/A totalWidth(params->issueWidth), 942068SN/A commitToIEWDelay(params->commitToIEWDelay) 952068SN/A{ 962068SN/A assert(fuPool); 972068SN/A 982068SN/A numThreads = params->numThreads; 992068SN/A 1002068SN/A // Set the number of total physical registers 1012068SN/A numPhysRegs = params->numPhysIntRegs + params->numPhysFloatRegs + 1022068SN/A params->numPhysCCRegs; 1032068SN/A 1042068SN/A //Create an entry for each physical register within the 1052068SN/A //dependency graph. 1062068SN/A dependGraph.resize(numPhysRegs); 1072068SN/A 1082068SN/A // Resize the register scoreboard. 1092068SN/A regScoreboard.resize(numPhysRegs); 1102068SN/A 1112068SN/A //Initialize Mem Dependence Units 1122068SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1133953Sstever@eecs.umich.edu memDepUnit[tid].init(params, tid); 1142068SN/A memDepUnit[tid].setIQ(this); 1152068SN/A } 1162068SN/A 1172068SN/A resetState(); 1182068SN/A 1192068SN/A std::string policy = params->smtIQPolicy; 1202068SN/A 1212068SN/A //Convert string to lowercase 1222068SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1232068SN/A (int(*)(int)) tolower); 1242068SN/A 1252068SN/A //Figure out resource sharing policy 1262068SN/A if (policy == "dynamic") { 1272068SN/A iqPolicy = Dynamic; 1282068SN/A 1292068SN/A //Set Max Entries to Total ROB Capacity 1302227SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1312068SN/A maxEntries[tid] = numEntries; 13212616Sgabeblack@google.com } 13312616Sgabeblack@google.com 13412616Sgabeblack@google.com } else if (policy == "partitioned") { 13512616Sgabeblack@google.com iqPolicy = Partitioned; 1362068SN/A 1372068SN/A //@todo:make work if part_amt doesnt divide evenly. 1382068SN/A int part_amt = numEntries / numThreads; 1396181Sksewell@umich.edu 14010184SCurtis.Dunham@arm.com //Divide ROB up evenly 1416181Sksewell@umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 1422068SN/A maxEntries[tid] = part_amt; 1433953Sstever@eecs.umich.edu } 1442068SN/A 1453953Sstever@eecs.umich.edu DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 1462068SN/A "%i entries per thread.\n",part_amt); 1472068SN/A } else if (policy == "threshold") { 1482069SN/A iqPolicy = Threshold; 14912234Sgabeblack@google.com 1502068SN/A double threshold = (double)params->smtIQThreshold / 100; 1512068SN/A 1522068SN/A int thresholdIQ = (int)((double)threshold * numEntries); 1532132SN/A 1542068SN/A //Divide up by threshold amount 1552068SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1562068SN/A maxEntries[tid] = thresholdIQ; 1572069SN/A } 1582068SN/A 1592068SN/A DPRINTF(IQ, "IQ sharing policy set to Threshold:" 1602090SN/A "%i entries per thread.\n",thresholdIQ); 1618442Sgblack@eecs.umich.edu } else { 1622068SN/A assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 1632068SN/A "Partitioned, Threshold}"); 1642068SN/A } 1652090SN/A} 1662069SN/A 1672069SN/Atemplate <class Impl> 1682069SN/AInstructionQueue<Impl>::~InstructionQueue() 1692069SN/A{ 1702069SN/A dependGraph.reset(); 1712069SN/A#ifdef DEBUG 1722069SN/A cprintf("Nodes traversed: %i, removed: %i\n", 1732069SN/A dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1742095SN/A#endif 17512234Sgabeblack@google.com} 1762095SN/A 1772095SN/Atemplate <class Impl> 1782095SN/Astd::string 1792132SN/AInstructionQueue<Impl>::name() const 1802095SN/A{ 1812095SN/A return cpu->name() + ".iq"; 1822095SN/A} 1832095SN/A 1842095SN/Atemplate <class Impl> 1852095SN/Avoid 1862098SN/AInstructionQueue<Impl>::regStats() 18711303Ssteve.reinhardt@amd.com{ 1882095SN/A using namespace Stats; 1892095SN/A iqInstsAdded 1902095SN/A .name(name() + ".iqInstsAdded") 1912095SN/A .desc("Number of instructions added to the IQ (excludes non-spec)") 1922095SN/A .prereq(iqInstsAdded); 1932095SN/A 1942095SN/A iqNonSpecInstsAdded 1952095SN/A .name(name() + ".iqNonSpecInstsAdded") 19612234Sgabeblack@google.com .desc("Number of non-speculative instructions added to the IQ") 1972095SN/A .prereq(iqNonSpecInstsAdded); 1982095SN/A 1992132SN/A iqInstsIssued 2002095SN/A .name(name() + ".iqInstsIssued") 2012095SN/A .desc("Number of instructions issued") 2022506SN/A .prereq(iqInstsIssued); 2032095SN/A 2048442Sgblack@eecs.umich.edu iqIntInstsIssued 2052095SN/A .name(name() + ".iqIntInstsIssued") 2062098SN/A .desc("Number of integer instructions issued") 2072095SN/A .prereq(iqIntInstsIssued); 2082095SN/A 2092095SN/A iqFloatInstsIssued 2102098SN/A .name(name() + ".iqFloatInstsIssued") 2112095SN/A .desc("Number of float instructions issued") 2122095SN/A .prereq(iqFloatInstsIssued); 2132095SN/A 2142095SN/A iqBranchInstsIssued 2152095SN/A .name(name() + ".iqBranchInstsIssued") 2162095SN/A .desc("Number of branch instructions issued") 2172095SN/A .prereq(iqBranchInstsIssued); 2182095SN/A 2192069SN/A iqMemInstsIssued 22012234Sgabeblack@google.com .name(name() + ".iqMemInstsIssued") 2212069SN/A .desc("Number of memory instructions issued") 2222069SN/A .prereq(iqMemInstsIssued); 2232069SN/A 2242132SN/A iqMiscInstsIssued 2254027Sstever@eecs.umich.edu .name(name() + ".iqMiscInstsIssued") 2264027Sstever@eecs.umich.edu .desc("Number of miscellaneous instructions issued") 2274027Sstever@eecs.umich.edu .prereq(iqMiscInstsIssued); 2284027Sstever@eecs.umich.edu 2294027Sstever@eecs.umich.edu iqSquashedInstsIssued 2304027Sstever@eecs.umich.edu .name(name() + ".iqSquashedInstsIssued") 2314027Sstever@eecs.umich.edu .desc("Number of squashed instructions issued") 2324027Sstever@eecs.umich.edu .prereq(iqSquashedInstsIssued); 2334027Sstever@eecs.umich.edu 2344027Sstever@eecs.umich.edu iqSquashedInstsExamined 2354027Sstever@eecs.umich.edu .name(name() + ".iqSquashedInstsExamined") 2368442Sgblack@eecs.umich.edu .desc("Number of squashed instructions iterated over during squash;" 2378442Sgblack@eecs.umich.edu " mainly for profiling") 2384027Sstever@eecs.umich.edu .prereq(iqSquashedInstsExamined); 2394027Sstever@eecs.umich.edu 2404027Sstever@eecs.umich.edu iqSquashedOperandsExamined 2414027Sstever@eecs.umich.edu .name(name() + ".iqSquashedOperandsExamined") 2424027Sstever@eecs.umich.edu .desc("Number of squashed operands that are examined and possibly " 2434027Sstever@eecs.umich.edu "removed from graph") 2444027Sstever@eecs.umich.edu .prereq(iqSquashedOperandsExamined); 2454027Sstever@eecs.umich.edu 2464027Sstever@eecs.umich.edu iqSquashedNonSpecRemoved 2474027Sstever@eecs.umich.edu .name(name() + ".iqSquashedNonSpecRemoved") 2484027Sstever@eecs.umich.edu .desc("Number of squashed non-spec instructions that were removed") 2494027Sstever@eecs.umich.edu .prereq(iqSquashedNonSpecRemoved); 2504027Sstever@eecs.umich.edu/* 2514027Sstever@eecs.umich.edu queueResDist 2524027Sstever@eecs.umich.edu .init(Num_OpClasses, 0, 99, 2) 25312234Sgabeblack@google.com .name(name() + ".IQ:residence:") 2544027Sstever@eecs.umich.edu .desc("cycles from dispatch to issue") 2554027Sstever@eecs.umich.edu .flags(total | pdf | cdf ) 2564027Sstever@eecs.umich.edu ; 2574027Sstever@eecs.umich.edu for (int i = 0; i < Num_OpClasses; ++i) { 2582069SN/A queueResDist.subname(i, opClassStrings[i]); 2592069SN/A } 2602069SN/A*/ 2612069SN/A numIssuedDist 2622069SN/A .init(0,totalWidth,1) 2632069SN/A .name(name() + ".issued_per_cycle") 2642069SN/A .desc("Number of insts issued each cycle") 2652090SN/A .flags(pdf) 2662069SN/A ; 2672069SN/A/* 2682069SN/A dist_unissued 2692090SN/A .init(Num_OpClasses+2) 2708442Sgblack@eecs.umich.edu .name(name() + ".unissued_cause") 2718442Sgblack@eecs.umich.edu .desc("Reason ready instruction not issued") 2722069SN/A .flags(pdf | dist) 2732069SN/A ; 2742090SN/A for (int i=0; i < (Num_OpClasses + 2); ++i) { 2752069SN/A dist_unissued.subname(i, unissued_names[i]); 2762069SN/A } 2772069SN/A*/ 2782090SN/A statIssuedInstType 2792069SN/A .init(numThreads,Enums::Num_OpClass) 2802069SN/A .name(name() + ".FU_type") 2812069SN/A .desc("Type of FU issued") 2822069SN/A .flags(total | pdf | dist) 2832069SN/A ; 2842069SN/A statIssuedInstType.ysubnames(Enums::OpClassStrings); 2852069SN/A 2862095SN/A // 28712234Sgabeblack@google.com // How long did instructions for a particular FU type wait prior to issue 2882095SN/A // 2892095SN/A/* 2902095SN/A issueDelayDist 2912132SN/A .init(Num_OpClasses,0,99,2) 2922095SN/A .name(name() + ".") 2932095SN/A .desc("cycles from operands ready to issue") 2942506SN/A .flags(pdf | cdf) 2952095SN/A ; 2962095SN/A 2972095SN/A for (int i=0; i<Num_OpClasses; ++i) { 2982098SN/A std::stringstream subname; 2992095SN/A subname << opClassStrings[i] << "_delay"; 3002095SN/A issueDelayDist.subname(i, subname.str()); 3012095SN/A } 3022098SN/A*/ 3038442Sgblack@eecs.umich.edu issueRate 3048442Sgblack@eecs.umich.edu .name(name() + ".rate") 3052095SN/A .desc("Inst issue rate") 3062095SN/A .flags(total) 3072095SN/A ; 3082095SN/A issueRate = iqInstsIssued / cpu->numCycles; 3092095SN/A 3102095SN/A statFuBusy 3112095SN/A .init(Num_OpClasses) 3122095SN/A .name(name() + ".fu_full") 31312234Sgabeblack@google.com .desc("attempts to use FU when none available") 3142095SN/A .flags(pdf | dist) 3152095SN/A ; 3167712Sgblack@eecs.umich.edu for (int i=0; i < Num_OpClasses; ++i) { 3172623SN/A statFuBusy.subname(i, Enums::OpClassStrings[i]); 3182623SN/A } 3192623SN/A 3202623SN/A fuBusy 3212623SN/A .init(numThreads) 32212234Sgabeblack@google.com .name(name() + ".fu_busy_cnt") 3232623SN/A .desc("FU busy when requested") 3242623SN/A .flags(total) 3252623SN/A ; 3262623SN/A 3272623SN/A fuBusyRate 3282623SN/A .name(name() + ".fu_busy_rate") 3292623SN/A .desc("FU busy rate (busy events/executed inst)") 3304040Ssaidi@eecs.umich.edu .flags(total) 3312095SN/A ; 3322098SN/A fuBusyRate = fuBusy / iqInstsIssued; 3332095SN/A 3342095SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 3352095SN/A // Tell mem dependence unit to reg stats as well. 3362098SN/A memDepUnit[tid].regStats(); 3372095SN/A } 3382095SN/A 3392095SN/A intInstQueueReads 3402095SN/A .name(name() + ".int_inst_queue_reads") 3412095SN/A .desc("Number of integer instruction queue reads") 3422095SN/A .flags(total); 3432095SN/A 3442069SN/A intInstQueueWrites 3452069SN/A .name(name() + ".int_inst_queue_writes") 34612234Sgabeblack@google.com .desc("Number of integer instruction queue writes") 3472068SN/A .flags(total); 3482068SN/A 3498607Sgblack@eecs.umich.edu intInstQueueWakeupAccesses 3502132SN/A .name(name() + ".int_inst_queue_wakeup_accesses") 3512068SN/A .desc("Number of integer instruction queue wakeup accesses") 3522068SN/A .flags(total); 3532068SN/A 3542069SN/A fpInstQueueReads 3552068SN/A .name(name() + ".fp_inst_queue_reads") 3562068SN/A .desc("Number of floating instruction queue reads") 3578406Sksewell@umich.edu .flags(total); 3582090SN/A 3592069SN/A fpInstQueueWrites 3602068SN/A .name(name() + ".fp_inst_queue_writes") 3612068SN/A .desc("Number of floating instruction queue writes") 3622090SN/A .flags(total); 3632068SN/A 3642068SN/A fpInstQueueWakeupQccesses 3652068SN/A .name(name() + ".fp_inst_queue_wakeup_accesses") 3667725SAli.Saidi@ARM.com .desc("Number of floating instruction queue wakeup accesses") 3677725SAli.Saidi@ARM.com .flags(total); 3682095SN/A 36912234Sgabeblack@google.com intAluAccesses 3702095SN/A .name(name() + ".int_alu_accesses") 3712095SN/A .desc("Number of integer alu accesses") 3726185Sksewell@umich.edu .flags(total); 3736185Sksewell@umich.edu 3742098SN/A fpAluAccesses 3752095SN/A .name(name() + ".fp_alu_accesses") 3762095SN/A .desc("Number of floating point alu accesses") 3772095SN/A .flags(total); 3782095SN/A 3792095SN/A} 38012234Sgabeblack@google.com 3812095SN/Atemplate <class Impl> 3822095SN/Avoid 3836185Sksewell@umich.eduInstructionQueue<Impl>::resetState() 3846185Sksewell@umich.edu{ 3852110SN/A //Initialize thread IQ counts 3862098SN/A for (ThreadID tid = 0; tid <numThreads; tid++) { 3872095SN/A count[tid] = 0; 3882095SN/A instList[tid].clear(); 3892095SN/A } 3906179Sksewell@umich.edu 3912068SN/A // Initialize the number of free IQ entries. 3922068SN/A freeEntries = numEntries; 3932068SN/A 3942068SN/A // Note that in actuality, the registers corresponding to the logical 3952068SN/A // registers start off as ready. However this doesn't matter for the 3962068SN/A // IQ as the instruction should have been correctly told if those 3972068SN/A // registers are ready in rename. Thus it can all be initialized as 3982068SN/A // unready. 3992068SN/A for (int i = 0; i < numPhysRegs; ++i) { 4002068SN/A regScoreboard[i] = false; 4012068SN/A } 4022068SN/A 4032068SN/A for (ThreadID tid = 0; tid < numThreads; ++tid) { 4042068SN/A squashedSeqNum[tid] = 0; 4052068SN/A } 4062068SN/A 4072068SN/A for (int i = 0; i < Num_OpClasses; ++i) { 4082068SN/A while (!readyInsts[i].empty()) 4092068SN/A readyInsts[i].pop(); 4102068SN/A queueOnList[i] = false; 4112068SN/A readyIt[i] = listOrder.end(); 4122068SN/A } 4132068SN/A nonSpecInsts.clear(); 4142068SN/A listOrder.clear(); 4152068SN/A deferredMemInsts.clear(); 4162068SN/A blockedMemInsts.clear(); 4172068SN/A retryMemInsts.clear(); 4182075SN/A} 4192075SN/A 4202069SN/Atemplate <class Impl> 4212075SN/Avoid 4222075SN/AInstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 4232075SN/A{ 4242068SN/A activeThreads = at_ptr; 4253953Sstever@eecs.umich.edu} 4263953Sstever@eecs.umich.edu 4273953Sstever@eecs.umich.edutemplate <class Impl> 4282068SN/Avoid 4292068SN/AInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 4305736Snate@binkert.org{ 4315745Snate@binkert.org issueToExecuteQueue = i2e_ptr; 4322068SN/A} 4332068SN/A 4342069SN/Atemplate <class Impl> 4352623SN/Avoid 4364027Sstever@eecs.umich.eduInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 4374027Sstever@eecs.umich.edu{ 4382623SN/A timeBuffer = tb_ptr; 4392623SN/A 4402069SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 4412095SN/A} 4422095SN/A 4432069SN/Atemplate <class Impl> 4442068SN/Abool 4453953Sstever@eecs.umich.eduInstructionQueue<Impl>::isDrained() const 4466181Sksewell@umich.edu{ 4472068SN/A bool drained = dependGraph.empty() && instsToExecute.empty(); 4486181Sksewell@umich.edu for (ThreadID tid = 0; tid < numThreads; ++tid) 4493953Sstever@eecs.umich.edu drained = drained && memDepUnit[tid].isDrained(); 4506192Sksewell@umich.edu 4512068SN/A return drained; 4522068SN/A} 4532075SN/A 4542075SN/Atemplate <class Impl> 4552068SN/Avoid 4562075SN/AInstructionQueue<Impl>::drainSanityCheck() const 4572069SN/A{ 4582069SN/A assert(dependGraph.empty()); 4592068SN/A assert(instsToExecute.empty()); 4602068SN/A for (ThreadID tid = 0; tid < numThreads; ++tid) 4612068SN/A memDepUnit[tid].drainSanityCheck(); 4622068SN/A} 4632075SN/A 4642075SN/Atemplate <class Impl> 4652068SN/Avoid 4662068SN/AInstructionQueue<Impl>::takeOverFrom() 4672075SN/A{ 4682069SN/A resetState(); 4692069SN/A} 4702068SN/A 4712068SN/Atemplate <class Impl> 4722068SN/Aint 4732075SN/AInstructionQueue<Impl>::entryAmount(ThreadID num_threads) 4742075SN/A{ 4752075SN/A if (iqPolicy == Partitioned) { 4762075SN/A return numEntries / num_threads; 4772075SN/A } else { 4786739Sgblack@eecs.umich.edu return 0; 4797725SAli.Saidi@ARM.com } 4802068SN/A} 4812068SN/A 4827725SAli.Saidi@ARM.com 4832075SN/Atemplate <class Impl> 4842068SN/Avoid 4852068SN/AInstructionQueue<Impl>::resetEntries() 4862068SN/A{ 4872068SN/A if (iqPolicy != Dynamic || numThreads > 1) { 4882068SN/A int active_threads = activeThreads->size(); 4892068SN/A 4902068SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 4912075SN/A list<ThreadID>::iterator end = activeThreads->end(); 4922075SN/A 4932068SN/A while (threads != end) { 4942075SN/A ThreadID tid = *threads++; 4952069SN/A 4962068SN/A if (iqPolicy == Partitioned) { 4972068SN/A maxEntries[tid] = numEntries / active_threads; 4982068SN/A } else if(iqPolicy == Threshold && active_threads == 1) { 4992075SN/A maxEntries[tid] = numEntries; 5002075SN/A } 5012075SN/A } 5022068SN/A } 5032075SN/A} 5042623SN/A 5052068SN/Atemplate <class Impl> 5062068SN/Aunsigned 5072068SN/AInstructionQueue<Impl>::numFreeEntries() 5082068SN/A{ 5092075SN/A return freeEntries; 5102075SN/A} 5112068SN/A 5122075SN/Atemplate <class Impl> 5132069SN/Aunsigned 5142068SN/AInstructionQueue<Impl>::numFreeEntries(ThreadID tid) 5152068SN/A{ 5162068SN/A return maxEntries[tid] - count[tid]; 517} 518 519// Might want to do something more complex if it knows how many instructions 520// will be issued this cycle. 521template <class Impl> 522bool 523InstructionQueue<Impl>::isFull() 524{ 525 if (freeEntries == 0) { 526 return(true); 527 } else { 528 return(false); 529 } 530} 531 532template <class Impl> 533bool 534InstructionQueue<Impl>::isFull(ThreadID tid) 535{ 536 if (numFreeEntries(tid) == 0) { 537 return(true); 538 } else { 539 return(false); 540 } 541} 542 543template <class Impl> 544bool 545InstructionQueue<Impl>::hasReadyInsts() 546{ 547 if (!listOrder.empty()) { 548 return true; 549 } 550 551 for (int i = 0; i < Num_OpClasses; ++i) { 552 if (!readyInsts[i].empty()) { 553 return true; 554 } 555 } 556 557 return false; 558} 559 560template <class Impl> 561void 562InstructionQueue<Impl>::insert(DynInstPtr &new_inst) 563{ 564 new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 565 // Make sure the instruction is valid 566 assert(new_inst); 567 568 DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n", 569 new_inst->seqNum, new_inst->pcState()); 570 571 assert(freeEntries != 0); 572 573 instList[new_inst->threadNumber].push_back(new_inst); 574 575 --freeEntries; 576 577 new_inst->setInIQ(); 578 579 // Look through its source registers (physical regs), and mark any 580 // dependencies. 581 addToDependents(new_inst); 582 583 // Have this instruction set itself as the producer of its destination 584 // register(s). 585 addToProducers(new_inst); 586 587 if (new_inst->isMemRef()) { 588 memDepUnit[new_inst->threadNumber].insert(new_inst); 589 } else { 590 addIfReady(new_inst); 591 } 592 593 ++iqInstsAdded; 594 595 count[new_inst->threadNumber]++; 596 597 assert(freeEntries == (numEntries - countInsts())); 598} 599 600template <class Impl> 601void 602InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) 603{ 604 // @todo: Clean up this code; can do it by setting inst as unable 605 // to issue, then calling normal insert on the inst. 606 new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 607 608 assert(new_inst); 609 610 nonSpecInsts[new_inst->seqNum] = new_inst; 611 612 DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s " 613 "to the IQ.\n", 614 new_inst->seqNum, new_inst->pcState()); 615 616 assert(freeEntries != 0); 617 618 instList[new_inst->threadNumber].push_back(new_inst); 619 620 --freeEntries; 621 622 new_inst->setInIQ(); 623 624 // Have this instruction set itself as the producer of its destination 625 // register(s). 626 addToProducers(new_inst); 627 628 // If it's a memory instruction, add it to the memory dependency 629 // unit. 630 if (new_inst->isMemRef()) { 631 memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 632 } 633 634 ++iqNonSpecInstsAdded; 635 636 count[new_inst->threadNumber]++; 637 638 assert(freeEntries == (numEntries - countInsts())); 639} 640 641template <class Impl> 642void 643InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) 644{ 645 memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 646 647 insertNonSpec(barr_inst); 648} 649 650template <class Impl> 651typename Impl::DynInstPtr 652InstructionQueue<Impl>::getInstToExecute() 653{ 654 assert(!instsToExecute.empty()); 655 DynInstPtr inst = instsToExecute.front(); 656 instsToExecute.pop_front(); 657 if (inst->isFloating()){ 658 fpInstQueueReads++; 659 } else { 660 intInstQueueReads++; 661 } 662 return inst; 663} 664 665template <class Impl> 666void 667InstructionQueue<Impl>::addToOrderList(OpClass op_class) 668{ 669 assert(!readyInsts[op_class].empty()); 670 671 ListOrderEntry queue_entry; 672 673 queue_entry.queueType = op_class; 674 675 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 676 677 ListOrderIt list_it = listOrder.begin(); 678 ListOrderIt list_end_it = listOrder.end(); 679 680 while (list_it != list_end_it) { 681 if ((*list_it).oldestInst > queue_entry.oldestInst) { 682 break; 683 } 684 685 list_it++; 686 } 687 688 readyIt[op_class] = listOrder.insert(list_it, queue_entry); 689 queueOnList[op_class] = true; 690} 691 692template <class Impl> 693void 694InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 695{ 696 // Get iterator of next item on the list 697 // Delete the original iterator 698 // Determine if the next item is either the end of the list or younger 699 // than the new instruction. If so, then add in a new iterator right here. 700 // If not, then move along. 701 ListOrderEntry queue_entry; 702 OpClass op_class = (*list_order_it).queueType; 703 ListOrderIt next_it = list_order_it; 704 705 ++next_it; 706 707 queue_entry.queueType = op_class; 708 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 709 710 while (next_it != listOrder.end() && 711 (*next_it).oldestInst < queue_entry.oldestInst) { 712 ++next_it; 713 } 714 715 readyIt[op_class] = listOrder.insert(next_it, queue_entry); 716} 717 718template <class Impl> 719void 720InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 721{ 722 DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 723 assert(!cpu->switchedOut()); 724 // The CPU could have been sleeping until this op completed (*extremely* 725 // long latency op). Wake it if it was. This may be overkill. 726 iewStage->wakeCPU(); 727 728 if (fu_idx > -1) 729 fuPool->freeUnitNextCycle(fu_idx); 730 731 // @todo: Ensure that these FU Completions happen at the beginning 732 // of a cycle, otherwise they could add too many instructions to 733 // the queue. 734 issueToExecuteQueue->access(-1)->size++; 735 instsToExecute.push_back(inst); 736} 737 738// @todo: Figure out a better way to remove the squashed items from the 739// lists. Checking the top item of each list to see if it's squashed 740// wastes time and forces jumps. 741template <class Impl> 742void 743InstructionQueue<Impl>::scheduleReadyInsts() 744{ 745 DPRINTF(IQ, "Attempting to schedule ready instructions from " 746 "the IQ.\n"); 747 748 IssueStruct *i2e_info = issueToExecuteQueue->access(0); 749 750 DynInstPtr mem_inst; 751 while (mem_inst = getDeferredMemInstToExecute()) { 752 addReadyMemInst(mem_inst); 753 } 754 755 // See if any cache blocked instructions are able to be executed 756 while (mem_inst = getBlockedMemInstToExecute()) { 757 addReadyMemInst(mem_inst); 758 } 759 760 // Have iterator to head of the list 761 // While I haven't exceeded bandwidth or reached the end of the list, 762 // Try to get a FU that can do what this op needs. 763 // If successful, change the oldestInst to the new top of the list, put 764 // the queue in the proper place in the list. 765 // Increment the iterator. 766 // This will avoid trying to schedule a certain op class if there are no 767 // FUs that handle it. 768 int total_issued = 0; 769 ListOrderIt order_it = listOrder.begin(); 770 ListOrderIt order_end_it = listOrder.end(); 771 772 while (total_issued < totalWidth && order_it != order_end_it) { 773 OpClass op_class = (*order_it).queueType; 774 775 assert(!readyInsts[op_class].empty()); 776 777 DynInstPtr issuing_inst = readyInsts[op_class].top(); 778 779 issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++; 780 781 assert(issuing_inst->seqNum == (*order_it).oldestInst); 782 783 if (issuing_inst->isSquashed()) { 784 readyInsts[op_class].pop(); 785 786 if (!readyInsts[op_class].empty()) { 787 moveToYoungerInst(order_it); 788 } else { 789 readyIt[op_class] = listOrder.end(); 790 queueOnList[op_class] = false; 791 } 792 793 listOrder.erase(order_it++); 794 795 ++iqSquashedInstsIssued; 796 797 continue; 798 } 799 800 int idx = -2; 801 Cycles op_latency = Cycles(1); 802 ThreadID tid = issuing_inst->threadNumber; 803 804 if (op_class != No_OpClass) { 805 idx = fuPool->getUnit(op_class); 806 issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++; 807 if (idx > -1) { 808 op_latency = fuPool->getOpLatency(op_class); 809 } 810 } 811 812 // If we have an instruction that doesn't require a FU, or a 813 // valid FU, then schedule for execution. 814 if (idx == -2 || idx != -1) { 815 if (op_latency == Cycles(1)) { 816 i2e_info->size++; 817 instsToExecute.push_back(issuing_inst); 818 819 // Add the FU onto the list of FU's to be freed next 820 // cycle if we used one. 821 if (idx >= 0) 822 fuPool->freeUnitNextCycle(idx); 823 } else { 824 Cycles issue_latency = fuPool->getIssueLatency(op_class); 825 // Generate completion event for the FU 826 FUCompletion *execution = new FUCompletion(issuing_inst, 827 idx, this); 828 829 cpu->schedule(execution, 830 cpu->clockEdge(Cycles(op_latency - 1))); 831 832 // @todo: Enforce that issue_latency == 1 or op_latency 833 if (issue_latency > Cycles(1)) { 834 // If FU isn't pipelined, then it must be freed 835 // upon the execution completing. 836 execution->setFreeFU(); 837 } else { 838 // Add the FU onto the list of FU's to be freed next cycle. 839 fuPool->freeUnitNextCycle(idx); 840 } 841 } 842 843 DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 844 "[sn:%lli]\n", 845 tid, issuing_inst->pcState(), 846 issuing_inst->seqNum); 847 848 readyInsts[op_class].pop(); 849 850 if (!readyInsts[op_class].empty()) { 851 moveToYoungerInst(order_it); 852 } else { 853 readyIt[op_class] = listOrder.end(); 854 queueOnList[op_class] = false; 855 } 856 857 issuing_inst->setIssued(); 858 ++total_issued; 859 860#if TRACING_ON 861 issuing_inst->issueTick = curTick() - issuing_inst->fetchTick; 862#endif 863 864 if (!issuing_inst->isMemRef()) { 865 // Memory instructions can not be freed from the IQ until they 866 // complete. 867 ++freeEntries; 868 count[tid]--; 869 issuing_inst->clearInIQ(); 870 } else { 871 memDepUnit[tid].issue(issuing_inst); 872 } 873 874 listOrder.erase(order_it++); 875 statIssuedInstType[tid][op_class]++; 876 } else { 877 statFuBusy[op_class]++; 878 fuBusy[tid]++; 879 ++order_it; 880 } 881 } 882 883 numIssuedDist.sample(total_issued); 884 iqInstsIssued+= total_issued; 885 886 // If we issued any instructions, tell the CPU we had activity. 887 // @todo If the way deferred memory instructions are handeled due to 888 // translation changes then the deferredMemInsts condition should be removed 889 // from the code below. 890 if (total_issued || !retryMemInsts.empty() || !deferredMemInsts.empty()) { 891 cpu->activityThisCycle(); 892 } else { 893 DPRINTF(IQ, "Not able to schedule any instructions.\n"); 894 } 895} 896 897template <class Impl> 898void 899InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 900{ 901 DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 902 "to execute.\n", inst); 903 904 NonSpecMapIt inst_it = nonSpecInsts.find(inst); 905 906 assert(inst_it != nonSpecInsts.end()); 907 908 ThreadID tid = (*inst_it).second->threadNumber; 909 910 (*inst_it).second->setAtCommit(); 911 912 (*inst_it).second->setCanIssue(); 913 914 if (!(*inst_it).second->isMemRef()) { 915 addIfReady((*inst_it).second); 916 } else { 917 memDepUnit[tid].nonSpecInstReady((*inst_it).second); 918 } 919 920 (*inst_it).second = NULL; 921 922 nonSpecInsts.erase(inst_it); 923} 924 925template <class Impl> 926void 927InstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 928{ 929 DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 930 tid,inst); 931 932 ListIt iq_it = instList[tid].begin(); 933 934 while (iq_it != instList[tid].end() && 935 (*iq_it)->seqNum <= inst) { 936 ++iq_it; 937 instList[tid].pop_front(); 938 } 939 940 assert(freeEntries == (numEntries - countInsts())); 941} 942 943template <class Impl> 944int 945InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 946{ 947 int dependents = 0; 948 949 // The instruction queue here takes care of both floating and int ops 950 if (completed_inst->isFloating()) { 951 fpInstQueueWakeupQccesses++; 952 } else { 953 intInstQueueWakeupAccesses++; 954 } 955 956 DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 957 958 assert(!completed_inst->isSquashed()); 959 960 // Tell the memory dependence unit to wake any dependents on this 961 // instruction if it is a memory instruction. Also complete the memory 962 // instruction at this point since we know it executed without issues. 963 // @todo: Might want to rename "completeMemInst" to something that 964 // indicates that it won't need to be replayed, and call this 965 // earlier. Might not be a big deal. 966 if (completed_inst->isMemRef()) { 967 memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 968 completeMemInst(completed_inst); 969 } else if (completed_inst->isMemBarrier() || 970 completed_inst->isWriteBarrier()) { 971 memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 972 } 973 974 for (int dest_reg_idx = 0; 975 dest_reg_idx < completed_inst->numDestRegs(); 976 dest_reg_idx++) 977 { 978 PhysRegIndex dest_reg = 979 completed_inst->renamedDestRegIdx(dest_reg_idx); 980 981 // Special case of uniq or control registers. They are not 982 // handled by the IQ and thus have no dependency graph entry. 983 // @todo Figure out a cleaner way to handle this. 984 if (dest_reg >= numPhysRegs) { 985 DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg, 986 numPhysRegs); 987 continue; 988 } 989 990 DPRINTF(IQ, "Waking any dependents on register %i.\n", 991 (int) dest_reg); 992 993 //Go through the dependency chain, marking the registers as 994 //ready within the waiting instructions. 995 DynInstPtr dep_inst = dependGraph.pop(dest_reg); 996 997 while (dep_inst) { 998 DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] " 999 "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 1000 1001 // Might want to give more information to the instruction 1002 // so that it knows which of its source registers is 1003 // ready. However that would mean that the dependency 1004 // graph entries would need to hold the src_reg_idx. 1005 dep_inst->markSrcRegReady(); 1006 1007 addIfReady(dep_inst); 1008 1009 dep_inst = dependGraph.pop(dest_reg); 1010 1011 ++dependents; 1012 } 1013 1014 // Reset the head node now that all of its dependents have 1015 // been woken up. 1016 assert(dependGraph.empty(dest_reg)); 1017 dependGraph.clearInst(dest_reg); 1018 1019 // Mark the scoreboard as having that register ready. 1020 regScoreboard[dest_reg] = true; 1021 } 1022 return dependents; 1023} 1024 1025template <class Impl> 1026void 1027InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 1028{ 1029 OpClass op_class = ready_inst->opClass(); 1030 1031 readyInsts[op_class].push(ready_inst); 1032 1033 // Will need to reorder the list if either a queue is not on the list, 1034 // or it has an older instruction than last time. 1035 if (!queueOnList[op_class]) { 1036 addToOrderList(op_class); 1037 } else if (readyInsts[op_class].top()->seqNum < 1038 (*readyIt[op_class]).oldestInst) { 1039 listOrder.erase(readyIt[op_class]); 1040 addToOrderList(op_class); 1041 } 1042 1043 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 1044 "the ready list, PC %s opclass:%i [sn:%lli].\n", 1045 ready_inst->pcState(), op_class, ready_inst->seqNum); 1046} 1047 1048template <class Impl> 1049void 1050InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 1051{ 1052 DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 1053 1054 // Reset DTB translation state 1055 resched_inst->translationStarted(false); 1056 resched_inst->translationCompleted(false); 1057 1058 resched_inst->clearCanIssue(); 1059 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 1060} 1061 1062template <class Impl> 1063void 1064InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 1065{ 1066 memDepUnit[replay_inst->threadNumber].replay(); 1067} 1068 1069template <class Impl> 1070void 1071InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 1072{ 1073 ThreadID tid = completed_inst->threadNumber; 1074 1075 DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n", 1076 completed_inst->pcState(), completed_inst->seqNum); 1077 1078 ++freeEntries; 1079 1080 completed_inst->memOpDone(true); 1081 1082 memDepUnit[tid].completed(completed_inst); 1083 count[tid]--; 1084} 1085 1086template <class Impl> 1087void 1088InstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst) 1089{ 1090 deferredMemInsts.push_back(deferred_inst); 1091} 1092 1093template <class Impl> 1094void 1095InstructionQueue<Impl>::blockMemInst(DynInstPtr &blocked_inst) 1096{ 1097 blocked_inst->translationStarted(false); 1098 blocked_inst->translationCompleted(false); 1099 1100 blocked_inst->clearIssued(); 1101 blocked_inst->clearCanIssue(); 1102 blockedMemInsts.push_back(blocked_inst); 1103} 1104 1105template <class Impl> 1106void 1107InstructionQueue<Impl>::cacheUnblocked() 1108{ 1109 retryMemInsts.splice(retryMemInsts.end(), blockedMemInsts); 1110 // Get the CPU ticking again 1111 cpu->wakeCPU(); 1112} 1113 1114template <class Impl> 1115typename Impl::DynInstPtr 1116InstructionQueue<Impl>::getDeferredMemInstToExecute() 1117{ 1118 for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); 1119 ++it) { 1120 if ((*it)->translationCompleted() || (*it)->isSquashed()) { 1121 DynInstPtr mem_inst = *it; 1122 deferredMemInsts.erase(it); 1123 return mem_inst; 1124 } 1125 } 1126 return nullptr; 1127} 1128 1129template <class Impl> 1130typename Impl::DynInstPtr 1131InstructionQueue<Impl>::getBlockedMemInstToExecute() 1132{ 1133 if (retryMemInsts.empty()) { 1134 return nullptr; 1135 } else { 1136 DynInstPtr mem_inst = retryMemInsts.front(); 1137 retryMemInsts.pop_front(); 1138 return mem_inst; 1139 } 1140} 1141 1142template <class Impl> 1143void 1144InstructionQueue<Impl>::violation(DynInstPtr &store, 1145 DynInstPtr &faulting_load) 1146{ 1147 intInstQueueWrites++; 1148 memDepUnit[store->threadNumber].violation(store, faulting_load); 1149} 1150 1151template <class Impl> 1152void 1153InstructionQueue<Impl>::squash(ThreadID tid) 1154{ 1155 DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 1156 "the IQ.\n", tid); 1157 1158 // Read instruction sequence number of last instruction out of the 1159 // time buffer. 1160 squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 1161 1162 // Call doSquash if there are insts in the IQ 1163 if (count[tid] > 0) { 1164 doSquash(tid); 1165 } 1166 1167 // Also tell the memory dependence unit to squash. 1168 memDepUnit[tid].squash(squashedSeqNum[tid], tid); 1169} 1170 1171template <class Impl> 1172void 1173InstructionQueue<Impl>::doSquash(ThreadID tid) 1174{ 1175 // Start at the tail. 1176 ListIt squash_it = instList[tid].end(); 1177 --squash_it; 1178 1179 DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 1180 tid, squashedSeqNum[tid]); 1181 1182 // Squash any instructions younger than the squashed sequence number 1183 // given. 1184 while (squash_it != instList[tid].end() && 1185 (*squash_it)->seqNum > squashedSeqNum[tid]) { 1186 1187 DynInstPtr squashed_inst = (*squash_it); 1188 squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 1189 1190 // Only handle the instruction if it actually is in the IQ and 1191 // hasn't already been squashed in the IQ. 1192 if (squashed_inst->threadNumber != tid || 1193 squashed_inst->isSquashedInIQ()) { 1194 --squash_it; 1195 continue; 1196 } 1197 1198 if (!squashed_inst->isIssued() || 1199 (squashed_inst->isMemRef() && 1200 !squashed_inst->memOpDone())) { 1201 1202 DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", 1203 tid, squashed_inst->seqNum, squashed_inst->pcState()); 1204 1205 bool is_acq_rel = squashed_inst->isMemBarrier() && 1206 (squashed_inst->isLoad() || 1207 (squashed_inst->isStore() && 1208 !squashed_inst->isStoreConditional())); 1209 1210 // Remove the instruction from the dependency list. 1211 if (is_acq_rel || 1212 (!squashed_inst->isNonSpeculative() && 1213 !squashed_inst->isStoreConditional() && 1214 !squashed_inst->isMemBarrier() && 1215 !squashed_inst->isWriteBarrier())) { 1216 1217 for (int src_reg_idx = 0; 1218 src_reg_idx < squashed_inst->numSrcRegs(); 1219 src_reg_idx++) 1220 { 1221 PhysRegIndex src_reg = 1222 squashed_inst->renamedSrcRegIdx(src_reg_idx); 1223 1224 // Only remove it from the dependency graph if it 1225 // was placed there in the first place. 1226 1227 // Instead of doing a linked list traversal, we 1228 // can just remove these squashed instructions 1229 // either at issue time, or when the register is 1230 // overwritten. The only downside to this is it 1231 // leaves more room for error. 1232 1233 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 1234 src_reg < numPhysRegs) { 1235 dependGraph.remove(src_reg, squashed_inst); 1236 } 1237 1238 1239 ++iqSquashedOperandsExamined; 1240 } 1241 } else if (!squashed_inst->isStoreConditional() || 1242 !squashed_inst->isCompleted()) { 1243 NonSpecMapIt ns_inst_it = 1244 nonSpecInsts.find(squashed_inst->seqNum); 1245 1246 // we remove non-speculative instructions from 1247 // nonSpecInsts already when they are ready, and so we 1248 // cannot always expect to find them 1249 if (ns_inst_it == nonSpecInsts.end()) { 1250 // loads that became ready but stalled on a 1251 // blocked cache are alreayd removed from 1252 // nonSpecInsts, and have not faulted 1253 assert(squashed_inst->getFault() != NoFault || 1254 squashed_inst->isMemRef()); 1255 } else { 1256 1257 (*ns_inst_it).second = NULL; 1258 1259 nonSpecInsts.erase(ns_inst_it); 1260 1261 ++iqSquashedNonSpecRemoved; 1262 } 1263 } 1264 1265 // Might want to also clear out the head of the dependency graph. 1266 1267 // Mark it as squashed within the IQ. 1268 squashed_inst->setSquashedInIQ(); 1269 1270 // @todo: Remove this hack where several statuses are set so the 1271 // inst will flow through the rest of the pipeline. 1272 squashed_inst->setIssued(); 1273 squashed_inst->setCanCommit(); 1274 squashed_inst->clearInIQ(); 1275 1276 //Update Thread IQ Count 1277 count[squashed_inst->threadNumber]--; 1278 1279 ++freeEntries; 1280 } 1281 1282 instList[tid].erase(squash_it--); 1283 ++iqSquashedInstsExamined; 1284 } 1285} 1286 1287template <class Impl> 1288bool 1289InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 1290{ 1291 // Loop through the instruction's source registers, adding 1292 // them to the dependency list if they are not ready. 1293 int8_t total_src_regs = new_inst->numSrcRegs(); 1294 bool return_val = false; 1295 1296 for (int src_reg_idx = 0; 1297 src_reg_idx < total_src_regs; 1298 src_reg_idx++) 1299 { 1300 // Only add it to the dependency graph if it's not ready. 1301 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 1302 PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 1303 1304 // Check the IQ's scoreboard to make sure the register 1305 // hasn't become ready while the instruction was in flight 1306 // between stages. Only if it really isn't ready should 1307 // it be added to the dependency graph. 1308 if (src_reg >= numPhysRegs) { 1309 continue; 1310 } else if (!regScoreboard[src_reg]) { 1311 DPRINTF(IQ, "Instruction PC %s has src reg %i that " 1312 "is being added to the dependency chain.\n", 1313 new_inst->pcState(), src_reg); 1314 1315 dependGraph.insert(src_reg, new_inst); 1316 1317 // Change the return value to indicate that something 1318 // was added to the dependency graph. 1319 return_val = true; 1320 } else { 1321 DPRINTF(IQ, "Instruction PC %s has src reg %i that " 1322 "became ready before it reached the IQ.\n", 1323 new_inst->pcState(), src_reg); 1324 // Mark a register ready within the instruction. 1325 new_inst->markSrcRegReady(src_reg_idx); 1326 } 1327 } 1328 } 1329 1330 return return_val; 1331} 1332 1333template <class Impl> 1334void 1335InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) 1336{ 1337 // Nothing really needs to be marked when an instruction becomes 1338 // the producer of a register's value, but for convenience a ptr 1339 // to the producing instruction will be placed in the head node of 1340 // the dependency links. 1341 int8_t total_dest_regs = new_inst->numDestRegs(); 1342 1343 for (int dest_reg_idx = 0; 1344 dest_reg_idx < total_dest_regs; 1345 dest_reg_idx++) 1346 { 1347 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 1348 1349 // Instructions that use the misc regs will have a reg number 1350 // higher than the normal physical registers. In this case these 1351 // registers are not renamed, and there is no need to track 1352 // dependencies as these instructions must be executed at commit. 1353 if (dest_reg >= numPhysRegs) { 1354 continue; 1355 } 1356 1357 if (!dependGraph.empty(dest_reg)) { 1358 dependGraph.dump(); 1359 panic("Dependency graph %i not empty!", dest_reg); 1360 } 1361 1362 dependGraph.setInst(dest_reg, new_inst); 1363 1364 // Mark the scoreboard to say it's not yet ready. 1365 regScoreboard[dest_reg] = false; 1366 } 1367} 1368 1369template <class Impl> 1370void 1371InstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 1372{ 1373 // If the instruction now has all of its source registers 1374 // available, then add it to the list of ready instructions. 1375 if (inst->readyToIssue()) { 1376 1377 //Add the instruction to the proper ready list. 1378 if (inst->isMemRef()) { 1379 1380 DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 1381 1382 // Message to the mem dependence unit that this instruction has 1383 // its registers ready. 1384 memDepUnit[inst->threadNumber].regsReady(inst); 1385 1386 return; 1387 } 1388 1389 OpClass op_class = inst->opClass(); 1390 1391 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 1392 "the ready list, PC %s opclass:%i [sn:%lli].\n", 1393 inst->pcState(), op_class, inst->seqNum); 1394 1395 readyInsts[op_class].push(inst); 1396 1397 // Will need to reorder the list if either a queue is not on the list, 1398 // or it has an older instruction than last time. 1399 if (!queueOnList[op_class]) { 1400 addToOrderList(op_class); 1401 } else if (readyInsts[op_class].top()->seqNum < 1402 (*readyIt[op_class]).oldestInst) { 1403 listOrder.erase(readyIt[op_class]); 1404 addToOrderList(op_class); 1405 } 1406 } 1407} 1408 1409template <class Impl> 1410int 1411InstructionQueue<Impl>::countInsts() 1412{ 1413#if 0 1414 //ksewell:This works but definitely could use a cleaner write 1415 //with a more intuitive way of counting. Right now it's 1416 //just brute force .... 1417 // Change the #if if you want to use this method. 1418 int total_insts = 0; 1419 1420 for (ThreadID tid = 0; tid < numThreads; ++tid) { 1421 ListIt count_it = instList[tid].begin(); 1422 1423 while (count_it != instList[tid].end()) { 1424 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 1425 if (!(*count_it)->isIssued()) { 1426 ++total_insts; 1427 } else if ((*count_it)->isMemRef() && 1428 !(*count_it)->memOpDone) { 1429 // Loads that have not been marked as executed still count 1430 // towards the total instructions. 1431 ++total_insts; 1432 } 1433 } 1434 1435 ++count_it; 1436 } 1437 } 1438 1439 return total_insts; 1440#else 1441 return numEntries - freeEntries; 1442#endif 1443} 1444 1445template <class Impl> 1446void 1447InstructionQueue<Impl>::dumpLists() 1448{ 1449 for (int i = 0; i < Num_OpClasses; ++i) { 1450 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 1451 1452 cprintf("\n"); 1453 } 1454 1455 cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 1456 1457 NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 1458 NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 1459 1460 cprintf("Non speculative list: "); 1461 1462 while (non_spec_it != non_spec_end_it) { 1463 cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(), 1464 (*non_spec_it).second->seqNum); 1465 ++non_spec_it; 1466 } 1467 1468 cprintf("\n"); 1469 1470 ListOrderIt list_order_it = listOrder.begin(); 1471 ListOrderIt list_order_end_it = listOrder.end(); 1472 int i = 1; 1473 1474 cprintf("List order: "); 1475 1476 while (list_order_it != list_order_end_it) { 1477 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 1478 (*list_order_it).oldestInst); 1479 1480 ++list_order_it; 1481 ++i; 1482 } 1483 1484 cprintf("\n"); 1485} 1486 1487 1488template <class Impl> 1489void 1490InstructionQueue<Impl>::dumpInsts() 1491{ 1492 for (ThreadID tid = 0; tid < numThreads; ++tid) { 1493 int num = 0; 1494 int valid_num = 0; 1495 ListIt inst_list_it = instList[tid].begin(); 1496 1497 while (inst_list_it != instList[tid].end()) { 1498 cprintf("Instruction:%i\n", num); 1499 if (!(*inst_list_it)->isSquashed()) { 1500 if (!(*inst_list_it)->isIssued()) { 1501 ++valid_num; 1502 cprintf("Count:%i\n", valid_num); 1503 } else if ((*inst_list_it)->isMemRef() && 1504 !(*inst_list_it)->memOpDone()) { 1505 // Loads that have not been marked as executed 1506 // still count towards the total instructions. 1507 ++valid_num; 1508 cprintf("Count:%i\n", valid_num); 1509 } 1510 } 1511 1512 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 1513 "Issued:%i\nSquashed:%i\n", 1514 (*inst_list_it)->pcState(), 1515 (*inst_list_it)->seqNum, 1516 (*inst_list_it)->threadNumber, 1517 (*inst_list_it)->isIssued(), 1518 (*inst_list_it)->isSquashed()); 1519 1520 if ((*inst_list_it)->isMemRef()) { 1521 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 1522 } 1523 1524 cprintf("\n"); 1525 1526 inst_list_it++; 1527 ++num; 1528 } 1529 } 1530 1531 cprintf("Insts to Execute list:\n"); 1532 1533 int num = 0; 1534 int valid_num = 0; 1535 ListIt inst_list_it = instsToExecute.begin(); 1536 1537 while (inst_list_it != instsToExecute.end()) 1538 { 1539 cprintf("Instruction:%i\n", 1540 num); 1541 if (!(*inst_list_it)->isSquashed()) { 1542 if (!(*inst_list_it)->isIssued()) { 1543 ++valid_num; 1544 cprintf("Count:%i\n", valid_num); 1545 } else if ((*inst_list_it)->isMemRef() && 1546 !(*inst_list_it)->memOpDone()) { 1547 // Loads that have not been marked as executed 1548 // still count towards the total instructions. 1549 ++valid_num; 1550 cprintf("Count:%i\n", valid_num); 1551 } 1552 } 1553 1554 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 1555 "Issued:%i\nSquashed:%i\n", 1556 (*inst_list_it)->pcState(), 1557 (*inst_list_it)->seqNum, 1558 (*inst_list_it)->threadNumber, 1559 (*inst_list_it)->isIssued(), 1560 (*inst_list_it)->isSquashed()); 1561 1562 if ((*inst_list_it)->isMemRef()) { 1563 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 1564 } 1565 1566 cprintf("\n"); 1567 1568 inst_list_it++; 1569 ++num; 1570 } 1571} 1572 1573#endif//__CPU_O3_INST_QUEUE_IMPL_HH__ 1574