inst_queue_impl.hh revision 10032
11689SN/A/* 27944SGiacomo.Gabrielli@arm.com * Copyright (c) 2011-2013 ARM Limited 37944SGiacomo.Gabrielli@arm.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47944SGiacomo.Gabrielli@arm.com * All rights reserved. 57944SGiacomo.Gabrielli@arm.com * 67944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 77944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 87944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 97944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 107944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 117944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 127944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 137944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 142326SN/A * 151689SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392665Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412831Sksewell@umich.edu * Authors: Kevin Lim 421689SN/A * Korey Sewell 431689SN/A */ 442064SN/A 451060SN/A#ifndef __CPU_O3_INST_QUEUE_IMPL_HH__ 461060SN/A#define __CPU_O3_INST_QUEUE_IMPL_HH__ 472292SN/A 481717SN/A#include <limits> 494762Snate@binkert.org#include <vector> 506221Snate@binkert.org 514762Snate@binkert.org#include "cpu/o3/fu_pool.hh" 521060SN/A#include "cpu/o3/inst_queue.hh" 536221Snate@binkert.org#include "debug/IQ.hh" 545529Snate@binkert.org#include "enums/OpClass.hh" 551061SN/A#include "params/DerivO3CPU.hh" 562292SN/A#include "sim/core.hh" 575606Snate@binkert.org 585606Snate@binkert.org// clang complains about std::set being overloaded with Packet::set if 595606Snate@binkert.org// we open up the entire namespace std 601060SN/Ausing std::list; 612292SN/A 622292SN/Atemplate <class Impl> 632292SN/AInstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 642292SN/A int fu_idx, InstructionQueue<Impl> *iq_ptr) 652292SN/A : Event(Stat_Event_Pri, AutoDelete), 662292SN/A inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 672292SN/A{ 682326SN/A} 692292SN/A 702292SN/Atemplate <class Impl> 712292SN/Avoid 722292SN/AInstructionQueue<Impl>::FUCompletion::process() 732292SN/A{ 742292SN/A iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 755336Shines@cs.fsu.edu inst = NULL; 762292SN/A} 774873Sstever@eecs.umich.edu 782292SN/A 792292SN/Atemplate <class Impl> 802292SN/Aconst char * 814329Sktlim@umich.eduInstructionQueue<Impl>::FUCompletion::description() const 825529Snate@binkert.org{ 834329Sktlim@umich.edu return "Functional unit completion"; 844329Sktlim@umich.edu} 854329Sktlim@umich.edu 862292SN/Atemplate <class Impl> 872292SN/AInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 882292SN/A DerivO3CPUParams *params) 892292SN/A : cpu(cpu_ptr), 902292SN/A iewStage(iew_ptr), 912292SN/A fuPool(params->fuPool), 922292SN/A numEntries(params->numIQEntries), 932292SN/A totalWidth(params->issueWidth), 942307SN/A commitToIEWDelay(params->commitToIEWDelay) 952307SN/A{ 965529Snate@binkert.org assert(fuPool); 971060SN/A 981060SN/A numThreads = params->numThreads; 991060SN/A 1001060SN/A // Set the number of total physical registers 1011060SN/A numPhysRegs = params->numPhysIntRegs + params->numPhysFloatRegs + 1021060SN/A params->numPhysCCRegs; 1032326SN/A 1041060SN/A //Create an entry for each physical register within the 1051060SN/A //dependency graph. 1061060SN/A dependGraph.resize(numPhysRegs); 1071060SN/A 1082292SN/A // Resize the register scoreboard. 1096221Snate@binkert.org regScoreboard.resize(numPhysRegs); 1106221Snate@binkert.org 1116221Snate@binkert.org //Initialize Mem Dependence Units 1121060SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1131060SN/A memDepUnit[tid].init(params, tid); 1142307SN/A memDepUnit[tid].setIQ(this); 1152292SN/A } 1162980Sgblack@eecs.umich.edu 1172292SN/A resetState(); 1182292SN/A 1192292SN/A std::string policy = params->smtIQPolicy; 1202292SN/A 1212292SN/A //Convert string to lowercase 1222292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1232292SN/A (int(*)(int)) tolower); 1242292SN/A 1252292SN/A //Figure out resource sharing policy 1262292SN/A if (policy == "dynamic") { 1276221Snate@binkert.org iqPolicy = Dynamic; 1286221Snate@binkert.org 1292292SN/A //Set Max Entries to Total ROB Capacity 1302292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1312292SN/A maxEntries[tid] = numEntries; 1322292SN/A } 1332292SN/A 1342292SN/A } else if (policy == "partitioned") { 1352292SN/A iqPolicy = Partitioned; 1362292SN/A 1372292SN/A //@todo:make work if part_amt doesnt divide evenly. 1386221Snate@binkert.org int part_amt = numEntries / numThreads; 1396221Snate@binkert.org 1402292SN/A //Divide ROB up evenly 1412292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1422831Sksewell@umich.edu maxEntries[tid] = part_amt; 1432292SN/A } 1442292SN/A 1452292SN/A DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 1462292SN/A "%i entries per thread.\n",part_amt); 1472292SN/A } else if (policy == "threshold") { 1482292SN/A iqPolicy = Threshold; 1492292SN/A 1502292SN/A double threshold = (double)params->smtIQThreshold / 100; 1512292SN/A 1526221Snate@binkert.org int thresholdIQ = (int)((double)threshold * numEntries); 1536221Snate@binkert.org 1542292SN/A //Divide up by threshold amount 1552292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 1562831Sksewell@umich.edu maxEntries[tid] = thresholdIQ; 1572292SN/A } 1582292SN/A 1592292SN/A DPRINTF(IQ, "IQ sharing policy set to Threshold:" 1602292SN/A "%i entries per thread.\n",thresholdIQ); 1612292SN/A } else { 1622292SN/A assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 1632292SN/A "Partitioned, Threshold}"); 1642292SN/A } 1652292SN/A} 1662292SN/A 1672326SN/Atemplate <class Impl> 1682348SN/AInstructionQueue<Impl>::~InstructionQueue() 1692326SN/A{ 1702326SN/A dependGraph.reset(); 1712348SN/A#ifdef DEBUG 1722292SN/A cprintf("Nodes traversed: %i, removed: %i\n", 1732292SN/A dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1742292SN/A#endif 1752292SN/A} 1762292SN/A 1772292SN/Atemplate <class Impl> 1782292SN/Astd::string 1791060SN/AInstructionQueue<Impl>::name() const 1801060SN/A{ 1811061SN/A return cpu->name() + ".iq"; 1821060SN/A} 1831062SN/A 1841062SN/Atemplate <class Impl> 1852301SN/Avoid 1861062SN/AInstructionQueue<Impl>::regStats() 1871062SN/A{ 1881062SN/A using namespace Stats; 1891062SN/A iqInstsAdded 1901062SN/A .name(name() + ".iqInstsAdded") 1911062SN/A .desc("Number of instructions added to the IQ (excludes non-spec)") 1921062SN/A .prereq(iqInstsAdded); 1931062SN/A 1941062SN/A iqNonSpecInstsAdded 1951062SN/A .name(name() + ".iqNonSpecInstsAdded") 1962301SN/A .desc("Number of non-speculative instructions added to the IQ") 1972301SN/A .prereq(iqNonSpecInstsAdded); 1982301SN/A 1992301SN/A iqInstsIssued 2001062SN/A .name(name() + ".iqInstsIssued") 2011062SN/A .desc("Number of instructions issued") 2021062SN/A .prereq(iqInstsIssued); 2031062SN/A 2041062SN/A iqIntInstsIssued 2051062SN/A .name(name() + ".iqIntInstsIssued") 2061062SN/A .desc("Number of integer instructions issued") 2071062SN/A .prereq(iqIntInstsIssued); 2081062SN/A 2091062SN/A iqFloatInstsIssued 2101062SN/A .name(name() + ".iqFloatInstsIssued") 2111062SN/A .desc("Number of float instructions issued") 2121062SN/A .prereq(iqFloatInstsIssued); 2131062SN/A 2141062SN/A iqBranchInstsIssued 2151062SN/A .name(name() + ".iqBranchInstsIssued") 2161062SN/A .desc("Number of branch instructions issued") 2171062SN/A .prereq(iqBranchInstsIssued); 2181062SN/A 2191062SN/A iqMemInstsIssued 2201062SN/A .name(name() + ".iqMemInstsIssued") 2211062SN/A .desc("Number of memory instructions issued") 2221062SN/A .prereq(iqMemInstsIssued); 2231062SN/A 2241062SN/A iqMiscInstsIssued 2251062SN/A .name(name() + ".iqMiscInstsIssued") 2261062SN/A .desc("Number of miscellaneous instructions issued") 2271062SN/A .prereq(iqMiscInstsIssued); 2281062SN/A 2291062SN/A iqSquashedInstsIssued 2301062SN/A .name(name() + ".iqSquashedInstsIssued") 2311062SN/A .desc("Number of squashed instructions issued") 2321062SN/A .prereq(iqSquashedInstsIssued); 2331062SN/A 2341062SN/A iqSquashedInstsExamined 2351062SN/A .name(name() + ".iqSquashedInstsExamined") 2361062SN/A .desc("Number of squashed instructions iterated over during squash;" 2371062SN/A " mainly for profiling") 2381062SN/A .prereq(iqSquashedInstsExamined); 2391062SN/A 2401062SN/A iqSquashedOperandsExamined 2411062SN/A .name(name() + ".iqSquashedOperandsExamined") 2421062SN/A .desc("Number of squashed operands that are examined and possibly " 2431062SN/A "removed from graph") 2441062SN/A .prereq(iqSquashedOperandsExamined); 2451062SN/A 2461062SN/A iqSquashedNonSpecRemoved 2472361SN/A .name(name() + ".iqSquashedNonSpecRemoved") 2482326SN/A .desc("Number of squashed non-spec instructions that were removed") 2492301SN/A .prereq(iqSquashedNonSpecRemoved); 2502301SN/A/* 2512301SN/A queueResDist 2522301SN/A .init(Num_OpClasses, 0, 99, 2) 2532301SN/A .name(name() + ".IQ:residence:") 2542301SN/A .desc("cycles from dispatch to issue") 2552326SN/A .flags(total | pdf | cdf ) 2562301SN/A ; 2572361SN/A for (int i = 0; i < Num_OpClasses; ++i) { 2582326SN/A queueResDist.subname(i, opClassStrings[i]); 2592307SN/A } 2602301SN/A*/ 2612301SN/A numIssuedDist 2622307SN/A .init(0,totalWidth,1) 2632301SN/A .name(name() + ".issued_per_cycle") 2642301SN/A .desc("Number of insts issued each cycle") 2652301SN/A .flags(pdf) 2662301SN/A ; 2672301SN/A/* 2682301SN/A dist_unissued 2692301SN/A .init(Num_OpClasses+2) 2702301SN/A .name(name() + ".unissued_cause") 2712301SN/A .desc("Reason ready instruction not issued") 2722301SN/A .flags(pdf | dist) 2732301SN/A ; 2742301SN/A for (int i=0; i < (Num_OpClasses + 2); ++i) { 2752326SN/A dist_unissued.subname(i, unissued_names[i]); 2764762Snate@binkert.org } 2772301SN/A*/ 2782301SN/A statIssuedInstType 2792301SN/A .init(numThreads,Enums::Num_OpClass) 2802301SN/A .name(name() + ".FU_type") 2814762Snate@binkert.org .desc("Type of FU issued") 2822301SN/A .flags(total | pdf | dist) 2832301SN/A ; 2842301SN/A statIssuedInstType.ysubnames(Enums::OpClassStrings); 2852301SN/A 2862361SN/A // 2872326SN/A // How long did instructions for a particular FU type wait prior to issue 2882301SN/A // 2892301SN/A/* 2902301SN/A issueDelayDist 2912301SN/A .init(Num_OpClasses,0,99,2) 2922301SN/A .name(name() + ".") 2932301SN/A .desc("cycles from operands ready to issue") 2942301SN/A .flags(pdf | cdf) 2952980Sgblack@eecs.umich.edu ; 2962301SN/A 2972326SN/A for (int i=0; i<Num_OpClasses; ++i) { 2982301SN/A std::stringstream subname; 2992361SN/A subname << opClassStrings[i] << "_delay"; 3002326SN/A issueDelayDist.subname(i, subname.str()); 3012301SN/A } 3022301SN/A*/ 3032301SN/A issueRate 3042301SN/A .name(name() + ".rate") 3052326SN/A .desc("Inst issue rate") 3062727Sktlim@umich.edu .flags(total) 3072326SN/A ; 3082301SN/A issueRate = iqInstsIssued / cpu->numCycles; 3092301SN/A 3102301SN/A statFuBusy 3112301SN/A .init(Num_OpClasses) 3122301SN/A .name(name() + ".fu_full") 3132301SN/A .desc("attempts to use FU when none available") 3144762Snate@binkert.org .flags(pdf | dist) 3152301SN/A ; 3162301SN/A for (int i=0; i < Num_OpClasses; ++i) { 3172326SN/A statFuBusy.subname(i, Enums::OpClassStrings[i]); 3182301SN/A } 3192301SN/A 3202301SN/A fuBusy 3212301SN/A .init(numThreads) 3222301SN/A .name(name() + ".fu_busy_cnt") 3232301SN/A .desc("FU busy when requested") 3242326SN/A .flags(total) 3252301SN/A ; 3262301SN/A 3272301SN/A fuBusyRate 3282301SN/A .name(name() + ".fu_busy_rate") 3292326SN/A .desc("FU busy rate (busy events/executed inst)") 3302301SN/A .flags(total) 3316221Snate@binkert.org ; 3322292SN/A fuBusyRate = fuBusy / iqInstsIssued; 3336221Snate@binkert.org 3342292SN/A for (ThreadID tid = 0; tid < numThreads; tid++) { 3357897Shestness@cs.utexas.edu // Tell mem dependence unit to reg stats as well. 3367897Shestness@cs.utexas.edu memDepUnit[tid].regStats(); 3377897Shestness@cs.utexas.edu } 3387897Shestness@cs.utexas.edu 3397897Shestness@cs.utexas.edu intInstQueueReads 3407897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_reads") 3417897Shestness@cs.utexas.edu .desc("Number of integer instruction queue reads") 3427897Shestness@cs.utexas.edu .flags(total); 3437897Shestness@cs.utexas.edu 3447897Shestness@cs.utexas.edu intInstQueueWrites 3457897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_writes") 3467897Shestness@cs.utexas.edu .desc("Number of integer instruction queue writes") 3477897Shestness@cs.utexas.edu .flags(total); 3487897Shestness@cs.utexas.edu 3497897Shestness@cs.utexas.edu intInstQueueWakeupAccesses 3507897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_wakeup_accesses") 3517897Shestness@cs.utexas.edu .desc("Number of integer instruction queue wakeup accesses") 3527897Shestness@cs.utexas.edu .flags(total); 3537897Shestness@cs.utexas.edu 3547897Shestness@cs.utexas.edu fpInstQueueReads 3557897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_reads") 3567897Shestness@cs.utexas.edu .desc("Number of floating instruction queue reads") 3577897Shestness@cs.utexas.edu .flags(total); 3587897Shestness@cs.utexas.edu 3597897Shestness@cs.utexas.edu fpInstQueueWrites 3607897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_writes") 3617897Shestness@cs.utexas.edu .desc("Number of floating instruction queue writes") 3627897Shestness@cs.utexas.edu .flags(total); 3637897Shestness@cs.utexas.edu 3647897Shestness@cs.utexas.edu fpInstQueueWakeupQccesses 3657897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_wakeup_accesses") 3667897Shestness@cs.utexas.edu .desc("Number of floating instruction queue wakeup accesses") 3677897Shestness@cs.utexas.edu .flags(total); 3687897Shestness@cs.utexas.edu 3697897Shestness@cs.utexas.edu intAluAccesses 3707897Shestness@cs.utexas.edu .name(name() + ".int_alu_accesses") 3717897Shestness@cs.utexas.edu .desc("Number of integer alu accesses") 3727897Shestness@cs.utexas.edu .flags(total); 3737897Shestness@cs.utexas.edu 3747897Shestness@cs.utexas.edu fpAluAccesses 3757897Shestness@cs.utexas.edu .name(name() + ".fp_alu_accesses") 3761062SN/A .desc("Number of floating point alu accesses") 3771062SN/A .flags(total); 3781062SN/A 3791062SN/A} 3802307SN/A 3811060SN/Atemplate <class Impl> 3822307SN/Avoid 3836221Snate@binkert.orgInstructionQueue<Impl>::resetState() 3846221Snate@binkert.org{ 3856221Snate@binkert.org //Initialize thread IQ counts 3862307SN/A for (ThreadID tid = 0; tid <numThreads; tid++) { 3871060SN/A count[tid] = 0; 3882307SN/A instList[tid].clear(); 3892307SN/A } 3902307SN/A 3912307SN/A // Initialize the number of free IQ entries. 3922307SN/A freeEntries = numEntries; 3932307SN/A 3942307SN/A // Note that in actuality, the registers corresponding to the logical 3952307SN/A // registers start off as ready. However this doesn't matter for the 3962307SN/A // IQ as the instruction should have been correctly told if those 3972307SN/A // registers are ready in rename. Thus it can all be initialized as 3982307SN/A // unready. 3992307SN/A for (int i = 0; i < numPhysRegs; ++i) { 4006221Snate@binkert.org regScoreboard[i] = false; 4016221Snate@binkert.org } 4022307SN/A 4032307SN/A for (ThreadID tid = 0; tid < numThreads; ++tid) { 4042307SN/A squashedSeqNum[tid] = 0; 4052307SN/A } 4062307SN/A 4072307SN/A for (int i = 0; i < Num_OpClasses; ++i) { 4082307SN/A while (!readyInsts[i].empty()) 4092307SN/A readyInsts[i].pop(); 4102307SN/A queueOnList[i] = false; 4112307SN/A readyIt[i] = listOrder.end(); 4127944SGiacomo.Gabrielli@arm.com } 4131060SN/A nonSpecInsts.clear(); 4141060SN/A listOrder.clear(); 4151061SN/A deferredMemInsts.clear(); 4161060SN/A} 4176221Snate@binkert.org 4181060SN/Atemplate <class Impl> 4192292SN/Avoid 4202064SN/AInstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 4212064SN/A{ 4222064SN/A activeThreads = at_ptr; 4232064SN/A} 4242292SN/A 4252064SN/Atemplate <class Impl> 4264318Sktlim@umich.eduvoid 4271060SN/AInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 4281060SN/A{ 4291061SN/A issueToExecuteQueue = i2e_ptr; 4301060SN/A} 4311060SN/A 4321060SN/Atemplate <class Impl> 4331060SN/Avoid 4341060SN/AInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 4351060SN/A{ 4361060SN/A timeBuffer = tb_ptr; 4371060SN/A 4381684SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 4392307SN/A} 4402307SN/A 4412307SN/Atemplate <class Impl> 4422367SN/Avoid 4432367SN/AInstructionQueue<Impl>::drainSanityCheck() const 4442367SN/A{ 4452367SN/A assert(dependGraph.empty()); 4462367SN/A assert(instsToExecute.empty()); 4472367SN/A for (ThreadID tid = 0; tid < numThreads; ++tid) 4482367SN/A memDepUnit[tid].drainSanityCheck(); 4492307SN/A} 4502326SN/A 4512367SN/Atemplate <class Impl> 4522307SN/Avoid 4536221Snate@binkert.orgInstructionQueue<Impl>::takeOverFrom() 4546221Snate@binkert.org{ 4552307SN/A resetState(); 4562307SN/A} 4572307SN/A 4582307SN/Atemplate <class Impl> 4592307SN/Aint 4602307SN/AInstructionQueue<Impl>::entryAmount(ThreadID num_threads) 4612307SN/A{ 4622307SN/A if (iqPolicy == Partitioned) { 4632307SN/A return numEntries / num_threads; 4642307SN/A } else { 4652307SN/A return 0; 4662292SN/A } 4676221Snate@binkert.org} 4682292SN/A 4692292SN/A 4702292SN/Atemplate <class Impl> 4712292SN/Avoid 4722292SN/AInstructionQueue<Impl>::resetEntries() 4732292SN/A{ 4742292SN/A if (iqPolicy != Dynamic || numThreads > 1) { 4752292SN/A int active_threads = activeThreads->size(); 4762292SN/A 4772292SN/A list<ThreadID>::iterator threads = activeThreads->begin(); 4782292SN/A list<ThreadID>::iterator end = activeThreads->end(); 4792292SN/A 4802292SN/A while (threads != end) { 4812292SN/A ThreadID tid = *threads++; 4823867Sbinkertn@umich.edu 4832292SN/A if (iqPolicy == Partitioned) { 4846221Snate@binkert.org maxEntries[tid] = numEntries / active_threads; 4856221Snate@binkert.org } else if(iqPolicy == Threshold && active_threads == 1) { 4862292SN/A maxEntries[tid] = numEntries; 4873867Sbinkertn@umich.edu } 4886221Snate@binkert.org } 4893867Sbinkertn@umich.edu } 4902292SN/A} 4913867Sbinkertn@umich.edu 4922292SN/Atemplate <class Impl> 4933867Sbinkertn@umich.eduunsigned 4942292SN/AInstructionQueue<Impl>::numFreeEntries() 4952292SN/A{ 4962292SN/A return freeEntries; 4972292SN/A} 4982292SN/A 4992292SN/Atemplate <class Impl> 5001684SN/Aunsigned 5011684SN/AInstructionQueue<Impl>::numFreeEntries(ThreadID tid) 5021684SN/A{ 5031684SN/A return maxEntries[tid] - count[tid]; 5041684SN/A} 5051684SN/A 5062292SN/A// Might want to do something more complex if it knows how many instructions 5072292SN/A// will be issued this cycle. 5086221Snate@binkert.orgtemplate <class Impl> 5092292SN/Abool 5102292SN/AInstructionQueue<Impl>::isFull() 5112292SN/A{ 5122292SN/A if (freeEntries == 0) { 5131060SN/A return(true); 5141060SN/A } else { 5151061SN/A return(false); 5161060SN/A } 5171060SN/A} 5181060SN/A 5191060SN/Atemplate <class Impl> 5201060SN/Abool 5211060SN/AInstructionQueue<Impl>::isFull(ThreadID tid) 5221060SN/A{ 5231060SN/A if (numFreeEntries(tid) == 0) { 5241060SN/A return(true); 5251060SN/A } else { 5261061SN/A return(false); 5272292SN/A } 5286221Snate@binkert.org} 5292292SN/A 5302292SN/Atemplate <class Impl> 5312292SN/Abool 5322292SN/AInstructionQueue<Impl>::hasReadyInsts() 5332292SN/A{ 5342292SN/A if (!listOrder.empty()) { 5352292SN/A return true; 5362292SN/A } 5372292SN/A 5382292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 5392292SN/A if (!readyInsts[i].empty()) { 5402292SN/A return true; 5412292SN/A } 5422292SN/A } 5432292SN/A 5442292SN/A return false; 5452292SN/A} 5462292SN/A 5472292SN/Atemplate <class Impl> 5482292SN/Avoid 5492292SN/AInstructionQueue<Impl>::insert(DynInstPtr &new_inst) 5502292SN/A{ 5512292SN/A new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 5522292SN/A // Make sure the instruction is valid 5532292SN/A assert(new_inst); 5542292SN/A 5551060SN/A DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n", 5561061SN/A new_inst->seqNum, new_inst->pcState()); 5571060SN/A 5587897Shestness@cs.utexas.edu assert(freeEntries != 0); 5591060SN/A 5601060SN/A instList[new_inst->threadNumber].push_back(new_inst); 5611060SN/A 5627720Sgblack@eecs.umich.edu --freeEntries; 5637720Sgblack@eecs.umich.edu 5641060SN/A new_inst->setInIQ(); 5651060SN/A 5661060SN/A // Look through its source registers (physical regs), and mark any 5672292SN/A // dependencies. 5681060SN/A addToDependents(new_inst); 5692064SN/A 5701060SN/A // Have this instruction set itself as the producer of its destination 5712292SN/A // register(s). 5721060SN/A addToProducers(new_inst); 5731060SN/A 5741060SN/A if (new_inst->isMemRef()) { 5751060SN/A memDepUnit[new_inst->threadNumber].insert(new_inst); 5761060SN/A } else { 5771060SN/A addIfReady(new_inst); 5781060SN/A } 5792326SN/A 5801060SN/A ++iqInstsAdded; 5811061SN/A 5822292SN/A count[new_inst->threadNumber]++; 5831062SN/A 5841062SN/A assert(freeEntries == (numEntries - countInsts())); 5851061SN/A} 5861061SN/A 5871062SN/Atemplate <class Impl> 5881060SN/Avoid 5892292SN/AInstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) 5902292SN/A{ 5911060SN/A // @todo: Clean up this code; can do it by setting inst as unable 5921060SN/A // to issue, then calling normal insert on the inst. 5931060SN/A new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 5941061SN/A 5951061SN/A assert(new_inst); 5962292SN/A 5971061SN/A nonSpecInsts[new_inst->seqNum] = new_inst; 5981061SN/A 5991061SN/A DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s " 6007897Shestness@cs.utexas.edu "to the IQ.\n", 6011061SN/A new_inst->seqNum, new_inst->pcState()); 6022292SN/A 6031061SN/A assert(freeEntries != 0); 6042292SN/A 6051061SN/A instList[new_inst->threadNumber].push_back(new_inst); 6067720Sgblack@eecs.umich.edu 6072326SN/A --freeEntries; 6087720Sgblack@eecs.umich.edu 6092064SN/A new_inst->setInIQ(); 6101061SN/A 6111061SN/A // Have this instruction set itself as the producer of its destination 6122292SN/A // register(s). 6131061SN/A addToProducers(new_inst); 6142064SN/A 6151061SN/A // If it's a memory instruction, add it to the memory dependency 6162292SN/A // unit. 6171061SN/A if (new_inst->isMemRef()) { 6181061SN/A memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 6191061SN/A } 6202326SN/A 6211061SN/A ++iqNonSpecInstsAdded; 6221061SN/A 6231061SN/A count[new_inst->threadNumber]++; 6242292SN/A 6252292SN/A assert(freeEntries == (numEntries - countInsts())); 6261061SN/A} 6271062SN/A 6281062SN/Atemplate <class Impl> 6292292SN/Avoid 6302292SN/AInstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) 6312292SN/A{ 6322292SN/A memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 6331061SN/A 6341061SN/A insertNonSpec(barr_inst); 6351061SN/A} 6361060SN/A 6372292SN/Atemplate <class Impl> 6381060SN/Atypename Impl::DynInstPtr 6392292SN/AInstructionQueue<Impl>::getInstToExecute() 6401060SN/A{ 6412292SN/A assert(!instsToExecute.empty()); 6422292SN/A DynInstPtr inst = instsToExecute.front(); 6431060SN/A instsToExecute.pop_front(); 6442064SN/A if (inst->isFloating()){ 6452333SN/A fpInstQueueReads++; 6462333SN/A } else { 6472333SN/A intInstQueueReads++; 6482333SN/A } 6492333SN/A return inst; 6502333SN/A} 6517897Shestness@cs.utexas.edu 6527897Shestness@cs.utexas.edutemplate <class Impl> 6537897Shestness@cs.utexas.eduvoid 6547897Shestness@cs.utexas.eduInstructionQueue<Impl>::addToOrderList(OpClass op_class) 6557897Shestness@cs.utexas.edu{ 6562333SN/A assert(!readyInsts[op_class].empty()); 6572333SN/A 6581060SN/A ListOrderEntry queue_entry; 6592333SN/A 6602064SN/A queue_entry.queueType = op_class; 6612292SN/A 6622292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 6632292SN/A 6642292SN/A ListOrderIt list_it = listOrder.begin(); 6652292SN/A ListOrderIt list_end_it = listOrder.end(); 6662292SN/A 6672292SN/A while (list_it != list_end_it) { 6682292SN/A if ((*list_it).oldestInst > queue_entry.oldestInst) { 6692292SN/A break; 6702292SN/A } 6712292SN/A 6722292SN/A list_it++; 6732292SN/A } 6742292SN/A 6752292SN/A readyIt[op_class] = listOrder.insert(list_it, queue_entry); 6762292SN/A queueOnList[op_class] = true; 6772292SN/A} 6782292SN/A 6792292SN/Atemplate <class Impl> 6801060SN/Avoid 6811060SN/AInstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 6822292SN/A{ 6832292SN/A // Get iterator of next item on the list 6842292SN/A // Delete the original iterator 6851060SN/A // Determine if the next item is either the end of the list or younger 6862292SN/A // than the new instruction. If so, then add in a new iterator right here. 6872292SN/A // If not, then move along. 6882292SN/A ListOrderEntry queue_entry; 6892292SN/A OpClass op_class = (*list_order_it).queueType; 6902292SN/A ListOrderIt next_it = list_order_it; 6912292SN/A 6922292SN/A ++next_it; 6932292SN/A 6942292SN/A queue_entry.queueType = op_class; 6952292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 6962292SN/A 6972292SN/A while (next_it != listOrder.end() && 6982292SN/A (*next_it).oldestInst < queue_entry.oldestInst) { 6992292SN/A ++next_it; 7002292SN/A } 7012292SN/A 7022292SN/A readyIt[op_class] = listOrder.insert(next_it, queue_entry); 7032292SN/A} 7042292SN/A 7052292SN/Atemplate <class Impl> 7062292SN/Avoid 7071060SN/AInstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 7081060SN/A{ 7092292SN/A DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 7101060SN/A assert(!cpu->switchedOut()); 7111060SN/A // The CPU could have been sleeping until this op completed (*extremely* 7122292SN/A // long latency op). Wake it if it was. This may be overkill. 7132292SN/A iewStage->wakeCPU(); 7142292SN/A 7152292SN/A if (fu_idx > -1) 7162367SN/A fuPool->freeUnitNextCycle(fu_idx); 7172292SN/A 7182292SN/A // @todo: Ensure that these FU Completions happen at the beginning 7192307SN/A // of a cycle, otherwise they could add too many instructions to 7202367SN/A // the queue. 7212367SN/A issueToExecuteQueue->access(-1)->size++; 7222307SN/A instsToExecute.push_back(inst); 7232307SN/A} 7242307SN/A 7252292SN/A// @todo: Figure out a better way to remove the squashed items from the 7262292SN/A// lists. Checking the top item of each list to see if it's squashed 7272326SN/A// wastes time and forces jumps. 7282326SN/Atemplate <class Impl> 7292292SN/Avoid 7302326SN/AInstructionQueue<Impl>::scheduleReadyInsts() 7312326SN/A{ 7322326SN/A DPRINTF(IQ, "Attempting to schedule ready instructions from " 7335327Smengke97@hotmail.com "the IQ.\n"); 7342333SN/A 7352292SN/A IssueStruct *i2e_info = issueToExecuteQueue->access(0); 7362292SN/A 7371061SN/A DynInstPtr deferred_mem_inst; 7381061SN/A int total_deferred_mem_issued = 0; 7391061SN/A while (total_deferred_mem_issued < totalWidth && 7401061SN/A (deferred_mem_inst = getDeferredMemInstToExecute()) != 0) { 7411060SN/A issueToExecuteQueue->access(0)->size++; 7421060SN/A instsToExecute.push_back(deferred_mem_inst); 7431060SN/A total_deferred_mem_issued++; 7442292SN/A } 7452292SN/A 7461060SN/A // Have iterator to head of the list 7471060SN/A // While I haven't exceeded bandwidth or reached the end of the list, 7481060SN/A // Try to get a FU that can do what this op needs. 7497944SGiacomo.Gabrielli@arm.com // If successful, change the oldestInst to the new top of the list, put 7507944SGiacomo.Gabrielli@arm.com // the queue in the proper place in the list. 7517944SGiacomo.Gabrielli@arm.com // Increment the iterator. 7527962Ssaidi@eecs.umich.edu // This will avoid trying to schedule a certain op class if there are no 7537944SGiacomo.Gabrielli@arm.com // FUs that handle it. 7547944SGiacomo.Gabrielli@arm.com ListOrderIt order_it = listOrder.begin(); 7557944SGiacomo.Gabrielli@arm.com ListOrderIt order_end_it = listOrder.end(); 7567944SGiacomo.Gabrielli@arm.com int total_issued = 0; 7577944SGiacomo.Gabrielli@arm.com 7582292SN/A while (total_issued < (totalWidth - total_deferred_mem_issued) && 7592292SN/A iewStage->canIssue() && 7602292SN/A order_it != order_end_it) { 7612292SN/A OpClass op_class = (*order_it).queueType; 7622292SN/A 7632292SN/A assert(!readyInsts[op_class].empty()); 7642292SN/A 7652292SN/A DynInstPtr issuing_inst = readyInsts[op_class].top(); 7662292SN/A 7672292SN/A issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++; 7682292SN/A 7691060SN/A assert(issuing_inst->seqNum == (*order_it).oldestInst); 7707944SGiacomo.Gabrielli@arm.com 7712820Sktlim@umich.edu if (issuing_inst->isSquashed()) { 7722326SN/A readyInsts[op_class].pop(); 7732292SN/A 7741060SN/A if (!readyInsts[op_class].empty()) { 7752292SN/A moveToYoungerInst(order_it); 7761060SN/A } else { 7772292SN/A readyIt[op_class] = listOrder.end(); 7781060SN/A queueOnList[op_class] = false; 7797897Shestness@cs.utexas.edu } 7807897Shestness@cs.utexas.edu 7812292SN/A listOrder.erase(order_it++); 7821060SN/A 7832292SN/A ++iqSquashedInstsIssued; 7842292SN/A 7851060SN/A continue; 7862292SN/A } 7872292SN/A 7882292SN/A int idx = -2; 7892292SN/A Cycles op_latency = Cycles(1); 7902292SN/A ThreadID tid = issuing_inst->threadNumber; 7911060SN/A 7921060SN/A if (op_class != No_OpClass) { 7932292SN/A idx = fuPool->getUnit(op_class); 7941060SN/A issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++; 7952292SN/A if (idx > -1) { 7962292SN/A op_latency = fuPool->getOpLatency(op_class); 7972292SN/A } 7981060SN/A } 7991060SN/A 8002326SN/A // If we have an instruction that doesn't require a FU, or a 8012326SN/A // valid FU, then schedule for execution. 8026221Snate@binkert.org if (idx == -2 || idx != -1) { 8031060SN/A if (op_latency == Cycles(1)) { 8042326SN/A i2e_info->size++; 8052326SN/A instsToExecute.push_back(issuing_inst); 8067897Shestness@cs.utexas.edu 8072326SN/A // Add the FU onto the list of FU's to be freed next 8082326SN/A // cycle if we used one. 8091060SN/A if (idx >= 0) 8101060SN/A fuPool->freeUnitNextCycle(idx); 8111060SN/A } else { 8122348SN/A Cycles issue_latency = fuPool->getIssueLatency(op_class); 8132348SN/A // Generate completion event for the FU 8142326SN/A FUCompletion *execution = new FUCompletion(issuing_inst, 8152292SN/A idx, this); 8162292SN/A 8172333SN/A cpu->schedule(execution, 8181060SN/A cpu->clockEdge(Cycles(op_latency - 1))); 8192326SN/A 8202326SN/A // @todo: Enforce that issue_latency == 1 or op_latency 8212326SN/A if (issue_latency > Cycles(1)) { 8222326SN/A // If FU isn't pipelined, then it must be freed 8232292SN/A // upon the execution completing. 8242292SN/A execution->setFreeFU(); 8252326SN/A } else { 8262326SN/A // Add the FU onto the list of FU's to be freed next cycle. 8272326SN/A fuPool->freeUnitNextCycle(idx); 8281060SN/A } 8297823Ssteve.reinhardt@amd.com } 8301060SN/A 8312326SN/A DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 8322292SN/A "[sn:%lli]\n", 8332348SN/A tid, issuing_inst->pcState(), 8342348SN/A issuing_inst->seqNum); 8352326SN/A 8362292SN/A readyInsts[op_class].pop(); 8372292SN/A 8382326SN/A if (!readyInsts[op_class].empty()) { 8392292SN/A moveToYoungerInst(order_it); 8401060SN/A } else { 8411060SN/A readyIt[op_class] = listOrder.end(); 8427720Sgblack@eecs.umich.edu queueOnList[op_class] = false; 8432292SN/A } 8447720Sgblack@eecs.umich.edu 8452292SN/A issuing_inst->setIssued(); 8461060SN/A ++total_issued; 8472292SN/A 8481061SN/A#if TRACING_ON 8492292SN/A issuing_inst->issueTick = curTick() - issuing_inst->fetchTick; 8502292SN/A#endif 8512292SN/A 8522292SN/A if (!issuing_inst->isMemRef()) { 8532292SN/A // Memory instructions can not be freed from the IQ until they 8541060SN/A // complete. 8551060SN/A ++freeEntries; 8562064SN/A count[tid]--; 8572292SN/A issuing_inst->clearInIQ(); 8582064SN/A } else { 8592292SN/A memDepUnit[tid].issue(issuing_inst); 8602292SN/A } 8612292SN/A 8622292SN/A listOrder.erase(order_it++); 8632301SN/A statIssuedInstType[tid][op_class]++; 8642731Sktlim@umich.edu iewStage->incrWb(issuing_inst->seqNum); 8652292SN/A } else { 8662301SN/A statFuBusy[op_class]++; 8672292SN/A fuBusy[tid]++; 8682292SN/A ++order_it; 8692292SN/A } 8702326SN/A } 8712820Sktlim@umich.edu 8722292SN/A numIssuedDist.sample(total_issued); 8732326SN/A iqInstsIssued+= total_issued; 8742326SN/A 8752292SN/A // If we issued any instructions, tell the CPU we had activity. 8761060SN/A // @todo If the way deferred memory instructions are handeled due to 8771060SN/A // translation changes then the deferredMemInsts condition should be removed 8781062SN/A // from the code below. 8792326SN/A if (total_issued || total_deferred_mem_issued || deferredMemInsts.size()) { 8802326SN/A cpu->activityThisCycle(); 8812307SN/A } else { 8822348SN/A DPRINTF(IQ, "Not able to schedule any instructions.\n"); 8838071SAli.Saidi@ARM.com } 8848071SAli.Saidi@ARM.com} 8858071SAli.Saidi@ARM.com 8868071SAli.Saidi@ARM.comtemplate <class Impl> 8872292SN/Avoid 8882292SN/AInstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 8892292SN/A{ 8902292SN/A DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 8911060SN/A "to execute.\n", inst); 8921060SN/A 8931061SN/A NonSpecMapIt inst_it = nonSpecInsts.find(inst); 8941060SN/A 8951061SN/A assert(inst_it != nonSpecInsts.end()); 8961060SN/A 8972292SN/A ThreadID tid = (*inst_it).second->threadNumber; 8982292SN/A 8991062SN/A (*inst_it).second->setAtCommit(); 9002292SN/A 9011060SN/A (*inst_it).second->setCanIssue(); 9021061SN/A 9031060SN/A if (!(*inst_it).second->isMemRef()) { 9046221Snate@binkert.org addIfReady((*inst_it).second); 9052292SN/A } else { 9064033Sktlim@umich.edu memDepUnit[tid].nonSpecInstReady((*inst_it).second); 9074033Sktlim@umich.edu } 9081061SN/A 9091060SN/A (*inst_it).second = NULL; 9101062SN/A 9111062SN/A nonSpecInsts.erase(inst_it); 9121062SN/A} 9132292SN/A 9141062SN/Atemplate <class Impl> 9151060SN/Avoid 9162292SN/AInstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 9172292SN/A{ 9181061SN/A DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 9191060SN/A tid,inst); 9201060SN/A 9211061SN/A ListIt iq_it = instList[tid].begin(); 9221061SN/A 9236221Snate@binkert.org while (iq_it != instList[tid].end() && 9242292SN/A (*iq_it)->seqNum <= inst) { 9252292SN/A ++iq_it; 9262292SN/A instList[tid].pop_front(); 9272292SN/A } 9282292SN/A 9292292SN/A assert(freeEntries == (numEntries - countInsts())); 9302292SN/A} 9312292SN/A 9322292SN/Atemplate <class Impl> 9332292SN/Aint 9342292SN/AInstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 9352292SN/A{ 9362292SN/A int dependents = 0; 9372292SN/A 9382292SN/A // The instruction queue here takes care of both floating and int ops 9392292SN/A if (completed_inst->isFloating()) { 9402301SN/A fpInstQueueWakeupQccesses++; 9411684SN/A } else { 9421684SN/A intInstQueueWakeupAccesses++; 9432301SN/A } 9442301SN/A 9457897Shestness@cs.utexas.edu DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 9467897Shestness@cs.utexas.edu 9477897Shestness@cs.utexas.edu assert(!completed_inst->isSquashed()); 9487897Shestness@cs.utexas.edu 9497897Shestness@cs.utexas.edu // Tell the memory dependence unit to wake any dependents on this 9507897Shestness@cs.utexas.edu // instruction if it is a memory instruction. Also complete the memory 9517897Shestness@cs.utexas.edu // instruction at this point since we know it executed without issues. 9522292SN/A // @todo: Might want to rename "completeMemInst" to something that 9532292SN/A // indicates that it won't need to be replayed, and call this 9542292SN/A // earlier. Might not be a big deal. 9551684SN/A if (completed_inst->isMemRef()) { 9561684SN/A memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 9572292SN/A completeMemInst(completed_inst); 9582326SN/A } else if (completed_inst->isMemBarrier() || 9592326SN/A completed_inst->isWriteBarrier()) { 9602326SN/A memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 9612326SN/A } 9621684SN/A 9632292SN/A for (int dest_reg_idx = 0; 9642292SN/A dest_reg_idx < completed_inst->numDestRegs(); 9652292SN/A dest_reg_idx++) 9662292SN/A { 9672292SN/A PhysRegIndex dest_reg = 9681684SN/A completed_inst->renamedDestRegIdx(dest_reg_idx); 9691684SN/A 9701684SN/A // Special case of uniq or control registers. They are not 9711684SN/A // handled by the IQ and thus have no dependency graph entry. 9721684SN/A // @todo Figure out a cleaner way to handle this. 9731684SN/A if (dest_reg >= numPhysRegs) { 9741684SN/A DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg, 9751684SN/A numPhysRegs); 9761684SN/A continue; 9771684SN/A } 9781684SN/A 9791684SN/A DPRINTF(IQ, "Waking any dependents on register %i.\n", 9801684SN/A (int) dest_reg); 9817599Sminkyu.jeong@arm.com 9827599Sminkyu.jeong@arm.com //Go through the dependency chain, marking the registers as 9831684SN/A //ready within the waiting instructions. 9841684SN/A DynInstPtr dep_inst = dependGraph.pop(dest_reg); 9851684SN/A 9862292SN/A while (dep_inst) { 9871684SN/A DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] " 9881684SN/A "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 9892326SN/A 9902326SN/A // Might want to give more information to the instruction 9912326SN/A // so that it knows which of its source registers is 9921684SN/A // ready. However that would mean that the dependency 9932326SN/A // graph entries would need to hold the src_reg_idx. 9947599Sminkyu.jeong@arm.com dep_inst->markSrcRegReady(); 9957720Sgblack@eecs.umich.edu 9961684SN/A addIfReady(dep_inst); 9971684SN/A 9982326SN/A dep_inst = dependGraph.pop(dest_reg); 9992326SN/A 10002326SN/A ++dependents; 10012326SN/A } 10021684SN/A 10032326SN/A // Reset the head node now that all of its dependents have 10041684SN/A // been woken up. 10052326SN/A assert(dependGraph.empty(dest_reg)); 10061684SN/A dependGraph.clearInst(dest_reg); 10072301SN/A 10081684SN/A // Mark the scoreboard as having that register ready. 10091684SN/A regScoreboard[dest_reg] = true; 10102326SN/A } 10112326SN/A return dependents; 10122326SN/A} 10132326SN/A 10141684SN/Atemplate <class Impl> 10151684SN/Avoid 10161684SN/AInstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 10171684SN/A{ 10182301SN/A OpClass op_class = ready_inst->opClass(); 10192064SN/A 10202064SN/A readyInsts[op_class].push(ready_inst); 10212064SN/A 10222064SN/A // Will need to reorder the list if either a queue is not on the list, 10232292SN/A // or it has an older instruction than last time. 10242064SN/A if (!queueOnList[op_class]) { 10252292SN/A addToOrderList(op_class); 10262292SN/A } else if (readyInsts[op_class].top()->seqNum < 10272292SN/A (*readyIt[op_class]).oldestInst) { 10282292SN/A listOrder.erase(readyIt[op_class]); 10292326SN/A addToOrderList(op_class); 10302326SN/A } 10312326SN/A 10322326SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 10332326SN/A "the ready list, PC %s opclass:%i [sn:%lli].\n", 10342326SN/A ready_inst->pcState(), op_class, ready_inst->seqNum); 10352326SN/A} 10362326SN/A 10372326SN/Atemplate <class Impl> 10382326SN/Avoid 10392292SN/AInstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 10407720Sgblack@eecs.umich.edu{ 10417720Sgblack@eecs.umich.edu DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 10422064SN/A 10432064SN/A // Reset DTB translation state 10442064SN/A resched_inst->translationStarted(false); 10452064SN/A resched_inst->translationCompleted(false); 10462292SN/A 10472064SN/A resched_inst->clearCanIssue(); 10484033Sktlim@umich.edu memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 10497944SGiacomo.Gabrielli@arm.com} 10507944SGiacomo.Gabrielli@arm.com 10517944SGiacomo.Gabrielli@arm.comtemplate <class Impl> 10527944SGiacomo.Gabrielli@arm.comvoid 10537944SGiacomo.Gabrielli@arm.comInstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 10544033Sktlim@umich.edu{ 10552292SN/A memDepUnit[replay_inst->threadNumber].replay(replay_inst); 10562064SN/A} 10572064SN/A 10582064SN/Atemplate <class Impl> 10592064SN/Avoid 10602292SN/AInstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 10612064SN/A{ 10622292SN/A ThreadID tid = completed_inst->threadNumber; 10632292SN/A 10642292SN/A DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n", 10652292SN/A completed_inst->pcState(), completed_inst->seqNum); 10662292SN/A 10672292SN/A ++freeEntries; 10682292SN/A 10696221Snate@binkert.org completed_inst->memOpDone(true); 10702292SN/A 10717720Sgblack@eecs.umich.edu memDepUnit[tid].completed(completed_inst); 10727720Sgblack@eecs.umich.edu count[tid]--; 10732292SN/A} 10742292SN/A 10752292SN/Atemplate <class Impl> 10762292SN/Avoid 10772292SN/AInstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst) 10782292SN/A{ 10792292SN/A deferredMemInsts.push_back(deferred_inst); 10801684SN/A} 10811684SN/A 10821684SN/Atemplate <class Impl> 10831684SN/Atypename Impl::DynInstPtr 10847944SGiacomo.Gabrielli@arm.comInstructionQueue<Impl>::getDeferredMemInstToExecute() 10857944SGiacomo.Gabrielli@arm.com{ 10867944SGiacomo.Gabrielli@arm.com for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); 10877944SGiacomo.Gabrielli@arm.com ++it) { 10887944SGiacomo.Gabrielli@arm.com if ((*it)->translationCompleted() || (*it)->isSquashed()) { 10897944SGiacomo.Gabrielli@arm.com DynInstPtr ret = *it; 10907944SGiacomo.Gabrielli@arm.com deferredMemInsts.erase(it); 10917944SGiacomo.Gabrielli@arm.com return ret; 10927944SGiacomo.Gabrielli@arm.com } 10937944SGiacomo.Gabrielli@arm.com } 10947944SGiacomo.Gabrielli@arm.com return NULL; 10957944SGiacomo.Gabrielli@arm.com} 10967944SGiacomo.Gabrielli@arm.com 10977944SGiacomo.Gabrielli@arm.comtemplate <class Impl> 10987944SGiacomo.Gabrielli@arm.comvoid 10997944SGiacomo.Gabrielli@arm.comInstructionQueue<Impl>::violation(DynInstPtr &store, 11007944SGiacomo.Gabrielli@arm.com DynInstPtr &faulting_load) 11017944SGiacomo.Gabrielli@arm.com{ 11027944SGiacomo.Gabrielli@arm.com intInstQueueWrites++; 11037944SGiacomo.Gabrielli@arm.com memDepUnit[store->threadNumber].violation(store, faulting_load); 11047944SGiacomo.Gabrielli@arm.com} 11057944SGiacomo.Gabrielli@arm.com 11061061SN/Atemplate <class Impl> 11071061SN/Avoid 11081061SN/AInstructionQueue<Impl>::squash(ThreadID tid) 11097897Shestness@cs.utexas.edu{ 11102292SN/A DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 11111061SN/A "the IQ.\n", tid); 11121061SN/A 11131061SN/A // Read instruction sequence number of last instruction out of the 11141060SN/A // time buffer. 11156221Snate@binkert.org squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 11161060SN/A 11172292SN/A // Call doSquash if there are insts in the IQ 11182292SN/A if (count[tid] > 0) { 11191060SN/A doSquash(tid); 11201060SN/A } 11211060SN/A 11222292SN/A // Also tell the memory dependence unit to squash. 11231060SN/A memDepUnit[tid].squash(squashedSeqNum[tid], tid); 11241681SN/A} 11252292SN/A 11262292SN/Atemplate <class Impl> 11271681SN/Avoid 11281061SN/AInstructionQueue<Impl>::doSquash(ThreadID tid) 11291061SN/A{ 11302292SN/A // Start at the tail. 11311060SN/A ListIt squash_it = instList[tid].end(); 11321060SN/A --squash_it; 11331061SN/A 11341061SN/A DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 11356221Snate@binkert.org tid, squashedSeqNum[tid]); 11361061SN/A 11372326SN/A // Squash any instructions younger than the squashed sequence number 11382326SN/A // given. 11392326SN/A while (squash_it != instList[tid].end() && 11401061SN/A (*squash_it)->seqNum > squashedSeqNum[tid]) { 11412292SN/A 11422292SN/A DynInstPtr squashed_inst = (*squash_it); 11431061SN/A squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 11441061SN/A 11451061SN/A // Only handle the instruction if it actually is in the IQ and 11462326SN/A // hasn't already been squashed in the IQ. 11472326SN/A if (squashed_inst->threadNumber != tid || 11482292SN/A squashed_inst->isSquashedInIQ()) { 11492326SN/A --squash_it; 11507897Shestness@cs.utexas.edu continue; 11511061SN/A } 11521061SN/A 11531061SN/A if (!squashed_inst->isIssued() || 11542292SN/A (squashed_inst->isMemRef() && 11552292SN/A !squashed_inst->memOpDone())) { 11562326SN/A 11572292SN/A DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", 11582292SN/A tid, squashed_inst->seqNum, squashed_inst->pcState()); 11592292SN/A 11602292SN/A bool is_acq_rel = squashed_inst->isMemBarrier() && 11612292SN/A (squashed_inst->isLoad() || 11622292SN/A (squashed_inst->isStore() && 11631062SN/A !squashed_inst->isStoreConditional())); 11647720Sgblack@eecs.umich.edu 11657720Sgblack@eecs.umich.edu // Remove the instruction from the dependency list. 11662367SN/A if (is_acq_rel || 11671061SN/A (!squashed_inst->isNonSpeculative() && 11682292SN/A !squashed_inst->isStoreConditional() && 11692336SN/A !squashed_inst->isMemBarrier() && 11702292SN/A !squashed_inst->isWriteBarrier())) { 11712292SN/A 11721061SN/A for (int src_reg_idx = 0; 11731061SN/A src_reg_idx < squashed_inst->numSrcRegs(); 11741681SN/A src_reg_idx++) 11751061SN/A { 11761061SN/A PhysRegIndex src_reg = 11771061SN/A squashed_inst->renamedSrcRegIdx(src_reg_idx); 11781061SN/A 11791061SN/A // Only remove it from the dependency graph if it 11802326SN/A // was placed there in the first place. 11812326SN/A 11822326SN/A // Instead of doing a linked list traversal, we 11832326SN/A // can just remove these squashed instructions 11842326SN/A // either at issue time, or when the register is 11852326SN/A // overwritten. The only downside to this is it 11862326SN/A // leaves more room for error. 11872326SN/A 11882292SN/A if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 11891061SN/A src_reg < numPhysRegs) { 11901061SN/A dependGraph.remove(src_reg, squashed_inst); 11912326SN/A } 11921061SN/A 11931062SN/A 11942292SN/A ++iqSquashedOperandsExamined; 11951062SN/A } 11961061SN/A } else if (!squashed_inst->isStoreConditional() || 11974033Sktlim@umich.edu !squashed_inst->isCompleted()) { 11984033Sktlim@umich.edu NonSpecMapIt ns_inst_it = 11992292SN/A nonSpecInsts.find(squashed_inst->seqNum); 12002292SN/A 12012292SN/A // we remove non-speculative instructions from 12024033Sktlim@umich.edu // nonSpecInsts already when they are ready, and so we 12034033Sktlim@umich.edu // cannot always expect to find them 12044033Sktlim@umich.edu if (ns_inst_it == nonSpecInsts.end()) { 12051062SN/A // loads that became ready but stalled on a 12064033Sktlim@umich.edu // blocked cache are alreayd removed from 12071681SN/A // nonSpecInsts, and have not faulted 12084033Sktlim@umich.edu assert(squashed_inst->getFault() != NoFault || 12091062SN/A squashed_inst->isMemRef()); 12104033Sktlim@umich.edu } else { 12114033Sktlim@umich.edu 12121061SN/A (*ns_inst_it).second = NULL; 12131061SN/A 12141061SN/A nonSpecInsts.erase(ns_inst_it); 12151061SN/A 12161061SN/A ++iqSquashedNonSpecRemoved; 12171061SN/A } 12181061SN/A } 12192292SN/A 12202292SN/A // Might want to also clear out the head of the dependency graph. 12211681SN/A 12221681SN/A // Mark it as squashed within the IQ. 12232731Sktlim@umich.edu squashed_inst->setSquashedInIQ(); 12242292SN/A 12252292SN/A // @todo: Remove this hack where several statuses are set so the 12262292SN/A // inst will flow through the rest of the pipeline. 12271681SN/A squashed_inst->setIssued(); 12281681SN/A squashed_inst->setCanCommit(); 12291061SN/A squashed_inst->clearInIQ(); 12301061SN/A 12312326SN/A //Update Thread IQ Count 12321062SN/A count[squashed_inst->threadNumber]--; 12331061SN/A 12341060SN/A ++freeEntries; 12351060SN/A } 12361061SN/A 12371060SN/A instList[tid].erase(squash_it--); 12381061SN/A ++iqSquashedInstsExamined; 12391060SN/A } 12401060SN/A} 12411060SN/A 12421060SN/Atemplate <class Impl> 12431060SN/Abool 12441060SN/AInstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 12451060SN/A{ 12461060SN/A // Loop through the instruction's source registers, adding 12471060SN/A // them to the dependency list if they are not ready. 12481060SN/A int8_t total_src_regs = new_inst->numSrcRegs(); 12491060SN/A bool return_val = false; 12501060SN/A 12511060SN/A for (int src_reg_idx = 0; 12521060SN/A src_reg_idx < total_src_regs; 12531060SN/A src_reg_idx++) 12541060SN/A { 12551060SN/A // Only add it to the dependency graph if it's not ready. 12561060SN/A if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 12571061SN/A PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 12581061SN/A 12591061SN/A // Check the IQ's scoreboard to make sure the register 12607720Sgblack@eecs.umich.edu // hasn't become ready while the instruction was in flight 12611060SN/A // between stages. Only if it really isn't ready should 12627720Sgblack@eecs.umich.edu // it be added to the dependency graph. 12631060SN/A if (src_reg >= numPhysRegs) { 12642326SN/A continue; 12651060SN/A } else if (regScoreboard[src_reg] == false) { 12661060SN/A DPRINTF(IQ, "Instruction PC %s has src reg %i that " 12671060SN/A "is being added to the dependency chain.\n", 12681060SN/A new_inst->pcState(), src_reg); 12691060SN/A 12707720Sgblack@eecs.umich.edu dependGraph.insert(src_reg, new_inst); 12711060SN/A 12727720Sgblack@eecs.umich.edu // Change the return value to indicate that something 12731060SN/A // was added to the dependency graph. 12742326SN/A return_val = true; 12751060SN/A } else { 12761060SN/A DPRINTF(IQ, "Instruction PC %s has src reg %i that " 12771060SN/A "became ready before it reached the IQ.\n", 12781060SN/A new_inst->pcState(), src_reg); 12791060SN/A // Mark a register ready within the instruction. 12801060SN/A new_inst->markSrcRegReady(src_reg_idx); 12811060SN/A } 12821061SN/A } 12831060SN/A } 12842326SN/A 12851060SN/A return return_val; 12862326SN/A} 12872326SN/A 12882326SN/Atemplate <class Impl> 12892326SN/Avoid 12901060SN/AInstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) 12911060SN/A{ 12921060SN/A // Nothing really needs to be marked when an instruction becomes 12931060SN/A // the producer of a register's value, but for convenience a ptr 12941060SN/A // to the producing instruction will be placed in the head node of 12951060SN/A // the dependency links. 12961061SN/A int8_t total_dest_regs = new_inst->numDestRegs(); 12971061SN/A 12981061SN/A for (int dest_reg_idx = 0; 12991061SN/A dest_reg_idx < total_dest_regs; 13001061SN/A dest_reg_idx++) 13011061SN/A { 13021061SN/A PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 13031061SN/A 13041060SN/A // Instructions that use the misc regs will have a reg number 13051060SN/A // higher than the normal physical registers. In this case these 13062326SN/A // registers are not renamed, and there is no need to track 13072326SN/A // dependencies as these instructions must be executed at commit. 13082292SN/A if (dest_reg >= numPhysRegs) { 13092064SN/A continue; 13101062SN/A } 13112326SN/A 13121062SN/A if (!dependGraph.empty(dest_reg)) { 13131060SN/A dependGraph.dump(); 13141060SN/A panic("Dependency graph %i not empty!", dest_reg); 13151060SN/A } 13161060SN/A 13171060SN/A dependGraph.setInst(dest_reg, new_inst); 13181061SN/A 13191060SN/A // Mark the scoreboard to say it's not yet ready. 13201061SN/A regScoreboard[dest_reg] = false; 13211060SN/A } 13222326SN/A} 13231060SN/A 13241060SN/Atemplate <class Impl> 13251061SN/Avoid 13261060SN/AInstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 13272292SN/A{ 13281061SN/A // If the instruction now has all of its source registers 13292292SN/A // available, then add it to the list of ready instructions. 13301061SN/A if (inst->readyToIssue()) { 13311062SN/A 13321062SN/A //Add the instruction to the proper ready list. 13332292SN/A if (inst->isMemRef()) { 13341062SN/A 13352292SN/A DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 13362292SN/A 13371062SN/A // Message to the mem dependence unit that this instruction has 13382292SN/A // its registers ready. 13391061SN/A memDepUnit[inst->threadNumber].regsReady(inst); 13402292SN/A 13417720Sgblack@eecs.umich.edu return; 13427720Sgblack@eecs.umich.edu } 13431061SN/A 13442292SN/A OpClass op_class = inst->opClass(); 13451061SN/A 13462326SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 13472326SN/A "the ready list, PC %s opclass:%i [sn:%lli].\n", 13482326SN/A inst->pcState(), op_class, inst->seqNum); 13492326SN/A 13502326SN/A readyInsts[op_class].push(inst); 13512326SN/A 13522326SN/A // Will need to reorder the list if either a queue is not on the list, 13532326SN/A // or it has an older instruction than last time. 13541060SN/A if (!queueOnList[op_class]) { 13551060SN/A addToOrderList(op_class); 13561060SN/A } else if (readyInsts[op_class].top()->seqNum < 13571060SN/A (*readyIt[op_class]).oldestInst) { 13581061SN/A listOrder.erase(readyIt[op_class]); 13591061SN/A addToOrderList(op_class); 13601061SN/A } 13611061SN/A } 13622698Sktlim@umich.edu} 13632292SN/A 13642292SN/Atemplate <class Impl> 13652292SN/Aint 13662698Sktlim@umich.eduInstructionQueue<Impl>::countInsts() 13671061SN/A{ 13681061SN/A#if 0 13696221Snate@binkert.org //ksewell:This works but definitely could use a cleaner write 13706221Snate@binkert.org //with a more intuitive way of counting. Right now it's 13711681SN/A //just brute force .... 13726221Snate@binkert.org // Change the #if if you want to use this method. 13732292SN/A int total_insts = 0; 13742292SN/A 13752292SN/A for (ThreadID tid = 0; tid < numThreads; ++tid) { 13762292SN/A ListIt count_it = instList[tid].begin(); 13772292SN/A 13782292SN/A while (count_it != instList[tid].end()) { 13792292SN/A if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 13802292SN/A if (!(*count_it)->isIssued()) { 13812292SN/A ++total_insts; 13822292SN/A } else if ((*count_it)->isMemRef() && 13832292SN/A !(*count_it)->memOpDone) { 13842292SN/A // Loads that have not been marked as executed still count 13851061SN/A // towards the total instructions. 13861061SN/A ++total_insts; 13871061SN/A } 13881061SN/A } 13892292SN/A 13902292SN/A ++count_it; 13912292SN/A } 13921681SN/A } 13931681SN/A 13941681SN/A return total_insts; 13951681SN/A#else 13961061SN/A return numEntries - freeEntries; 13971061SN/A#endif 13982292SN/A} 13992292SN/A 14001061SN/Atemplate <class Impl> 14012292SN/Avoid 14022292SN/AInstructionQueue<Impl>::dumpLists() 14031061SN/A{ 14041061SN/A for (int i = 0; i < Num_OpClasses; ++i) { 14051061SN/A cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 14062292SN/A 14072292SN/A cprintf("\n"); 14081061SN/A } 14091061SN/A 14101061SN/A cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 14112292SN/A 14127720Sgblack@eecs.umich.edu NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 14132292SN/A NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 14141061SN/A 14151061SN/A cprintf("Non speculative list: "); 14161061SN/A 14171061SN/A while (non_spec_it != non_spec_end_it) { 14181061SN/A cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(), 14192292SN/A (*non_spec_it).second->seqNum); 14202292SN/A ++non_spec_it; 14212292SN/A } 14222292SN/A 14232292SN/A cprintf("\n"); 14242292SN/A 14252292SN/A ListOrderIt list_order_it = listOrder.begin(); 14262292SN/A ListOrderIt list_order_end_it = listOrder.end(); 14272292SN/A int i = 1; 14282292SN/A 14292292SN/A cprintf("List order: "); 14302292SN/A 14312292SN/A while (list_order_it != list_order_end_it) { 14322292SN/A cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 14332292SN/A (*list_order_it).oldestInst); 14341061SN/A 14352292SN/A ++list_order_it; 14362292SN/A ++i; 14372292SN/A } 14382292SN/A 14392292SN/A cprintf("\n"); 14402292SN/A} 14416221Snate@binkert.org 14422292SN/A 14432292SN/Atemplate <class Impl> 14446221Snate@binkert.orgvoid 14452292SN/AInstructionQueue<Impl>::dumpInsts() 14466221Snate@binkert.org{ 14476221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 14482292SN/A int num = 0; 14492292SN/A int valid_num = 0; 14502292SN/A ListIt inst_list_it = instList[tid].begin(); 14512292SN/A 14522292SN/A while (inst_list_it != instList[tid].end()) { 14532292SN/A cprintf("Instruction:%i\n", num); 14542326SN/A if (!(*inst_list_it)->isSquashed()) { 14552326SN/A if (!(*inst_list_it)->isIssued()) { 14562292SN/A ++valid_num; 14572292SN/A cprintf("Count:%i\n", valid_num); 14582292SN/A } else if ((*inst_list_it)->isMemRef() && 14592292SN/A !(*inst_list_it)->memOpDone()) { 14602292SN/A // Loads that have not been marked as executed 14617720Sgblack@eecs.umich.edu // still count towards the total instructions. 14622292SN/A ++valid_num; 14637720Sgblack@eecs.umich.edu cprintf("Count:%i\n", valid_num); 14642292SN/A } 14652292SN/A } 14662292SN/A 14672292SN/A cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 14682292SN/A "Issued:%i\nSquashed:%i\n", 14692292SN/A (*inst_list_it)->pcState(), 14702292SN/A (*inst_list_it)->seqNum, 14712292SN/A (*inst_list_it)->threadNumber, 14722292SN/A (*inst_list_it)->isIssued(), 14732292SN/A (*inst_list_it)->isSquashed()); 14742292SN/A 14752292SN/A if ((*inst_list_it)->isMemRef()) { 14762292SN/A cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 14772292SN/A } 14782292SN/A 14792348SN/A cprintf("\n"); 14802348SN/A 14812348SN/A inst_list_it++; 14822348SN/A ++num; 14832348SN/A } 14842348SN/A } 14852348SN/A 14862348SN/A cprintf("Insts to Execute list:\n"); 14872348SN/A 14882348SN/A int num = 0; 14892348SN/A int valid_num = 0; 14902348SN/A ListIt inst_list_it = instsToExecute.begin(); 14912348SN/A 14922348SN/A while (inst_list_it != instsToExecute.end()) 14932348SN/A { 14942348SN/A cprintf("Instruction:%i\n", 14952348SN/A num); 14962348SN/A if (!(*inst_list_it)->isSquashed()) { 14972348SN/A if (!(*inst_list_it)->isIssued()) { 14982348SN/A ++valid_num; 14992348SN/A cprintf("Count:%i\n", valid_num); 15002348SN/A } else if ((*inst_list_it)->isMemRef() && 15012348SN/A !(*inst_list_it)->memOpDone()) { 15022348SN/A // Loads that have not been marked as executed 15037720Sgblack@eecs.umich.edu // still count towards the total instructions. 15042348SN/A ++valid_num; 15057720Sgblack@eecs.umich.edu cprintf("Count:%i\n", valid_num); 15062348SN/A } 15072348SN/A } 15082348SN/A 15092348SN/A cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 15102348SN/A "Issued:%i\nSquashed:%i\n", 15112348SN/A (*inst_list_it)->pcState(), 15122348SN/A (*inst_list_it)->seqNum, 15132348SN/A (*inst_list_it)->threadNumber, 15142348SN/A (*inst_list_it)->isIssued(), 15152348SN/A (*inst_list_it)->isSquashed()); 15162348SN/A 15172348SN/A if ((*inst_list_it)->isMemRef()) { 15182348SN/A cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 15192348SN/A } 15202292SN/A 1521 cprintf("\n"); 1522 1523 inst_list_it++; 1524 ++num; 1525 } 1526} 1527 1528#endif//__CPU_O3_INST_QUEUE_IMPL_HH__ 1529